Compressed logical-to-physical mapping for sequentially stored data

Abstract

The present application is directed to a compressed logical-to-physical mapping for sequentially stored data. A memory device may use a hierarchical set of logical-to-physical mapping tables for mapping logical block addresses generated by a host device to physical addresses of the memory device. The memory device may determine whether all entries of a terminal logical-to-physical mapping table are consecutive physical addresses. In response to determining that all entries contain consecutive physical addresses, the memory device may store the starting physical address of the consecutive physical addresses as an entry in a higher-level table along with a flag indicating that the entry points directly to data in the memory device rather than to a terminal logical-to-physical mapping table. For subsequent reads of data stored in one or more of the consecutive physical addresses, the memory device may skip the terminal table to read the data.

Description

[0001] Cross-references

[0002] This patent application claims priority to U.S. patent application No. 16 / 870,674, filed by Cariello et al. on May 8, 2020, entitled "COMPRESSED LOGICAL-TO-PHYSICAL MAPPING FOR SEQUENTIALLY STORED DATA," which is assigned to the present assignee and is expressly incorporated herein by reference in its entirety.

[0003] The technical field relates to compressed logical-to-physical mapping for sequentially stored data. Background Art

[0004] The following relates generally to one or more memory systems, and more specifically, to compressed logical to physical mapping for sequentially stored data.

[0005] Memory devices are widely used to store information in various electronic devices such as computers, wireless communication devices, cameras, digital displays, etc. Information is stored by programming memory cells within the memory device to various states. For example, a binary memory cell can be programmed to one of two supported states, often indicated by a logical 1 or a logical 0. To access the stored information, a component can read or sense at least one stored state in the memory device. To store information, a component can write or program a state in the memory device.

[0006] There are various types of memory devices, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), 3D cross point memory (3D Xpoint), flash memory (such as floating gate flash devices and charge trap flash devices, which can be used in "NOR" or "NAND" memory devices), etc. Memory devices can be volatile or non-volatile. Non-volatile memory cells (such as flash memory cells) can maintain their stored logic state for a long time even in the absence of external power. Volatile memory cells (such as DRAM cells) may lose their stored state over time unless they are periodically refreshed by an external power source. Flash-based memory devices can have different performance compared to other non-volatile and volatile memory devices. Summary of the invention

[0007] An apparatus is described. The apparatus may include a memory array and a control component coupled to the memory array and configured to cause the apparatus to: receive a read command from a host device, the read command including a first logical block address associated with a location of at least a portion of data stored in the apparatus, wherein the data spans a plurality of consecutive physical addresses; determine, based at least in part on the first logical block address, a memory location for mapping a first plurality of logical block addresses including the first logical block address to a first plurality of entries of corresponding first plurality of physical addresses; read, based at least in part on the first logical block address, a first entry of the first plurality of entries, the first entry including a first physical address of the plurality of consecutive physical addresses and a first value of a flag; read at least a portion of the data from a second physical address of the plurality of consecutive physical addresses based at least in part on the first physical address and the first value of the flag; and transmit the data to the host device.

[0008] An apparatus is described. The apparatus may include a memory array and a control component coupled to the memory array and configured to cause the apparatus to: receive a plurality of write commands from a host device for writing data to the apparatus, the plurality of write commands including: a first write command including a first logical block address corresponding to a first entry in a number of entries for mapping a plurality of consecutive logical block addresses to a corresponding plurality of physical addresses, and a plurality of remaining write commands in the plurality of write commands, each including a corresponding consecutive logical block address; store data in the apparatus at a plurality of consecutive physical addresses starting from the first physical address based at least in part on receiving the plurality of write commands; determine whether the number of logical block addresses including the first logical block address and the corresponding logical block address matches the number of entries; and store the first physical address and a first value of a flag in a first entry in a plurality of entries for mapping a plurality of logical block addresses including the number of logical block addresses to a corresponding plurality of physical block addresses including the plurality of consecutive physical addresses based at least in part on determining that the number of logical block addresses matches the number of entries.

[0009] A non-transitory computer-readable medium is described. The non-transitory computer-readable medium may store code including instructions that, when executed by a processor of an electronic device, cause the electronic device to: receive a read command from a host device, the read command including a first logical block address associated with a location of at least a portion of data stored in the electronic device, wherein the data spans a plurality of consecutive physical addresses; determine, based at least in part on the first logical block address, a memory location for mapping a first plurality of logical block addresses including the first logical block address to a first plurality of entries of corresponding first plurality of physical addresses; read, based at least in part on the first logical block address, a first entry of the first plurality of entries, the first entry including a first physical address of the plurality of consecutive physical addresses and a first value of a flag; read at least a portion of the data from a second physical address of the plurality of consecutive physical addresses based at least in part on the first physical address and the first value of the flag; and transmit the data to the host device. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 An example of a memory device supporting compressed logical-to-physical mapping for sequentially stored data according to examples disclosed herein is described.

[0011] Figure 2 An example of a NAND circuit that supports compressed logical-to-physical mapping for sequentially stored data according to examples disclosed herein is described.

[0012] Figure 3 An example of a system supporting compressed logical-to-physical mapping for sequentially stored data according to examples disclosed herein is described.

[0013] Figure 4 An example of an operational flow supporting compressed logical-to-physical mapping for sequentially stored data according to examples disclosed herein is described.

[0014] Figure 5 An example of an operational flow supporting compressed logical-to-physical mapping for sequentially stored data according to examples disclosed herein is described.

[0015] Figure 6 An example of a process that supports compressed logical-to-physical mapping for sequentially stored data according to examples disclosed herein is described.

[0016] Figure 7 A block diagram is shown of a memory device supporting compressed logical-to-physical mapping for sequentially stored data according to examples disclosed herein.

[0017] Figure 8 and 9A flow chart illustrating one or more methods of supporting compressed logical-to-physical mapping for sequentially stored data according to examples disclosed herein is shown. DETAILED DESCRIPTION

[0018] A memory device, such as a device including flash memory, among other examples, may be coupled to a host device and may receive commands (e.g., read and write commands) from the host device for reading or writing data. Flash memory is typically organized into pages and blocks, where each block may contain multiple pages. Flash memory cells may be read and written at the page level, but may be erased at the block level. In some examples, flash memory cells may not be rewritten without first being erased. Thus, when a flash memory device updates a page of data (e.g., in response to a command from a host device), the memory device may write the new data to a different page and mark the old page as obsolete rather than erasing the memory block and rewriting any valid pages in the block.

[0019] For write operations, the host device may refer to the location of data stored in the memory device using a logical block address (LBA) to identify the logical (e.g., conceptual) location of a page of data. The LBA may be mapped to the physical address of a memory page of the memory device where the data is stored. Because the physical address of the data may change (e.g., when the data is updated by writing the updated data to a different page), some memory devices maintain one or more logical-to-physical (L2P) tables that map the LBAs generated by the host device to the corresponding physical addresses of pages in the memory device. In this way, the host device may request to read data from the memory device using the same LBA as the LBA used to write the data, even if the data has been moved to a different physical address. In some instances, the physical address may include an offset index indicating a specific subset of the page. For example, if the memory device has a page size of 16kB, each page may be further divided into four 4kB page subsets that can be accessed based on the offset index of the physical address.

[0020] A memory device with a relatively large storage capacity may use a hierarchical L2P table architecture with multiple levels of tables to identify the location of a data page to be read, such as a dual-level architecture or a triple-level architecture. In some instances, the memory device may use multiple levels of L2P tables to step back to the location of the data page in the flash memory. For example, a three-level L2P table architecture may include a relatively small first-level table, which may include a list of physical addresses pointing to the locations of multiple second-level L2P tables. The second-level L2P table may include a list of physical addresses pointing to the locations of multiple third-level L2P tables. The third-level L2P table may include a list of physical addresses pointing to the locations of data pages in the flash memory; for example, it may be a terminal (e.g., last) table in the hierarchical structure. Therefore, in order to access data in the flash memory, the memory device may navigate through three levels to identify the location of the requested data page. Such an approach may allow a relatively small first-level L2P table to be stored in SRAM on a memory device for fast access and updates, but may increase read latency by introducing additional operations, such as two additional reads (e.g., to read entries in the first-level table and the second-level table) to identify the physical address of the data.

[0021] The third level table may include a list of physical addresses that may be sorted by corresponding LBA index. That is, the first entry in the third level table may include a physical address corresponding to LBA0, the second entry may include a physical address corresponding to LBA 1, and so on. The physical addresses may not be sequential in all cases. However, when host data is written sequentially to the flash memory (e.g., data is written to sequential physical addresses), similar to the corresponding LBAs, the physical addresses in the third level L2P table may also be sequential. Such sequential writes may be faster than non-sequential writes and may occur, for example, when downloading or streaming data.

[0022] In some examples, the third level L2P table may contain between 512 bytes and 4 kB of physical addresses (depending on the architecture), thereby mapping between 2 and 16 MB of user data in flash memory.

[0023] In some examples, if the data pages of the third level table are stored sequentially (e.g., the physical addresses in the table are sequential), the data pages mapped by the third level table may be subsequently read based on the first physical address of the third level table (e.g., the starting physical address corresponding to the first LBA of the table). For example, the memory device may calculate the physical address of any of the pages of sequentially stored data based on the first physical address, or may read multiple sequential pages of data starting from the first physical address. Such sequentially stored data may be an example of or referred to as a data stream.

[0024] As described herein, the starting physical address of sequentially stored data may be stored as an entry in the second-level L2P table (e.g., rather than storing a pointer to an entry in the third-level L2P table), and may point directly to the sequential data. In this example, the memory device may locate the data by traversing the first two levels of L2P tables without accessing the third-level L2P table, thereby eliminating one of the L2P table reads and improving read latency, among other advantages.

[0025] In some examples, the second level L2P may include some entries pointing to physical addresses of sequential user data (e.g., bypassing the need for the third level L2P table), and other entries including pointers to the third level L2P table (e.g., for data stored non-sequentially). In some examples, it may be beneficial to provide an indication to the memory device as to which of these two types of entries is included in each of the second level L2P entries, so that the memory device can accurately locate the user data and bypass the third level L2P table when possible.

[0026] In some examples, each entry (e.g., a pointer) in the L2P table may occupy 4 bytes (for ease of calculation) and may point to up to 16TB of flash memory (with 4kB memory blocks). In memory devices with smaller capacities (e.g., up to 512GB), some bits in each entry may not be available for L2P mapping. Any available bits of each entry may actually be used to store additional information, such as whether the physical address is valid. In some examples, one or more such available bits may be used to indicate to the memory device whether the L2P entry contains a pointer to a third-level L2P table or a pointer to user data, among other examples.

[0027] The techniques described herein may provide several benefits. For example, random read performance may be improved by calculating the physical address of a data page in sequential data based on an offset of the physical address starting from the first LBA to eliminate the terminal L2P table lookup. In addition, the terminal L2P table update may be eliminated, resulting in more available space in the NAND flash memory (e.g., the third level L2P table may consume hundreds of MB) and less wear on the NAND memory cells for performing unnecessary operations.

[0028] To optimize read levels, the memory device may store temperature and time codes from when a programming operation (e.g., a write operation) occurs for each page or LBA in the NAND flash memory. By using indicators in the second-level L2P table to indicate sequential data, when filling an entire block (e.g., the entire terminal L2P table), the dedicated SRAM table may be compressed and the temperature and time stamps of each page in the block may be skipped, since sequential writes are done atomically.

[0029] At the beginning, I referred to Figure 1 and 2 Features of the present disclosure are described in the context of the memory devices and NAND circuits described herein. Figure 3-6 Features of the present disclosure are further described in the context of systems, processes, and procedures for generating and using entries in an L2P table for sequentially stored data. These and other features of the present disclosure are further illustrated and described with reference to device diagrams and flow diagrams, which relate to reference to Figures 7 to 9 A compressed logical-to-physical mapping for sequentially stored data is described.

[0030] Figure 1 An example of a memory device 100 according to examples disclosed herein is described. In some examples, the memory device 100 may be referred to as (or may be included in) a managed memory device, a universal flash storage (UFS) device, a solid-state storage device, a memory chip, or an electronic device or apparatus. The memory device 100 may include one or more memory cells, such as memory cell 105-a and memory cell 105-b (other memory cells are not labeled). The memory cell 105 may be, for example, a flash memory cell (e.g., Figure 1 ), a DRAM memory cell, a FeRAM memory cell, a PCM memory cell, or another type of memory cell.

[0031] Each memory cell 105 can be programmed to store a logic state representing one or more bits of information. Different memory cell architectures can store logic states in different ways. In a FeRAM architecture, for example, each memory cell 105 may include a capacitor including a ferroelectric material for storing a charge and / or polarization representing a programmable state. In a DRAM architecture, each memory cell 105 may include a capacitor including a dielectric material (e.g., an insulator) for storing a charge representing a programmable state. In a flash memory architecture, each memory cell 105 may include a transistor having a floating gate and / or a dielectric material for storing a charge representing a logic state. For example, an enlarged view of memory cell 105-a is a flash memory cell including a transistor 110 (e.g., a metal oxide semiconductor (MOS) transistor) that can be used to store a logic state. Transistor 110 has a control gate 115 and may include a floating gate 120 sandwiched between dielectric materials 125. Transistor 110 includes a first node 130 (e.g., a source or drain) and a second node 135 (e.g., a drain or source). A logic state may be stored in transistor 110 by placing (e.g., writing, storing) a certain number of electrons (e.g., charge) on floating gate 120. The amount of charge to be stored on floating gate 120 may depend on the logic state to be stored. The charge stored on floating gate 120 may affect the threshold voltage of transistor 110, thereby affecting the amount of current that may flow through transistor 110 when transistor 110 is activated. The logic state stored in transistor 110 may be read by applying a voltage to control gate 115 (e.g., at control node 140) to activate transistor 110 and measuring (e.g., detecting, sensing) the resulting amount of current flowing between first node 130 and second node 135.

[0032] For example, the sensing component 170 can determine the logic state stored on the flash memory cell based on the presence or absence of current from the memory cell or based on whether the current is above or below a threshold current. Similarly, a flash memory cell can be written by applying a voltage (e.g., a voltage above a threshold or a voltage below a threshold) to the memory cell to store (or not store) a charge representing one of the possible logic states on the floating gate.

[0033] A charge trapping flash memory cell may operate in a manner similar to a floating gate flash memory cell, but instead of (or in addition to) storing charge on a floating gate 120, a charge trapping flash memory cell may store charge representing a state in a dielectric material beneath the control gate 115. Thus, a charge trapping flash memory cell may or may not include a floating gate 120.

[0034] In some examples, each row of memory cells 105 may be connected to a word line 160, and each column of memory cells 105 may be connected to a digit line 165. Thus, one memory cell 105 may be located at the intersection of a word line 160 and a digit line 165. This intersection may be referred to as the address of the memory cell. A digit line is sometimes referred to as a bit line. In some examples, word lines 160 and digit lines 165 may be generally perpendicular to each other and may create an array of memory cells 105 (e.g., in a memory array). In some examples, word lines 160 and digit lines 165 may be generally referred to as access lines or select lines.

[0035] In some examples, memory device 100 may include a three-dimensional (3D) memory array in which multiple two-dimensional (1D) memory arrays are formed on top of each other. This may increase the number of memory cells that may be placed or produced on a single die or substrate compared to a 1D array, which in turn may reduce manufacturing costs, or increase the performance of the memory array, or both. Figure 1 In an example of memory device 100, memory device 100 includes multiple levels of memory arrays. In some examples, the levels can be separated by electrically insulating materials. Each level can be aligned or positioned so that memory cells 105 can be aligned (exactly, overlapping, or approximately) with each other on each level, thereby forming a memory cell stack 175. In some examples, memory cell stack 175 can be referred to as a memory cell string, with reference to Figure 3 Discuss in more detail.

[0036] Access to the memory cells 105 may be controlled by a row decoder 145 and a column decoder 150. For example, the row decoder 145 may receive a row address from a memory controller 155 (e.g., a control component) and activate the appropriate word line 160 based on the received row address. Similarly, the column decoder 150 may receive a column address from the memory controller 155 and activate the appropriate digit line 165. Thus, by activating one word line 160 and one digit line 165, one memory cell 105 may be accessed.

[0037] After access, the memory cell 105 can be read or sensed by the sensing component 170. For example, the sensing component 170 can be configured to determine the stored logic state of the memory cell 105 based on the signal generated by accessing the memory cell 105. The signal can include a voltage or a current, or both, and the sensing component 170 can include a voltage sense amplifier, a current sense amplifier, or both. For example, a current or a voltage can be applied to the memory cell 105 (using the corresponding word line 160 and / or the digit line 165), and the magnitude of the resulting current or voltage on the digit line 165 can depend on the logic state stored by the memory cell 105. For example, for a flash memory cell, the amount of charge stored on the floating gate or in the insulating layer of the transistor in the memory cell 105 can affect the threshold voltage of the transistor, thereby affecting the amount of current flowing through the transistor in the memory cell 105 when the memory cell 105 is accessed. The difference in such current can be used to determine the logic state stored on the memory cell 105.

[0038] The sensing component 170 may include various transistors or amplifiers in order to detect and amplify the signal (e.g., current or voltage) on the digital line 165. The detected logic state of the memory cell 105 may then be output via the input / output block 180. In some examples, the sensing component 170 may be part of the column decoder 150 or the row decoder 145, or the sensing component 170 may be otherwise connected or in electronic communication with the column decoder 150 or the row decoder 145.

[0039] A memory cell 105 may be set or written to by similarly activating the associated word line 160 and digit line 165 to enable a logic state (e.g., representing one or more bits of information) to be stored in the memory cell 105. The column decoder 150 or row decoder 145 may accept data to be written to the memory cell 105, for example, from the input / output block 180. As previously discussed, in the case of flash memory, such as that used in NAND and 3D NAND memory devices, the memory cell 105 may be written to by storing electrons in a floating gate or insulating layer.

[0040] The memory controller 155 may control the operation (e.g., read, write, rewrite, refresh, etc.) of the memory cell 105 through various components such as the row decoder 145, the column decoder 150, and the sensing component 170. In some examples, one or more of the row decoder 145, the column decoder 150, and the sensing component 170 may be co-located with the memory controller 155. The memory controller 155 may generate row and column address signals in order to activate the desired word lines 160 and digit lines 165. The memory controller 155 may also generate and control various voltages or currents used during the operation of the memory device 100. In some examples, the memory controller 155 or another component of the memory device 100 may construct (e.g., build, generate, and / or maintain) one or more L2P tables for mapping LBAs (e.g., LBAs generated by a host device) to physical addresses in the memory device 100 (e.g., addresses of physical pages in the memory device 100 corresponding to the LBAs). In some examples, the memory device 100 may generate and / or maintain multiple levels of L2P tables, such as in a three-level L2P table architecture. In some examples, the memory device 100 may determine whether a terminal L2P table (e.g., a third-level L2P table) is populated with (or will be populated with) sequential physical addresses, such as when data is sequentially written to the memory device. In this case, the memory device 100 may store a first physical address of the sequential physical addresses in an entry of a higher-level L2P table (e.g., a second-level L2P table), and may discard (or avoid generating) the terminal L2P table (e.g., a third-level L2P table). The memory device 100 may store an indication of whether the entry contains a pointer directly to the sequential physical data (e.g., the value of a flag) in one or more entries of the higher-level L2P table (e.g., the second-level L2P table), thereby enabling the memory device 100 to skip the terminal L2P table (e.g., the third-level L2P table), or a pointer to the terminal L2P table.

[0041] Although the discussion in this document focuses on a three-tier L2P table architecture, similar methods may be used in other instances of a multi-tier L2P table architecture, such as a two-tier L2P architecture, a four-tier L2P architecture, etc., wherein a terminal (e.g., last) L2P table may be eliminated (e.g., discarded, not generated, skipped) if the data pointed to by the table is stored sequentially.

[0042] Figure 2 An example of a NAND circuit 200 that supports compressed logical-to-physical mapping for sequentially stored data is illustrated according to an example of the present disclosure. The NAND circuit 200 may be an example of a portion of a memory device (eg, memory device 100). Figure 2Some elements contained in the drawings are labeled with reference numerals, while other corresponding elements are not labeled, but are the same or will be understood to be similar, in order to increase visibility and clarity of the features being depicted.

[0043] The NAND circuit 200 includes a plurality of flash memory cells 205 (which may be, for example, reference 200) connected in a NAND configuration. Figure 1 In a NAND memory configuration (referred to as a NAND memory), a plurality of flash memory cells 205 are connected in series with one another to form a string 210 of memory cells 205, wherein the drain of each flash memory cell 205 in the string 210 is coupled with the source of another flash memory cell 205 in the string. In some examples, the flash memory cells connected in a NAND configuration to form a NAND memory may be referred to as NAND memory cells.

[0044] Each string 210 of memory cells 205 can be associated with a corresponding digit line 215 (e.g., digit lines 215-a, 215-b) that is shared by the memory cells 205 in the string 210. Each memory cell 205 in a string 210 can be associated with a separate word line 230 (e.g., word lines 230-a, 230-i, 230-n) such that the number of word lines 230 can be equal to the number of memory cells 205 in the string 210.

[0045] NAND memory can be hierarchically organized into strings 210 including multiple memory cells 205, pages 255 including one or more memory cells 205 (e.g., memory cells 205 from multiple strings 210) connected to the same word line 230, blocks 260 including one or more pages 255, planes including one or more blocks 260, and dies including one or more planes. In some examples, a die can include one plane, or can include two planes that can operate in parallel. A page of memory can be, for example, 4kB of memory, 8kB of memory, or another size.

[0046] The NAND memory cell may be erased before it can be rewritten. In some examples, the NAND memory may be written and read at a page granularity level (e.g., by activating the corresponding word line 230), but may not be erased at a page granularity level. In some examples, the NAND memory may actually be erased at a higher granularity level (e.g., at a block granularity level). That is, a page 255 may be the smallest unit that can be written, and a block 260 may be the smallest unit that can be erased in some examples. Different memory devices may have different read / write / erase characteristics.

[0047] Each string 210 of memory cells 205 in the NAND circuit 200 is coupled with a drain-side select gate device (SGD) transistor 220 at one end of the string 210 and coupled with a source-side select gate device (SGS) transistor 235 at the other end of the string 210. The SGD transistor 220 and the SGS transistor 235 may be used to couple the string 210 of memory cells 205 to a digit line 215 and / or a source node 250 (e.g., source nodes 250-a, 250-b) by applying a voltage at a gate 245 of the SGD transistor 220 and / or a gate 240 of the SGS transistor 235, respectively.

[0048] During NAND memory operations, various voltage levels associated with source node 250, gate 240 of SGS transistor 235 associated with source node 250, word line 230, drain node 225, gate 245 of SGD transistor 220 associated with drain node 225, and digit line 215 may be applied to perform one or more operations (e.g., programming, erasing, or reading) on ​​at least some of the NAND memory cells in string 210.

[0049] In some examples, during a read operation, a positive voltage may be applied to the digit line 215 connected to the drain node 225, while the source node 250 may be connected to ground or a virtual ground (e.g., approximately 0V). For example, the voltage applied to the drain node 225 may be 1V. At the same time, the voltage applied to the gates 245 and 240 may increase above the threshold voltage of the one or more SGS transistors 235 associated with the source node 250 and the one or more SGD transistors 220 associated with the drain node 225, so that a channel associated with the string 210 may be electrically connected to the drain node 225 and the source node 250. The channel may be an electrical path through the memory cells 205 in the string 210 (e.g., through transistors in the memory cells 205) that may conduct current under certain operating conditions.

[0050] At the same time, a plurality of word lines 230 (e.g., word lines 230-a, 230-i, 230-n, or in some examples, all word lines 230) other than the selected word line (i.e., the word lines associated with the unselected cells in the string 210) may be connected to a voltage (e.g., VREAD) that is higher than the highest threshold voltage (VT) of the memory cells in the string 210. VREAD may cause all unselected memory cells in the string 210 to be "turned on" so that each unselected memory cell may maintain high conductivity in the channel associated therewith. In some examples, the word line 230 associated with the selected cell may be connected to a voltage Vtarget. Vtarget may be selected to be a value between the VT of the erased memory cells and the VT of the programmed memory cells in the string 210. When the selected memory cell exhibits an erased VT (e.g., Vtarget>VT of the selected memory cell), the selected memory cell 205 can be turned "on" in response to application of Vtarget, and thus allow current to flow from digit line 215 to source 250 in the channel of string 210. When the selected memory cell exhibits a programmed VT (e.g., so that Vtarget<VT of the selected memory cell), the selected memory cell can be turned "off" in response to Vtarget, and thus inhibit current from flowing from digit line 215 to source 250 in the channel of string 210. The amount of current (or lack thereof) can be determined by reference to Figure 1 The depicted sensing component 170 senses to read the stored information in the selected memory cells 205 within the string 210 .

[0051] Figure 3 3 is an example of a system 300 that supports compressed logical-to-physical mapping for sequentially stored data according to an example of the present disclosure. The system 300 includes a host device 305 coupled to a memory device 310.

[0052] The memory device 310 may be a Figure 1 Examples of the described memory device 100 are, for example, managed memory devices, storage devices, memory modules, or a mixture of storage devices and memory modules. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash storage devices (UFS) drives, and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and non-volatile dual in-line memory modules (NVDIMMs).

[0053] The memory device 310 may include a memory device controller 315 and one or more memory arrays 320 for storing data. Figure 11. The memory array 320 may include one or more NAND memory arrays, for example, or other types of memory arrays for reading and writing data from the host device 305; for example, data provided by the host device 305. The memory array 320 may include user data blocks 325 for storing user data.

[0054] The host device 305 may use the memory device 310 to store data in and read data from the one or more memory arrays 320. The host device 305 may be a computing device such as a desktop computer, a laptop computer, a network server, a mobile device, a vehicle (e.g., an airplane, a drone, a train, a car, or other transportation), a device with Internet of Things (IoT) capabilities, an embedded computer (e.g., an embedded computer included in a vehicle, industrial equipment, or a networked commercial device), or such computing devices that include memory and processing devices. Examples of physical host interfaces include, but are not limited to, a Serial Advanced Technology Attachment (SATA) interface, a Peripheral Component Interconnect Express (PCIe) interface, a Universal Serial Bus (USB) interface, a Fibre Channel, a Serial Attached SCSI (SAS), etc.

[0055] In some examples, memory device 310 may include, for example, SRAM 330 in addition to memory array 320 or other types of memory that may be used by memory device 310 for internal storage or computation. In some examples, SRAM 330 may be included within or coupled with memory device controller 315. In some examples, memory device 310 may store (e.g., write) a first-level L2P table (e.g., a set of entries) in SRAM 330.

[0056] In some examples, the memory device 310 may include a system table block 335, which may be used, for example, to store information related to the status of blocks of the memory array 320. In some examples, the system table block 335 may be included within the memory array 320. The system table block 335 may include non-volatile memory, such as NAND memory, DRAM, ferroelectric memory, other types of memory, or any combination thereof. In some examples, the memory device 310 may store one or more second-level L2P tables and / or third-level L2P tables (or other levels of L2P tables that may be referred to as sets of entries) in the system table block 335.

[0057] In some examples, SRAM 330 and system table block 335 may be coupled to each other, and SRAM 330 and / or system table block 335 may be coupled to memory device controller 315 .

[0058] In some examples, the memory device 310 may maintain one or more sets of entries (e.g., L2P lookup tables) for mapping LBAs generated by the host device 305 to physical addresses (e.g., page addresses) of the memory array 320. Such sets of entries may be generated based on receiving one or more write commands from the host device 305 that each include an LBA for writing data. In some examples, the L2P table may include a first-level L2P table with entries pointing to a second-level L2P table, which in turn may include entries pointing to a third-level (e.g., terminal) L2P table or directly to data stored sequentially in the memory array 320.

[0059] In some examples, the entries of the terminal L2P table may be ordered sequentially by LBA index. For example, the first entry in the terminal L2P table (for example) may include a first physical address corresponding to LBAN (thus mapping LBA N to the first physical address), the second (consecutive) entry in the set of entries includes a second physical address corresponding to LBA N+1, the third entry includes a third physical address corresponding to LBA N+2, etc. In some examples, if the entire terminal L2P table consists of sequential physical addresses (e.g., corresponding to sequentially indexed LBAs of the table), the memory device controller 315 may store entries in a higher-level L2P table that include the first physical address (e.g., the first physical address corresponding to the first LBA (LBA N) of the table) together with an indication that the entry points directly to data in the memory array 320 rather than to the terminal L2P table in the system table block 335.

[0060] The host device 305 includes a host controller interface 340. The host controller interface 340 may provide an interface for passing control, address, data, and other signals between the host device 305 and the memory device 310. The host device 305 may transmit memory access commands (e.g., read or write commands) to the memory device 310 using the host controller interface 340.

[0061] The memory device controller 315 may receive signals from the host device 305 via the host controller interface 340, and may cause the memory device 310 to perform certain operations in response to receiving such signals. For example, the memory device controller 315 may receive a read or write command from the host device 305, and in response, may cause the memory device 310 to read data or write data to the memory array 320 based on the received command.

[0062] In some examples, the memory device controller 315 may access an entry in a first-level L2P table in the SRAM 330 based on an LBA received in a read command from the host device 305 during a read operation. The entry in the first-level L2P table may point to a page of a system block 335 that includes a second-level L2P table associated with the LBA received in the read command. The memory device controller 315 may access an entry in the second-level L2P table based on the LBA. The entry in the second-level L2P table may include a pointer to a physical address of the memory array 320 (e.g., for accessing data within sequentially stored data in the user data block 325) or a pointer to a third-level (e.g., terminal) L2P table in the system table block 335. The entry in the second-level L2P table may also include a value of a flag indicating whether the entry points to data in the user data block 325 or to a third-level L2P table in the system table block 335.

[0063] If the entry in the second-level L2P table indicates that the entry points to sequential data in the user data block 325, the memory device controller 315 may read at least some (if not all) of the sequential data (e.g., one or more pages of data) in the user data block 325 based on the starting physical address, and may transmit the data to the host device 305.

[0064] If the entry in the second-level L2P table indicates that the entry points to the third-level (terminal) L2P table in the system table block 335, the memory device controller 315 may read the entry of the third-level L2P table in the system table block 335 to identify the physical address of the data in the user data block 325. The memory device controller 315 may read the data (e.g., a data page) in the user data block 325 based on the physical address, and may transmit the data to the host device 305.

[0065] Figure 4 An operational flow 400 is illustrated for reading data from a memory array using a hierarchical L2P table (e.g., L2P tables 405, 415, 430) that supports a compressed logical-to-physical mapping for sequentially stored data according to examples disclosed herein. In some examples, the operational flow 400 may be performed by a memory device (e.g., memory device 310) in response to (e.g., based on) receiving a read command (e.g., from a host device 305) that includes or involves LBAs, and may include or involve mapping the LBAs to physical addresses in user data blocks 425 of the memory device. The operational flow 400 may illustrate an example of a process for reading data that bypasses a terminal (e.g., third level) L2P table.

[0066] Operation flow 400 may be used as a reference. Figure 3Purpose of system table block 410 of example of system table block 335 described. System table block 410 may be included in or coupled to an SRAM of a memory device (e.g., SRAM 330). System table block 410 may be organized into multiple dies (e.g., die 0 and die 1), each of which includes one or more planes (e.g., plane 0, plane 1). Each plane may include multiple pages (e.g., pages 0 to 9). In some examples, each square 440 (e.g., square 440-a) of system table block 410 may represent a page or a subset of a page. For example, if the pages of system table block 410 are 16kB, each square 440 (e.g., including square 440-a) may represent a 4kB subset of a page.

[0067] The operation flow 400 is further described as follows. Figure 3 The purpose of user data block 425 of the example of user data block 325 described. User data block 425 may be included in a memory array (e.g., memory array 320) of a memory device. Similar to system table block 410, user data block 425 may be organized into multiple dies (e.g., die 0 and die 1), each of which includes one or more planes (e.g., plane 0, plane 1). Each plane may include multiple pages (e.g., pages 0-9). Each square 440 of user data block 425 (e.g., including square 440-b) may represent a page or a subset of a page.

[0068] In some examples, the first-level L2P table 405 may be stored in the system table block 410. In response to receiving a read command including an LBA, the memory device may read (e.g., retrieve, lookup) an entry 405-a in the first-level L2P table 405 based on the LBA. In some examples, the entry 405-a may be associated with a group of LBAs including the LBA received in the read command. The entry 405-a may include a physical address of a page of the system table block 410, which contains (e.g., stores) the second-level L2P table 415. In the operation flow 400, for example, the entry 405-a may include a physical address pointing to page 5 (or a subset of page 5) of plane 0 of die 0, which may contain the second-level L2P table 415.

[0069] The memory device may then read entry 415-a in the second-level L2P table 415 based on the LBA. Entry 415-a may include a physical address of a page of user data block 425 that corresponds to a first page of multiple pages of sequentially stored data. The multiple pages of sequentially stored data may include a page of data requested by the host device; for example, a page of data indicated by the LBA in the read command.

[0070] In the example of operational flow 400, entry 415-a may be a four-byte entry including a physical address pointing to page 4 (or a subset of page 4) of plane 0 of die 1, where page 4 may be the first of multiple pages including sequentially stored data. (Depending on various characteristics of the memory device, the size of the entries of the L2P table may vary.)

[0071] In some examples, entry 415-a may include flag 420, which may be set to a first value indicating that the physical address in entry 415-a directly points to a data page in user data block 425, or may be set to a second value indicating that the physical address in entry 415-a points to a third-level L2P table in system table block 410. In operation flow 400, the value of the flag may be the first value indicating that the physical address of entry 415-a directly points to a data page in user data block 425. In some examples, the value of flag 420 may occupy one or more bits in entry 415-a, such as bits in the least significant byte (e.g., byte 3).

[0072] If the LBA included in the read command corresponds to the starting page 435 (e.g., the first page, the initial page) of sequentially stored data (e.g., the page pointed to by the physical address in entry 415-a), the memory device can read the data from the starting page 435 and transmit the data to the host device.

[0073] If the LBA included in the read command corresponds to a different page of sequentially stored data (e.g., a page different from the starting page), the memory device may determine (e.g., calculate) a second physical address corresponding to the different page, such as by applying an offset to the physical address of entry 415-a to determine the second physical address. The memory device may read data from the different page indicated by the second physical address based on determining (e.g., calculating) the second physical address corresponding to the different page. The memory device may transmit the data to the host device.

[0074] Figure 5 An operational flow 500 is illustrated for reading data from a memory array using a hierarchical L2P table (e.g., L2P tables 405, 415, 430) that supports a compressed logical-to-physical mapping for sequentially stored data according to examples disclosed herein. In some examples, the operational flow 500 may be performed by a memory device (e.g., memory device 310) based on receiving a read command including an LBA (e.g., from a host device 305), and may include mapping the LBA to a physical address in a user data block 425 of the memory device. The operational flow 500 may be similar to the operational flow 400, but may illustrate an example of a process for reading data that does not bypass a terminal (e.g., third level) L2P table.

[0075] In response to receiving a read command that includes a different LBA (e.g., a different LBA than that described with reference to operational flow 400). In operational flow 500, the different LBA may be included within a group of LBAs associated with entry 405-a. Thus, the memory device may read entry 405-a in first-level L2P table 405 based on the different LBA. As discussed with reference to operational flow 400, entry 405-a may include a physical address of a page of system table block 410 containing second-level L2P table 415. In various examples, the different LBA may be within a different group of LBAs and may therefore be associated with a different entry of first-level L2P table 405 that points to a different second-level L2P table than second-level L2P table 415.

[0076] The memory device may read entry 415-b in the second-level L2P table 415 based on the LBA. Entry 415-b may be associated with a group of LBAs that include different LBAs and may include a physical address of a page of a system table block 410 that contains a third-level L2P table 430 for mapping the group of LBAs to physical addresses. In operation flow 500, for example, entry 415-b may include a physical address pointing to page 8 (or a subset of page 8) of plane 0 of die 1, which may contain the third-level L2P table 430.

[0077] In the example of operation flow 500, similar to entry 415-a of operation flow 400, entry 415-b may be a four-byte entry including flag 420, the value of which indicates whether the physical address in entry 415-b directly points to a data page in user data block 425 or to a third-level L2P table in system table block 410. In operation flow 500, the value of the flag may indicate that the physical address of entry 415-b points to the third-level L2P table.

[0078] The memory device may read entry 430-a in the third-level L2P table 430 based on the LBA and based on a value flag indicating that the physical address points to the third-level L2P table in the system table block 410; for example, based on the LBA and in response to determining that the value of the flag indicates that the physical address points to the third-level L2P table. Entry 430-a may include data requested by the host device; for example, a physical address of a page of the user data block 425 of data associated with the LBA included in the read command. The memory device may read the data at the page of the user data block 425 pointed to by the physical address of the entry 430-a, and transmit the data to the host device.

[0079] Therefore, operation flow 500 may incur additional latency for reading data requested by the host device relative to operation flow 400 because in operation flow 500, the memory device may traverse (e.g., read entries from) L2P tables at all three levels, while in operation flow 400, the memory device may skip the terminal L2P table.

[0080] Figure 6 An example of a process 600 for building or updating a built-in L2P table supporting a compressed logical-to-physical mapping for sequentially stored data according to examples disclosed herein is illustrated. The process 600 may be used to build or update an intermediate L2P table (e.g., a second-level L2P table) that may include entries that directly point to sequentially stored data and other entries that point to a terminal L2P table.

[0081] At 605, the memory device may initiate a process for building or updating one or more L2P tables in response to (eg, based on) receiving a write command, such as from a host device. The write command may include an LBA associated with writing data to a user data block of the memory device.

[0082] In response to receiving the write command, the memory device may determine whether sequential data flow is on at 610. For example, the memory device may determine whether the LBAs included in the write command received at 605 are sequential (have sequential indexes, are continuous, are contiguous) with the LBAs included in a previous write command (e.g., a previous write command that was most recently received), or whether the physical addresses corresponding to the LBAs included in the write command are continuous with the physical addresses corresponding to the LBAs of the previous write command, or whether other conditions or relationships exist, or any combination thereof.

[0083] In response to determining that the stream is not open, the memory device may determine whether the LBA included in the write command corresponds to the first LBA of the terminal L2P table (e.g., the third-level L2P table) at 615. That is, in the event that a subsequent write command causes the memory device to store data sequentially, the memory device may determine whether a new stream can be initialized.

[0084] In response to determining that the LBA included in the write command does not correspond to the first LBA of the terminal L2P table, at 620, the memory device may store (e.g., write, save) one or more physical addresses pointing to the data written in response to receiving the write command in the L2P table, and the current process may end at 650. In some examples, the L2P table may be a terminal table (e.g., if step 620 is performed after determining at 610 that the stream is not to be opened) or a higher-level table, such as a second-level table (e.g., if step 620 is performed after the stream is closed at 635, as described below).

[0085] In response to determining that the LBA included in the write command does correspond to the first LBA of the terminal L2P table, the memory device may initialize the stream at 625. For example, the memory device may store an indication that a stream associated with the L2P table has been opened or that data has been written at a physical address corresponding to the first entry of the terminal L2P table. In some examples, the memory device may save an indication of the number of entries in the L2P table that correspond to the pages that have been stored sequentially. In some examples, the memory device may store the physical address in the first entry of the terminal L2P table.

[0086] Returning to decision point 610, in response to determining that the stream is open (e.g., at least the first entry of the terminal L2P table has been written to the terminal L2P table or data has been written to the user data block at the physical address corresponding to the first entry of the terminal table), the memory device may determine whether the stream is continuing (e.g., associated with one or more previous processes or operations, such as access operations) at 630. For example, the memory device may determine whether the LBA in the write command received at 605 is associated with storing data sequentially (e.g., at consecutive physical addresses) relative to data written in response to receiving a previous write command in the stream.

[0087] In response to determining that the flow is not continuing, the memory device may close the flow at 635. For example, the memory device may update an indication associated with the L2P table that the flow was open to indicate that the flow is now closed. The memory device may continue to 615 and perform other steps of flow 600 as previously discussed.

[0088] In response to determining that the flow continues, the memory device may update the flow at 640. For example, the memory device may update (eg, increment) an indication of the number of entries in the L2P table that correspond to pages that have been sequentially stored.

[0089] At 645, the memory device may determine whether the terminal L2P table has been populated with sequentially stored physical addresses.

[0090] In response to determining that the terminal L2P table has not been populated with sequentially stored physical addresses, the memory device may end the current process at 650 .

[0091] In response to determining that the terminal L2P table has been populated with sequentially stored physical addresses, the memory device may close the stream at 635, as previously described. In this case, the memory device may save the physical address of the first LBA of the terminal table in a higher level L2P table, such as a second level L2P table, at 620.

[0092] In some instances, while the stream is open, the memory device may continue to store entries (physical addresses) in the terminal L2P table each time the memory device stores data at a sequential physical address, and may subsequently discard (e.g., erase, overwrite) the terminal L2P table if the memory device determines that the terminal L2P table is full of sequentially stored physical addresses.

[0093] Thus, flow 600 describes a process for building or maintaining an L2P table that may enable a memory device to skip accessing (or maintaining) a terminal L2P table when sequentially storing data.

[0094] In some examples, a memory device may receive two or more interleaved streams of write commands, wherein each stream includes write commands that may include consecutive logical block addresses that may cause the memory device to write data for each stream to a corresponding set of consecutive physical addresses. In this example, the memory device may identify different blocks of memory at which to write data for each stream so that multiple streams can be associated with corresponding entries in a second-level L2P table. For example, the memory device may write a first data stream (e.g., associated with a first stream of write commands) at consecutive physical addresses of a first block of memory, and may write a second data stream (e.g., associated with a second stream of write commands) at consecutive physical addresses of a second block of memory (e.g., different from the first block of memory). The memory device may store the first entry in the L2P table including the starting physical address of the first stream, and may store the second entry in the L2P table including the starting physical address of the second stream.

[0095] Figure 7 A block diagram 700 is shown of a memory device that supports compressed logical to physical mapping for sequentially stored data according to examples disclosed herein. The memory device 705 may be a memory device such as that described in reference Figures 1 to 5 An example of aspects of the described memory device. The memory device 705 may include a command component 710, a position determination component 715, a data read component 720, a data transmit component 725, a data write component 730, and a table management component 735. Each of these modules can communicate with each other directly or indirectly (e.g., via one or more buses).

[0096] The command component 710 can receive, at a memory device from a host device, a read command including a first logical block address associated with a location of at least a portion of data stored in the memory device, wherein the data spans a set of consecutive physical addresses.

[0097] In some examples, command component 710 may receive, at a memory device, from a host device, a set of write commands for writing data to the memory device, the set of write commands comprising: a first write command comprising a first logical block address corresponding to a first entry of a number of entries for mapping a set of consecutive logical block addresses to a corresponding set of physical addresses, and a set of remaining write commands in the set of write commands, each comprising a corresponding consecutive logical block address.

[0098] In some examples, command component 710 can receive, at the memory device from the host device, a second read command including a second logical block address associated with second data stored in the memory device.

[0099] In some examples, command component 710 may receive a set of write commands from a host device prior to receiving a read command, a first write command in the set of write commands including a first logical block address corresponding to a first physical address, wherein the set of write commands is associated with writing data to a set of consecutive physical addresses.

[0100] In some examples, the command component 710 may receive, at the memory device, from the host device a read command including a third logical block address of the consecutive logical block addresses after storing the first physical address and the first value of the flag in the first entry.

[0101] In some examples, command component 710 may receive, at a memory device, from a host device, a second set of write commands for writing second data to the memory device, the second set of write commands being interleaved with the set of write commands and including: a second write command including a third logical block address corresponding to a first entry of a second number of entries of a corresponding second set for mapping a second set of consecutive logical block addresses to physical addresses, and a second set of remaining write commands in the second set of write commands, each including a second corresponding consecutive logical block address.

[0102] In some examples, the first logical block address corresponds to the first physical address, and each of the respective consecutive logical block addresses corresponds to a respective consecutive physical address in the set of consecutive physical addresses.

[0103] The location determination component 715 can determine, based on the first logical block address, memory locations of a first set of entries for mapping a first set of logical block addresses including the first logical block address to a corresponding first set of physical addresses.

[0104] In some examples, the location determination component 715 can determine the second physical address based on the first physical address and the first value of the flag and based on identifying an offset relative to the first physical address.

[0105] In some examples, the location determination component 715 can determine, based on the first logical block address, a third physical address indicating a location of the first set of entries.

[0106] In some examples, the location determination component 715 may determine memory locations of a first set of entries for mapping a first set of logical block addresses to a corresponding first set of physical addresses based on the second logical block address, wherein the first set of logical block addresses includes the second logical block address.

[0107] In some examples, the location determination component 715 can identify a second block different from the first block based on receiving the second set of write commands.

[0108] In some examples, the third physical address indicates a location of a first page of a first type of memory of the memory device, and the set of consecutive physical addresses indicates a location of a set of pages of a second type of memory in the memory device.

[0109] In some examples, the first type of memory includes SRAM of the memory device and the second type of memory includes NAND memory of the memory device.

[0110] The data read component 720 can read at least a portion of the data from a second physical address in the set of consecutive physical addresses based on the first physical address and the first value of the flag.

[0111] In some examples, the data read component 720 can read the second data from the fourth physical address based on identifying the first entry in the second set of entries.

[0112] In some examples, the data read component 720 can read the second portion of the data from the second physical address based on identifying the second physical address.

[0113] The data transmission component 725 can transmit data to the host device.

[0114] In some examples, data transmission component 725 may transmit the second data to the host device.

[0115] In some examples, data transmission component 725 may transmit the second portion of the data to the host device.

[0116] The data write component 730 can store data in the memory device at a set of consecutive physical addresses starting from the first physical address based on receiving the set of write commands.

[0117] In some examples, the data write component 730 can store data at a set of consecutive physical addresses based on receiving a set of write commands.

[0118] In some examples, the data write component 730 may store the second data in the memory device at a second set of consecutive physical addresses of the second block starting at the fourth physical address.

[0119] The table management component 735 can read a first entry in the first set of entries based on the first logical block address, the first entry including a first physical address in the set of consecutive physical addresses and a first value of the flag.

[0120] In some examples, the table management component 735 can determine whether the number of logical block addresses including the first logical block address and the corresponding logical block address matches the number of entries.

[0121] In some instances, the table management component 735 may store the first physical address and the first value of the flag in a first entry in a set of entries that map a set of logical block addresses that includes a certain number of logical block addresses to a corresponding set of physical block addresses that includes a set of consecutive physical addresses based on determining that the number of logical block addresses matches the number of entries.

[0122] In some examples, the table management component 735 may read a second entry in the first set of entries based on determining a memory location of the first set of entries and based on a second logical block address, the second entry including a second physical address and a second value of the flag, wherein the second physical address indicates a location of the second set of entries for mapping a subset of the first set of logical block addresses including the second logical block address to a corresponding subset of the first set of physical addresses.

[0123] In some examples, the table management component 735 can identify a first entry in the second set of entries based on a second entry in the first set of entries, the first entry in the second set of entries including a fourth physical address indicating a location of the second data.

[0124] In some examples, table management component 735 can store a first value of the flag and a first physical address in the set of consecutive physical addresses in a first entry in the first set of entries based on writing data to the set of consecutive physical addresses prior to receiving the read command.

[0125] In some examples, the table management component 735 may store, for each write command in the set of write commands, a corresponding entry in a second set of entries including a number of entries, the second set of entries being used to map a number of logical block addresses to a set of contiguous physical addresses.

[0126] In some examples, the table management component 735 can discard the second set of entries based on determining that the number of logical block addresses matches the number of entries.

[0127] In some examples, the table management component 735 can read a first entry in the set of entries to read the first physical address and the first value of the flag based on receiving a read command including the third logical block address.

[0128] In some examples, the table management component 735 can identify a second physical address in the set of consecutive physical addresses based on reading the first entry.

[0129] In some examples, the table management component 735 can determine whether a second number of logical block addresses including the third logical block address and the second corresponding logical block address matches the second number of entries.

[0130] In some instances, the table management component 735 may store the fourth physical address and the first value of the flag in a first entry in a second set of entries for mapping a second set of logical block addresses including a second number of logical block addresses to a corresponding second set of physical block addresses including a second set of consecutive physical addresses based on determining that the second number of logical block addresses matches the second number of entries.

[0131] In some examples, the first physical address corresponds to a starting page in a set of pages that corresponds to a set of consecutive physical addresses.

[0132] In some examples, the first physical address and the second physical address are the same physical address.

[0133] In some examples, the first value of the flag indicates that the first physical address includes a location of at least a portion of the data.

[0134] Figure 8 A flowchart illustrating one or more methods 800 for supporting compressed logical to physical mapping for sequentially stored data according to aspects of the present disclosure is shown. The operations of the method 800 may be implemented by a memory device or components thereof as described herein. For example, the operations of the method 800 may be implemented by a memory device or components thereof as described in reference to Figure 7 The memory device described herein performs. In some examples, the memory device may execute a set of instructions to control the functional elements of the memory device to perform the described functions. Additionally or alternatively, the memory device may use dedicated hardware to perform aspects of the described functions.

[0135] At 805, a memory device may receive, at the memory device, from a host device, a read command including a first logical block address associated with a location of at least a portion of data stored in the memory device, wherein the data spans a set of consecutive physical addresses. The operations of 805 may be performed according to the methods described herein. In some examples, the read command may be performed as described in reference to Figure 7 Aspects of the operations of command component execution 805 are described.

[0136] At 810, the memory device may determine, based on the first logical block address, a memory location for mapping a first set of logical block addresses including the first logical block address to a first set of entries of a corresponding first set of physical addresses. The operations of 810 may be performed according to the methods described herein. In some examples, the memory device may be configured as described in reference to Figure 7 The depicted location determination component performs aspects of the operations of 810 .

[0137] At 815, the memory device may read a first entry in the first set of entries based on the first logical block address, the first entry including a first physical address in the set of consecutive physical addresses and a first value of the flag. The operation of 815 may be performed according to the methods described herein. In some examples, the first entry may be read by a processor as described in reference to FIG. Figure 7 Aspects of the operations of table management component execution 815 are described.

[0138] At 820, the memory device may read at least a portion of the data from a second physical address in the set of consecutive physical addresses based on the first physical address and the first value of the flag. The operation of 820 may be performed according to the methods described herein. In some examples, the memory device may be configured as described in reference to Figure 7 The described data reading component performs aspects of the operation of 820 .

[0139] At 825, the memory device may transmit the data to the host device. The operation of 825 may be performed according to the methods described herein. In some examples, the memory device may be transmitted as described in reference to Figure 7 Aspects of the operations of the data transmission component 825 are described.

[0140] In some examples, an apparatus as described herein may perform one or more methods, such as method 800. The apparatus may include features, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for: receiving, at a memory device from a host device, a read command including a first logical block address associated with a location of at least a portion of data stored in the memory device, wherein the data spans a set of consecutive physical addresses; determining, based on the first logical block address, a memory location for mapping a first set of logical block addresses including the first logical block address to a first set of entries of a corresponding first set of physical addresses; reading, based on the first logical block address, a first entry in the first set of entries, the first entry including a first physical address in the first set of consecutive physical addresses and a first value of a flag; reading, based on the first physical address and the first value of the flag, at least a portion of the data from a second physical address in the set of consecutive physical addresses; and transmitting the data to the host device.

[0141] Some examples of method 800 and apparatus described herein may further include operations, features, means, or instructions for determining a second physical address based on the first physical address and the first value of the flag and based on identifying an offset relative to the first physical address.

[0142] In some examples of the method 800 and apparatus described herein, the first physical address corresponds to a starting page of a set of pages corresponding to a set of consecutive physical addresses.

[0143] In some examples of the method 800 and apparatus described herein, the first physical address and the second physical address may be the same physical address.

[0144] In some examples of method 800 and apparatus described herein, determining the memory location of the first set of entries may include operations, features, means, or instructions for determining a third physical address indicating the location of the first set of entries based on the first logical block address.

[0145] In some examples of method 800 and apparatus described herein, the third physical address indicates a location of a first page of a first type of memory of the memory device, and the set of consecutive physical addresses indicates a location of a set of pages of a second type of memory in the memory device.

[0146] In some examples of the method 800 and apparatus described herein, the first type of memory includes SRAM of the memory device and the second type of memory includes NAND memory of the memory device.

[0147] Some examples of method 800 and apparatus described herein may further include operations, features, means, or instructions for: receiving, at a memory device, from a host device, a second read command including a second logical block address associated with second data stored in the memory device; determining, based on the second logical block address, a memory location of a first set of entries for mapping a first set of logical block addresses to a corresponding first set of physical addresses, wherein the first set of logical block addresses includes the second logical block address; reading a second entry in the first set of entries based on determining the memory location of the first set of entries and based on the second logical block address, the second entry including the second physical address and a second value of a flag, wherein the second physical address indicates a location of a second set of entries for mapping a subset of the first set of logical block addresses including the second logical block address to a corresponding subset of the first set of physical addresses; identifying, based on the second entry in the first set of entries, a first entry in the second set of entries, the first entry in the second set of entries including a fourth physical address indicating a location of the second data; reading the second data from the fourth physical address based on identifying the first entry in the second set of entries; and transmitting the second data to the host device.

[0148] Some instances of method 800 and the apparatus described herein may further include operations, features, components, or instructions for receiving a set of write commands from a host device prior to receiving a read command, a first write command in the set of write commands including a first logical block address corresponding to a first physical address, wherein the set of write commands may be associated with writing data to a set of consecutive physical addresses and storing the data at the set of consecutive physical addresses based on receiving the set of write commands.

[0149] Some instances of method 800 and the devices described herein may further include operations, features, components, or instructions for storing a first value of a flag for a first entry in a first set of entries and a first physical address in a set of consecutive physical addresses based on writing data to the set of consecutive physical addresses prior to receiving a read command.

[0150] In some examples of the method 800 and apparatus described herein, the first value of the flag indicates that the first physical address includes a location of at least a portion of the data.

[0151] Fig. 9 A flowchart illustrating one or more methods 900 for supporting compressed logical to physical mapping for sequentially stored data according to aspects of the present disclosure is shown. The operations of the method 900 may be implemented by a memory device or components thereof as described herein. For example, the operations of the method 900 may be implemented by a memory device or components thereof as described in reference to Figure 7The memory device described herein performs. In some examples, the memory device may execute a set of instructions to control the functional elements of the memory device to perform the described functions. Additionally or alternatively, the memory device may use dedicated hardware to perform aspects of the described functions.

[0152] At 905, the memory device may receive at the memory device from the host device a set of write commands for writing data to the memory device, the set of write commands comprising. The operations of 905 may be performed according to the methods described herein. In some examples, the instructions may be written as described in reference to Figure 7 Aspects of the operations of command component execution 905 are described.

[0153] At 910, the memory device may store data in the memory device at a set of consecutive physical addresses starting from a first physical address based on receiving a set of write commands. The operations of 910 may be performed according to the methods described herein. In some examples, the operations may be performed as described in reference to Figure 7 The described data writing component performs aspects of the operation of 910 .

[0154] At 915, the memory device may determine whether the number of logical block addresses including the first logical block address and the corresponding logical block address matches the number of entries. The operation of 915 may be performed according to the methods described herein. In some examples, the number of logical block addresses may be determined by referring to Figure 7 Aspects of the operations of table management component execution 915 are described.

[0155] At 920, the memory device may store the first physical address and the first value of the flag in a first entry in a set of entries for mapping a set of logical block addresses including a certain number of logical block addresses to a corresponding set of physical block addresses including a set of consecutive physical addresses based on determining that the number of logical block addresses matches the number of entries. The operation of 920 may be performed according to the methods described herein. In some examples, the flag may be stored as described in reference to Figure 7 The described table management component performs aspects of the operation of 920 .

[0156] In some examples, an apparatus as described herein may perform one or more methods, such as method 900. The apparatus may include features, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for: receiving, at a memory device, from a host device, a set of write commands for writing data to the memory device, the set of write commands including: a first write command including a first logical block address corresponding to a first entry in a number of entries for mapping a plurality of consecutive logical block addresses to a corresponding plurality of physical addresses, and a plurality of remaining write commands in a plurality of write commands, each including a respective consecutive logical block address; based on receiving the set of write commands, storing data in the memory device at a set of consecutive physical addresses starting with the first physical address; determining whether a number of logical block addresses including the first logical block address and the respective logical block address matches a number of entries; and based on determining that the number of logical block addresses matches the number of entries, storing the first physical address and a first value of a flag in a first entry in a set of entries for mapping a set of logical block addresses including the number of logical block addresses to a corresponding set of physical block addresses including the set of consecutive physical addresses.

[0157] In some examples of the method 900 and devices described herein, the first logical block address corresponds to the first physical address, and each of the respective consecutive logical block addresses corresponds to a respective consecutive physical address in a set of consecutive physical addresses.

[0158] Some instances of method 900 and the devices described herein may further include operations, features, components, or instructions for: for each write command in a set of write commands, storing a corresponding entry in a second set of entries comprising a certain number of entries, the second set of entries being used to map a certain number of logical block addresses to a set of contiguous physical addresses; and discarding the second set of entries based on determining that the number of logical block addresses matches the number of entries.

[0159] Some examples of method 900 and the apparatus described herein may further include operations, features, components, or instructions for: receiving a read command at a memory device from a host device after storing the first physical address and the first value of the flag in the first entry, the read command including a third logical block address among the consecutive logical block addresses; reading a first entry in the set of entries to read the first physical address and the first value of the flag based on receiving the read command including the third logical block address; identifying a second physical address in the set of consecutive physical addresses based on reading the first entry; reading a second portion of the data from the second physical address based on identifying the second physical address; and transmitting the second portion of the data to the host device.

[0160] Method 900 and some examples of the apparatus described herein may further include operations, features, components, or instructions for: receiving, at a memory device, from a host device, a second set of write commands for writing second data to the memory device, the second set of write commands being interleaved with the set of write commands and including: a second write command including a third logical block address corresponding to a first entry in a second number of entries for mapping a second plurality of consecutive logical block addresses to a corresponding second plurality of physical addresses, and a second plurality of remaining write commands in the second plurality of write commands, each including a second corresponding consecutive logical block address; identifying a second block different from the first block based on receiving the second set of write commands; storing the second data in the memory device at a second set of consecutive physical addresses of the second block starting at a fourth physical address; determining whether a second number of logical block addresses including the third logical block address and the second corresponding logical block address match a second number of entries; and storing the fourth physical address and a first value of a flag in a first entry in a second set of entries for mapping a second set of logical block addresses including the second number of logical block addresses to a corresponding second set of physical block addresses of the second set of consecutive physical addresses based on determining that the second number of logical block addresses matches the second number of entries.

[0161] It should be noted that the methods described herein are possible embodiments, and that the operations and steps may be rearranged or modified, and other embodiments are possible. In addition, portions from two or more methods may be combined.

[0162] The information and signals described herein may be represented using any of a variety of different techniques and technologies. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. Some diagrams may illustrate a signal as a single signal; however, one skilled in the art will understand that the signal may represent a signal bus, where the bus may have a variety of bit widths.

[0163] The devices including memory arrays discussed herein may be formed on a semiconductor substrate, such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, etc. In some examples, the substrate is a semiconductor wafer. In other cases, the substrate may be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOS), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or a sub-region of the substrate may be controlled by doping using various chemical species including, but not limited to, phosphorus, boron, or arsenic. Doping may be performed during the initial formation or growth of the substrate, by ion implantation, or by any other doping method.

[0164] The switch assembly or transistor discussed herein may represent a field effect transistor (FET) and include a three-terminal device including a source, a drain, and a gate. The terminals may be connected to other electronic components by conductive materials such as metals. The source and drain may be conductive and may include heavily doped (e.g., degenerate) semiconductor regions. The source and drain may be separated by a lightly doped semiconductor region or channel. If the channel is n-type (i.e., most of the carriers are electrons), the FET may be referred to as an n-type FET. If the channel is p-type (i.e., most of the carriers are holes), the FET may be referred to as a p-type FET. The channel may be terminated by an insulating gate oxide. Channel conductivity may be controlled by applying a voltage to the gate. For example, applying a positive voltage or a negative voltage to an n-type FET or a p-type FET, respectively, may cause the channel to become conductive. When a voltage greater than or equal to the threshold voltage of the transistor is applied to the transistor gate, the transistor may be "turned on" or "activated". When a voltage less than the threshold voltage of the transistor is applied to the transistor gate, the transistor may be "turned off" or "deactivated".

[0165] The description set forth herein in conjunction with the accompanying drawings describes example configurations and does not represent all examples that may be implemented or within the scope of the claims. The term "exemplary" as used herein means "serving as an example, instance, or illustration" and is not "preferred to" or "superior to other examples". The specific implementation includes specific details that provide an understanding of the described technology. However, these technologies may be practiced without these specific details. In some cases, well-known structures and devices are shown in block diagram form to avoid obscuring the concepts of the described examples.

[0166] In the drawings, similar components or features may have the same reference label. In addition, various components of the same type may be distinguished by following the reference label with a dash and a second label that distinguishes among the similar components. If only the first reference label is used in the specification, the description may apply to any of the similar components having the same first reference label regardless of the second reference label.

[0167] The information and signals described herein may be represented using any of a variety of different techniques and technologies. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, optical fields or optical particles, or any combination thereof.

[0168] The various illustrative blocks and modules described in conjunction with the present disclosure herein may be implemented or executed with a general purpose processor, a DSP, an ASIC, an FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0169] The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions may be stored as one or more instructions or codes on a computer-readable medium or transmitted via a computer-readable medium. Other examples and embodiments are within the scope of the present disclosure and the appended claims. For example, due to the nature of software, the functions described above may be implemented using software, hardware, firmware, hard wiring, or any combination of these executed by a processor. The features of the implementation functions may also be physically located at various locations, including being distributed so that the various parts of the functions are implemented at different physical locations. In addition, as used herein (included in the claims), as used in a list of items (e.g., a list of items beginning with a phrase such as "at least one of" or "one or more of"), "or" indicates an inclusive list, such that a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). In addition, as used herein, the phrase "based on" should not be understood to refer to a closed conditional set. For example, without departing from the scope of the present disclosure, an exemplary step described as "based on condition A" may be based on both condition A and condition B. In other words, as used herein, the phrase "based on" should be equally interpreted as the phrase "based at least in part on."

[0170] Computer-readable media include both non-transitory computer storage media and communication media including any media that facilitates the transfer of computer programs from one place to another. Non-transitory storage media can be any available media that can be accessed by a general or special computer. By way of example and not limitation, non-transitory computer-readable media may include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), compact disk (CD) ROM or other optical disk storage device, magnetic disk storage device or other magnetic storage device, or can be used to carry or store the desired program code components in the form of instructions or data structures and can be accessed by a general or special computer or a general or special processor. Any other non-transitory media. In addition, any connection is appropriately referred to as a computer-readable medium. For example, if a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL) or wireless technologies such as infrared, radio and microwaves are used to transmit software from a website, server or other remote source, the coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL) or wireless technologies such as infrared, radio and microwaves are included in the definition of media. Disk and disc, as used herein, includes CD, laser disc, optical disc, digital versatile disc (DVD), floppy disk and Blu-ray disc, where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above are also included within the scope of computer-readable media.

[0171] The description herein is provided to enable those skilled in the art to make or use the present disclosure. Various modifications of the present disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the scope of the present disclosure. Therefore, the present disclosure is not limited to the examples and designs described herein, but is given the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A memory device, comprising: Memory array; and a control component coupled to the memory array and configured to cause the memory device to: receiving a read command from a host device, the read command comprising a first logical block address associated with a location of at least a portion of data stored in the memory device, wherein the data spans a plurality of consecutive physical addresses; determining, based at least in part on the first logical block address, memory locations of a first plurality of entries for mapping a first plurality of logical block addresses including the first logical block address to a corresponding first plurality of physical addresses; reading a first entry of the first plurality of entries based at least in part on the first logical block address, the first entry comprising a first physical address of the plurality of consecutive physical addresses and a first value of a flag, wherein the first value of the flag indicates that the first physical address is one of the plurality of consecutive physical addresses spanned by at least the portion of the data; reading at least the portion of the data from a second physical address of the plurality of consecutive physical addresses based at least in part on the first physical address and the first value of the flag; as well as The data is transmitted to the host device.

2. The memory device of claim 1 , wherein the control component is further configured to cause the memory device to: The second physical address is determined based at least in part on the first physical address and the first value of the flag and based at least in part on identifying an offset relative to the first physical address. 3 . The memory device of claim 1 , wherein the first physical address corresponds to a start page of a plurality of pages corresponding to the plurality of consecutive physical addresses.

4. The memory device of claim 1, wherein the first physical address and the second physical address are the same physical address.

5. The memory device of claim 1 , wherein the control component is configured to cause the memory device to determine the memory locations of the first plurality of entries by determining a third physical address indicating the locations of the first plurality of entries based at least in part on the first logical block address.

6. The memory device of claim 5, wherein the third physical address indicates a location of a first page of a first type of memory in the memory device, and the plurality of consecutive physical addresses indicate locations of a plurality of pages of a second type of memory in the memory device.

7. The memory device of claim 6, wherein the first type of memory comprises SRAM of the memory device and the second type of memory comprises NAND memory of the memory device.

8. The memory device of claim 1, wherein the control component is further configured to cause the memory device to: receiving, from the host device, a second read command including a second logical block address associated with second data stored in the memory device; determining the memory locations of the first plurality of entries for mapping the first plurality of logical block addresses to the corresponding first plurality of physical addresses based at least in part on the second logical block address, wherein the first plurality of logical block addresses includes the second logical block address; reading a second entry of the first plurality of entries based at least in part on determining the memory locations of the first plurality of entries and based on the second logical block address, the second entry comprising a second physical address and a second value of the flag, wherein the second physical address indicates a location of a second plurality of entries for mapping a subset of the first plurality of logical block addresses including the second logical block address to a corresponding subset of the first plurality of physical addresses; identifying a first entry in the second plurality of entries based at least in part on the second entry in the first plurality of entries, the first entry in the second plurality of entries comprising a fourth physical address indicating a location of the second data; reading the second data from the fourth physical address based at least in part on identifying the first entry in the second plurality of entries; as well as The second data is transmitted to the host device.

9. The memory device of claim 1, wherein the control component is further configured to cause the memory device to: receiving a plurality of write commands from the host device prior to receiving the read command, a first write command of the plurality of write commands including the first logical block address corresponding to the first physical address, wherein the plurality of write commands are associated with writing the data to the plurality of consecutive physical addresses; and The data is stored at the plurality of consecutive physical addresses based at least in part on receiving the plurality of write commands.

10. The memory device of claim 9, wherein the control component is further configured to cause the memory device to: The first value of the flag and the first physical address of the plurality of consecutive physical addresses are stored in the first entry of the first plurality of entries based at least in part on writing the data to the plurality of consecutive physical addresses prior to receiving the read command.

11. The memory device of claim 1, wherein the first value of the flag indicates that the first physical address includes a location of at least the portion of the data.

12. A memory device comprising: Memory array; and a control component coupled to the memory array and configured to cause the memory device to: receiving a plurality of write commands from a host device for writing data to the memory device, the plurality of write commands comprising: a first write command including a first logical block address corresponding to a first entry of a number of entries for mapping a plurality of consecutive logical block addresses to a corresponding plurality of physical addresses, and A plurality of remaining write commands among the plurality of write commands, each of which comprises a corresponding continuous logical block address; storing the data in the memory device at a plurality of consecutive physical addresses starting from a first physical address based at least in part on receiving the plurality of write commands; determining whether a number of logical block addresses including the first logical block address and the corresponding consecutive logical block addresses matches the number of entries; and Based at least in part on determining that the number of logical block addresses matches the number of entries, the first physical address and a first value of a flag are stored in a first entry of a plurality of entries used to map a plurality of logical block addresses including the number of logical block addresses to a corresponding plurality of physical block addresses including the plurality of consecutive physical addresses, wherein the first value of the flag indicates that the first physical address is one of the plurality of consecutive physical addresses storing at least a portion of the data.

13. The memory device of claim 12, wherein the first logical block address corresponds to the first physical address, and each of the respective consecutive logical block addresses corresponds to a respective consecutive physical address of the plurality of consecutive physical addresses.

14. The memory device of claim 12, wherein the control component is further configured to cause the memory device to: for each write command in the plurality of write commands, storing a corresponding entry in a second plurality of entries including the number of entries, the second plurality of entries being used to map the number of logical block addresses to the plurality of consecutive physical addresses; and The second plurality of entries is discarded based at least in part on determining that the number of logical block addresses matches the number of entries.

15. The memory device of claim 12, wherein the control component is further configured to cause the memory device to: receiving, from the host device, a read command including a third logical block address of the consecutive logical block addresses after storing the first physical address and the first value of the flag in the first entry; reading the first entry of the plurality of entries to read the first physical address and the first value of the flag based at least in part on receiving the read command including the third logical block address; identifying a second physical address among the plurality of consecutive physical addresses based at least in part on reading the first entry; reading a second portion of the data from the second physical address based at least in part on identifying the second physical address; as well as The second portion of the data is transmitted to the host device.

16. The memory device of claim 12, wherein the plurality of consecutive physical addresses are contained in a first block of the memory device, the memory device further comprising: receiving from the host device a second plurality of write commands for writing second data to the memory device, the second plurality of write commands being interleaved with the plurality of write commands and comprising: a second write command including a third logical block address corresponding to a first entry of a second number of entries for mapping a second plurality of consecutive logical block addresses to a corresponding second plurality of physical addresses, and a second plurality of remaining write commands of the second plurality of write commands each including a second respective contiguous logical block address; identifying a second block different from the first block based at least in part on receiving the second plurality of write commands; storing the second data in the memory device at a second plurality of consecutive physical addresses of the second block starting at a fourth physical address; determining whether a second number of logical block addresses including the third logical block address and the second corresponding logical block address matches the second number of entries; and Based at least in part on determining that the second number of logical block addresses matches the second number of entries, the fourth physical address and the first value of the flag are stored in a first entry of a second plurality of entries that maps a second plurality of logical block addresses including the second number of logical block addresses to a corresponding second plurality of physical block addresses including the second plurality of consecutive physical addresses.

17. A non-transitory computer-readable medium storing code including instructions that, when executed by a processor of an electronic device, cause the electronic device to: receiving a read command from a host device, the read command including a first logical block address associated with a location of at least a portion of data stored in the electronic device, wherein the data spans a plurality of consecutive physical addresses; determining, based at least in part on the first logical block address, memory locations of a first plurality of entries for mapping a first plurality of logical block addresses including the first logical block address to a corresponding first plurality of physical addresses; reading a first entry of the first plurality of entries based at least in part on the first logical block address, the first entry comprising a first physical address of the plurality of consecutive physical addresses and a first value of a flag, wherein the first value of the flag indicates that the first physical address is one of the plurality of consecutive physical addresses spanned by at least the portion of the data; reading at least the portion of the data from a second physical address of the plurality of consecutive physical addresses based at least in part on the first physical address and the first value of the flag; as well as The data is transmitted to the host device.

18. The non-transitory computer-readable medium of claim 17, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to: The second physical address is determined based at least in part on the first physical address and the first value of the flag and based at least in part on identifying an offset relative to the first physical address.

19. The non-transitory computer-readable medium of claim 17, wherein the first physical address corresponds to a starting page of a plurality of pages corresponding to the plurality of consecutive physical addresses.

20. The non-transitory computer-readable medium of claim 17, wherein the first physical address and the second physical address are the same physical address.

21. The non-transitory computer-readable medium of claim 17, wherein the instructions, when executed by the processor of the electronic device, cause the electronic device to determine the memory locations of the first plurality of entries by determining a third physical address indicating the locations of the first plurality of entries based at least in part on the first logical block address.

22. The non-transitory computer-readable medium of claim 21, wherein the third physical address indicates a location of a first page of a first type of memory of the electronic device, and the plurality of consecutive physical addresses indicate locations of a plurality of pages of a second type of memory in the electronic device.

23. The non-transitory computer-readable medium of claim 22, wherein the first type of memory comprises SRAM of the electronic device and the second type of memory comprises NAND memory of the electronic device.

24. The non-transitory computer-readable medium of claim 17, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to: receiving, from the host device, a second read command including a second logical block address associated with second data stored in the electronic device; determining the memory locations of the first plurality of entries for mapping the first plurality of logical block addresses to the corresponding first plurality of physical addresses based at least in part on the second logical block address, wherein the first plurality of logical block addresses includes the second logical block address; reading a second entry of the first plurality of entries based at least in part on determining the memory locations of the first plurality of entries and based on the second logical block address, the second entry comprising a second physical address and a second value of the flag, wherein the second physical address indicates a location of a second plurality of entries for mapping a subset of the first plurality of logical block addresses including the second logical block address to a corresponding subset of the first plurality of physical addresses; identifying a first entry in the second plurality of entries based at least in part on the second entry in the first plurality of entries, the first entry in the second plurality of entries comprising a fourth physical address indicating a location of the second data; reading the second data from the fourth physical address based at least in part on identifying the first entry in the second plurality of entries; as well as The second data is transmitted to the host device.

25. The non-transitory computer-readable medium of claim 17, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to: receiving a plurality of write commands from the host device prior to receiving the read command, a first write command of the plurality of write commands including the first logical block address corresponding to the first physical address, wherein the plurality of write commands are associated with writing the data to the plurality of consecutive physical addresses; and The data is stored at the plurality of consecutive physical addresses based at least in part on receiving the plurality of write commands.

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