A computer task management method and a computer device

Abstract

The present invention relates to a computer task management system and a computer device, which are applied to an X86 and ARM hybrid architecture, and include: a first X86 processor receives a new task; the first X86 processor analyzes all complex instructions used to execute the new task based on the X86 complex instruction set, and determines whether the new task is to be executed by a second X86 processor or an ARM processor according to the all complex instructions and the ARM reduced instruction set; the first X86 processor allocates the new task to the second X86 processor or the ARM processor according to the judgment result of step S20, so that the second X86 processor executes the new task or the ARM processor executes the new task. The present invention improves on the existing X86 and ARM hybrid architecture processor system, enabling it to simultaneously process different instruction tasks.

Description

Technical Field

[0001] The present invention relates to the field of computer technologies, and particularly to a computer task management method and a computer device. Background Art

[0002] The X86 processor is a CPU architecture processor launched by Intel. The X86 processing uses a complex instruction set and can better handle complex calculations; it is widely used in PC computers and servers. At the same time, the X86 has relatively high power consumption and large heat dissipation requirements.

[0003] The ARM processor is a RISC microprocessor. The characteristics of the ARM processor are small size, low power consumption, low cost, and high performance; a large number of registers are used, and the instruction execution speed is faster; most data operations are completed in registers; the addressing mode is flexible and simple, and the execution efficiency is high.

[0004] In recent years, in the field of information system technologies, the application of independent and controllable core components has become more and more extensive. The Feiteng CPU based on the ARM architecture and the Galaxy Kylin operating system have become independent and controllable core products. Currently, most information systems in China are based on the X86 technology system. During the application of independent and controllable products, system reliability is an important problem that needs to be solved urgently. Among them, the instruction lengths executed by processors based on the X86 and ARM hybrid architecture are fixed, and only a single instruction can be processed when processing instructions. When encountering multiple instructions, it will cause instruction retention and result in the problem that tasks cannot be processed in time. Summary of the Invention

[0005] The purpose of the present invention is to propose a computer task management method and a computer device, which are improved on the existing X86 and ARM hybrid architecture processor system so that it can process different instruction tasks simultaneously.

[0006] To achieve the above purpose, an embodiment of the present invention proposes a computer task management method, which is applied to the X86 and ARM hybrid architecture. The method includes the following steps:

[0007] Step S10: The first X86 processor receives a new task;

[0008] Step S20: The first X86 processor analyzes all complex instructions used to execute the new task based on the X86 complex instruction set, and determines whether the new task is to be executed by the second X86 processor or the ARM processor according to the all complex instructions and the ARM reduced instruction set;

[0009] Step S30: According to the judgment result of step S20, the first X86 processor allocates the new task to the second X86 processor or the ARM processor, so that the second X86 processor executes the new task or the ARM processor executes the new task.

[0010] Preferably, step S20 includes:

[0011] The first X86 processor obtains all complex instructions used to execute the new task in the way of X86 architecture trial operation, and translates all the complex instructions. If at least 90% or more of all the complex instructions can be directly translated into the reduced instructions in the ARM reduced instruction set, it is determined that the ARM processor executes the new task alone, or the ARM processor and the second X86 processor execute the new task alternately. Otherwise, it is determined that the second X86 processor executes the new task alone.

[0012] Preferably, step S20 includes:

[0013] The first X86 processor obtains all complex instructions used to execute the new task in the way of X86 architecture trial operation, and translates all the complex instructions. If at least 90% or more of all the complex instructions can be directly translated into the reduced instructions in the ARM reduced instruction set, and the amount of translated instructions increases by no more than 130%, it is determined that the ARM processor executes the new task alone, or the ARM processor and the second X86 processor execute the new task alternately. Otherwise, it is determined that the second X86 processor executes the new task alone.

[0014] Preferably, the determination that the ARM processor executes the new task alone, or the ARM processor and the second X86 processor execute the new task alternately, includes:

[0015] If all the complex instructions can be directly translated into the reduced instructions in the ARM reduced instruction set, the ARM processor executes the new task; if a part of all the complex instructions cannot be directly translated into the reduced instructions in the ARM reduced instruction set, the ARM processor and the second X86 processor execute the new task alternately. The ARM processor processes the part of instructions that can be directly translated into the reduced instructions in the ARM reduced instruction set, and the second X86 processor processes the part of instructions that cannot be directly translated into the reduced instructions in the ARM reduced instruction set.

[0016] Preferably, step S30 further includes:

[0017] When it is determined in step S20 that the new task is to be alternately executed by the ARM processor and the second X86 processor, set a breakpoint for the new task and allocate it to the second X86 processor or the ARM processor, so that the second X86 processor and the ARM processor alternately execute the new task according to the breakpoint.

[0018] Preferably, during the process of the second X86 processor and the ARM processor alternately executing the tasks assigned by the first X86 processor,

[0019] When the task processed by the second X86 processor reaches the breakpoint, request the relevant processing results of the ARM processor required for the processing task from the ARM processor, interrupt the task and wait for the relevant processing results of the ARM processor, and continue to execute the task according to the relevant processing results of the ARM processor after receiving the relevant processing results of the ARM processor;

[0020] When the task processed by the ARM processor reaches the breakpoint, request the relevant processing results of the second X86 processor required for the processing task from the second X86 processor, interrupt the task and wait for the processing results of the second X86 processor, and continue to execute the task according to the relevant processing results of the second X86 processor after receiving the relevant processing results of the second X86 processor.

[0021] Preferably, step S30 further includes:

[0022] When it is determined in step S20 that the new task is to be alternately executed by the ARM processor and the second X86 processor, set a breakpoint and a priority for the new task, and allocate it to the second X86 processor or the ARM processor, so that the second X86 processor and the ARM processor alternately execute the new task according to the breakpoint and the priority.

[0023] Preferably, during the process of the second X86 processor and the ARM processor alternately executing the tasks assigned by the first X86 processor,

[0024] When the second X86 processor receives a request from the ARM processor to obtain the relevant processing results of the second X86 processor required for the processing task, the request carries a task priority mark. The second X86 processor compares the priority of the task being interrupted by the ARM processor and the priority of the task being processed by the second X86 processor. The second X86 processor preferentially processes the request from the ARM processor to obtain the relevant processing results of the second X86 processor required for the processing task or the task being processed by the second X86 processor according to the priority comparison result;

[0025] When the ARM processor receives a request from the second X86 processor for relevant processing results of the ARM processor required for obtaining a processing task, the request carries a task priority tag. The ARM processor compares the priority of the task being interrupted by the second X86 processor and the priority of the task being processed by the ARM processor. The ARM processor preferentially processes the request from the second X86 processor for relevant processing results of the ARM processor required for obtaining a processing task or the task being processed by the ARM processor according to the priority comparison result.

[0026] Preferably, the second X86 processor preferentially processes the request from the ARM processor for relevant processing results of the second X86 processor required for obtaining a processing task or the task being processed by the second X86 processor according to the priority comparison result, including:

[0027] When the priority of the task being interrupted by the ARM processor is higher, preferentially process the request from the ARM processor for relevant processing results of the second X86 processor required for obtaining a processing task, process the relevant task according to the request of the ARM processor, and feedback the processing result to the ARM processor, and then continue the task being processed by the second X86 processor;

[0028] The ARM processor preferentially processes the request from the second X86 processor for relevant processing results of the ARM processor required for obtaining a processing task or the task being processed by the ARM processor according to the priority comparison result, including:

[0029] When the priority of the task being interrupted by the second X86 processor is higher, preferentially process the request from the second X86 processor for relevant processing results of the ARM processor required for obtaining a processing task, process the relevant task according to the request of the second X86 processor, and feedback the processing result to the second X86 processor, and then continue the task being processed by the ARM processor.

[0030] An embodiment of the present invention further provides a computer device, including a first X86 processor, a second X86 processor, and an ARM processor, for implementing the above computer task management method.

[0031] The embodiment of the present invention has at least the following beneficial effects:

[0032] The embodiments of the present invention are improved on the existing X86 and ARM hybrid architecture processor systems, enabling different instruction tasks to be processed simultaneously. An X86 processor is added for task execution allocation and guidance. The X86 processor and the ARM processor perform arithmetic processing in a divided or alternating manner according to their differences in programs or transactions to be processed, so that the X86 and ARM hybrid architecture processor system can process different instruction tasks simultaneously.

[0033] Other features and advantages of the embodiments of the present invention will be described in the subsequent specification. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the accompanying drawings required for the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0035] Figure 1 It is a flowchart of a computer task management method according to an embodiment of the present invention.

[0036] Figure 2 It is a schematic diagram of a computer device according to another embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0037] The following will detail various exemplary embodiments, features, and aspects of the present disclosure with reference to the accompanying drawings. Additionally, for a better understanding of the present invention, numerous specific details are given in the following detailed embodiments. Those skilled in the art should understand that the present invention can be implemented without some of these specific details. In some instances, means well-known to those skilled in the art are not described in detail to highlight the gist of the present invention.

[0038] Refer to Figure 1 , an embodiment of the present invention provides a computer task management method, which is applied to an X86 and ARM hybrid architecture. The method includes the following steps:

[0039] Step S10: The first X86 processor receives a new task;

[0040] Step S20: The first X86 processor analyzes all complex instructions used to execute the new task based on the X86 complex instruction set, and determines whether the second X86 processor or the ARM processor executes the new task according to the all complex instructions and the ARM reduced instruction set;

[0041] Step S30: According to the judgment result of step S20, the first X86 processor allocates the new task to the second X86 processor or the ARM processor, so that the second X86 processor executes the new task or the ARM processor executes the new task.

[0042] Specifically, for tasks that are suitable for processing by the X86 complex instruction set, they should be processed by the X86 complex instruction set through task allocation as much as possible; for example, complex operations and non-standard tasks. For tasks that are suitable for processing by the ARM reduced instruction set, they should be processed by the ARM reduced instruction set through task allocation as much as possible; for example, some standard repetitive tasks such as mathematical operations and image processing.

[0043] The embodiment of the present invention improves on the existing X86 and ARM hybrid architecture processor system, enabling it to process different instruction tasks simultaneously. An additional X86 processor is added for task execution allocation and guidance. The X86 processor and the ARM processor perform arithmetic processing in a divided or alternating manner according to the differences in the programs or the transactions to be processed by themselves, so that the X86 and ARM hybrid architecture processor system can process different instruction tasks simultaneously.

[0044] In some embodiments, step S20 includes:

[0045] The first X86 processor obtains all the complex instructions used to execute the new task by means of X86 architecture trial operation and translates all the complex instructions. If at least 90% or more of all the complex instructions can be directly translated into the reduced instructions in the ARM reduced instruction set, it is determined that the new task is to be executed independently by the ARM processor or the ARM processor and the second X86 processor execute the new task alternately; otherwise, it is determined that the new task is to be executed independently by the second X86 processor.

[0046] In some embodiments, step S20 includes:

[0047] The first X86 processor obtains all the complex instructions used to execute the new task by means of X86 architecture trial operation and translates all the complex instructions. If at least 90% or more of all the complex instructions can be directly translated into the reduced instructions in the ARM reduced instruction set and the amount of the translated instructions does not increase by more than 130%, it is determined that the new task is to be executed independently by the ARM processor or the ARM processor and the second X86 processor execute the new task alternately; otherwise, it is determined that the new task is to be executed independently by the second X86 processor.

[0048] During the implementation of the method according to the embodiment of the present invention, two results will occur. The new task is processed or alternately run by the ARM processor and the second X86 processor. The division of labor processing is relatively simple, and only a single processor needs to complete the processing during the processing; for relatively large tasks, tasks that need to alternately run the second X86 processor and the ARM processor to produce results require special design. Specifically, in some embodiments, the judgment of whether the ARM processor alone executes the new task or the ARM processor and the second X86 processor alternately execute the new task includes:

[0049] If all the complex instructions can be directly translated into the reduced instructions in the ARM reduced instruction set, the ARM processor executes the new task; if a part of all the complex instructions cannot be directly translated into the reduced instructions in the ARM reduced instruction set, the ARM processor and the second X86 processor alternately execute the new task. The ARM processor processes the part of the instructions that can be directly translated into the reduced instructions in the ARM reduced instruction set, and the second X86 processor processes the part of the instructions that cannot be directly translated into the reduced instructions in the ARM reduced instruction set.

[0050] Further, in some embodiments, the step S30 further includes:

[0051] When it is determined in step S20 that the ARM processor and the second X86 processor alternately execute the new task, set an interrupt point for the new task and allocate it to the second X86 processor or the ARM processor, so that the second X86 processor and the ARM processor alternately execute the new task according to the interrupt point.

[0052] Further, during the process that the second X86 processor and the ARM processor alternately execute the task assigned by the first X86 processor according to the interrupt point,

[0053] When the task processed by the second X86 processor reaches the interrupt point, request the relevant processing results of the ARM processor required for processing the task from the ARM processor, interrupt the task and wait for the relevant processing results of the ARM processor, and continue to execute the task according to the relevant processing results of the ARM processor after receiving the relevant processing results of the ARM processor;

[0054] When the task processed by the ARM processor reaches the interrupt point, request the relevant processing results of the second X86 processor required for processing the task from the second X86 processor, interrupt the task and wait for the processing results of the second X86 processor, and continue to execute the task according to the relevant processing results of the second X86 processor after receiving the relevant processing results of the second X86 processor.

[0055] In some embodiments, step S30 further includes:

[0056] When step S20 determines that the new task is alternately executed by the ARM processor and the second X86 processor, set breakpoints and priorities for the new task and allocate it to the second X86 processor or the ARM processor, so that the second X86 processor and the ARM processor alternately execute the new task according to the breakpoints and priorities;

[0057] Specifically, the second X86 processor or the ARM processor compares the priorities of all tasks being processed or to be processed according to the task priorities, and preferentially processes the tasks with higher priorities.

[0058] Furthermore, during the process that the second X86 processor and the ARM processor alternately execute the tasks assigned by the first X86 processor according to the breakpoints and priorities,

[0059] When the second X86 processor receives a request from the ARM processor for the relevant processing results of the second X86 processor required for processing the task, the request carries a task priority mark (assigned by the first X86 processor). The second X86 processor compares the priority of the task being interrupted by the ARM processor and the priority of the task being processed by the second X86 processor. The second X86 processor preferentially processes the request from the ARM processor for the relevant processing results of the second X86 processor required for processing the task or the task being processed by the second X86 processor according to the priority comparison result;

[0060] When the ARM processor receives a request from the second X86 processor for the relevant processing results of the ARM processor required for processing the task, the request carries a task priority mark (assigned by the first X86 processor). The ARM processor compares the priority of the task being interrupted by the second X86 processor and the priority of the task being processed by the ARM processor. The ARM processor preferentially processes the request from the second X86 processor for the relevant processing results of the ARM processor required for processing the task or the task being processed by the ARM processor according to the priority comparison result;

[0061] Among them, the data transmission between the second X86 processor and the ARM processor is realized through the forwarding of the first X86 processor, that is, the requests and the sending of relevant processing results between the second X86 processor and the ARM processor are first sent by the sender to the first X86 processor, and then forwarded by the first X86 processor to the receiver;

[0062] When the ARM processor reaches a task interruption point during task execution and needs to obtain the relevant processing results of the second X86 processor to assist in alternate execution in order to continue subsequent processing, the ARM processor sends a request for the part of the task that requires the second X86 processor to process to the first X86 processor. The first X86 processor sets a priority for this part of the task and then forwards it to the second X86 processor;

[0063] When the second X86 processor reaches a task interruption point during task execution and needs to obtain the relevant processing results of the ARM processor to assist in alternate execution in order to continue subsequent processing, the second X86 processor sends a request for the part of the task that requires the ARM processor to process to the first X86 processor. The first X86 processor sets a priority for this part of the task and then forwards it to the ARM processor.

[0064] In some embodiments, the second X86 processor preferentially processes the request of the ARM processor for the relevant processing results of the second X86 processor required for obtaining processing tasks or the task being processed by the second X86 processor according to the priority comparison result, including:

[0065] When the priority of the task being interrupted by the ARM processor is high, preferentially process the request of the ARM processor for the relevant processing results of the second X86 processor required for obtaining processing tasks, process the relevant tasks according to the request of the ARM processor, and feed back the processing results to the ARM processor, and then continue the task being processed by the second X86 processor;

[0066] Among them, the ARM processor preferentially processes the request of the second X86 processor for the relevant processing results of the ARM processor required for obtaining processing tasks or the task being processed by the ARM processor according to the priority comparison result, including:

[0067] When the priority of the task being interrupted by the second X86 processor is high, preferentially process the request of the second X86 processor for the relevant processing results of the ARM processor required for obtaining processing tasks, process the relevant tasks according to the request of the second X86 processor, and feed back the processing results to the second X86 processor, and then continue the task being processed by the ARM processor.

[0068] Specifically, in this embodiment, for a task that requires the other party to interrupt the current task processing and perform an insertion process during the task processing, it is achieved through the following method: The sender in the second X86 processor and the ARM processor sends a request to the first X86 processor. After receiving the request, the first X86 processor determines the priority of the task being processed by the recipient, sets a level one higher than the other party's priority for the requested task, and hands the requested task to the other party for priority processing. Since only a very small part of the tasks that need to be processed by the other party are usually involved and can be processed very quickly, this embodiment can avoid the long interrupt waiting of the processor during the alternate execution of tasks, thereby improving the efficiency of the alternate execution of tasks.

[0069] It should be noted that in the past, program interrupts and priorities were set and allocated internally by the same processor, which was a chip-level scheduling. The interrupts and priorities in this embodiment are software-level scheduling. Its important feature is that for the X86 and ARM hybrid architecture processing, a preprocessing first X86 processor is set for scheduling, and the target task is to fully utilize the operation efficiency of the different instruction sets of the two processor architectures to schedule the program.

[0070] Refer to Figure 2 , Another embodiment of the present invention further proposes a computer device, including a first X86 processor 1, a second X86 processor 2, and an ARM processor 3, which are used to implement the steps of the computer task management method described in the above embodiment.

[0071] It should be noted that the computer device in this embodiment corresponds to the method in the above embodiment. Therefore, the content not detailed in the computer device in this embodiment can be obtained by referring to the content of the method in the above embodiment, and will not be elaborated here.

[0072] The various embodiments of the present invention have been described above. The above description is exemplary and not exhaustive, and is not limited to the disclosed embodiments. Many modifications and variations are obvious to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The choice of terms used herein is intended to best explain the principles of the embodiments, practical applications, or improvements to technologies in the market, or to enable other ordinary skilled persons in the art to understand the embodiments disclosed herein.

Claims

1. A computer task management method, applied to an X86 and ARM hybrid architecture, characterized in that, The method includes the following steps: Step S10: The first X86 processor receives a new task; Step S20: The first X86 processor analyzes all complex instructions used to execute the new task based on the X86 complex instruction set, and determines whether the second X86 processor or the ARM processor executes the new task according to the all complex instructions and the ARM reduced instruction set; The first X86 processor obtains all complex instructions used to execute the new task in the way of trial operation with the X86 architecture, and translates the all complex instructions. If at least more than 90% of the all complex instructions can be directly translated into reduced instructions in the ARM reduced instruction set, and the amount of translated instructions does not increase by more than 130%, it is determined that the ARM processor executes the new task alone, or the ARM processor and the second X86 processor execute the new task alternately. Otherwise, it is determined that the second X86 processor executes the new task alone; The determination that the ARM processor executes the new task alone, or the ARM processor and the second X86 processor execute the new task alternately, includes: If all the complex instructions can be directly translated into reduced instructions in the ARM reduced instruction set, the ARM processor executes the new task; if a part of the all complex instructions cannot be directly translated into reduced instructions in the ARM reduced instruction set, the ARM processor and the second X86 processor execute the new task alternately. The ARM processor processes the part of instructions that can be directly translated into reduced instructions in the ARM reduced instruction set, and the second X86 processor processes the part of instructions that cannot be directly translated into reduced instructions in the ARM reduced instruction set; Step S30: The first X86 processor distributes the new task to the second X86 processor or the ARM processor according to the determination result of Step S20, so that the second X86 processor executes the new task or the ARM processor executes the new task; When Step S20 determines that the ARM processor and the second X86 processor execute the new task alternately, set breakpoints and priorities for the new task, and distribute them to the second X86 processor or the ARM processor, so that the second X86 processor and the ARM processor execute the new task alternately according to the breakpoints and priorities; During the process of the second X86 processor and the ARM processor executing the tasks assigned by the first X86 processor alternately, When the second X86 processor receives a request from the ARM processor to obtain the relevant processing results of the second X86 processor required for processing the task, the request carries a task priority mark. The second X86 processor compares the priority of the task being interrupted by the ARM processor and the priority of the task being processed by the second X86 processor. The second X86 processor preferentially processes the request from the ARM processor to obtain the relevant processing results of the second X86 processor required for processing the task or the task being processed by the second X86 processor according to the priority comparison result; When the ARM processor receives a request from the second X86 processor to obtain the relevant processing results of the ARM processor required for a processing task, the request carries a task priority tag. The ARM processor compares the priority of the task being interrupted by the second X86 processor and the priority of the task being processed by the ARM processor. The ARM processor preferentially processes the request from the second X86 processor to obtain the relevant processing results of the ARM processor required for the processing task or the task being processed by the ARM processor according to the priority comparison result.

2. The computer task management method according to claim 1, wherein, The second X86 processor preferentially processes the request from the ARM processor to obtain the relevant processing results of the second X86 processor required for the processing task or the task being processed by the second X86 processor according to the priority comparison result, including: When the priority of the task being interrupted by the ARM processor is higher, preferentially process the request from the ARM processor to obtain the relevant processing results of the second X86 processor required for the processing task, process the relevant task according to the request of the ARM processor, and feedback the processing result to the ARM processor, and then continue the task being processed by the second X86 processor; The ARM processor preferentially processes the request from the second X86 processor to obtain the relevant processing results of the ARM processor required for the processing task or the task being processed by the ARM processor according to the priority comparison result, including: When the priority of the task being interrupted by the second X86 processor is higher, preferentially process the request from the second X86 processor to obtain the relevant processing results of the ARM processor required for the processing task, process the relevant task according to the request of the second X86 processor, and feedback the processing result to the second X86 processor, and then continue the task being processed by the ARM processor.

3. A computer device, characterized in that, It includes a first X86 processor, a second X86 processor and an ARM processor, and is used to implement the computer task management method described in claim 1 or 2.

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