Circuit structure and method for realizing memory storage using memory cell and MRAM stacking

Abstract

The present disclosure provides a circuit structure and method for implementing memory storage using a memory cell and a magnetic random access memory (MRAM) stack. The circuit structure includes: a memory cell having a first latch configured to store a digital bit; a first diode coupled to the first latch; and a first magnetic random access memory (MRAM) stack coupled to the first latch of the memory cell through the first diode. The first MRAM stack includes a first layer and a second layer having respective magnetic moments. The magnetic moment of the second layer is adjustable between a parallel orientation and an antiparallel orientation relative to the magnetic moment of the first layer. In addition, the magnetic anisotropy (VCMA effect) of the second layer can be changed by applying an applied voltage. The spin Hall electrode is directly coupled to the first MRAM stack.

Description

Technical Field

[0001] Embodiments of the present disclosure generally relate to memory devices for integrated circuits (ICs). More specifically, embodiments of the present disclosure provide circuit structures and methods for implementing memory storage using memory cells combined with magnetic random access memory (MRAM) stacks. Background Art

[0002] Random access memory (RAM) structures are important to the operation of integrated circuits (ICs). RAM refers to a collection of electrically operated storage cells that can be read and / or written in any order and can provide storage for working data or machine code for a device. RAM is considered a "volatile" form of memory because power is required to retain the stored information. The two most common types of volatile RAM structures are static random access memory (SRAM) and dynamic random access memory (DRAM). Other types of RAM can include magnetic random access memory (MRAM), resistive random access memory (RRAM), and other storage elements with different operating principles and storage characteristics.

[0003] When RAM is employed in intermittently powered devices (i.e., any device that switches back and forth quickly between "off" and "on"), the RAM can be used in conjunction with various forms of non-volatile memory (NVM). However, the use of NVM can present other technical challenges. In IC structures that include both NVM and SRAM, relatively high energy is required to implement the "checkpoint" operation used to copy SRAM data to the NVM element. In the alternative of using NVM instead of SRAM for intermittently powered devices, the NVM will exhibit lower access speeds than the SRAM. Conventional approaches to mitigate these schemes (e.g., combining multiple types of RAM into hybrid circuits) have proven to be less than satisfactory because of lower sensitivity and energy requirements that are still much higher than pure SRAM configurations. These solutions also typically require a large amount of surface area on the IC chip. Summary of the invention

[0004] Some aspects of the present disclosure provide a circuit structure, the circuit structure comprising: a latch having a first inverter and configured to store a digital bit; a first diode coupled to the first inverter of the latch; a first magnetic random access memory (MRAM) stack coupled to the first inverter of the latch through the first diode, the first MRAM stack comprising: a first layer and a second layer, each having a respective magnetic moment, wherein the magnetic moment of the second layer is adjustable between a parallel orientation and an antiparallel orientation relative to the magnetic moment of the first layer; and a spin Hall electrode directly coupled to the first MRAM stack.

[0005] Another aspect of the present disclosure provides a circuit structure, the circuit structure including: a static random access memory (SRAM) cell having a first inverter configured to store a first logic voltage and a second inverter configured to store a second logic voltage; a first magnetic random access memory (MRAM) stack coupled to the first inverter of the SRAM cell through a first access transistor; a second MRAM stack coupled to the second inverter of the SRAM cell through a second access transistor, wherein each of the first MRAM stack and the second MRAM stack includes: a first layer and a second layer, each having a respective magnetic moment, wherein the magnetic moment of the second layer is adjustable between a parallel orientation and an antiparallel orientation relative to the magnetic moment of the first layer in response to an applied voltage; and a spin Hall electrode directly coupled to the first MRAM stack and the second MRAM stack.

[0006] Further aspects of the present disclosure provide a method for recording data within an integrated circuit (IC) structure, the method comprising: providing a circuit structure, the circuit structure comprising: a latch electrically coupled to another component of the IC structure and having a first inverter configured to store a digital bit; a first diode coupled to the first inverter; a first magnetic random access memory (MRAM) stack coupled to the first inverter of the latch through the first diode, the first MRAM stack comprising: a first layer having a first magnetic moment in a first orientation, and a second layer located on the first layer and having a second magnetic moment, the second magnetic moment being adjustable between the first orientation and a second orientation opposite to the first orientation in response to an applied voltage; and a spin Hall electrode directly coupled to the first MRAM stack; transmitting a read current from the first inverter of the memory cell to the first MRAM stack across the first diode; and transmitting a write current across the spin Hall electrode, wherein transmitting the write current records the digital bit of the memory cell within the first MRAM stack. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] These and other features of the present disclosure will be more readily understood from the following detailed description of the various aspects of the disclosure taken in conjunction with the accompanying drawings which illustrate various embodiments of the disclosure.

[0008] Figure 1 A schematic diagram showing a circuit structure according to an embodiment of the present disclosure is shown.

[0009] Figure 2 A schematic diagram showing a circuit structure according to another embodiment of the present disclosure is shown.

[0010] Figure 3A schematic diagram showing a circuit structure according to yet another embodiment of the present invention is shown.

[0011] Figure 4 A schematic diagram of a circuit structure having multiple memory cells and a magnetic random access memory (MRAM) stack according to an embodiment of the present disclosure is shown.

[0012] Please note that the drawings of the present disclosure are not necessarily drawn to scale. The drawings are intended to depict only typical aspects of the present disclosure and therefore should not be considered to limit the scope of the present disclosure. In the drawings, like reference numerals represent like elements between the drawings. DETAILED DESCRIPTION

[0013] In the following description, reference is made to the accompanying drawings which form a part of the present invention, and in which specific exemplary embodiments in which the present teachings may be practiced are shown by way of illustration. The description of these embodiments is detailed enough to enable those skilled in the art to practice the present teachings, and it should be understood that other embodiments may be used and may be modified without departing from the scope of the present teachings. Therefore, the following description is illustrative only.

[0014] It will be understood that when an element such as a layer, region, or substrate is referred to as being "on" or "above" another element, it may be directly on the other element or there may be intervening elements. In contrast, when an element is referred to as being "directly on" or "directly above" another element, there are no intervening elements. It will also be understood that when an element is referred to as being "connected" or "coupled" to another element, it may be directly connected or coupled to the other element or there may be intervening elements. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements.

[0015] References in the specification to "one embodiment" or "an embodiment" of the present disclosure and other variations thereof mean that the specific features, structures, characteristics, etc. described in conjunction with the embodiment are included in at least one embodiment of the present disclosure. Therefore, the phrases "in one embodiment" or "in an embodiment" and any other variations appearing throughout the specification do not necessarily refer to the same embodiment. It should be understood that, for example, the use of any of " / ", "and / or", and "at least one of" in the case of "A / B", "A and / or B", and "at least one of A and B" is intended to include selecting only the first listed option (a), or only the second listed option (B), or both options (A and B) at the same time. As other examples, in the case of "A, B, and / or C" and "at least one of A, B, and C," these phrases are intended to include selecting only the first listed option (A), or only the second listed option (B), or only the third listed option (C), or only the first and second listed options (A and B), or only the first and third listed options (A and C), or only the second and third listed options (B and C), or all three options (A, B, and C). This scenario can be extended to many of the listed items, as will be apparent to one of ordinary skill in the art.

[0016] Embodiments of the present disclosure relate to circuit structures and related methods for recording data within an integrated circuit (IC) structure. Embodiments of the present disclosure integrate various types of random access memory (RAM) to provide memory "checkpoints", that is, the ability to store digital bits in redundant non-volatile storage elements. Embodiments of the present disclosure provide this capability while maintaining lower operating energy and surface area than conventional storage structures. RAM refers to any type of storage cell designed to temporarily store data. RAM can take a variety of forms, including static RAM ("SRAM") or dynamic RAM ("DRAM"). RAM can be implemented using a variety of circuit structures, electronic components and / or device architectures. The components of RAM provide a storage cell that can electronically store data in the form of binary digits (i.e., recorded high voltages or low voltages for implementing various types of logic). During operation, the storage cells in the RAM must be configured to facilitate writing information (i.e., storing high voltages and low voltages) and reading information (i.e., identifying the voltage stored in a given cell).

[0017] Embodiments of the present disclosure provide a circuit structure including a memory cell (e.g., a portion of a RAM) having a latch for storing digital bits. A first diode may couple the first latch to a magnetic random access memory (MRAM) stack. The MRAM stack may be outside the memory cell structure. The MRAM stack may include a first layer (sometimes referred to as a "fixed layer") and a second layer (sometimes referred to as a "free layer"). The material composition of each layer may produce a magnetic field in a specific orientation, referred to as a "magnetic moment". The magnetic moment of the first layer may be fixed in one orientation. The magnetic moment of the second layer may be adjustable between a parallel orientation and an antiparallel orientation relative to the magnetic orientation of the first layer. A threshold voltage difference may be formed across the MRAM stack by transmitting a "write current" through a spin Hall electrode. The voltage difference across the MRAM stack may cause the magnetic orientation of the second layer to change between its parallel state and its antiparallel state.

[0018] In addition, an MRAM element that exhibits voltage-controlled magnetic anisotropy (VCMA) can be employed to assist or inhibit the ability of the spin Hall electrode to change the magnetic orientation of the first layer. Although a voltage difference applied across the top and bottom electrodes of the MRAM element is used, the barrier for changing the orientation of the free layer can be increased (making it more difficult to switch / write) or reduced (increasing the ability to write / switch states).

[0019] The structure may also include a spin Hall electrode directly coupled to the first MRAM stack. A "spin Hall electrode" refers to a conductive material that can exhibit a "spin Hall effect" (i.e., the accumulation of "spins" (i.e., the angular moment exhibited by particles) on the sides of a material as current is transmitted across the material). Such a material may include a density of at least about five grams per cubic centimeter (g / cm 3 ) metal. Such metals are commonly known as "heavy metals" and may include, but are not limited to, the following materials: tantalum (ta), osmium (Os), gold (Au), silver (Ag), cobalt (Co), etc. The spin Hall electrode material can be coupled to the first MRAM stack at one side thereof, so that when current flows through the spin Hall electrode, spins are generated along the edge of the MRAM stack. The accumulated spins can impart energy to the second layer of the MRAM stack. When current flows through the spin Hall electrode, the current transmitted from the diode to the MRAM stack can form a magnetic tunnel junction. During circuit operation, the magnetic tunnel junction and the accumulated spins selectively change the orientation of their magnetic moments between parallel and antiparallel states. The MRAM stack in a parallel orientation can indicate a first digital bit (which can be represented as a "high" or "low" logic voltage). The MRAM stack in an antiparallel orientation can indicate an opposite second digital bit and / or logic voltage.

[0020] refer to Figure 1, in which a circuit structure (hereinafter referred to as “structure”) 100 according to various embodiments of the present disclosure is shown. Structure 100 may include a latch 102, which may be implemented as an SRAM cell and / or any other currently known or later developed storage structure. Latch 102 may particularly be provided in the form of a volatile memory cell. Latch 102 of structure 100 may include a first inverter 104 and optionally a second inverter 106, which together are capable of storing digital bits in the form of a first logic voltage and a second logic voltage, respectively. “Latch” refers to a device consisting of two cross-coupled inverting elements (e.g., Figure 1 The latch 102 is an electrical data storage element formed by a set of two transistors (shown) and capable of switching between two stable states. The two stable states of each inverter 104, 106 can correspond to two logic voltages, which represent "1" or "0", respectively. The logic voltage of one or both of the inverters 104, 106 can correspond to a digital bit "1" or "0". Each inverter 104, 106 can be electrically coupled to the ground GND. In this case, when electrically disconnected from the power supply, the digital bit stored in the latch 102 will be cleared.

[0021] The structure 100 may include at least a first diode 108 electrically coupled to the first inverter 104. The first diode 108 may provide an electrical connection between the first inverter 104 and a first magnetic random access memory (MRAM) stack 110 across its opposite terminals. The first diode 108 may allow current to flow from the first inverter 104 to the first MRAM stack 110, but not in the opposite direction. During operation, the first MRAM stack 110 of the structure 100 may be used as a storage medium to copy a digital bit previously stored in the first inverter 104. This operation is called a checkpoint, and the MRAM stack 110 may be used as a "backup" memory storage element for the digital bits stored in the latch 102 of the structure 100.

[0022] The first MRAM stack 110 may include, for example, a first layer 112 and a second layer 114, which are separated from each other by an insulator layer 116 therebetween. The first layer 112 may be referred to as a "fixed layer" and the second layer 114 may be referred to as a "free layer". The insulator layer 116 may be very thin (e.g., about ten angstroms) to allow a magnetic tunnel junction to be formed between the layers 112 and 114, as discussed herein. In addition, the size, shape, and composition of the layer 114 may be selected so that the second layer 114 exhibits a VCMA effect during operation. Each layer 112, 114 of the first MRAM stack 110 may be formed of one or more ferromagnetic metals, or more generally, may include any material having a magnetic moment in a detectable orientation. During manufacture, the first plate 112 may be formed as a permanent magnet set to a specific polarity, while the second plate 114 may have a different magnetization level. The magnetization level of the second plate 114 may be selected so that the magnetic field of the second plate 114 may be reoriented by applying a threshold voltage to at least the first MRAM stack 110. When a threshold voltage is applied across the first MRAM stack 110, the magnetic field of the second plate 114 may be reoriented due to the formation of a magnetic tunnel junction across the insulator layer 116. The two magnetic moment orientations of the second plate 114 may include a first orientation parallel to the first plate 112 (i.e., a "parallel orientation") and a second orientation oppositely oriented relative to the first plate 112 (i.e., an "anti-parallel orientation"). During operation, each of the two magnetic orientations of the second plate 114 may correspond to a predetermined digital value (i.e., "1" or "0").

[0023] The structure 100 may include additional components for writing data to the first MRAM stack 110 and / or clearing data from the first MRAM stack 110. As shown, the first MRAM stack 110 may be directly coupled to the spin Hall electrode 120 (e.g., by being formed directly on the spin Hall electrode 120). As discussed above, the spin Hall electrode 120 may include a density of at least about 5 grams per cubic centimeter (g / cm 3 ) of a metal, such as one or more “heavy metals”. Regardless of how it is implemented, when a write current I is transmitted across the spin Hall electrode 120 W When the spin Hall electrode 120 is turned on, the components of the spin Hall electrode 120 will accumulate spins at its side edges. The spin Hall electrode 120 can be electrically coupled to the ground GND through the recovery transistor 122. The gate terminal RG of the recovery transistor 122 can control whether the spin Hall electrode 120 is electrically coupled to the ground GND, which in turn allows the first MRAM stack 110 to undergo a “checkpoint” or “recovery” operation, as described herein.

[0024] To enable the random access memory function, the structure 100 includes a set of memory access transistors MT1, MT2 for controlling read and write operations. The first memory access transistor MT1 can be coupled to the first inverter 104, and the second memory access transistor MT2 can be coupled to the second inverter 106. The first memory access transistor MT1 can be coupled to a bitline 130 configured to have an adjustable voltage level, and the second memory access transistor MT2 can be coupled to a bitline-bar 132, which can also be set to an adjustable voltage. The bitline 130 and the bitline bar 132 can each be coupled to another component (hereinafter referred to as "component") 134, which represents one or more circuits connected to the structure 100. The component 134 can represent any functional device including and / or connected to one or more of the following: power supply coupling, one or more digital logic circuits, one or more metal wiring layers and / or any other device configured to interact with the latch 102 of the structure 100. The bit line 130 and the bit line bar 132 may each be electrically connected to other structures 100 and other latches 102, but for clarity of description, Figure 1 These connections are omitted.

[0025] To read memory from structure 100, bit line 130 and bit line bar 132 are precharged and brought to a high voltage. Then, the gate of each memory access transistor MT1, MT2 is turned on. The side with the internal node set to the "low" data bit discharges faster. An amplifier circuit (not shown) coupled to structure 100 will evaluate the voltage difference between 130 and 132, and when the voltage difference exceeds a threshold, the lower side is considered to be zero. In order to save (checkpoint) data in the memory cell, such as Figure 1 As shown, diode 108 is connected to latch 102. During a checkpoint operation, access transistors MT1 and MT2 are turned off by setting a first word line 150 coupled to first memory access transistor MT1 and a second word line 150 coupled to second memory access transistor MT2 to a logic "low" voltage.

[0026] At this stage, the checkpoint operation can be implemented in two stages. First, the terminal RG is set to a low voltage, the line 124 to the voltage V1 is set to a low voltage, and the line 126 to the voltage V2 is set to a high voltage. In an alternative embodiment, the same checkpoint operation can be implemented in the following case: that is, the gate of the transistor is not coupled to the terminal RG, and only the two voltages V1 and V2 are set to ground and the voltage of the terminal SG is set to a high voltage. When the terminal SG is set to a high voltage, a high negative Iw is transmitted through the spin Hall electrode 120. The application of this current sets the second layer 114 in the MRAM cell 110 to its antiparallel state (indicating, for example, a logical "1"). The second step of the checkpoint includes setting the terminal SG to a low voltage, reversing the voltage difference between V1 and V2, and setting it to a level that causes a small positive current Iw to pass through the spin Hall electrode 120. SG is set to a high voltage again, and Iw is sent through the spin Hall electrode 120. At this stage, the MRAM stack 110 will exhibit a voltage difference between the first layer 112 and the second layer 114 (due to the presence of the insulating layer 116). The amount of this voltage difference (between 112 and 114) will depend on the state of the internal node 160 between the two transistors of the first inverter 104 within the latch 102. If the node 160 is set to a low voltage, the resulting voltage difference will cause the VCMA effect of the MRAM stack 110 to reduce the energy barrier for the second layer 114 to switch its state. Passing a current through the spin Hall electrode 120 will cause a spin Hall transfer to the second layer 114, causing the magnetic state of the second layer to switch to its parallel state (e.g., corresponding to a logic level "0") and store the corresponding logic level. If the internal node 160 is set to a high voltage, the VCMA effect is not triggered, and the second layer 114 resists being switched and remains in an anti-parallel state (e.g., logic "1" in this example) during the application of the current Iw. At this time, the terminal SG remains set to a low voltage.

[0027] Still refer to Figure 1, the structure 100 can also provide a restore operation in which the data previously recorded in the MRAM stack 110 is restored to the inverters 104, 106 of the latch 102. Here, the bit line bar 132 is placed at a voltage level corresponding to the midpoint of the resistance of the MRAM cell 110. The bit line 130 is correspondingly set to a power supply voltage, denoted as "Vdd". At this time, the memory access transistors MT1 and MT2 can be turned on via a high voltage applied through the word lines 150, 152. The terminal SG is set to a low voltage, thereby disconnecting the lines 124 and 126 from the spin Hall electrode 120. The terminal RG is set to a high voltage, thereby grounding the spin Hall electrode 120. At this time, the current will flow in the bit line 130 through the memory access transistor MT1, the diode 108 and the MRAM stack 110 to the spin Hall electrode 120 and the ground. Depending on the resistance of the MRAM stack 110, the voltage at the internal node 160 will be higher or lower than the voltage of the bit line bar 132. If the MRAM stack 110 is in a low resistance state (logic 0), the internal node 160 will be pulled to a lower level than the internal node 162 of the second inverter 106. In this case, the inverters 104, 106 interpret the internal node 160 as "low" and the node 162 of the second latch 152 as high. Conversely, in the case where the internal node 160 is at a higher voltage than the node 162, the inverters 104, 106 interpret the internal node 160 as "high" and the node 162 as "low". At this time, the memory access transistors MT1, MT2 are disconnected (setting the word lines 150 and 152 to a low voltage), and the line 120 is set to "floating" (i.e., V1, V2 are disconnected).

[0028] refer to Figure 2 , another embodiment of the structure 100 may include multiple MRAM elements for selectively recording digital bits from both sides of the latch 102 by connecting to the first inverter 104 and the second inverter 106. Here, the second diode 138 can electrically couple the second inverter 106 to the second MRAM. The second MRAM stack 140 can in turn be directly electrically coupled to another portion of the spin Hall electrode 120. The second MRAM stack 140 may include a third layer 142, a fourth layer 144, and an insulator layer 146 located therebetween, arranged in a manner similar to the first MRAM stack 110. Therefore, the second MRAM stack 140 can store digital bits based on the parallel or antiparallel magnetic moments of the fourth layer 144 therein. In this configuration, the second MRAM stack 140 can be electrically coupled to the second inverter 106 and can store a logic voltage recorded in the second inverter 106.

[0029] The second MRAM stack 140 can operate independently of the first MRAM stack 110 to separately store the logic voltage from the second inverter 106. To implement the checkpoint operation in this configuration, the same as described above with respect to Figure 1 Due to the complementary nature of the internal nodes 160 and 162, when the checkpoint operation is completed substantially as described above, the MRAM stacks 110 and 140 will store logic values ​​on each side of the latch 102 and are complementary to each other. In this way, the logic levels within the inverters 104, 106 will be replicated in the MRAM stacks 110, 140, rather than each MRAM stack 110, 140 being specific to the digital bits stored within the latch 102.

[0030] Reference again Figure 2 , the user can perform the recovery operation without a reference voltage. To implement the recovery operation, the operator can precharge the bit line 130 and the bit line bar 132 to a high voltage state at the same time. Then, the word line 150 can also be set to a high voltage to allow access to the latch 102. In addition, the recovery transistor 122 can be set to be turned on (that is, RG is set to a high voltage), so that the spin Hall electrode 120 is grounded. At this time, the current will flow through the bit line 130, the diode 108 and the MRAM stack 110 and enter the spin Hall electrode 120 and reach the ground GND. Similarly, the current will also flow through the bit line bar 132, the diode 138, the MRAM stack 140, enter the spin Hall electrode 120 and reach the ground. After these processes are completed, the MRAM stack 110 will be in a resistance state opposite to that of the MRAM stack 140 (that is, higher or lower). This in turn causes the internal node 160 to be at a voltage level opposite to that of the node 162. This voltage ramp between 160 and 162 will be enforced by current flow in latch 102 , causing the latch to mimic the logic levels stored in MRAM cells 110 and 140 .

[0031] Reference now Figure 3, other embodiments of the present disclosure may structurally integrate the first diode 108 and / or the second diode 138 into other components (e.g., the first access transistor AT1 and the second access transistor AT2). In the circuit, when at least a threshold voltage is applied to the gate of the transistor, the channel region connecting the source and drain of the transistor may operate in the same manner as a diode. The first access transistor AT1 may include a first diode 108 between its source and drain terminals, so that the first diode 108 electrically couples the first inverter 104 to the first MRAM stack 110. Similarly, the second access transistor AT2 may include a second diode 138 between its source and drain terminals. Therefore, the second diode of the second access transistor 138 may electrically couple the second inverter 106 to the second MRAM stack 140. The gate of each access transistor MT1, MT2 may be coupled to a word line 150. The word line 150 may have a word line voltage V W , which can be adjusted between high and low values ​​to enable or disable current flow across access transistors AT1, AT2. When current flow across access transistors AT1, AT2 is enabled, an operator of structure 100 can selectively cause a write current I to be transmitted through spin Hall electrode 120. W , to copy data from latch 102 to MRAM stack 110, 140 (as previously described with reference to Figure 2 When current flow across the access transistors AT1, AT2 is disabled, the MRAM stack 110, 140 may be electrically isolated from the latch 102 when data is written to or read from the first latch and / or the second inverter 104, 106.

[0032] Reference now Figure 4 , embodiments of the present disclosure may provide MRAM stacks 110, 140 to store data from multiple latches 102 using one spin Hall electrode 120. In one such configuration, the structure 100 may include a first latch 102A, a second latch 102B, and a third latch 102C. The first latch 102A may be coupled to the spin Hall electrode 120 through a first group of MRAM stacks 110A, 140A. The latches 102B, 102C may similarly be coupled to the spin Hall electrode 120 through corresponding MRAM stack groups (110B and 140B, 110C and 140C). The structure 100 may optionally include more or less than three latches 102, Figure 4 Only three latches are shown in FIG. 1 to provide an example.

[0033] Each latch 102A, 102B, 102C may be configured as described herein. Figures 1 to 3The write current I is coupled to the corresponding component 134 (or coupled to the same component) in the same manner as in any of the figures to drive the operation of the latch 102. By transmitting the write current I through the spin Hall electrode 120 W , while also applying a voltage to the word line 150, the data in each latch 102A, 102B, 102C can be simultaneously copied in each MRAM stack 110A, 140A, 110B, 140B, 110C, 140C. In a further configuration, the structure 100 can include multiple spin Hall electrodes 120 and word lines 150, each of which is connected to a single group of latches 102 and MRAM stacks 110, 140. In this case, an operator of the structure 100 can select only one group of latches 102 to be switched by applying a voltage V W is applied to the word line 150 and the write current I W is applied to the spin Hall electrodes 120 to store digital bits in the corresponding MRAM stacks 110 , 140 .

[0034] Embodiments of the present disclosure provide various technical and commercial advantages, some of which are described herein as examples. As described herein, embodiments of structure 100 combine multiple forms of RAM (i.e., electrical and magnetic RAM) to replicate previously stored data in a manner that minimizes the penalty for the surface area and operating energy of the device. In addition, the use of spin Hall electrodes 120 allows the same combination of components to be used for checkpointing data entering MRAM stacks 110, 140 from latches 102, and for restoring checkpointed data to latches 102 after the device is restarted. Embodiments of the present disclosure can be easily integrated into popular circuit schemes, such as by inserting MRAM stacks 110, 140 and spin Hall electrodes 120 into electrical connections with word lines 150, or near the location of existing latches 102, where applicable. The use of the bistable MRAM stack 110, 140 specifically allows the electrically recorded "0" or "1" in the latch 102 to be replaced with the parallel or antiparallel magnetic moments of the second layer 114 or the fourth layer 144 with little risk of errors during checkpoint and restore operations.

[0035] The above method is used for the manufacture of integrated circuit chips. The resulting integrated circuit chips can be distributed by the manufacturer in raw wafer form (i.e., as a single wafer with multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case, the chip is mounted in the form of a single chip package (e.g., a plastic carrier whose leads are fixed to a motherboard or other higher-level carrier) or a multi-chip package (e.g., a ceramic carrier with surface interconnects and / or buried interconnects). In any case, the chip is then integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of (a) an intermediate product (e.g., a motherboard) or (b) a final product. The final product can be any product that includes an integrated circuit chip, from toys and other low-end applications to advanced computer products with displays, keyboards or other input devices, and central processing units.

[0036] The description of various embodiments of the present disclosure has been given for the purpose of illustration, but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The selection of terms used herein is intended to best explain the principles of the various embodiments, practical applications, or technical improvements to technologies found in the marketplace, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A circuit structure comprising: a latch having a first inverter and configured to store a digital bit; a first diode coupled to the first inverter of the latch; a first magnetic random access memory (MRAM) stack coupled to the first inverter of the latch through the first diode, the first magnetic random access memory stack comprising: a first layer and a second layer, each having a respective magnetic moment, wherein the magnetic moment of the second layer is adjustable between a parallel orientation and an antiparallel orientation relative to the magnetic moment of the first layer; a spin Hall electrode directly coupled to the first magnetic random access memory stack; a recovery transistor electrically coupled between the spin Hall electrode and ground; and A first additional transistor and a second additional transistor, the spin Hall electrode is connected between the first additional transistor and the second additional transistor to apply a write current through the spin Hall electrode, wherein the first additional transistor has one of a first source and a first drain connected to the spin Hall electrode, the other of the first source and the first drain connected to a first voltage line, and a first gate connected to a first SG line, wherein the second additional transistor has one of a second source and a second drain connected to the spin Hall electrode, the other of the second source and the second drain connected to a second voltage line, and a second gate connected to a second SG line, and wherein the first voltage line, the second voltage line, the first SG line, and the second SG line are independent of the output node of the first inverter and the first diode.

2. The circuit structure according to claim 1, wherein: The material composition of the second layer is configured to modulate a magnetic moment in response to an applied voltage.

3. The circuit structure of claim 1 , further comprising an access transistor coupled between the first inverter of the latch and the first layer of the first magnetic random access memory stack, wherein: The first diode extends across a source terminal and a drain terminal of the access transistor.

4. The circuit structure according to claim 1, wherein: The second layer of the first magnetic random access memory stack contacts the spin Hall electrode and covers the spin Hall electrode.

5. The circuit structure according to claim 1, wherein: The spin Hall electrode includes at least one metal having a density of at least about 5 g / cm3. 3 ).

6. The circuit structure according to claim 1, wherein: The latch includes a static random access memory (SRAM) circuit having the first inverter and a second inverter.

7. The circuit structure according to claim 6, further comprising: a second diode coupled to the second inverter; as well as a second magnetic random access memory stack coupled to the second inverter of the latch through the second diode, the second magnetic random access memory stack comprising: The third layer, and a fourth layer, which is located between the third layer and the spin Hall electrode, The third layer and the fourth layer each have their own magnetic moment, and the magnetic moment of the fourth layer is adjustable between a parallel orientation and an antiparallel orientation relative to the magnetic moment of the third layer.

8. The circuit structure according to claim 7, further comprising: a first access transistor coupled between the first inverter of the latch and the first layer of the first magnetic random access memory stack, wherein the first diode extends across a source terminal and a drain terminal of the first access transistor; a second access transistor coupled between the second inverter of the latch and the third layer of the second magnetic random access memory stack, wherein the second diode extends across a source terminal and a drain terminal of the second access transistor; and A word line is coupled to a gate terminal of the first access transistor and a gate terminal of the second access transistor.

9. A circuit structure comprising: a static random access memory (SRAM) cell having a first inverter configured to store a first logic voltage and a second inverter configured to store a second logic voltage; a first magnetic random access memory (MRAM) stack coupled to the first inverter of the SRAM cell through a first access transistor; a second magnetic random access memory stack coupled to the second inverter of the SRAM cell through a second access transistor, wherein each of the first magnetic random access memory stack and the second magnetic random access memory stack comprises: a first layer and a second layer, each having a respective magnetic moment, wherein the magnetic moment of the second layer is adjustable between a parallel orientation and an antiparallel orientation relative to the magnetic moment of the first layer in response to an applied voltage; a spin Hall electrode directly coupled to the first magnetic random access memory stack and the second magnetic random access memory stack; a recovery transistor electrically coupled between the spin Hall electrode and ground; and A first additional transistor and a second additional transistor, the spin Hall electrode is connected between the first additional transistor and the second additional transistor to apply a write current through the spin Hall electrode, wherein the first additional transistor has one of a first source and a first drain connected to the spin Hall electrode, the other of the first source and the first drain connected to a first voltage line, and a first gate connected to a first SG line, wherein the second additional transistor has one of a second source and a second drain connected to the spin Hall electrode, the other of the second source and the second drain connected to a second voltage line, and a second gate connected to a second SG line, and wherein the first voltage line, the second voltage line, the first SG line, and the second SG line are independent of the output node of the first inverter, the first access transistor, and the second access transistor.

10. The circuit structure according to claim 9, wherein: Each of the first magnetic random access memory stack and the second magnetic random access memory stack contacts the spin Hall electrode and covers the spin Hall electrode.

11. The circuit structure according to claim 9, wherein: The spin Hall electrode includes at least one metal having a density of at least about 5 g / cm3. 3 ).

12. The circuit structure of claim 9, further comprising a word line coupled to a gate terminal of the first access transistor and a gate terminal of the second access transistor, wherein: The word line selectively causes current to flow across the first access transistor and the second access transistor.

13. A method for recording data within an integrated circuit (IC) structure, the method comprising: A circuit structure is provided, the circuit structure comprising: a latch electrically coupled to another component of the IC structure and having a first inverter configured to store a digital bit; a first diode coupled to the first inverter; a first magnetic random access memory (MRAM) stack coupled to the first inverter of the latch through the first diode, the first magnetic random access memory stack comprising: a first layer having a first magnetic moment in a first orientation, and a second layer disposed on the first layer and having a second magnetic moment adjustable between the first orientation and a second orientation opposite the first orientation in response to an applied voltage; a spin Hall electrode directly coupled to the first magnetic random access memory stack; a recovery transistor electrically coupled between the spin Hall electrode and ground; and a first additional transistor and a second additional transistor, the spin Hall electrode being connected between the first additional transistor and the second additional transistor to apply a write current through the spin Hall electrode, wherein the first additional transistor has one of a first source and a first drain connected to the spin Hall electrode, the other of the first source and the first drain connected to a first voltage line, and a first gate connected to a first SG line, wherein the second additional transistor has one of a second source and a second drain connected to the spin Hall electrode, the other of the second source and the second drain connected to a second voltage line, and a second gate connected to a second SG line, and wherein the first voltage line, the second voltage line, the first SG line, and the second SG line are independent of an output node of the first inverter and the first diode, transmitting a read current from the first inverter of a memory cell to the first magnetic random access memory stack across the first diode; and A write current is transmitted across the spin Hall electrode, wherein transmitting the write current records the digital bit of the memory cell within the first magnetic random access memory stack.

14. The method according to claim 13, further comprising: disconnecting the memory cell from the other component of the IC structure; as well as The spin Hall electrode is electrically coupled to ground, wherein electrically coupling the spin Hall electrode to ground records the digital bit of the magnetic random access memory stack within the latch.

15. The method according to claim 13, wherein: Transmitting the read current across the first diode includes applying a voltage to an access transistor coupled between the first inverter of the memory cell and the first magnetic random access memory stack, wherein the first diode extends across a source terminal and a drain terminal of the access transistor. 16 . The method of claim 13 , further comprising transmitting a data current to the first inverter of the memory cell after transmitting the read current across the first diode. 17 . The method of claim 16 , further comprising transmitting a reference current to a portion of the latch simultaneously with transmitting the read current across the first diode.

18. The method according to claim 13, wherein: The first magnetic random access memory stack of the provided circuit is one of a plurality of magnetic random access memory stacks, each magnetic random access memory stack being coupled to the spin Hall electrode and a corresponding latch of the memory cell, and wherein transmitting the write current records a plurality of digital bits from the plurality of latches within the plurality of magnetic random access memory stacks.

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