Method for manufacturing a semiconductor device

Abstract

Provided is a method for manufacturing a semiconductor device capable of suppressing inflow of solder. A method for manufacturing a semiconductor device includes: a step of forming a thermosetting resin film on a first metal layer; a step of forming an opening portion in the resin film; a step of forming a second metal layer covering a region from an upper surface of the first metal layer exposed from the opening portion of the resin film to an upper surface of the resin film; a step of performing heat treatment at a temperature higher than a temperature at which the resin film is cured, after the step of forming the second metal layer; a step of forming a cover film covering an upper surface of the resin film and a side surface of the second metal layer, after the step of performing heat treatment; and a step of forming solder on an upper surface of the second metal layer exposed from the opening portion of the cover film, after the step of forming the cover film.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a manufacturing method of a semiconductor device. BACKGROUND

[0002] In order to mount a semiconductor device on a substrate or the like in a flip-chip manner, a package of a ball grid array (BGA) is sometimes used. A solder ball is formed on such a semiconductor device. A semiconductor device having a solder bump on an electrode formed of a plurality of metal films including a reinforcing layer is described, for example, in Patent Literature 1.

[0003] In order to suppress diffusion of solder to a wiring layer, a metal layer (under bump metal, UBM) is sometimes provided on the wiring layer, and a solder ball is provided thereon. In addition, in order to protect a semiconductor layer from moisture or the like, an insulating film formed of polyimide or the like, for example, is provided on the semiconductor layer.

[0004] PRIOR ART DOCUMENTS

[0005] PATENT LITERATURE

[0006] [Patent Literature 1] Japanese Patent Application Publication No. 2006-120803 SUMMARY

[0007] PROBLEMS TO BE SOLVED BY THE INVENTION

[0008] Since the coefficient of thermal expansion of the metal layer and the coefficient of thermal expansion of the insulating film are different, a temperature change at the time of providing the solder ball can cause a decrease in adhesion of the metal layer and the insulating film. A gap is sometimes generated between the metal layer and the insulating film. Solder sometimes flows into the gap and reaches the wiring layer. Migration of the solder and the wiring layer occurs, and the reliability of the semiconductor device decreases. Therefore, an object is to provide a manufacturing method of a semiconductor device capable of suppressing inflow of solder.

[0009] MEANS FOR SOLVING THE PROBLEMS

[0010] The method for manufacturing a semiconductor device disclosed herein includes: a step of forming a thermosetting resin film on a first metal layer; a step of forming an opening in the resin film; a step of forming a second metal layer, the second metal layer covering a region from the upper surface of the first metal layer exposed from the opening in the resin film to the upper surface of the resin film; a step of performing heat treatment at a temperature above the curing temperature of the resin film after the step of forming the second metal layer; a step of forming a cover film after the step of performing heat treatment, the cover film covering the upper surface of the resin film and the side surface of the second metal layer; and a step of forming solder on the upper surface of the second metal layer exposed from the opening in the cover film after the step of forming the cover film.

[0011] Invention Effects

[0012] According to this disclosure, the inflow of solder can be suppressed. Attached Figure Description

[0013] [ FIG. 1A ] FIG. 1A The following is a top view of a semiconductor device according to an example embodiment.

[0014] [ FIG. 1B ] FIG. 1B For along FIG. 1A A cross-sectional view of line AA.

[0015] [ FIG. 2A ] FIG. 2A The following is a cross-sectional view illustrating a semiconductor device manufacturing method.

[0016] [ FIG. 2B ] FIG. 2B The following is a cross-sectional view illustrating a semiconductor device manufacturing method.

[0017] [ FIG. 2C ] FIG. 2C The following is a cross-sectional view illustrating a semiconductor device manufacturing method.

[0018] [ FIG. 2D ] FIG. 2D The following is a cross-sectional view illustrating a semiconductor device manufacturing method.

[0019] [ FIG. 3A ] FIG. 3A The following is a cross-sectional view illustrating a semiconductor device manufacturing method.

[0020] [ FIG. 3B ] FIG. 3B The following is a cross-sectional view illustrating a semiconductor device manufacturing method.

[0021] [ FIG. 3C ] FIG. 3CThe following is a cross-sectional view illustrating a semiconductor device manufacturing method.

[0022] [ FIG. 4 ] FIG. 4 A cross-sectional view of the manufacturing method of the semiconductor device involved in the comparative example is shown. Detailed Implementation

[0023] [Description of Implementation Methods of this Disclosure]

[0024] First, the implementation methods of this disclosure will be described.

[0025] One aspect of this disclosure is (1) a method for manufacturing a semiconductor device, comprising: a step of forming a thermosetting resin film on a first metal layer; a step of forming an opening in the resin film; a step of forming a second metal layer, the second metal layer covering a region from the upper surface of the first metal layer exposed from the opening in the resin film to the upper surface of the resin film; a step of performing heat treatment at a temperature above the curing temperature of the resin film after the step of forming the second metal layer; a step of forming a cover film after the step of performing heat treatment, the cover film covering the upper surface of the resin film and the side surface of the second metal layer; and a step of forming solder on the upper surface of the second metal layer exposed from the opening in the cover film after the step of forming the cover film. The heat treatment creates a gap between the second metal layer and the resin film. By blocking the gap with the cover film, the inflow of solder can be suppressed during the solder formation step.

[0026] (2) The resin film may be a polyimide film. Due to heat treatment, the resin film shrinks, forming a gap between the resin film and the second metal layer. By sealing the gap with a cover film, the inflow of solder can be suppressed.

[0027] (3) The process of forming the second metal layer may include: forming a third metal layer, the third metal layer covering the region from the upper surface of the first metal layer exposed from the opening of the resin film to the upper surface of the resin film; and forming a fourth metal layer, the fourth metal layer covering the region from the upper surface of the third metal layer to the upper surface of the resin film, specifically the outer portion of the third metal layer. The second metal layer, comprising the third metal layer and the fourth metal layer, functions as a barrier layer to inhibit solder diffusion into the first metal layer.

[0028] (4) The first metal layer may contain gold, the third metal layer may contain palladium, and the process of forming the fourth metal layer may be a process of forming the fourth metal layer containing nickel by chemical plating. The second metal layer, comprising the third and fourth metal layers, functions as a barrier layer to inhibit solder diffusion into the first metal layer. Due to heat treatment, the fourth metal layer is subjected to stress, reducing its adhesion to the resin film. The use of a cover film can inhibit solder inflow.

[0029] (5) The solder wettability of the covering film can be lower than that of the second metal layer. This can effectively suppress solder inflow.

[0030] (6) The process of forming the cover film may be a process of forming the cover film covering the area from the upper surface of the resin film to the upper surface of the second metal layer. The cover film is not easy to peel off and can effectively suppress the inflow of solder.

[0031] (7) The temperature during the heat treatment process can be above the melting point of the solder. By performing heat treatment at a temperature above the melting point of the solder before the solder formation process, a gap is pre-formed between the second metal layer and the resin film. During the solder ball formation process, the cover film is less susceptible to stress. By blocking the gap with the cover film, the inflow of solder can be suppressed.

[0032] [Details of the implementation of this disclosure]

[0033] Hereinafter, specific examples of a method for manufacturing a semiconductor device according to embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be noted that the present disclosure is not limited to these examples, but is defined by the claims and is intended to include all modifications within the meaning and scope equivalent to the claims.

[0034] (Semiconductor devices)

[0035] FIG. 1A A top view of the semiconductor device 100 according to an example embodiment is shown. FIG. 1A As shown, the semiconductor device 100 is a BGA-type semiconductor device having a plurality of solder balls 22 disposed on the surface of a substrate 10. The plurality of solder balls 22 are arranged in a grid on one surface of the substrate 10 and are pads for electrical connection between the semiconductor device 100 and an external device.

[0036] FIG. 1B For along FIG. 1A The cross-sectional view of line AA. (See diagram below.) FIG. 1B As shown, the semiconductor device 100 includes a substrate 10, a semiconductor layer 12, an insulating film 13, a resin film 16, a wiring layer 14 (first metal layer), a UBM 19 (second metal layer), a cover film 20, and solder balls 22.

[0037] The substrate 10 is an insulating substrate, for example, formed of an insulator such as silicon carbide (SiC) or sapphire. A semiconductor layer 12 is disposed on the upper surface of the substrate 10. The semiconductor layer 12 includes, for example, a channel layer of gallium nitride (GaN) and an electron supply layer of aluminum gallium nitride (AlGaN), and a field-effect transistor (FET) is formed thereon.

[0038] The insulating film 13 is, for example, an inorganic insulating film such as silicon nitride (SiN) with a thickness of 0.1 μm to 0.5 μm, or an organic insulating film such as polyimide, and is a passivation film covering the upper surface of the semiconductor layer 12.

[0039] A wiring layer 14 is disposed on the upper surface of the insulating film 13, and is formed of a metal such as gold (Au). The insulating film 13 has an opening (not shown) through which the wiring layer 14 is electrically connected to the semiconductor layer 12.

[0040] A resin film 16 is disposed on the upper surface of the insulating film 13, and is an interlayer film formed, for example, of a thermosetting resin such as polyimide or benzocyclobutene (BCB) with a thickness of 5 μm. The resin film 16 has an opening 16a on the wiring layer 14.

[0041] The UBM19 has a base layer 17 (third metal layer) and a plating layer 18 (fourth metal layer). The base layer 17, for example, has a thickness of 15 nm and is a stack of titanium (Ti) and palladium (Pd) layers. The base layer 17 is disposed on the upper surface of the wiring layer 14 exposed from the opening 16a, the inner wall of the opening 16a, and the upper surface of the resin film 16, in the portion near the opening 16a. The plating layer 18 is formed, for example, by chemical plating, and is formed of nickel-phosphorus (Ni-P) or the like with a thickness of 3.5 nm. It is disposed on the upper surface and side surfaces of the base layer 17, and is also disposed on the resin film 16 with a gap 15 in between. A gap 15 is formed between the lower surface of the UBM19 and the upper surface of the resin film 16.

[0042] The cover film 20 covers the upper surface of the resin film 16, the side surface of the UBM 19, and the periphery of the upper surface of the UBM 19. The cover film 20 surrounds the UBM 19 and the gap 15, and blocks the gap 15. The cover film 20 can be formed, for example, of metals such as zinc (Zn), chromium (Cr), nickel-chromium alloy (Ni / Cr), titanium (Ti), molybdenum (Mo), aluminum (Al), and iron (Fe), and oxides of these metals; it can also be formed of insulators such as SiN or SiO2, or resins such as polyimide. The thickness T1 of the cover film 20 is sufficient to block the gap 15. For example, the thickness T1 of a polyimide cover film 20 is 5 μm. For example, the thickness T1 of a metal or insulator cover film 20 is 1.5 μm. The polyimide cover film 20 covers the space between multiple UBMs 19, and the width W1 of the portion of the cover film 20 in contact with the resin film 16 is, for example, 200 μm. The width W1 of the cover film 20, which is made of metal or insulator, is, for example, 1.5 μm. The width W2 of the portion of the cover film 20 that contacts the plating layer 18 is, for example, 1.5 μm. The cover film 20 has an opening 20a.

[0043] The solder ball 22 is formed of metals such as tin-gold alloy (Sn-Au), tin-silver alloy (Sn-Ag), and tin-silver-copper alloy (Sn-Ag-Cu). The solder ball 22 is in contact with the upper surface of the plating 18 of UBM19 exposed from the opening 20a of the cover film 20.

[0044] (Manufacturing method)

[0045] FIGS. 2A-3C This is a cross-sectional view illustrating a manufacturing method of a semiconductor device 100, showing a method similar to... FIG. 1B The corresponding cross section. In FIG. 2A Prior to the process, a semiconductor layer 12 is epitaxially grown on the upper surface of the substrate 10 using a method such as Metal-Organic Chemical Vapor Deposition (MOCVD). An insulating film 13 of SiN is formed on the upper surface of the semiconductor layer 12 using a method such as Chemical Vapor Deposition (CVD).

[0046] like FIG. 2A As shown, a wiring layer 14 is formed on the upper surface of the insulating film 13 through electroplating or other processes. FIG. 2B As shown, a resin film 16 is formed on the upper surface of the insulating film 13. FIG. 2CAs shown, a photosensitive photoresist is applied to the upper surface of the resin film 16, the photoresist is patterned, and a photoresist mask 24 is provided. The resin film 16 is etched using the photoresist mask 24 to form an opening 16a on the resin film 16. The wiring layer 14 is exposed from the opening 16a. After etching, the photoresist mask 24 is removed.

[0047] like FIG. 2D As shown, the substrate layer 17 is formed near the opening 16a in the section from the upper surface of the wiring layer 14 to the upper surface of the resin film 16 by vacuum evaporation and stripping. FIG. 3A As shown, for example, a plating layer 18 is formed by chemical plating using a substrate layer 17 as a seed metal. The plating layer 18 is disposed on the portion outside the substrate layer 17 extending from the upper surface of the substrate layer 17 to the upper surface of the resin film 16. The substrate layer 17 and the plating layer 18 are in contact with the upper surface of the resin film 16.

[0048] After the coating 18 is formed, a heat treatment is performed, for example, by maintaining the temperature at 350°C for 30 minutes. Since the resin film 16 is a thermosetting resin such as polyimide, it shrinks due to the heat treatment. The coating 18 is subjected to stress, and the adhesion between the UBM 19 and the resin film 16 decreases. As a result, such as FIG. 3B As shown, a gap 15 is created between UBM19 and resin film 16.

[0049] like FIG. 3C As shown, after heat treatment, a cover film 20 is formed by vacuum evaporation-stripping or plating. The cover film 20 covers the outer peripheral region from the upper surface of the resin film 16 to the upper surface of the plating layer 18 and blocks the gaps 15. The upper surface of the plating layer 18 is exposed through the opening 20a of the cover film 20.

[0050] After the cover film 20 is applied, flux is applied to the upper surface of the plating layer 18 exposed from the opening 20a. Solder paste is applied to the upper surface of the plating layer 18, and the temperature is raised to, for example, above the melting point of the solder, such as 260°C, and a reflow soldering process is performed. Solder balls 22 are formed on the plating layer 18 by the reflow soldering process. The semiconductor device 100 is formed through the above processes.

[0051] (Comparative Example)

[0052] FIG. 4 A cross-sectional view is shown in the comparative example illustrating the manufacturing method of the semiconductor device involved. The comparative example also includes... FIGS. 2A-3A The process involves reflow soldering after the formation of UBM19, without heat treatment or the formation of the cover film 20. FIG. 4As shown, solder balls 22 are formed. During the reflow soldering process, the temperature is raised to 260°C, which is above the melting point of the solder. Due to the difference in the coefficients of thermal expansion between UBM19 and the resin film 16, the plating layer 18 of UBM19 is subjected to stress. Due to the stress, a gap 26 is generated between the plating layer 18 and the resin film 16. Therefore, the function of the plating layer 18 as a barrier layer against the solder is reduced.

[0053] like FIG. 4 As indicated by the arrows, a portion of the molten solder flows into gap 26, for example, diffusing through substrate 17 to wiring layer 14. Additionally, it penetrates into wiring layer 14, for example, from the interface between substrate 17 and resin film 16. The solder reacts with Au in wiring layer 14, causing migration. As a result, the lifespan of the semiconductor device is shortened.

[0054] In contrast, according to this embodiment, UBM19 is disposed in the region from the upper surface of wiring layer 14 to the upper surface of resin film 16, and then heat treatment is performed. Since resin film 16 is a thermosetting resin such as polyimide, it shrinks due to heat treatment, thus pre-forming a gap 15 between resin film 16 and UBM19. After heat treatment, a cover film 20 is disposed covering the sides of UBM19, and solder balls 22 are formed. By using the cover film 20 to block the gap 15 generated by heat treatment, the inflow of solder into the gap 15 can be suppressed. As a result, the migration of solder to wiring layer 14 can also be suppressed. The degradation of the lifespan of semiconductor device 100 is suppressed.

[0055] A gap 15 is pre-formed between the resin film 16 and the UBM 19 through heat treatment. During the reflow soldering process, stress on the cover film 20 can be suppressed when the temperature rises, and peeling and damage to the cover film 20 can be suppressed. The resin film 16 is formed of resin such as polyimide and is a protective film that protects the semiconductor device 100 from the influence of moisture and other factors.

[0056] UBM19 functions as a barrier layer to inhibit solder diffusion into wiring layer 14. For example, UBM19 comprises a substrate layer 17 and a plating layer 18 stacked sequentially. To improve solder barrier properties, the substrate layer 17 preferably contains Pd, and the plating layer 18 preferably contains Ni. The plating layer 18, for example, is a Ni-Pd film formed by electroless plating, which is denser than a metal layer formed by vapor deposition and thus has high performance as a barrier layer.

[0057] On the other hand, the coating 18 is in contact with the upper surface of the resin film 16 (see...). FIG. 3AFurthermore, the coefficient of thermal expansion of the plating layer 18 differs from that of the resin film 16. Therefore, the plating layer 18 is subjected to stress due to temperature changes. Large stresses are generated in the plating layer 18, which is a chemically plated Ni-P plating layer, making it easier for the adhesion to the polyimide resin film 16 to decrease. According to the embodiment, since the side surface of the plating layer 18 is covered by the cover film 20, solder inflow can be suppressed. The base layer 17 can be formed of metals other than Pd, such as Cu. The plating layer 18 can be formed of metals other than Ni, such as a nickel-gold laminate (Ni / Au) or a nickel-silver laminate (Ni / Ag). Alternatively, a Ti / NiV / Ag layer obtained by sputtering can be used instead of the plating layer 18.

[0058] Solder wettability is preferably improved by applying flux to the surface of plating layer 18 and removing the oxide film on the surface before reflow soldering. Solder wettability can be improved by forming a film of a metal with higher solder wettability than Ni, such as Au, on the surface of plating layer 18. However, if the solder wettability at the interface between plating layer 18 and the base layer 17 becomes high, solder intrusion may occur. By using a metal with low solder wettability, such as Ni, for plating layer 18 and applying flux to the surface of plating layer 18, both improved solder wettability and suppression of solder intrusion can be achieved. It should be noted that wettability here can be evaluated by the angle (contact angle) of the area where the solder mounting surface intersects with the solder surface. A larger angle indicates lower wettability, and a smaller angle indicates higher wettability.

[0059] The solder has a melting point of, for example, below 250°C, and the temperature during reflow soldering is set to 260°C, above the melting point. The temperature during heat treatment is above the melting point of the solder. During heat treatment, for example, for a duration of 20 to 40 minutes, the temperature is set to 300°C to 400°C. The temperature can also be 350°C to 400°C. By raising the temperature during heat treatment to above the reflow soldering temperature, a gap 15 can be pre-formed between UBM19 and the resin film 16. By blocking the gap 15 with the cover film 20, solder inflow can be suppressed. Due to the heat treatment, a portion of UBM19 has already peeled off from the resin film 16, so peeling is less likely to occur during reflow soldering. Therefore, the cover film 20 is less likely to be stressed during reflow soldering.

[0060] The adhesion between the cover film 20 and the resin film 16 is preferably higher than that between UBM 19 and the resin film 16. The solder wettability of the cover film 20 is preferably lower than that of, for example, UBM 19. For example, the cover film 20 is formed of, for example, Zn, Cr, Ti, Mo, Al and Fe, or an alloy containing at least one of these metals. Solder does not easily spread onto the surface of the cover film 20, and solder inflow and short circuits between the plurality of solder balls 22 are suppressed. In order to suppress the loss of electrical signals, the resistance of the cover film 20 is preferably higher than that of, for example, UBM 19, wiring layer 14 and solder balls.

[0061] The cover film 20 covers the upper surface of the resin film 16, the sides and the upper surface of the UBM 19. Because the cover film 20 is applied to the upper surface of the UBM 19, it is not easily peeled off and effectively inhibits solder flow. Preferably, the cover film 20 completely surrounds the UBM 19.

[0062] The pads of the semiconductor device 100 can be configured as follows: FIG. 1A Such a BGA can also be configured in ways other than BGA. The substrate 10 is formed of an insulator such as SiC, silicon (Si), sapphire, or GaN. The semiconductor layer 12 is a compound semiconductor layer formed, for example, of a nitride semiconductor or an arsenic semiconductor. A nitride semiconductor refers to a nitrogen-containing (N) semiconductor, such as GaN, AlGaN, indium gallium nitride (InGaN), indium nitride (InN), and aluminum indium gallium nitride (AlInGaN). An arsenic semiconductor refers to an arsenic-containing (As) semiconductor, such as gallium arsenide (GaAs). Semiconductor devices other than FETs can also be formed in the semiconductor layer 12.

[0063] The embodiments of the present disclosure have been described in detail above. However, the present disclosure is not limited to this specific embodiment and various modifications and alterations can be made within the scope of the spirit of the present disclosure as stated in the claims.

[0064] Symbol Explanation

[0065] 10 substrate

[0066] 12 Semiconductor Layers

[0067] 13 Insulating film

[0068] 14 Wiring Layer

[0069] 15, 26 gap

[0070] 16 Resin film

[0071] 16a Opening

[0072] 17. Basal layer

[0073] 18 Coatings

[0074] 19 UBM

[0075] 20 Covering film

[0076] 22 welding balls

[0077] 24 Resist Mask

[0078] 100 Semiconductor Devices

Claims

1. A method for manufacturing a semiconductor device, comprising: The process of forming a thermosetting resin film on the first metal layer; The process of forming an opening in the resin film; The process of forming a second metal layer, wherein the second metal layer covers the area from the upper surface of the first metal layer exposed from the opening of the resin film to the upper surface of the resin film; A heat treatment process performed at a temperature above the temperature at which the resin film is cured, following the process of forming the second metal layer; After the heat treatment process, a process of forming a cover film is performed, wherein the cover film covers from the upper surface of the resin film to the side surface of the second metal layer, thereby covering the gap between the resin film and the second metal layer; and Following the process of forming the cover film, a process of forming solder on the upper surface of the second metal layer exposed from the opening of the cover film. The temperature during the heat treatment process is above the melting point of the solder.

2. The method for manufacturing a semiconductor device as claimed in claim 1, wherein, The resin film is a polyimide film.

3. The method for manufacturing a semiconductor device as claimed in claim 1 or claim 2, wherein, The process of forming the second metal layer includes: The process of forming a third metal layer, wherein the third metal layer covers the area from the upper surface of the first metal layer exposed from the opening of the resin film to the upper surface of the resin film; and The process of forming a fourth metal layer, the fourth metal layer covering the region of the outer portion of the third metal layer from the upper surface of the third metal layer to the upper surface of the resin film.

4. The method for manufacturing a semiconductor device as claimed in claim 3, wherein, The first metal layer contains gold. The third metal layer comprises palladium, and The process of forming the fourth metal layer is a process of forming the fourth metal layer containing nickel by chemical plating.

5. The method of manufacturing a semiconductor device as claimed in claim 1 or claim 2, wherein, The solder wettability of the cover film is lower than that of the solder wettability of the second metal layer.

6. The method of manufacturing a semiconductor device as claimed in claim 1 or claim 2, wherein, The covering film is formed of a metal, an oxide of the metal, an insulator, or a resin, wherein the metal is at least one of zinc (Zn), chromium (Cr), nickel-chromium alloy (Ni / Cr), titanium (Ti), molybdenum (Mo), aluminum (Al), and iron (Fe), the insulator is SiN or SiO2, and the resin is polyimide.

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