Protective elements for joint structures

Abstract

A bonding structure is disclosed, which may include a semiconductor element having an active circuit system. The bonding structure may include a protective element that is directly bonded to the semiconductor element along a bonding surface without adhesive. The protective element may include a barrier material disposed over at least a portion of the active circuit system. The barrier material may be configured to block external access to the active circuit system. The bonding structure may include an interruption structure configured to interrupt the function of at least a portion of the active circuit system once the protective element is peeled off from the semiconductor element.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to U.S. Nonprovisional Patent Application No. 16 / 844,941, filed April 9, 2020; U.S. Provisional Patent Application No. 62 / 851,512, filed May 22, 2019; U.S. Provisional Patent Application No. 62 / 953,071, filed December 23, 2019; U.S. Provisional Patent Application No. 62 / 833,491, filed April 12, 2019; and U.S. Provisional Patent Application No. 62 / 953,058, filed December 23, 2019, the contents of each of which are incorporated herein by reference in their entirety and used for all purposes. Technical Field

[0003] The art relates to protective or blocking elements for bonding structures, and more specifically, to interruption structures configured to interrupt the function of an active circuit system once the protective element is delaminated or reverse engineered. Background Technology

[0004] Semiconductor chips (e.g., integrated device dies) may include active circuit systems with security-sensitive components, which may include valuable and / or proprietary information, structures, or devices. For example, such security-sensitive components may include an entity's intellectual property, software or hardware security (e.g., encryption) features, privacy data, or any other components or data that the entity may wish to keep secure and hidden from third parties. For instance, malicious third parties may utilize various techniques to attempt to access security-sensitive components to gain economic and / or geopolitical advantages. Therefore, there remains a continuous need to improve the security of semiconductor chips to prevent third-party access. Attached Figure Description

[0005] Figure 1 A schematic side cross-sectional view is shown, including protective elements that are bonded (e.g., directly bonded) to semiconductor elements, and possible chemical attack paths for stripping or damaging sensitive circuit systems.

[0006] Figure 2A A schematic side cross-sectional view of the protective element is shown.

[0007] Figure 2B It shows Figure 1 A schematic side cross-sectional view of the bonding structure in the diagram, without showing the chemical attack path.

[0008] Figure 2C yes Figure 2B A top view of the joint structure.

[0009] Figure 3 This is a schematic side view of the protective elements and semiconductor elements prior to bonding, according to various embodiments.

[0010] Figure 4 This is a schematic side view of the protective element and semiconductor element before bonding, according to another embodiment.

[0011] Figures 5A-5B A schematic side cross-sectional view of the joining structure according to different embodiments is shown.

[0012] Figure 6A This is a schematic side cross-sectional view of the joining structure according to another embodiment.

[0013] Figure 6B yes Figure 6A An enlarged view of a portion of the joining structure shown.

[0014] Figure 7 This is a schematic side cross-sectional view of a protective element according to various embodiments.

[0015] Figure 8 This is a schematic diagram of an electronic system including one or more bonding structures according to an embodiment. Detailed Implementation

[0016] As described in this article, third parties (e.g., malicious third parties) can attempt to access security-sensitive components on devices such as integrated device dies. In some components, security-sensitive components are protected by network lists and non-volatile memory (NVM) data. However, third parties can attempt to illegally access security-sensitive components using a combination of destructive and non-destructive techniques, such as probing and / or de-layering the component to expose it or otherwise gaining access. In some cases, third parties may attempt to illegally access security-sensitive components by: pulsed electromagnetic (EM) waves onto the active circuitry of the component, using fault injection techniques, employing near-infrared triggering or focused ion beam (FIB) modification of the circuitry, chemical etching techniques, and other physical, chemical, and / or electromagnetic intrusion tools, and even reverse engineering. These techniques can be used to physically access the sensitive circuitry of microdevices such as integrated circuits to directly read encrypted information, trigger circuits from the outside to release otherwise encrypted information, learn about the manufacturing process, or even extract enough information to ultimately replicate the sensitive design. For example, in some cases, an unauthorized intruder can attempt to access an encryption key, which may be stored in the circuit design, memory, or a combination of both. Techniques can also be used to indirectly read sensitive information: analyzing outputs based on fault-injected inputs, and determining encryption keys or data content through recursive analysis. Structurally protecting security-sensitive components on building blocks is challenging.

[0017] Therefore, it is important to provide improved security for components that include safety-sensitive parts, such as semiconductor integrated dies.

[0018] One way to physically protect chips from such unauthorized access is to provide materials that are difficult to remove or penetrate by grinding, polishing, chemical etching, or other techniques. However, some such materials (e.g., abrasive materials) may have processing temperatures too high for application to the manufactured semiconductor devices, which have strict thermal budgets after manufacturing. The processing of some materials may be chemically incompatible with typical semiconductor processing foundries. Barrier materials may not be used or found in standard semiconductor processing foundries, and / or barrier materials may be processed using non-standard methods.

[0019] The various embodiments disclosed herein may utilize a chip or chiplet having a protective element 3 (also referred to herein as a barrier element) comprising, for example, a safety or barrier material 4 that protects the sensitive circuit region to which it is bonded (also referred to herein as a sensitive circuit system). Figure 1This is a schematic side cross-sectional view of the bonding structure 1, which includes a protective element 3 bonded (e.g., directly bonded) to a semiconductor element 2, and a possible chemical supply path P for stripping or damaging the sensitive circuit system. Figure 2A This is a schematic side cross-sectional view of protective element 3. Figure 2B yes Figure 1 A schematic side cross-sectional view of the joint structure 1, without showing the chemical supply path. Figure 2C yes Figure 2B Top view of the joint structure 1.

[0020] In some embodiments, the barrier material 4 may include a physically destructive material (e.g., an abrasive and / or hard material) configured to: physically damage or destroy a tool attempting to access the sensitive circuit system 6, physically damage or destroy the sensitive circuit system 6 itself, or otherwise prevent physical or mechanical access to the sensitive circuit system 6. In some embodiments, the barrier material 4 may include a light-blocking material configured to block incident electromagnetic radiation (e.g., infrared radiation, such as near-infrared light) from entering the sensitive circuit system 6.

[0021] In some embodiments, the barrier material 4 may include a light-blocking material that is also a destructive material, such that the barrier material can prevent physical and electromagnetic access to the sensitive circuit system 6. In some embodiments, the barrier material 4 may include a light-blocking material that is not a destructive material. In other embodiments, the barrier material 4 may include a destructive material that is not a light-blocking material. In some embodiments, the barrier material 4 may include a light-scattering, light-diffusing, or light-filtering material.

[0022] In embodiments utilizing a destructive material for the barrier material 4, the barrier material 4 may include, for example, diamond-based materials such as synthetic diamond, diamond-like carbon, or industrial diamond, tungsten, synthetic fibers, carbides (e.g., silicon carbide, tungsten carbide, boron carbide), borides (e.g., tungsten boride, rhenium boride, boron aluminum magnesium bromide, etc.), boron nitride, nitrogen carbide, sapphire, and certain types of ceramics and other suitable destructive materials or combinations thereof, which may be disposed adjacent to the bonding interface 8. In some embodiments, particles of these destructive materials may be dispersed in a mixture to form the barrier material 4. In various embodiments, the barrier material 4 may be an unpatterned and / or overlay material layer compared to a patterned layer. For example, the barrier layer 4 may include an overlay layer over the entire protective element 3, or an overlay layer over a sensitive region 6 of the circuit system to be protected. A bonding layer 5 (e.g., a semiconductor material or an inorganic dielectric) may be disposed over the overlay layer of the barrier material 4. As explained herein, the barrier material 4 can be directly bonded to the semiconductor element 2 without an adhesive to form a bonding structure 1 in various arrangements. As explained herein, the semiconductor element 2 can include any suitable type of semiconductor element, such as an integrated device die, an interposer, a semiconductor wafer, a reconfigured wafer, etc. The selected barrier material 4 can have a high shear modulus, a high bulk modulus, and can not exhibit plastic deformation. For example, a material having a hardness of at least 80 GPa (e.g., as measured on the Vickers hardness scale) can be used as the destructive material. In various embodiments, the destructive material can have a hardness of at least 12 GPa, at least 13 GPa, at least 15 GPa, at least 20 GPa, at least 30 GPa, or at least 50 GPa, as measured on the Vickers hardness scale. For example, the hardness of the destructive material can be in the range of 12.5 GPa to 150 GPa, 13 GPa to 150 GPa, 15 GPa to 150 GPa, 20 GPa to 150 GPa, 40 GPa to 150 GPa, or 80 GPa to 150 GPa, as measured on the Vickers hardness scale. In another embodiment, the abrasive or destructive material can have a higher hardness than typical materials used in semiconductor chips. For example, the hardness of the destructive material can be higher than that of materials such as Si, SiO, SiN, SiON, and SiCN. In some embodiments, the barrier material 4 may comprise one or more materials or layers deposited stacked on top of each other. Furthermore, the barrier material 4 may comprise continuous, discontinuous, or patterned layers, or the barrier material 4 may comprise several such continuous, discontinuous, or patterned layers. In some embodiments, there may be no circuitry or wiring within the barrier material 4.In other embodiments, the barrier material 4 may include a circuit system embedded in the material 4, or a conductive via that partially or completely penetrates the barrier material 4.

[0023] Barrier or protective element 3, (e.g., a chip or chiplet) can be directly bonded (e.g., using dielectric-to-dielectric bonding technology, such as that of Xperi in San Jose, California). The protective element 3 is directly bonded or co-bonded to element 2 (e.g., a semiconductor chip or integrated device die) to at least a sensitive region 6 (e.g., a region including security-sensitive components) of element 2, which can benefit from a high level of security protection against third-party tampering. For example, the dielectric-to-dielectric connection can be formed without adhesives using direct bonding techniques disclosed in at least U.S. Patent Nos. 9,391,143 and 10,434,749, the entire contents of each of which are incorporated herein by reference in their entirety and for all purposes. After the protective element 3 is directly or co-bonded to element 2 (e.g., a semiconductor chip or integrated device die), one or more layers of barrier material 4 (which may include destructive or abrasive materials, light-blocking materials, light-scattering materials, light-filtering materials, or light-diffusing materials, etc.) may be positioned near the bonding interface 8, for example, as close as possible to the bonding interface 8. In one embodiment, the barrier material 4 may be located less than 50 micrometers, less than 25 micrometers, or less than 10 micrometers from the bonding interface 8, for example, less than 5 micrometers from the bonding interface 8. In various embodiments, the barrier material 4 may be located within a range of about 1 micrometer to about 10 micrometers, or about 1 micrometer to about 5 micrometers, from the bonding interface 8. In other embodiments, two or more barrier or protective elements 3 are directly bonded to element 2.

[0024] In various embodiments, the direct-bonded structure can be formed directly without the use of intermediate adhesives. For example, the protective element 3 and the semiconductor element 2 may each have a bonding layer (e.g., bonding layer 5) associated with the dielectric bonding surfaces 9, 10. The respective dielectric bonding surfaces 9, 10 in the protective element 3 and the semiconductor element 2 may be polished to a high smoothness. The respective bonding surfaces 9, 10 may be cleaned and exposed to plasma and / or suitable chemicals (e.g., etchants) to activate the surfaces. In some embodiments, surfaces 9, 10 may terminate with a substance after activation or during activation (e.g., during plasma and / or chemical processes). In various embodiments, the terminating substance may include nitrogen. Furthermore, in some embodiments, bonding surfaces 9, 10 may be exposed to fluorine. For example, one or more fluorine peaks may be present near the layer and / or bonding interface 8. Thus, in the direct-bonded structure 1 disclosed herein, the bonding interface 8 between the two dielectric materials may include a smooth interface with a high nitrogen content and / or fluorine peaks at the bonding interface 8.

[0025] In various embodiments, direct bonding of the separately manufactured protective element 3 facilitates the use of separate processes that are difficult to apply directly to the manufactured integrated circuits or sensitive microelectronic components due to thermal budget, chemical compatibility constraints, or other technical reasons. For example, the barrier material 4 can be formed on the separate protective element 3 at a temperature higher than the direct bonding temperature. The direct bonding process itself consumes a relatively small thermal budget, including room-temperature initial covalent bonding between dielectric bonding layers and possible annealing to enhance bonding and / or promote metal bonding in hybrid bonding processes.

[0026] In some embodiments, if a third party attempts to remove destructive material (e.g., abrasive material and / or hard material), the removal tool may be damaged (by the abrasive material or the obstructing material) and / or the underlying active circuitry may be removed in an attempt to damage it. Therefore, obstructing material 4 may be "destructive" to the removal tool or the protected circuitry. Either result can introduce significant resistance to: full reverse engineering, unauthorized intrusion, inspection, or other breaches of the secure area, circuitry, or equipment.

[0027] In some embodiments, the barrier material 4 may include an abrasive and / or destructive layer on the chiplet. Additionally or optionally, the chiplet itself may include an abrasive and / or destructive material, and / or a hard material. Multiple abrasive and / or destructive materials may be incorporated into a pattern within multiple layers or layers to enhance the destructive effect. As explained above, the destructive material (e.g., an abrasive and / or hard material) may be very close to the bonding interface 8. For example, the destructive material may be located within 5 micrometers of the bonding interface 8. A third party may attempt to etch or grind away the protective chiplet. If the destructive material is very close to the bonding interface 8 between the protective element (chiplet) and the semiconductor element 2, the method of removing or grinding away the chiplet becomes very difficult.

[0028] In various embodiments, as described above, the barrier material 4 may alternatively or additionally comprise a light-blocking material configured to block light, and / or an electromagnetic absorbing or dissipating material configured to block electromagnetic waves. For example, the barrier material 4 may be selected to block light in the wavelength range of 700 nm to 1 mm, in the wavelength range of 750 nm to 2500 nm, or in the wavelength range of 800 nm to 2500 nm. The barrier material 4 may alternatively or additionally be selected or shaped to scatter incident light. The barrier material 4 may alternatively or additionally be conductive and can be effectively used as electromagnetic shielding. The barrier material 4 may additionally or alternatively absorb electromagnetic waves. In various embodiments, the barrier material 4 may be selected to block near-infrared (NIR) and focused ion beam (FIB) intrusion attempts. In another embodiment, the barrier material 4 may include or may be deposited together with one or more optical or infrared filter layers. Thin-film optical filters can be used to filter out or modify optical or IR light that passes through them in any direction, such as light incident on a circuit used to trigger a response or light emitted from a circuit used to detect a response to an unauthorized intrusion technique.

[0029] In some embodiments, a protected safety structure or portion of a circuit may be shared between a protective element 3 (e.g., a small chip with abrasive and / or destructive materials) and an element 2 to be protected (e.g., an integrated device die with a safety active region). For example, a hybrid bonding structure may be used to provide conductor-to-conductor direct bonding along a bonding interface 8, which includes covalently directly bonded dielectric-to-dielectric surfaces 9, 10. In various embodiments, conductor-to-conductor (e.g., contact pad-to-contact pad) direct bonding and dielectric-to-dielectric bonding may be formed using direct bonding techniques disclosed at least in U.S. Patents 9,716,033 and 9,852,988, the entire contents of each of which are incorporated herein by reference in their entirety and for all purposes.

[0030] For example, direct bonding surfaces 9 and 10 can be fabricated and can be directly bonded to each other without adhesive. Conductive connection pads (which may be surrounded by non-conductive dielectric field regions) can also be directly bonded to each other without adhesive. For example, in some embodiments, the respective connection pads may be flush with the dielectric surfaces 9 and 10, or recessed below the dielectric field regions, for example, in the range of 1 nm to 20 nm, or in the range of 4 nm to 10 nm. In some embodiments, the bonding surfaces 9 and 10 of the dielectric field regions can be directly bonded to each other at room temperature without adhesive, and subsequently, the bonding structure 1 can be annealed. During annealing, the contact pads can expand and contact each other to form a metal-to-metal direct bond.

[0031] Additional details of the protective element 3 having barrier material 4 can be found throughout U.S. Provisional Patent Applications Nos. 62 / 833,491 (“491 application”) and 62 / 953,058 (“058 application”), which are incorporated herein by reference in their entirety and for all purposes. The embodiments disclosed herein may be used in conjunction with any embodiments disclosed in the “491 application” and the “058 application”.

[0032] like Figure 1 and Figures 2A-2C As shown, the bonding structure 1 may include a protective element 3, which is directly bonded to the semiconductor element 2 along the bonding interface 8 on the sensitive active circuit system 6 without adhesive. Figure 1 and Figure 2C In this embodiment, the semiconductor element 2 can be directly electrically connected to the carrier 32 (such as a package substrate) via one or more bonding wires 34. In other embodiments, the semiconductor element 2 can be mounted onto the carrier 32 via solder balls in a flip-chip arrangement. In the illustrated embodiment, the carrier 32 includes a package substrate, such as a printed circuit board, a leaded substrate, a ceramic substrate, etc. In other embodiments, the carrier 32 may include an integrated circuit die, an intermediate, a reconfigured wafer, or any other possible device.

[0033] exist Figure 2A In this embodiment, the protective element 3 includes a semiconductor (e.g., silicon) substrate or base plate 7 (also referred to herein as a handle). In other embodiments, the substrate 7 for the security chip does not need to be semiconductor, as it primarily serves as a handle for the barrier material 4 and the bonding layer 5, as described herein, and can be replaced by other materials, such as glass or quartz. However, the semiconductor substrate is provided using existing equipment to facilitate processing and manipulation, and also has sufficient flatness and smoothness to simplify subsequent polishing of the bonding layer 5.

[0034] The protective element 3 may include a barrier material 4 (as a layer on the substrate or one or more substrates) on the substrate 7. The barrier material 4 may include destructive materials (e.g., abrasive and / or hard materials), light or electromagnetic wave blocking materials, conductive materials, light filtering or scattering materials, etc., and may have more than one of the properties described herein. As described herein, the protective element 3 may prevent external access to the safety-sensitive circuit system 6. As described above, the barrier material 4 may include abrasive and / or destructive materials (e.g., materials with high mechanical hardness compared to materials typically used in semiconductor manufacturing, such as silicon, silicon dioxide, aluminum, and copper).

[0035] In various embodiments, the barrier material 4 may additionally or alternatively be selected to block electromagnetic radiation from impacts. The barrier material 4 may include, for example, ceramic materials, composite materials, diamond, tungsten, a combination of tungsten and diamond, or any other suitable type of barrier material that prevents external access to the active circuitry system on the semiconductor element 2, to which the protective element 3 is bonded. In different embodiments, the barrier material 4 may include materials for which selective etchants may not be able to remove the barrier material 4 without removing the inorganic dielectrics commonly used in semiconductor manufacturing.

[0036] The barrier material 4 can be manufactured and assembled onto the handle or substrate 7 in the first facility at one or more process temperatures. For example, the barrier material 4 can be deposited on the handle or substrate 7 at a temperature of at least 400°C or at least 800°C (e.g., in the range of 400°C to at least 1000°C). Such high processing temperatures may not be suitable for foundries used to manufacture semiconductor elements 2, such as wafers or integrated device dies (which should not be exposed to temperatures above 300°C or 400°C for extended periods after manufacturing), as such high temperatures may damage the active circuit system 6 and other components of the semiconductor element 2. In some cases, the material used for the barrier layer may be incompatible with the semiconductor manufacturing facility due to contamination considerations.

[0037] like Figure 2A As shown, bonding layer 5 can be disposed on barrier material 4. Bonding layer 5 can include any suitable type of non-conductive or dielectric material, particularly inorganic dielectrics compatible with integrated circuit manufacturing, such as silicon dioxide, nitric oxide, etc. In some embodiments, bonding layer 11 can also be disposed on semiconductor element 2. Bonding layer 5 (e.g., silicon oxide) may be so thin that layer 5 cannot adequately protect or shield the security circuit system 6 to prevent third-party access. Figure 2B As shown, the protective element 3 can be directly bonded to the semiconductor element 2 along the bonding interface 8 without adhesive. As described herein, corresponding bonding layers 5, 11 can be prepared for bonding. For example, bonding layers 5, 11 can have bonding surfaces 9, 10, which are planarized to a high surface smoothness and exposed to a termination treatment (e.g., nitrogen termination). The bonding layers 5, 11 of the protective element 3 and the semiconductor element 2 can be contacted to each other at room temperature without applying adhesive or voltage. The bonding layers 5, 11 can form a strong covalent bond along the bonding interface 8. A strong covalent bond may be sufficient for processing and even for post-bonding processes (such as grinding, polishing, or otherwise thinning the substrate, monolithization, etc.), but post-bonding annealing can further enhance the bond strength.

[0038] Although the protective element 3 can block external access to the sensitive circuit system 6, a third party can attempt to access the security-sensitive active circuit system 6 by removing the protective element 3 from the semiconductor element 2 to expose the active circuit system 6. For example, as Figure 1 As shown, a third party could attempt to strip the protective element 3 from the semiconductor device by supplying etchant along the chemical attack path P. The various embodiments described herein relate to apparatuses and methods configured to prevent or deter a third party from removing or otherwise disrupting the function of the protective element 3 and the underlying sensitive circuitry. This deterrence can take the form of a combination of constructions designed to disable the function of the sensitive circuitry 6 upon removal of the protective element 3, thereby preventing meaningful access to the sensitive circuitry 6 by a third party.

[0039] Figure 3 This is a schematic side view of the protective element 3 and the semiconductor element 2 before bonding, according to various embodiments. The semiconductor element 2 may include a body substrate region 22, one or more intermediate layers 21, and one or more upper layers defining or including a sensitive circuit system 6, which includes, for example, a power grid region 20. The sensitive circuit system 6 (e.g., power grid region 20) may be defined at or near the upper bonding layer 11 of the semiconductor element 2. In the various embodiments disclosed herein, the bonding structure 1 may be designed to mate the dielectric material of the dielectric bonding layer 5 of the protective element 3 with the upper layer of the semiconductor element 2 (e.g., an integrated device die, such as a logic die), the bonding structure 1 including the upper bonding layer 11 of the semiconductor element 2 and a layer below the bonding layer 11 including a portion of the sensitive circuit system 6. Matching dielectric bonding layers 5, 11 may compromise with the upper layer (e.g., upper logic layer or power grid region 20) of the matching semiconductor element 2 (e.g., integrated device die), such that chemical etch attacks targeting the direct bonding interface 8 also attack and destroy the power grid region 20 and / or logic circuitry in the sensitive region 6 of the semiconductor element 2. For example, the semiconductor element 2 may have a silicon oxide-based material surrounding the metal in the upper metallization layer. Barrier and / or etch-stopping materials (e.g., SiN, SiC, SiOC, and SiON, etc.) may be absent or may be replaced by other etchant-sensitive materials that may selectively remove oxides (such as differently doped silicon oxide) or other materials used in bonding layers 5, 11 in other ways. While various embodiments describe bonding layers 5, 11 as comprising silicon oxide or silicon oxide-based materials for bonding surfaces 9, 10, any other suitable material (e.g., SiN) may also be used for bonding layers 5, 11.

[0040] In various embodiments, the power grid region 20 may be at least partially disposed on the adjacent protective element 3 such that if the protective element 3 is removed, the power grid region 20 (and / or other sensitive circuitry 6) may be non-functional. Figure 3 As shown, in some embodiments, the bonding layer 5 of the protective element 3 and the upper layer of the semiconductor element 2 (e.g., power grid region 20) may comprise the same material, such as silicon oxide in some embodiments. As described above, these layers 5, 11 may comprise features prepared for direct bonding, such as a significant spike in fluorine concentration at the oxide interface and / or a nitrogen spike at the bonding interface 8. In this arrangement, if a third party attempts to remove the protective element 3 from the semiconductor element 2 by selectively etching the material of the bonding layers 5, 11, the etchant will also damage the upper metallization layer (power grid layer or region 20) of the semiconductor element 2, thereby damaging the sensitive region 6 and preventing external access to it. Therefore, providing the sensitive circuit system 6 (e.g., power grid region 20) at or near the upper bonding layer 11 of the semiconductor element 2 can be used as an interruption structure 30, which can be configured to interrupt the function of the circuit system 6 once the protective element 3 is stripped from the semiconductor element 2. As explained herein, the materials of the matching dielectric bonding layers 5, 11 can provide an etching path that can interrupt the function of the circuit system 6 in the event of stripping or other interruptions. The interruption structure 30 described herein can interrupt the sensitive active circuit system 6, which includes one or more active devices (e.g., transistors and other active circuit systems), as well as local interconnects and wiring (e.g., back-end wiring) connected to the active devices.

[0041] In some embodiments, a conductive signal trace 23 may be provided through a sensitive circuit region 6 (e.g., power grid region 20). The conductive trace 23 may be configured to detect whether the protective element 3 has been stripped from the semiconductor element 2. For example, the conductive trace 23 may be connected to other circuitry (e.g., monitoring circuitry 24) that monitors impedance to determine if a direct bond has been compromised. If the protective element 3 is removed from the semiconductor element 2, the removal may trigger a signal along the trace 23 indicating the removal (e.g., detected by changes in impedance, current, voltage, etc.). The monitoring circuitry 24 may be formed in either the protective element 3 or the semiconductor element 2, or may scan both the protective element 3 and the semiconductor element 2. In the aforementioned embodiment, the monitoring circuitry 24 may be disposed in the body substrate region 22.

[0042] Figure 4 This is a schematic side view of the protective element 3 and the semiconductor element 2 before bonding, according to another embodiment. Unless otherwise indicated, Figure 4 The components can be with Figures 1-3Components with the same number are identical or largely similar. Figure 4 In this configuration, the semiconductor element 2 may include one or more intermediate layers 21 below the upper bonding layer, such as one or more interlayer dielectric materials (ILDs). The intermediate layers 21 may include one or more barrier layers 26 between dielectric wiring or circuit layers 27. The barrier layers 26 may, for example, serve as etch stop layers, as CMP stop layers and / or barrier layers for the semiconductor element 2 to be protected. Alternating layers of dielectric barrier layers 26 (e.g., barrier layers) and wiring layers 27 may include silicon nitride in some arrangements. Other examples of barrier layers 26 include SiC, SiON, SiOC, etc. These barrier layers can be effectively used as barrier layers selected against etchants used by third parties to remove the protective element 3. Figure 4 As shown, one or more openings 25 can be provided in the intermediate layer 21 (e.g., through the barrier layer 26) to create an etching path 28 that passes through the upper layer 11 and through at least a portion of the intermediate layer 21. If a third party attempts to remove the protective element 3 by etching, the openings 25 in the barrier layer 26 can be used to damage the sensitive circuit system 6 of the semiconductor element 2. The sensitive circuit system 6 can be disposed in one or more intermediate layers 21 and / or semiconductor regions 22.

[0043] Therefore, in various embodiments, the interruption structure 30 can be provided such that, once the protective element 3 is stripped from the semiconductor element 2, it interrupts the function of at least a portion of the sensitive active circuit system 6 (including active devices and / or interconnects or wiring structures connected to active devices). In various arrangements, the interruption structure 30 may include an etch path 28 through a portion of the semiconductor element 2. Advantageously, if a third party attempts to strip the protective element 3 by etching, the etch path 28 may cause chemical etchants to destroy or damage the circuit system 6 in the semiconductor element 2. In some arrangements, one or more barrier layers 26 (e.g., silicon nitride) may be present in the semiconductor element 2. These barrier layers 26 are typically present in integrated circuit metallization stacks and can be used, for example, as an etch stop or CMP stop during metallization or back-end (BEOL) structure processing, and / or as a diffusion barrier layer to prevent metal migration into the surrounding intermediate layer medium (ILDs, typically in the form of silicon oxide). During selective etching of the bonding layers 5, 11 that bond the protective element 3 to the sensitive circuit system 6, the barrier layer 26 may also incidentally protect the underlying interconnect pattern (e.g., power grid region 20) and the underlying circuit system 6. Therefore, an opening 25 may be selectively provided in the barrier layer 26 to create an etching path 28 in the lower or intermediate layer 21 of the semiconductor element 2 in the event of a chemical attack on the bonding layers 5, 11 (e.g., silicon oxide). This etching path 28 can disrupt or disable the underlying circuit system 6 of the semiconductor element 2, such as the power grid region 20 of the semiconductor element 2. In this embodiment, the semiconductor element 2 can be modified in conjunction with the addition of the protective element 3. The opening 25 in the barrier layer 26 may have a width in the range of 2 μm to 3 mm. For example, in various embodiments, the opening 25 may have a width in the range of 1 μm to 100 μm, 100 μm to 1 mm, or 1 mm to 3 mm.

[0044] In various embodiments, trenches ( Figure 4 (Not shown) can be arranged along the edge of the semiconductor element 2 (e.g., a die) so that any etchant used to strip the protective element 3 can erode the underlying layer of the semiconductor element 2. Although trenches can be used in some arrangements, other patterns that create cavities or voids may also be suitable.

[0045] In some embodiments, as described above, trace 23 may be disposed in the power grid region 20 of the semiconductor element 2. Trace 23 may be used by monitoring circuitry 24 to monitor the impedance or other electrical characteristics of the circuit system 6. Removal of the dielectric bonding layer 11 of the semiconductor element can cause a significant increase in impedance, thereby indicating that a third party may have tampered with the bonding structure 1. For example, trace 23 may include a jumper trace in the power grid region 20 that sags if the dielectric bonding layer 11 of the semiconductor element 2 is removed or detached from the protection element 3.

[0046] In various embodiments, the monitoring circuit 24 may be disposed on one or both of the protective element 3 and the semiconductor element 2. For example, in some embodiments, the monitoring circuit 24 may be disposed on the semiconductor element 2. The bonding structure 1 may also include a large number of conductive interconnects to the grid, which would be cut if the protective element 3 is removed. It is impractical to reconnect such a large number of interconnects to the grid using post-peel attachment. The monitoring circuit 24 may be configured to electrically disable the sensitive circuit system 6 if any tampering indication is detected.

[0047] Figures 5A-5B A schematic side cross-sectional view of the joining structure 1 according to various embodiments is shown, unless otherwise indicated. Figures 5A-5B The components can be with Figures 1-4 Components with the same number are identical or largely similar. Figures 5A-5B In this configuration, one or more cavities 29 may be disposed on the upper dielectric layer of the semiconductor element. For example, as shown in... Figures 5A-5B As shown, the cavity 29 can be formed in the bonding layer 11 and one or more intermediate layers 21 of the semiconductor element 2. Similar to... Figure 4 The opening in the middle is 25. Figures 5A-5B One or more cavities 29 in the semiconductor element 2 can similarly provide an interruption structure 30 including an etch path 28 to allow the etchant to penetrate the intermediate and lower layers of the semiconductor element 2, thereby interrupting the function of the safety-sensitive circuit system 6 (including active devices and / or wiring structures interconnecting or connected to active devices) once the protective element 3 is stripped from the semiconductor element 2. For example, in Figure 5AIn this configuration, the cavity 29 on the right side of structure 1 provides a vertical path 31 through the bonding layer 11 of semiconductor element 2 to the intermediate layer 21. Lateral channels 32 can connect this vertical path 31 to other cavities 33 in the intermediate layer 21, thereby providing a network of voids or cavities 29 to provide ready access across semiconductor element 2 and through the intermediate layer 21 for any stripping etchant. Known methods can form the cavities 29 and possibly the microchannels interconnecting them. The cavities 29 can have dimensions ranging from 1 micrometer to 3 micrometers in length, width, and height. For example, in various embodiments, the cavities 29 can have dimensions ranging from 1 micrometer to 100 micrometers, from 100 micrometers to 1 mm, or from 1 mm to 3 mm.

[0048] Figure 6A This is a schematic side cross-sectional view of the joining structure 1 according to another embodiment. Figure 6B yes Figure 6A An enlarged view of a portion of the joining structure 1 shown. Unless otherwise indicated, Figures 6A-6B The components can be with Figures 1-5B Components with the same number are identical or substantially similar. In various embodiments, the direct bonding layer 5 and conductive contact pads 40 of the protective element 3 can be directly bonded to the corresponding dielectric bonding layer 11 and corresponding conductive contacts 42 of the semiconductor element 2 without adhesive. In this arrangement, the directly bonded conductive contacts 40, 42 can be used to monitor the connectivity between the protective element 3 and the semiconductor element 2 as an indicator of tampering or stripping attempts. Multiple conductive contacts 40, 42 can be used, but in some arrangements, only a portion of the contacts can be connected, while other contacts create an electrical short circuit.

[0049] In some embodiments utilizing dielectrics and conductive direct bonding (e.g., direct bonding interconnects, or DBI, connections), if the dielectric bonding layers 5 and / or 11 (e.g., oxide) are removed and the protective element 3 detaches from the semiconductor element 3, such removal will result in defects (e.g., short circuits in power grid region 20). For example, an etch-resistant material will be embedded in a portion of the conductors (e.g., contact pads 40) within the protective element 3, such that the conductors remain connected to the protective element 3, even after selective etching of the bonding layers 5 and / or 11. Non-limiting examples of etch-resistant materials include silicon nitride capable of resisting selective etching of the silicon oxide bonding layer. Various embodiments may not utilize chain connections on a dummy die.

[0050] like Figure 6A and Figure 6BAs shown, in some embodiments, the dielectric bonding layer 5 and conductive contact pads 40 of the protective element 3 can be directly bonded to the corresponding dielectric bonding layer 11 and corresponding conductive contact pads 42 of the semiconductor element 2 without adhesive, in a hybrid direct bonding process, such as direct bonding interconnects or commercially available from Xperi Corporation of San Jose. Process. As described above, the dielectric bonding layers 5 and / or 11 can be selectively etched by a third party using an etchant that can remove the protective element 3 from the semiconductor element 2. However, removing the protective element 3 can destroy the underlying sensitive circuit system 6 by detaching the conductive vias and traces from the semiconductor element 2.

[0051] like Figures 6A-6B As shown, in some embodiments, a barrier layer 41 (e.g., silicon nitride) may be used in the protective element 3 and the semiconductor element 2 as a barrier to prevent the release of metal from the protective element 3 during a stripping attempt. The barrier layer 41 may be thicker than a conventional etch-stop layer (e.g., in the range of 250 nm to 400 nm) and may be used as an anchoring material layer to bond contact pads 40, 42 to the underlying sensitive circuitry 6 (via other internal traces and connections 43). In some embodiments, a persistent barrier or anchoring layer 41 (which may include one or more layers) may be provided in the protective element 3 to complicate the stripping process. In other embodiments, the barrier material 41 may be provided as a multilayer dielectric ring to complicate stripping and die separation. Even with selective removal of bonding layers 5, 11, the contact pads 40, 42 (e.g., metal) of the protective element 3 and the semiconductor element 2 to be protected remain connected and intact, such that separation of elements 3, 2 would cause physical damage to the semiconductor element 2. For example, even if the dielectric bonding layers 5 and 11 are etched away, the direct bonding connection between contact pads 40 and 42 and protected by barrier layer 41 can remain intact, which would result in the tearing and destruction of the circuitry in the underlying layer 21 and region 22 connected to contact pads 40 and 42. For example, connection 43 can be directly bonded to the wiring and circuitry in layer 21 from bonding pads 40 and 42 and / or extend to the sensitive circuitry itself. Furthermore, as disclosed above... Figure 4 In a related embodiment, in the lower semiconductor element 2, openings in the anchoring layer 41 and / or the barrier material 26 (e.g., the thick barrier layer protecting the metal of the semiconductor element 2, and / or the etch stop, CMP stop, or barrier layer) can be provided around the sensitive region 6 of the semiconductor element 2. These openings 25 can form etch paths, allowing the etchant to reach the lower layer of the semiconductor element 2 and disrupt the security-sensitive circuit system 6 and / or the wiring connected to the sensitive circuit system 6.

[0052] Figure 7Another example of interrupt structure 30 is shown. Unless otherwise noted, Figure 7 The components can be with Figures 1-6B Components with the same number are identical or largely similar. Figure 7 In this context, the barrier material 4 of the protective element 3 can be patterned to make delamination and stripping more difficult or uncontrollable. For example, vias or paths (e.g., openings) 45 through the barrier material can be provided to be filled with a dielectric material 46 (e.g., silicon oxide). Paths 45 can include over-etched vias, under-etched vias, through-vias, partial vias, or blind vias, etc. Figure 7 As shown. Vias or paths 46 through the barrier material 4 can make stripping more challenging without causing disabling damage to the semiconductor element 2 and the sensitive circuit system 6 it protects by complicating the stripping path. For example, openings 46 can allow etchants or plasma to etch more quickly through openings 46 (or partial openings), which may damage the underlying circuitry while the etchant or plasma is attempting to remove other barrier materials 4.

[0053] Figure 8 This is a schematic diagram of an electronic system 80 including one or more bonding structures 1 according to various embodiments. System 80 may include any suitable type of electronic device, such as a mobile electronic device (e.g., a smartphone, tablet computer device, laptop computer, etc.), a desktop computer, an automobile or a component thereof, a stereo system, a dependent device, a camera, or any other suitable type of system. In some embodiments, electronic system 80 may include a microprocessor, a graphics processor, an electronic recording device, or digital memory. System 80 may include one or more device packages 82 mechanically and electrically connected to system 80 (e.g., via one or more master packages). Each package 82 may include one or more bonding structures 1. Package 82 may be similar to or the same as package 30 described herein. Figure 8 The system 80 shown may include any joining structure 1 shown and described herein and associated protective element 3.

[0054] In one embodiment, a bonding structure is disclosed. The bonding structure may include a semiconductor element comprising an active circuit system. The bonding structure may include a barrier element bonded directly to the semiconductor element along the bonding interface without adhesive. The barrier element includes a barrier material disposed on at least a portion of the active circuit system, configured to block external access to the active circuit system. The bonding structure may include an interruption structure configured to interrupt the function of at least a portion of the active circuit system once the barrier element is peeled off from the semiconductor element.

[0055] In some embodiments, the barrier material may be positioned at a distance of less than 10 micrometers from the bonding interface. The barrier material may be positioned at a distance of less than 5 micrometers from the bonding interface. The barrier material may include a destructive material having a hardness in the range of 20 GPa to 150 GPa. The barrier material may include a destructive material with a hardness of at least 80 GPa. The interruption structure may include an etch path through a portion of the semiconductor element. The semiconductor element may include a first bonding layer, and the barrier element includes a second bonding layer directly bonded to the first bonding layer without adhesive. The first bonding layer may include a first material, and the etch path also includes the first material. The first material may include silicon oxide. The first bonding layer may also include one or more of fluorine and nitrogen. The interruption structure may be configured to interrupt the function of at least a portion of the active circuitry upon selective etch stripping from one or more of the first bonding layer and the second bonding layer. The first and second bonding layers may include silicon oxide. The bonding structure may include one or more intermediate layers between the first bonding layer and the active circuitry, the one or more intermediate layers including the circuitry, the etch path extending through at least a portion of the one or more intermediate layers. The one or more intermediate layers may include a barrier layer, with one or more openings formed in the barrier layer to block extension through the one or more openings. One or more openings in the barrier layer may include the material of the first bonding layer. The barrier layer may include silicon nitride. The bonding structure may include multiple dielectric layers separated by multiple barrier layers, the multiple dielectric layers comprising the same material as the first bonding layer. The interruption structure may include cavities within one or more intermediate layers. The bonding structure may include a first plurality of contact pads in the first bonding layer and a second plurality of contact pads in the second bonding layer, the first plurality of contact pads being directly bonded to the second plurality of contact pads. The bonding structure may include a first barrier layer in the first bonding layer and an anchoring material layer in the second bonding layer, the first barrier layer having one or more openings therethrough. The second plurality of contact pads may be at least partially embedded in the anchoring material layer. At least one contact pad may be connected to monitoring circuitry to monitor the connectivity of the directly bonded first plurality of contact pads and the second plurality of contact pads. At least two or more of the second plurality of contact pads may be electrically connected. The bonding structure may include a back-end (BEOL) layer comprising a power circuitry system in the barrier element. The interruption structure may include conductive traces configured to detect whether barrier material has been stripped from the semiconductor element. The barrier material can be patterned to expose portions of the semiconductor element, with etched paths extending through these exposed portions. The barrier material may have a first hardness greater than a second hardness of the semiconductor element or a third hardness of the material at the bonding interface. The barrier material may include an abrasive material. The barrier material may also include a light-blocking material. The light-blocking material can be configured to block near-infrared (NIR) wavelengths of light.Barrier materials can include optical or infrared (IR) blocking or modified materials.

[0056] In another embodiment, a bonding structure is disclosed. The bonding structure may include a semiconductor element comprising an active circuit system. The bonding structure may include a barrier element directly bonded to the semiconductor element along a bonding interface without adhesive. The barrier element includes a barrier material disposed over at least a portion of the active circuit system, the barrier material being configured to block external access to the active circuit system. The bonding structure may include an etch path through a portion of the semiconductor element, the etch path being configured to interrupt the function of at least a portion of the active circuit system when the barrier element is peeled off from the semiconductor element.

[0057] In some embodiments, the barrier material is positioned at a distance of 10 micrometers from the bonding interface. The barrier material may be positioned at a distance of less than 5 micrometers from the bonding interface. The barrier material may include a destructive material having a hardness in the range of 20 GPa to 150 GPa. The barrier material may include a destructive material having a hardness of at least 80 GPa. The semiconductor element may include a first bonding layer, and the barrier element may include a second bonding layer directly bonded to the first bonding layer without adhesive. The first bonding layer may include a first material, and the etching path also includes the first material. The first material may include silicon oxide. The first bonding layer may include one or more of fluorine and nitrogen. One or more intermediate layers may be between the first bonding layer and the active circuit system, the one or more intermediate layers including the circuit system, the etching path extending through at least a portion of the one or more intermediate layers. The one or more intermediate layers may include a barrier layer, one or more openings formed within the barrier layer, through which the etching path extends. The barrier layer may include silicon nitride. One or more openings or portions of the openings in the barrier layer may include the material of the bonding interface. Multiple dielectric layers may be separated by multiple barrier layers, the multiple barrier layers including the same material as the first bonding layer. A cavity may be in one or more intermediate layers. A first plurality of contact pads and a second plurality of contact pads in a first bonding layer may be in a second bonding layer, with the first plurality of contact pads directly bonded to the second plurality of contact pads. At least two or more of the second plurality of contact pads may be electrically connected. A first barrier layer may be in the first bonding layer and an anchoring material layer may be in the second bonding layer, the first barrier layer having one or more openings therethrough. The second plurality of contact pads may be at least partially embedded in the anchoring material layer. At least one contact pad may be connected to a monitoring circuit to monitor the connectivity of the directly bonded first plurality of contact pads and the second plurality of contact pads. The barrier material may be patterned to expose a portion of the semiconductor element, with an etch path extending through the exposed portion.

[0058] In another embodiment, a bonding structure is disclosed. The bonding structure may include a semiconductor element comprising an active circuit system. The bonding structure may include a barrier element directly bonded to the semiconductor element without adhesive. The barrier element includes a barrier material disposed over at least a portion of the active circuit system, the barrier material being configured to block external access to the active circuit system. The bonding structure may include a conductor connected to one or both of the semiconductor element and the barrier element, the conductor being configured to detect whether the barrier element has been peeled off from the semiconductor element.

[0059] In some embodiments, the semiconductor element may include a first bonding layer and a barrier element may include a second bonding layer directly bonded to the first bonding layer without adhesive. The first and second bonding layers may include silicon oxide. One or more intermediate layers may be present between the first bonding layer and an active circuit system, the one or more intermediate layers including the circuit system, and etch paths extending through at least a portion of the one or more intermediate layers. The one or more intermediate layers may include a barrier layer, with one or more openings formed in the barrier layer, and etch paths extending through the one or more openings. A conductor may be at least partially disposed in the one or more intermediate layers. A monitoring circuit may be configured to monitor current flowing through the conductor to determine whether a barrier element has been stripped from the semiconductor element. The monitoring circuit may be configured to indicate that a barrier element has been stripped from the semiconductor element in the event that an electrical signal flowing through the conductor is interrupted. A first plurality of contact pads may be in the first bonding layer and a second plurality of contact pads may be in the second bonding layer, the first plurality of contact pads being directly bonded to the second plurality of contact pads without adhesive. A first barrier layer may be in the first bonding layer and an anchoring material layer may be in the second bonding layer, the first barrier layer having one or more openings therethrough. The second plurality of contact pads may be at least partially embedded in the second barrier layer. At least one contact pad may be connected to a monitoring circuit to monitor the connectivity of a first plurality of contact pads and a second plurality of contact pads that are directly bonded. The first hardness of the barrier material may be greater than the second hardness of the semiconductor element. The barrier material may include an abrasive material. The barrier material may include a light-blocking material. The light-blocking material may be configured to block near-infrared (NIR) wavelengths of light.

[0060] In another embodiment, a method for forming a bonding structure is disclosed. The method may include patterning an interruption structure into at least one of a semiconductor element having an active circuit system and a barrier element, the barrier element comprising a barrier material disposed over at least a portion of the active circuit system, the barrier material being configured to block external access to the active circuit system. The method may include directly bonding the barrier element to the semiconductor element without an adhesive, the interruption structure being configured to interrupt the function of the semiconductor element once the barrier element is peeled off from the semiconductor element.

[0061] In some embodiments, the method may include depositing a first bonding layer on a semiconductor element and a second bonding layer on a barrier element, the method including directly bonding the first bonding layer and the second bonding layer without adhesive. The method may include forming a plurality of dielectric layers separated by a plurality of barrier layers, the plurality of dielectric layers comprising the same material as the first bonding layer. The method may include directly bonding a first plurality of contact pads in the first bonding layer to a second plurality of contact pads in the second bonding layer. The method may include forming a first barrier layer in the first bonding layer and forming an anchoring material layer in the second bonding layer, the first barrier layer having one or more openings therethrough. A patterned interruption structure may include patterning openings through one or more barrier layers within one or more intermediate layers. The method may include patterning openings in the barrier material to expose portions of the semiconductor element. The method may include monitoring electrical signals along a conductor at least partially disposed in one or both of the semiconductor element and the barrier element to determine whether the barrier element has been stripped from the semiconductor element.

[0062] Although disclosed in the context of certain embodiments and examples, those skilled in the art will understand that the invention extends beyond the specifically disclosed embodiments to other alternative embodiments and / or uses, as well as their obvious modifications and equivalents. Furthermore, unless otherwise indicated, components described may be identical or substantially similar to components with the same number in one or more different descriptions. Additionally, although several variations have been shown and described in detail, other modifications within the scope of this disclosure will readily conceive of those skilled in the art based on this disclosure. It is also conceivable that various combinations or sub-combinations of specific features and aspects of the embodiments may be made and still fall within the scope of the invention. It should be understood that various features and aspects of the disclosed embodiments may be combined or substituted with each other to form various modes of the disclosed invention. Therefore, the scope of the invention disclosed herein should not be limited to the specific disclosed embodiments described above, but should be determined only through a reasonable interpretation of the following aspects.

Claims

1. A joining structure, comprising: A semiconductor element, the semiconductor element comprising an active circuit system and a first bonding layer; A barrier element, the barrier element including a second bonding layer, the second bonding layer being directly bonded to a first bonding layer of the semiconductor element along a bonding interface without adhesive, the barrier element including a barrier material disposed on at least a portion of the active circuit system, the barrier material being configured to block external access to the active circuit system. as well as An interruption structure, including an etch path through a portion of the semiconductor element, is configured to interrupt the function of at least a portion of the active circuit system once the barrier element is stripped from the semiconductor element. The interruption structure further includes a conductive trace configured to detect whether the obstruction element has been stripped from the semiconductor element.

2. The bonding structure according to claim 1, wherein the barrier material is positioned at a distance of less than 10 micrometers from the bonding interface.

3. The bonding structure according to claim 1, wherein the barrier material is positioned at a distance of less than 5 micrometers from the bonding interface.

4. The joint structure according to claim 1, wherein the obstructive material comprises a destructive material having a hardness in the range of 20 GPa to 150 GPa on the Vickers hardness scale.

5. The bonding structure according to claim 1, wherein the obstructive material comprises a destructive material having a hardness of at least 80 GPa on the Vickers hardness scale.

6. The bonding structure according to claim 1, wherein the first bonding layer comprises a first material, and the etching path also comprises the first material.

7. The bonding structure according to claim 6, wherein the first material comprises silicon oxide.

8. The bonding structure according to claim 7, wherein the first bonding layer further comprises one or more of fluorine and nitrogen.

9. The bonding structure of claim 1, wherein the interruption structure is configured to interrupt the function of at least a portion of the active circuit system upon selective etch stripping from one or more of the first bonding layer and the second bonding layer.

10. The bonding structure according to claim 1, wherein the first bonding layer and the second bonding layer comprise silicon oxide.

11. The bonding structure of claim 1, further comprising one or more intermediate layers between the first bonding layer and the active circuit system, the one or more intermediate layers comprising the circuit system, the etch path extending through at least a portion of the one or more intermediate layers.

12. The joining structure of claim 11, wherein the one or more intermediate layers include a barrier layer, and one or more openings are formed in the barrier layer, the barrier extending through the one or more openings.

13. The bonding structure of claim 12, wherein one or more openings in the barrier layer comprise the material of the first bonding layer.

14. The bonding structure of claim 13, wherein the barrier layer comprises silicon nitride.

15. The bonding structure of claim 12, further comprising a plurality of dielectric layers separated by a plurality of barrier layers, the plurality of dielectric layers comprising the same material as the first bonding layer.

16. The joining structure of claim 11, wherein the interruption structure further comprises a cavity in the one or more intermediate layers.

17. The bonding structure according to claim 1, further comprising a first plurality of contact pads in the first bonding layer and a second plurality of contact pads in the second bonding layer, wherein the first plurality of contact pads are directly bonded to the second plurality of contact pads.

18. The joint structure of claim 17, further comprising a first barrier layer in the first joint layer and an anchoring material layer in the second joint layer, the first barrier layer having one or more openings therethrough.

19. The bonding structure of claim 18, wherein the second plurality of contact pads are at least partially embedded in the anchoring material layer.

20. The bonding structure of claim 17, wherein at least one contact pad is connected to a monitoring circuit to monitor the connectivity of the directly bonded first plurality of contact pads and second plurality of contact pads.

21. The bonding structure of claim 17, wherein at least two or more of the second plurality of contact pads are electrically connected.

22. The bonding structure of claim 17, further comprising a back-end layer, the back-end layer including the power circuitry in the barrier element.

23. The bonding structure of claim 1, wherein the barrier material is patterned to expose a portion of the semiconductor element, and the etch path extends through the exposed portion.

24. The bonding structure according to claim 1, wherein the first hardness of the barrier material is greater than the second hardness of the semiconductor element or the third hardness of the material at the bonding interface.

25. The joining structure according to claim 1, wherein the obstructive material comprises an abrasive material.

26. The bonding structure according to claim 1, wherein the barrier material comprises a light-blocking material.

27. The bonding structure of claim 26, wherein the light-blocking material is configured to block near-infrared wavelengths of light.

28. The bonding structure according to claim 1, wherein the barrier material comprises an optical or infrared blocking or modified material.

29. A joining structure, comprising: A semiconductor element, the semiconductor element comprising an active circuit system and a first bonding layer; A barrier element, the barrier element including a second bonding layer, the second bonding layer being directly bonded to a first bonding layer of the semiconductor element along a bonding interface without adhesive, the barrier element including a barrier material disposed on at least a portion of the active circuit system, the barrier material being configured to block external access to the active circuit system. as well as An etching path, passing through a portion of the semiconductor element, is configured to interrupt the function of at least a portion of the active circuit system while the obstructing element is being stripped from the semiconductor element.

30. The bonding structure of claim 29, wherein the barrier material is positioned at a distance of less than 10 micrometers from the bonding interface.

31. The bonding structure of claim 29, wherein the barrier material is positioned at a distance of less than 5 micrometers from the bonding interface.

32. The joint structure of claim 29, wherein the barrier material comprises a destructive material having a hardness in the range of 20 GPa to 150 GPa.

33. The bonding structure of claim 29, wherein the barrier material comprises a destructive material having a hardness of at least 80 GPa.

34. The bonding structure of claim 29, wherein the first bonding layer comprises a first material, and the etching path also comprises the first material.

35. The bonding structure of claim 34, wherein the first material comprises silicon oxide.

36. The bonding structure of claim 35, wherein the first bonding layer further comprises one or more of fluorine and nitrogen.

37. The bonding structure of claim 29, further comprising one or more intermediate layers between the first bonding layer and the active circuit system, the one or more intermediate layers including the circuit system, the etch path extending through at least a portion of the one or more intermediate layers.

38. The bonding structure of claim 37, wherein the one or more intermediate layers include a barrier layer, one or more openings are formed in the barrier layer, and the etch path extends through the one or more openings.

39. The bonding structure of claim 38, wherein the barrier layer comprises silicon nitride.

40. The bonding structure of claim 38, wherein one or more openings in the barrier layer comprise the material of the bonding interface.

41. The bonding structure of claim 38 further comprises a plurality of dielectric layers separated by a plurality of barrier layers, the plurality of dielectric layers comprising the same material as the first bonding layer.

42. The joining structure of claim 37, further comprising a cavity in one or more intermediate layers.

43. The bonding structure of claim 29 further includes a first plurality of contact pads in the first bonding layer and a second plurality of contact pads in the second bonding layer, wherein the first plurality of contact pads are directly bonded to the second plurality of contact pads.

44. The bonding structure of claim 43, wherein at least two or more of the second plurality of contact pads are electrically connected.

45. The joint structure of claim 43, further comprising a first barrier layer in the first joint layer and an anchoring material layer in the second joint layer, the first barrier layer having one or more openings therethrough.

46. ​​The joining structure according to claim 45, wherein, The second plurality of contact pads are at least partially embedded in the anchoring material layer.

47. The bonding structure of claim 43, wherein at least one contact pad is connected to a monitoring circuit to monitor the connectivity of the directly bonded first plurality of contact pads and second plurality of contact pads.

48. The bonding structure of claim 29, wherein the barrier material is patterned to expose a portion of the semiconductor element, and the etch path extends through the exposed portion.

49. A joining structure, comprising: Semiconductor device, including active circuit system, first bonding layer and etch path; A barrier element, the barrier element including a second bonding layer directly bonded to a first bonding layer of the semiconductor element without adhesive, the barrier element including a barrier material disposed on at least a portion of the active circuit system, the barrier material being configured to block external access to the active circuit system. as well as A conductor connected to one or both of the semiconductor element and the barrier element, the conductor being configured to detect whether the barrier element has been stripped from the semiconductor element. The etch path passes through a portion of the semiconductor element, and once the barrier element is stripped from the semiconductor element, the etch path disrupts the function of at least a portion of the active circuit system.

50. The bonding structure of claim 49, wherein the first bonding layer and the second bonding layer comprise silicon oxide.

51. The bonding structure of claim 49, further comprising one or more intermediate layers between the first bonding layer and the active circuit system, the one or more intermediate layers including the circuit system, the etch path extending through at least a portion of the one or more intermediate layers.

52. The bonding structure of claim 51, wherein the one or more intermediate layers include a barrier layer, one or more openings are formed in the barrier layer, and the etch path extends through the one or more openings.

53. The bonding structure according to claim 51, wherein the conductor is at least partially disposed in the one or more intermediate layers.

54. The bonding structure of claim 51 further includes a monitoring circuit configured to monitor the current through the conductor to determine whether the hindering element has been stripped from the semiconductor element.

55. The bonding structure of claim 54, wherein the monitoring circuit is configured to indicate that the barrier element has been stripped from the semiconductor element if an electrical signal through the conductor is interrupted.

56. The bonding structure of claim 49 further includes a first plurality of contact pads in the first bonding layer and a second plurality of contact pads in the second bonding layer, wherein the first plurality of contact pads are directly bonded to the second plurality of contact pads without adhesive.

57. The joint structure of claim 56, further comprising a first barrier layer in the first joint layer and an anchoring material layer in the second joint layer, the first barrier layer having one or more openings therethrough.

58. The bonding structure of claim 57, wherein the second plurality of contact pads are at least partially embedded in the second barrier layer.

59. The bonding structure of claim 56, wherein at least one contact pad is connected to a monitoring circuit to monitor the connectivity of the directly bonded first plurality of contact pads and second plurality of contact pads.

60. The joining structure according to claim 49, wherein, The first hardness of the barrier material is greater than the second hardness of the semiconductor element.

61. The joining structure according to claim 49, wherein the obstructive material comprises an abrasive material.

62. The bonding structure according to claim 49, wherein the barrier material comprises a light-blocking material.

63. The bonding structure according to claim 62, wherein the light-blocking material is configured to block near-infrared wavelengths of light.

64. A method for forming a joint structure, the method comprising: The interrupt structure is patterned as part of a semiconductor element having an active circuit system, wherein the interrupt structure includes an etch path; as well as A first bonding layer of a barrier element is directly bonded to a second bonding layer of the semiconductor element without an adhesive, wherein the barrier element comprises a barrier material disposed on at least a portion of the active circuit system, the barrier material being configured to block external access to the active circuit system, and the interruption structure being configured to interrupt the function of the semiconductor element once the barrier element is peeled off from the semiconductor element.

65. The method of claim 64, further comprising depositing the first bonding layer on the semiconductor element and depositing the second bonding layer on the barrier element.

66. The method of claim 65, further comprising forming a plurality of dielectric layers separated by a plurality of barrier layers, the plurality of dielectric layers comprising the same material as the first bonding layer.

67. The method of claim 65, further comprising directly bonding a first plurality of contact pads in the first bonding layer to a second plurality of contact pads in the second bonding layer.

68. The method of claim 67, further comprising forming a first barrier layer in the first bonding layer and forming an anchoring material layer in the second bonding layer, the first barrier layer having one or more openings therethrough.

69. The method of claim 68, wherein patterning the interruption structure includes patterning the one or more openings.

70. The method of claim 64, further comprising patterning openings in the barrier material to expose portions of the semiconductor element.

71. The method of claim 64, further comprising monitoring an electrical signal along a conductor to determine whether the barrier element has been stripped from the semiconductor element, the conductor being at least partially disposed in one or both of the semiconductor element and the barrier element.

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