A method and system for implementing a memory set optimization strategy

Abstract

The present invention relates to the field of microprocessor technology, and in particular to a method and system for implementing a memory set optimization strategy, comprising a store_buffer module, a pipeline module, a stream_model_dector module, and a WCB module. The present invention solves the problem in the prior art that, due to a miss, a reload request needs to be issued to L2, and then L2 returns the reloaded data, and finally the stored data and the reloaded data are written together into D_cache, which results in a too long latency; since a request is issued to L2, the reloaded data is actually useless, which unnecessarily increases the bandwidth of L2 requests; and causes pollution of D_cache, and the resulting polluted data is very large, which significantly reduces the hit rate of D_cache. The present invention reduces latency and simultaneously reduces the bandwidth of L1 requests to L2, without causing pollution of L1_cache and having a negative impact on the hit rate of D_cache, and has strong market application prospects.

Description

Technical Field

[0001] The present invention relates to the technical field of microprocessors, and in particular to a method and system for implementing a memory set optimization strategy. Background Art

[0002] For memory set programs, data at consecutive addresses need to be written into memory, which is likely to miss. If the data is reloaded normally and written into D_cache, but the data is not needed in subsequent instruction operations, it will cause D_cache pollution. The polluted data will be large, and the D_cache hit rate will be greatly reduced.

[0003] In the existing technology, due to a miss, a reload request needs to be issued to L2, and then L2 returns the reloaded data. Finally, the stored data and the reloaded data are written to D_cache together, which will result in excessive latency. Since the request is issued to L2, the reloaded data is actually useless, which unnecessarily increases the bandwidth of L2 requests. This also causes D_cache pollution, and the resulting polluted data can be large, significantly reducing the D_cache hit rate. Therefore, this paper proposes a method and system for implementing a memory set optimization strategy. Summary of the Invention

[0004] In response to the deficiencies of the prior art, the present invention discloses a method and system for implementing a memory set optimization strategy, which is used to solve the problems in the prior art where, due to a miss, a reload request needs to be issued to L2, L2 then returns the reloaded data, and finally both the stored data and the reloaded data are written into D_cache, which results in excessive latency; since a request is issued to L2, the reloaded data is actually useless, which unnecessarily increases the bandwidth of L2 requests; and causes D_cache pollution, and the resulting polluted data can be very large, which significantly reduces the hit rate of D_cache.

[0005] The present invention is achieved through the following technical solutions:

[0006] In a first aspect, the present invention discloses a method for implementing a memory set optimization strategy, comprising the following steps:

[0007] After S1 initialization is completed, the store instruction enters the store buffer module, and the store_buffer issues a read request to the pipeline;

[0008] S2 determines whether the D_cache is in M / E state, S state, or no hit state, and performs corresponding operations according to the state;

[0009] S3 sends a reload request to L2 based on the miss queue entry. L2 returns the reload E-state data and wakes up the store_buffer entry in the store buffer that misses the S-state.

[0010] S4 backfills the refill_buffer with the reloaded data, refills the pipeline, and detects in the store_buffer that data in the same cacheline needs to be stored;

[0011] S5 merges the store data and writes them to D_cache, while deallocating the store_buffer and refill_buffer entries.

[0012] After the entire cacheline is full, S6 writes the store data to L2. After confirming that the data has been written to L2, it deallocates the WCB entry.

[0013] Furthermore, in the method, if the M / E state is hit in the D_cache, the store_buffer then issues a write request to write the data into the D_cache and changes the status of the cacheline to the E state.

[0014] Furthermore, in the method, if the hit in D_cache is the S state, an entry item is requested to be allocated to the miss queue.

[0015] Furthermore, in the method, if there is no hit in D_cache, it is determined that if it is in stream_model mode, the data is directly written to WCB after the entire cacheline of the store is full. If it is not in stream_model mode, an entry item is requested to be allocated from the miss queue.

[0016] Furthermore, in the method, the awakened store_buffer entry item gives the refill pipeline a merge window of N clock cycles, where N is a natural number.

[0017] Furthermore, in the method, after the entire cacheline is full, the data is written to the WCB, and the WCB writes the stored data to the L2. The WCB receives a response ack message from the L2 confirming that the data has been written to the L2 and deallocates the WCB entry.

[0018] In a second aspect, the present invention discloses a system for implementing a memory set optimization strategy. The system is used to implement the method for implementing a memory set optimization strategy described in the first aspect, and includes a store_buffer module, a pipeline module, a stream_model_dector module, and a WCB module.

[0019] Furthermore, after the store queue completes the sta and std operations, the tore_buffer module obtains confirmation from the graduation module that the store data of the store instruction can be written to the memory, and then writes the store data into the store_buffer module. The store_buffer module determines whether to write the store data directly into the D_cache or request to allocate a missq entry item, or directly write it into the WCB after the entire cacheline is full, based on the hit status in the D_cache and the stream_model mode.

[0020] Furthermore, the pipeline module is responsible for data access after the instruction is put on the pipeline. If Miss requests to allocate an entry item in the new missq, the pipeline is refilled. If there is data in the store_buffer that is consistent with the address and needs to be stored, the two data are merged and written into D_cache together.

[0021] Furthermore, the stream model dector module is responsible for detecting the stream_model mode and determining whether to enter / exit / maintain the stream_model mode, and the WCB module is responsible for writing data into L2.

[0022] The beneficial effects of the present invention are:

[0023] The present invention reduces latency and bandwidth of L1 requests to L2, and does not cause pollution of L1_cache or negatively affect the hit rate of D_cache, thus having strong market application prospects. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0025] Figure 1 It is a flowchart of a method for implementing a memory set optimization strategy;

[0026] Figure 2 It is a structural diagram of the implementation system of the memory set optimization strategy;

[0027] Figure 3 It is a detection diagram for entering and exiting the stream model mode. DETAILED DESCRIPTION

[0028] To make the objectives, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0029] Example 1

[0030] See also Figure 1 As shown, the present invention discloses a method for implementing a memory set optimization strategy, comprising the following steps:

[0031] After S1 initialization is completed, the store instruction enters the store buffer module, and the store_buffer issues a read request to the pipeline;

[0032] S2 determines whether the D_cache is in M / E state, S state, or no hit state, and performs corresponding operations according to the state;

[0033] S3 sends a reload request to L2 based on the miss queue entry. L2 returns the reload E-state data and wakes up the store_buffer entry in the store buffer that misses the S-state.

[0034] S4 backfills the refill_buffer with the reloaded data, refills the pipeline, and detects in the store_buffer that data in the same cacheline needs to be stored;

[0035] S5 merges the store data and writes them to D_cache, while deallocating the store_buffer and refill_buffer entries.

[0036] After the entire cacheline is full, S6 writes the store data to L2. After confirming that the data has been written to L2, it deallocates the WCB entry.

[0037] In this embodiment, if the M / E state is hit in the D_cache, the store_buffer then issues a write request to write the data into the D_cache and changes the status of the cacheline to the E state.

[0038] In this embodiment, if the hit in the D_cache is the S state, a request is made to allocate an entry item to the miss queue.

[0039] In this embodiment, if there is no hit in D_cache, it is determined that if it is in stream_model mode, the data is directly written to WCB after the entire cacheline of the store is full. If it is not in stream_model mode, an entry item is requested to be allocated from the miss queue.

[0040] In this embodiment, the awakened store_buffer entry item provides a merge window of N clock cycles for the refill pipeline, where N is a natural number.

[0041] In this embodiment, after the entire cacheline is full, the data is written to the WCB, which then writes the stored data to the L2. After the WCB receives the response ack message from the L2 confirming that the data has been written to the L2, it deallocates the WCB entry.

[0042] This embodiment solves the problem in the prior art that due to a Miss, a reload request needs to be sent to L2, L2 then returns the reload data, and finally the store data and the reload data are written into D_cache together, which results in too long latency.

[0043] This embodiment solves the problem in the prior art that, due to a request sent to L2, the data reloaded back is actually useless, thus unreasonably increasing the bandwidth of L2 requests, causing D_cache pollution, and the resulting polluted data will be very large, which will significantly reduce the hit rate of D_cache.

[0044] Example 2

[0045] See also Figure 2 As shown, the main implementation scheme of this embodiment is in the store_buffer module, pipeline, stream_model_dector module and WCB module.

[0046] The store_buffer module of this embodiment is used for writing the store data into the store_buffer after the store queue completes the sta and std operations and obtains confirmation from the graduation module that the store data of the store instruction can be written into the memory.

[0047] store_buffer determines whether to write the store data directly to D_cache, request the allocation of a missq entry, or wait until the entire cacheline is full and write it directly to WCB based on the hit status in D_cache and the stream_model mode.

[0048] In this embodiment, the pipeline module is responsible for data access after the instruction is put on the pipeline. If Miss requests to allocate an entry item in the new missq, the pipeline is refilled. If there is data in the store_buffer that matches the address and needs to be stored, the two data are merged and written into D_cache together.

[0049] In this embodiment, the stream model dector module is responsible for detecting the stream_model mode and determining whether to enter / exit / maintain the stream_model mode.

[0050] In this embodiment, the WCB module is responsible for writing data into L2.

[0051] Example 3

[0052] See also Figure 3 As shown, this embodiment discloses a detection method for entering and exiting a stream model mode.

[0053] The entry condition of this embodiment is: there are N complete cache lines stored consecutively, where N is a configurable value.

[0054] The exit conditions of this embodiment are:

[0055] 1. The store address does not meet the continuity requirements;

[0056] 2. If the store size does not fill the entire cache line, store another cache line;

[0057] 3. pa[39:9] of the load pipeline == stream_pa[39:9]. If any of the above conditions is met, the stream model will be exited.

[0058] In this embodiment, the implementation of not detecting the store address and first obtaining the cacheable Eclusive attribute and then writing the store data into D_cache, just like a normal store instruction, is still within the protection scope of this embodiment.

[0059] In summary, the present invention reduces latency and bandwidth of L1 requests to L2 without causing L1_cache pollution or negatively affecting the D_cache hit rate, and has strong market application prospects.

[0060] The above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present invention.

Claims

1. A method for implementing a memory set optimization strategy, characterized in that: The method comprises the following steps: After S1 initialization is completed, the store instruction enters the store buffer module, and the store buffer issues a read request to the pipeline; S2 determines whether the D_cache is in M / E state, S state, or no hit state, and performs corresponding operations according to the state; S3 sends a reload request to L2 based on the miss queue entry. L2 returns the reload E-state data and wakes up the store buffer entry that miss-hit the S-state in the store buffer. S4 backfills the refill_buffer with the reloaded data, refills the pipeline, and detects in the store buffer that data in the same cacheline needs to be stored; S5 merges the store data and writes them to D_cache, while deallocating the storebuffer and refill_buffer entries. After the entire cacheline is full, S6 writes the store data to L2. After confirming that the data has been written to L2, it deals with the WCB entry.

2. The method for implementing a memory set optimization strategy according to claim 1, characterized in that: In the method, if the M / E state is hit in the D_cache, the store buffer then issues a write request to write the data into the D_cache and changes the status of the cacheline to the E state.

3. The method for implementing a memory set optimization strategy according to claim 1, wherein: In the method, if the hit in D_cache is the S state, a request is made to allocate an entry item to the miss queue.

4. The method for implementing a memory set optimization strategy according to claim 1, wherein: In the method, if there is no hit in D_cache, it is determined that if it is in stream_model mode, the data is directly written to WCB after the entire cacheline of the store is full. If it is not in stream_model mode, an entry item is requested to be allocated from the miss queue.

5. The method for implementing a memory set optimization strategy according to claim 1, wherein: In the method, the awakened store buffer entry item gives the refill pipeline a merge window of N clock cycles, where N is a natural number.

6. The method for implementing a memory set optimization strategy according to claim 1, wherein: In the method, after the entire cache line is full, the data is written to the WCB, and the WCB writes the stored data to the L2. After the WCB receives the response ack message from the L2 confirming that the data has been written to the L2, the WCB deallocates the WCB entry.

7. A system for implementing a memory set optimization strategy, the system being used to implement a method for implementing a memory set optimization strategy according to any one of claims 1 to 6, characterized in that: Includes store buffer module, pipeline module, stream model dector module and WCB module.

8. A memory set optimization strategy implementation system according to claim 7, characterized in that: The store buffer module, after the store queue completes the sta and std operations, obtains confirmation from the graduation module that the store data of the store instruction can be written to the memory, and then writes the store data into the store buffer module. The store buffer module determines whether to write the store data directly into the D_cache or request to allocate a missq entry item, or directly write it into the WCB after the entire cacheline is full, based on the hit status in the D_cache and the stream_model mode.

9. A memory set optimization strategy implementation system according to claim 7, characterized in that: The pipeline module is responsible for data access after the instruction is put on the pipeline. If Miss requests to allocate an entry item in the new missq, the pipeline is refilled. If there is data in the store buffer with the same address as the one requested in the missq that needs to be stored, the two data are merged and written into D_cache together.

10. A memory set optimization strategy implementation system according to claim 7, characterized in that: The stream model dector module is responsible for detecting the stream_model mode and determining whether to enter / exit / maintain the stream_model mode. The WCB module is responsible for writing data into L2.

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