Data management method, device, medium and product

Abstract

The application discloses a data management method and device, medium and product, relates to the technical field of computers, and when data of a program running on a certain processor core needs to be inserted into a shared cache, the data belonging to different application programs is placed in positions of different priorities according to the categories of the application programs. The shortest time for ensuring that the data stays in a private cache is the time for the data to go from a highest priority position matched with a processor core to which the data belongs to a lowest priority position, and the intermediate process is not accessed again. Further, the data block with a higher hit rate is stored in the cache system for a longer time, so that the overall hit rate of the cache system is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of computer, and in particular, relates to a data management method, device, medium and product. BACKGROUND

[0002] Inclusion cache system in multi-core processor occupies a certain share in the market of multi-core processor because it can effectively reduce cache consistency communication data volume.

[0003] However, when replacing a certain data in the shared cache, the inclusion cache system needs to process the corresponding data in the private cache at the same time to meet the inclusion requirement; and if the data access frequency is high, cache miss will occur, thereby affecting the performance of the overall cache system.

[0004] Therefore, there is an urgent need for a data management method that can improve cache hit rate while meeting the inclusion requirement to solve the above technical problems. SUMMARY

[0005] The present application provides a data management method, device, medium and product to at least solve the problems in the related art.

[0006] The present application provides a data management method, comprising:

[0007] In response to receiving a data access request initiated by a target processor core, obtaining an access data block matched with the data access request;

[0008] According to the access data block and the data distribution characteristics of the cache system, triggering a cache replacement operation:

[0009] According to the cached data blocks of the preset cache interval in the shared cache and the cached data blocks of the private cache, determining a target replacement data block;

[0010] Inserting the access data block into a target insertion position matched with the target processor core and deleting the target replacement data block.

[0011] The present application also provides an electronic device, comprising: a memory for storing a computer program; and a processor for executing the computer program to implement the steps of any of the above data management methods.

[0012] The present application also provides a computer-readable storage medium, which stores a computer program, wherein the computer program is executed by a processor to implement the steps of any of the above data management methods.

[0013] The present application also provides a computer program product comprising a computer program, which is executed by a processor to implement the steps of any of the above data management methods.

[0014] In the data management method disclosed in the present application, when the data of a program running on a certain processor core needs to be inserted into the shared cache, the data belonging to different application programs is placed in different priority positions according to the category of the application program. The shortest time for ensuring the data to stay in the private cache is the time for the data to go from the highest priority position matching the processor core to which the data belongs to the lowest priority position without being accessed again in the process. Further, the data block with a higher hit rate is allowed to stay in the cache system for a longer time, thereby improving the overall hit rate of the cache system. BRIEF DESCRIPTION OF DRAWINGS

[0015] In order to more clearly illustrate the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiments. Obviously, the drawings described below are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor on the basis of these drawings.

[0016] Figure 1 A data management method flow chart provided for the embodiments of the present application;

[0017] Figure 2 A traditional data management schematic diagram provided for the embodiments of the present application;

[0018] Figure 3 A data management schematic diagram provided for the embodiments of the present application;

[0019] Figure 4 An insertion position schematic diagram provided for the embodiments of the present application;

[0020] Figure 5 A cache system storage schematic diagram provided for the embodiments of the present application;

[0021] Figure 6 A cache system storage schematic diagram provided for the embodiments of the present application after cache replacement;

[0022] Figure 7 A data management system architecture diagram provided for the embodiments of the present application;

[0023] Figure 8 An electronic device schematic diagram provided for the embodiments of the present application. DETAILED DESCRIPTION

[0024] With reference to the drawings, the technical solutions in the embodiments of the present application will be clearly and completely described below. Obviously, the described embodiments are only a part of the embodiments of the present application, but not all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort should fall within the scope of the present application.

[0025] It should be noted that, in the description of the present application, the terms "comprising", "containing" or any other variants thereof are intended to cover non-exclusive containing, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such a process, method, article or device. The terms "first", "second" and the like in the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence.

[0026] As disclosed in the background art, the cache system in the processor chip is used to store instructions and data that can be frequently accessed to reduce access to the off-chip main memory, which plays an important role in improving system performance. The cache system usually presents a multi-layer architecture, for example, a typical three-layer architecture. The first and second levels of cache close to the target processor core are private to the target processor core, which is called private cache, and the last level is the third level of cache, which is shared by multiple target processor cores in the processor chip, which is called shared cache.

[0027] According to the inclusion relationship of data in the private cache and the shared cache, the cache system has three categories, namely, inclusive cache, non-inclusive cache and exclusive cache. Among them, the inclusive cache requires that the data in the private cache must be a subset of the data in the shared cache, that is, the data in the private cache can be found in the shared cache, and the data not in the shared cache cannot be stored in the private cache. The non-inclusive cache does not require the data in the private cache to be a subset of the data in the shared cache. The exclusive cache requires that the data in the private cache is not contained in the shared cache, and the data in the shared cache is not contained in the private cache.

[0028] Compared with other categories, the inclusive cache has both advantages and disadvantages. The advantage is that it can effectively reduce the amount of cache coherence communication data, for example, when it is determined that the data is not in the shared cache, there is no need to search the private cache. The disadvantage is that the overall cache hit rate is not high, because when the shared cache replaces a certain data from the cache space, if the data still exists in the private cache, and in order to meet the inclusive requirement, the data in the private cache needs to be invalidated. If the access frequency of this data is high, it will be accessed subsequently, which will cause cache miss, thereby affecting system performance.

[0029] The solution of the prior technical solution is that the shared cache does not directly determine the target data block for replacement, but determines a plurality of data blocks to be replaced; then the target private cache is selected according to the plurality of data blocks to be replaced, and the target private cache selects the target data block for replacement from the plurality of data blocks to be replaced. By transferring the operation of selecting the target replacement data block originally performed by the shared cache to the target private cache, the situation that the hot cache block in the private cache is invalidated due to the fact that the shared cache cannot know the hot degree of each cache block in each private cache can be avoided, the number of times that the hot cache block in the private cache is invalidated is reduced, and the cache hit rate of the cache system is improved. However, the determination manner of the final replaced data block in the prior art is unreasonable, because the final replaced data block is determined by the private cache from the data blocks to be replaced contained in the private cache, which inevitably causes a certain data block in the private cache to be invalidated. In addition, the prior technical solution does not consider the memory access characteristics of the application programs running on different target processor cores. Some application programs have good locality of memory access, and the accessed data will be accessed again in a short time. Keeping this data block in the cache is beneficial to improving the cache hit rate. However, some application programs have one-time memory access, that is, the data is only used once and will not be accessed again. Keeping this data block in the cache is not conducive to improving the cache hit rate, and therefore the cache space is wasted.

[0030] Therefore, in the face of the inclusive cache system in the multi-core processor, it is an urgent problem to improve the cache hit rate while guaranteeing the requirements of the inclusive cache.

[0031] Embodiments of the present application provide a data management method, which meets the requirements of the inclusive cache, considers the memory access characteristics of the programs running on different processor cores, ensures the rationality of the data blocks stored in the cache system, and improves the hit rate of the overall cache system. As shown in Figure 1 The method for managing the data blocks in the cache system includes the following steps.

[0032] S100, in response to receiving a data access request initiated by a target processor core, obtaining an access data block matched with the data access request.

[0033] The data management method disclosed in the application is applied to an inclusive cache system in a multi-processor. The inclusive cache system comprises a first cache and a second cache (i.e. a private cache) private to each processor core and a shared cache. The existing inclusive cache system proposes that when the shared cache needs to replace a data block, several data blocks with the lowest access frequency in the shared cache are determined as candidate data blocks to be replaced; then the number of data blocks to be replaced in the private cache of each processor core is determined, and the private cache of the processor core with the largest number of data blocks to be replaced is determined as a target private cache; then the target private cache determines the final replaced data block from the data blocks to be replaced contained in the target private cache, and the information is transmitted level by level until the shared cache; the shared cache receives the information of the final replaced data block, and then performs a replacement operation. However, the finally determined replaced data block in this processing scheme is not reasonable, which may cause a valid data block in the private cache to be set as invalid.

[0034] It can be understood that if multiple data access requests initiated by target processor cores are received at the same time, the data feedback and data replacement can be responded concurrently or sequentially in a certain response order. In order to save computing resources, the operations corresponding to the received multiple data access requests within a certain period can be integrated and then corresponding management operations are performed. Of course, in order to ensure response efficiency, the data access requests can also be processed immediately. The application does not limit this.

[0035] S200, triggering a cache replacement operation according to the accessed data block and the data distribution characteristics of the cache system.

[0036] The data distribution characteristics include cached data blocks and cache occupancy states. Specifically, the above-mentioned triggering a cache replacement operation according to the accessed data block and the data distribution characteristics of the cache system comprises:

[0037] If there is a cached data block matching the accessed data block in the cache system, the cached data block is fed back to respond to the data access request. That is, the accessed data block hits in the cache system, and at this time the corresponding data block information can be directly fed back to the target processor core initiating the data access request. If there is no cached data block matching the accessed data block in the cache system, whether to trigger a cache replacement operation is determined according to the cache occupancy state of the shared cache. It can be understood that when the accessed data block does not hit in the cache system, the method disclosed in the application embodiment obtains the corresponding accessed data block from the main memory and sends it to the corresponding target processor core in time; at the same time, the corresponding accessed data block is inserted into the shared cache, and whether to trigger a cache replacement operation is further determined according to the cache occupancy state of the shared cache.

[0038] Further, the above determining whether to trigger the cache replacement operation according to the cache occupancy state of the shared cache comprises: in response to detecting that the cache occupancy state of the shared cache is a full state, triggering the cache replacement operation; and in response to detecting that the cache occupancy state of the shared cache is a non-full state, inserting the access data block into a target insertion position matched with the target processor core, at this time, there is a free position in the shared cache, and the storage requirement of the access data block is met, and at this time, the cache replacement operation does not need to be triggered.

[0039] The embodiment of the present application sets a trigger condition, i.e., a corresponding multi-level logical judgment step, while ensuring timely data feedback, so as to ensure that the cache replacement operation is triggered only when the access data block misses the cache system and the shared cache is full, thereby saving the computing resources of the cache system.

[0040] In addition, different processor cores run different application programs, and there is no relationship between the application programs and no data sharing. In theory, the probability of the extreme scenario that the data accessed by one processor core exists in the private cache of another processor core is very small, but it is not absolute. Therefore, in order to improve the data block replacement accuracy and further ensure the stability of the cache system, the present application proposes the following operation when it is detected that there is a cached data block matched with the access data block in the cache system:

[0041] If the cached data block matched with the access data block belongs to the private cache and belongs to the target processor core, the cached data block is fed back to respond to the data access request; if the cached data block matched with the access data block belongs to the private cache but belongs to a non-target processor core, the data state of the cached data block is set to an invalid state in the non-target processor core, and the cached data block is fed back to the target processor core to respond to the data access request; if the cached data block matched with the access data block belongs to the shared cache, the cached data block is fed back to the target processor core to respond to the data access request. That is, by further judging the cache type of the hit and triggering the corresponding operation, the corresponding data block in the private cache of the non-target processor core is transferred to the target processor core in the above-mentioned extreme scenario, so as to ensure that the request of the processor core is responded while avoiding the problem of low cache system performance caused by repeated storage.

[0042] It can be understood that in the traditional data management method, it is not distinguished which processor core the data belongs to, and the access data block is usually placed in the highest priority position, as shown in Figure 2 However, the data management method disclosed in the present application proposes that when the data of the program running on a certain processor core needs to be inserted into the shared cache, the data belonging to different application programs is placed in different priority positions according to the category of the application program, as shown in Figure 3When the shared cache is full and data replacement needs to be performed, the cache usually selects a data block from a low priority position for replacement. Data with a low hit rate is no longer placed in the highest priority position, which can slow the speed at which high hit rate data is replaced and improve the overall cache hit rate. When the data is accessed again, the data is promoted to the highest priority position matching the processor core. Therefore, the shortest time for data to stay in the private cache is the time for the data to go from the highest priority position matching the processor core to which the data belongs to the lowest priority position, and the data is not accessed again in the process. This ensures that data blocks with a high hit rate stay in the cache system for a longer time, thereby improving the overall cache hit rate.

[0043] Specifically, the step S200 includes:

[0044] S210, determining a target replacement data block according to the cached data blocks in the preset cache interval in the shared cache and the cached data blocks in the private cache.

[0045] Specifically, the preset cache interval is determined by a fourth insertion position and a lowest priority position in the shared cache. The determination of the fourth insertion position is described in detail below, which is omitted here. The determination of the target replacement data block according to the cached data blocks in the first cache interval in the shared cache and the cached data blocks in the private cache includes:

[0046] The data block matching operation is performed to select a first cached data block from the cached data blocks in the preset cache interval and compare the first cached data block with the cached data blocks in the private cache. In response to detecting that the first cached data block is not repeated in the cached data blocks in the private cache, the first cached data block is determined as the target replacement data block. In response to detecting that the first cached data block is repeated in the cached data blocks in the private cache, the data block matching operation is repeatedly performed until the cached data blocks in the preset cache interval are traversed. In response to detecting that the first cached data block is repeated in the cached data blocks in the private cache, it is detected whether the first cached data block is the data block with the highest priority in the preset cache interval. In response to detecting that the first cached data block is the data block with the highest priority in the preset cache interval, the first cached data block is determined as the target replacement data block. The data block matching operation specifically includes selecting the first cached data block from the cached data blocks in the preset cache interval according to the priority from low to high, and detecting whether the first cached data block is repeated in the cached data blocks in the private cache. That is, when the cache replacement operation is triggered, that is, when the shared cache needs to replace a data block, it is determined in the preset cache interval whether the current data block (that is, the first cached data block) still exists in the private cache of a certain processor core. If the data block does not exist in the private cache of the processor core, the data block is determined as the target replacement data block. If the preset cache interval is traversed and the final target replacement data block is not found, the data block with the highest priority in the preset cache interval is selected as the final target replacement data block. In addition, when it is determined that the first cached data block is repeated in the cached data blocks in the private cache, the first cached data block is moved to the insertion position of the matched cache according to the first processor core to which the hit private cache belongs.

[0047] According to the above steps, when the cache replacement operation is triggered, the final target replacement data block is limited in the preset cache interval, and it is ensured that the data block finally replaced is the data block with low access efficiency, so that the hit rate of the overall cache system in subsequent data access is improved.

[0048] In order to improve the judgment efficiency of whether the first data block exists in the private cache of a certain processor core, the embodiment of the application further proposes that n bits are added to each data row in the cached data block of the shared cache, which is used to identify to which processor core the current data row belongs. If the total number of processor cores in a computer system is M, then n = log2M. When the data block matching operation is needed, the processor core to be compared matching the data block is determined according to the bit; whether the first cache data block and the data block in the processor core to be compared are repeated is detected, if the cached data block in the processor core to be compared is repeated with the first cache data block, that is, the first cache data block is not the replaceable data block, if the cached data block in the processor core to be compared is not repeated with the first cache data block, the first cache data block is the final replaceable data block. By narrowing the operation range of data matching, the processor core to be compared is limited by the bit added in the data row when comparing the data block, without broadcasting, the comparison efficiency is greatly improved, thereby improving the data block replacement efficiency of the whole cache system.

[0049] S220, inserting the access data block into the target insertion position matching the target processor core and deleting the target replacement data block.

[0050] Specifically, after the access data block is inserted into the target insertion position in the shared cache, the original data block is moved according to the positional relationship with the target insertion position. If the priority of the target insertion position is higher than that of the original data block, the original data block is moved by one position in the order of priority from high to low at this time.

[0051] The determination method of the target insertion position specifically includes obtaining the target program category matching the current running program of the target processor core, wherein the program category is determined according to the preset program classification rule; determining the target insertion position from a plurality of cache insertion positions according to the target program category and the preset mapping relationship table, wherein the mapping relationship table contains the relationship between the program category and the cache insertion position in the shared cache.

[0052] The program categories include a first category, a second category, a third category, and a fourth category. The first category represents a private cache friendly program, the type of program has a high local access to data, and data access hits occur mostly in the private cache space of the processor core. The second category represents a shared cache friendly program, the type of program has a medium local access to data, and data access hits are distributed in the private cache and the shared cache. The third category represents a shared cache jitter program, the type of program has a poor local access to data, and there is a hit if a part of the data is retained in the shared cache. The fourth category represents a streaming program, the type of program has a poor local access to data, and there is almost no data hit. It can be understood that the essence of the above four program types is to divide according to the access characteristics. Specifically, if the working set is less than the private cache space, the program category of the corresponding application program is determined as the first category; if the private cache space is less than the working set and the working set is less than the shared cache space, the program category of the corresponding application program is determined as the second category; if the working set is greater than the shared cache space, the program category of the corresponding application program is determined as the third category; and if the working set is much greater than the shared cache space, the program category of the corresponding application program is determined as the fourth category. The working set represents a data set accessed by the application program in a certain time period, and the time period is set by a person skilled in the art according to the performance of the cache system, which is not limited in the present application. However, the above division of the program categories based on the working set size is a theoretical division, and it is difficult to accurately divide in actual operation.

[0053] Therefore, on this basis, the embodiment of the present application provides a program classification rule, which includes: obtaining the highest non-zero bit position of an access register in a target processor core, the access register being used to record the number of data access requests initiated by the target processor core, that is, the value recorded by the read-write register is incremented by 1 each time, regardless of whether it is a hit or not; finding a first bit value matched with the highest non-zero bit position and a second bit value matched with a bit position after the highest non-zero bit position in a hit register in the target processor core, the hit register being used to record the number of hits of the data access request in the target processor core, and it can be determined that the value of the hit register is definitely less than the value of the access register; and determining the program category according to the first bit value and the second bit value. The access register and the hit register can be set as 32-bit registers, and of course they can also be set according to the actual scene, which is not limited in the present application. The embodiment of the present application describes the access characteristics of the application program running in each processor core by setting the above-mentioned access register and hit register in each processor core, realizes reasonable division of the program category, and further ensures the accuracy of the subsequently determined insertion position of the access data block.

[0054] Specifically, the determining procedure of the program category according to the first bit value and the second bit value comprises: in response to detecting that the first bit value and the second bit value are both the first preset value, determining that the target program category is the first category; in response to detecting that the first bit value is the first preset value and the second bit value is the second preset value, determining that the target program category is the second category; in response to detecting that the first bit value is the second preset value and the second bit value is the first preset value, determining that the target program category is the third category; and in response to detecting that the first bit value and the second bit value are both the second preset value, determining that the target program category is the fourth category. Preferably, the first preset value is set as 1 and the second preset value is set as 0; of course, the values can be changed according to actual conditions, which are not limited in the application.

[0055] It can be understood that when the target processor core switches the application program or runs a new application program, by default, in this initialization stage, the access register value corresponding to the target processor core is 2, i.e. 10b in binary, and the hit register value is 1, i.e. 01b in binary. From the above application program classification, it is assumed by default that the application program is the third category (i.e. the shared cache jitter type program); with the execution of the application program, the two register values dynamically change, and the insertion position of the data belonging to the target processor core in the shared cache also dynamically changes.

[0056] In some implementation scenarios, the above program classification rule can also determine the program category of the application program running on the target processor core according to the first cache hit rate of the target processor core. Specifically, in response to detecting that the first cache hit rate of the target processor core is greater than or equal to a high hit rate, it is determined that the target program category is the first category; in response to detecting that the first cache hit rate of the target processor core is greater than or equal to a medium hit rate and less than the high hit rate, it is determined that the target program category is the second category; in response to detecting that the first cache hit rate of the target processor core is greater than or equal to a low hit rate and less than the medium hit rate, it is determined that the target program category is the third category; and in response to detecting that the first cache hit rate of the target processor core is less than the low hit rate, it is determined that the target program category is the fourth category. An exemplary hit rate parameter is given in the embodiment of the application: the high hit rate a = 80%, the medium hit rate β = 50%, and the low hit rate γ = 20%; of course, the above hit rate parameters can be adjusted by those skilled in the art according to actual conditions, which are not limited in the application. At this time, when the target processor core switches the application program or runs a new application program, by default, in this initialization stage, the first cache hit rate corresponding to the target processor core is 50%, and it is assumed by default that the application program is the third category (i.e. the shared cache jitter type program); with the execution of the application program, the hit rate dynamically changes, and the insertion position of the data belonging to the target processor core in the shared cache also dynamically changes.

[0057] Specifically, the cache insertion position includes a first insertion position, a second insertion position, a third insertion position, and a fourth insertion position, and the determination method of the cache insertion position includes:

[0058] According to the first group of connection degrees of the shared cache, the first insertion position is determined, that is, the highest priority position of cache insertion; according to the first group of connection degrees, the second group of connection degrees of the private cache, and the first preset formula, the second insertion position is determined, wherein the first preset formula is L1=X+(Y-X) / 3, X represents the second group of connection degrees, Y represents the first group of connection degrees, and L1 represents the second insertion position; according to the first group of connection degrees, the second group of connection degrees, and the second preset formula, the third insertion position is determined, wherein the first preset formula is L2=Y-(Y-X) / 3, and L2 represents the third insertion position; and according to the second group of connection degrees, the fourth insertion position is determined, that is, the lowest priority position of cache insertion. For easy understanding, take Figure 4 The disclosed insertion position schematic diagram under a specific scenario is taken as an example for description, at this time, the first group of connection degrees corresponding to the shared cache is 16, and the second group of connection degrees corresponding to the private cache is 4, then the first insertion position is 16, the second insertion position is 16-(16-4) / 3=12, the third insertion position is 4+(16-4) / 3=7, and the fourth insertion position is 4.

[0059] Specifically, the determination of the target insertion position according to the target program category and the preset mapping relationship table includes: in response to detecting that the program category is the first category, determining that the first insertion position is the target insertion position; in response to detecting that the program category is the second category, determining that the second insertion position is the target insertion position; in response to detecting that the program category is the third category, determining that the third insertion position is the target insertion position; and in response to detecting that the program category is the fourth category, determining that the fourth insertion position is the target insertion position. That is, the first category matches the first insertion position, the second category matches the second insertion position, the third category matches the third insertion position, and the fourth category matches the fourth insertion position. Correspondingly, take Figure 4 The disclosed insertion position schematic diagram under a specific scenario is taken as an example for description, then the target insertion position corresponding to the first category is 16, the target insertion position corresponding to the second category is 12, the target insertion position corresponding to the third category is 7, and the target insertion position corresponding to the fourth category is 4.

[0060] Through the above steps, when an application program running on a target processor core needs to be inserted into a shared cache, according to the category of the application program determined, the insertion position matched with the program category is found from a preset mapping relationship table, the data belonging to different programs is placed in different priority positions, it is further ensured that the data with low hit rate will not be placed in a high priority position, the rate of high hit rate data being replaced is slowed down, and the overall cache hit rate is improved.

[0061] For the convenience of understanding, the present application provides the following specific implementation scenarios, assuming that at a certain moment, the data blocks stored in the cache system are as shown in Figure 5 The processor includes 4 cores: core 1, core 2, core 3 and core 4, a two-level cache system architecture, the group connection degree of the private first-level cache is 4, and the group connection degree of the shared second-level cache is 16. The program running on the core 1 is of the first category, the program running on the core 2 is of the second category, the program running on the core 3 is of the third category, and the program running on the core 4 is of the fourth category.

[0062] From the above, it can be known that the insertion positions of the data blocks belonging to different cores in the shared cache are respectively: the first insertion position corresponding to the core 1 is 16, the second insertion position corresponding to the core 2 is 12, the third insertion position corresponding to the core 3 is 7, and the fourth insertion position corresponding to the core 4 is 4. The number of bits added to a certain data row in the shared cache is 2 bits.

[0063] Suppose that at this moment, the core 1 accesses the data A11, and there is no hit in the private cache and the shared cache, at this moment, the data A11 needs to be read from the main memory to the cache system. At the same time, because the shared cache is full, a replacement operation needs to be performed. The data blocks in the shared cache from the low priority position 1 to the fourth insertion position 4 (i.e. the preset cache area) are traversed, C2 is still in the private cache of the core 3 and needs to be inserted into the third insertion position corresponding to the third category, that is, position 7; B9 is still in the private cache of the core 2 and needs to be inserted into the position corresponding to the second category, that is, position 12; A1 does not exist in any processor core and is selected as the final replaced data block. In addition, the data block A11 read from belongs to the core 1, and its insertion position in the cache is the first insertion position corresponding to the first category, which is the highest priority. After the above operation is completed, the cache system presents as shown in Figure 6 .

[0064] Through the description of the above implementation, those skilled in the art can clearly understand that the method according to the above embodiment can be realized by means of software and the necessary general hardware platform, of course, it can also be realized by hardware, but in many cases, the former is a better implementation.

[0065] The embodiment of the present application provides a data management system, as shown in Figure 7 , comprising:

[0066] The request receiving module 710 is configured to, in response to receiving a data access request initiated by a target processor core, acquire an access data block matched with the data access request;

[0067] The cache replacement module 720 is configured to trigger a cache replacement operation according to the access data block and the data distribution characteristics of the cache system.

[0068] The cache replacement module 720 is further configured to determine a target replacement data block according to the cached data blocks in the preset cache interval in the shared cache and the cached data blocks in the private cache; insert the access data block into a target insertion position matched with the target processor core and delete the target replacement data block.

[0069] Embodiments of the present application also provide an electronic device, which comprises one or more processors and a memory associated with the one or more processors, the memory being configured to store program instructions, which, when read and executed by the one or more processors, perform the following operations:

[0070] In response to receiving a data access request initiated by a target processor core, an access data block matched with the data access request is obtained.

[0071] A cache replacement operation is triggered according to the access data block and the data distribution characteristics of the cache system.

[0072] A target replacement data block is determined according to the cached data blocks in the preset cache interval in the shared cache and the cached data blocks in the private cache.

[0073] The access data block is inserted into a target insertion position matched with the target processor core, and the target replacement data block is deleted.

[0074] In some implementation scenarios, the program instructions, when read and executed by the one or more processors, further perform a determination method of the target insertion position.

[0075] A target program category matched with a current running program of the target processor core is obtained, wherein the program category is determined according to a preset program classification rule.

[0076] The target insertion position is determined from a plurality of cache insertion positions according to the target program category and a preset mapping relationship table, wherein the mapping relationship table contains the relationship between the program category and the cache insertion position in the shared cache.

[0077] In some implementation scenarios, the program instructions, when read and executed by the one or more processors, further perform the program classification rule.

[0078] The highest non-zero bit position of an access register in the target processor core is obtained, wherein the access register is configured to record the number of data access requests initiated by the target processor core.

[0079] find a first bit value and a second bit value in a hit register in the target processor core, the first bit value matching a highest non-zero bit position and the second bit value matching a bit position next to the highest non-zero bit position, the hit register being used to record a number of hits of a data access request in the target processor core;

[0080] determine a program category according to the first bit value and the second bit value.

[0081] In some implementation scenarios, the program instructions, when executed by one or more processors, further perform the following operations:

[0082] in response to detecting that the first bit value and the second bit value are both first preset values, determine that the target program category is a first category;

[0083] in response to detecting that the first bit value is the first preset value and the second bit value is a second preset value, determine that the target program category is a second category;

[0084] in response to detecting that the first bit value is the second preset value and the second bit value is both the first preset value, determine that the target program category is a third category;

[0085] in response to detecting that the first bit value and the second bit value are both the second preset value, determine that the target program category is a fourth category.

[0086] In some implementation scenarios, the program instructions, when executed by one or more processors, further perform a determination method of a cache insertion position:

[0087] determine a first insertion position according to a first degree of connection of the shared cache;

[0088] determine a second insertion position according to the first degree of connection, a second degree of connection of the private cache, and a first preset formula, wherein the first preset formula is L1=X+(Y-X) / 3, X represents the second degree of connection, Y represents the first degree of connection, and L1 represents the second insertion position;

[0089] determine a third insertion position according to the first degree of connection, the second degree of connection, and a second preset formula, wherein the first preset formula is L2=Y-(Y-X) / 3, and L2 represents the third insertion position;

[0090] determine a fourth insertion position according to the second degree of connection.

[0091] In some implementation scenarios, the program instructions, when executed by one or more processors, further perform the following operations:

[0092] in response to detecting that the program category is the first category, determine that the first insertion position is a target insertion position;

[0093] In response to detecting that the program category is the second category, determining the second insertion position as the target insertion position;

[0094] In response to detecting that the program category is the third category, determining the third insertion position as the target insertion position;

[0095] In response to detecting that the program category is the fourth category, determining the fourth insertion position as the target insertion position.

[0096] In some implementation scenarios, the program instructions, when read and executed by the one or more processors, further perform the following operations:

[0097] performing a data block matching operation to select a first cached data block from the cached data blocks within the preset cache interval for comparison with the cached data blocks of the private cache;

[0098] In response to detecting that the first cached data block is not duplicated in the cached data blocks within the private cache, determining the first cached data block as the target replacement data block;

[0099] In response to detecting that the first cached data block is duplicated in the cached data blocks within the private cache, repeatedly performing the data block matching operation until the cached data blocks within the preset cache interval are traversed.

[0100] In some implementation scenarios, the program instructions, when read and executed by the one or more processors, further perform the following data block matching operation:

[0101] selecting a first cached data block from the cached data blocks within the preset cache interval according to the priority from low to high;

[0102] detecting whether the first cached data block is duplicated in the cached data blocks within the private cache.

[0103] In some implementation scenarios, the program instructions, when read and executed by the one or more processors, further perform the following operations:

[0104] In response to detecting that the first cached data block is duplicated in the cached data blocks within the private cache, detecting whether the first cached data block is the data block with the highest priority within the preset cache interval;

[0105] In response to detecting that the first cached data block is the data block with the highest priority within the preset cache interval, determining the first cached data block as the target replacement data block.

[0106] In some implementation scenarios, the program instructions, when read and executed by the one or more processors, further perform the following operations:

[0107] if there is a cached data block matching the access data block in the cache system, feeding back the cached data block to respond to the data access request;

[0108] If there is no cached data block matching the access data block in the cache system, it is determined whether to trigger a cache replacement operation according to the cache occupancy state of the shared cache.

[0109] In some implementation scenarios, the program instructions, when read and executed by the one or more processors, further perform the following operations:

[0110] In response to detecting that the cache occupancy state of the shared cache is a full state, the cache replacement operation is triggered;

[0111] In response to detecting that the cache occupancy state of the shared cache is a non-full state, the access data block is inserted into a target insertion position matching the target processor core.

[0112] In some implementation scenarios, the program instructions, when read and executed by the one or more processors, further perform the following operations:

[0113] If the cached data block matching the access data block belongs to the private cache and belongs to the target processor core, the cached data block is fed back to respond to the data access request;

[0114] If the cached data block matching the access data block belongs to the private cache but belongs to a non-target processor core, the data state of the cached data block is set to an invalid state in the non-target processor core, and the cached data block is fed back to the target processor core to respond to the data access request;

[0115] If the cached data block matching the access data block belongs to the shared cache, the cached data block is fed back to the target processor core to respond to the data access request.

[0116] In the above embodiments, the processor can be a general-purpose CPU (Central Processing Unit), a microprocessor, an application-specific integrated circuit (ASIC), or one or more integrated circuits, etc. Figure 8 An exemplary architecture of an electronic device is shown, which can specifically include a processor 810, a video display adapter 811, a disk drive 812, an input / output interface 813, a network interface 814, and a memory 820. The processor 810, the video display adapter 811, the disk drive 812, the input / output interface 813, the network interface 814, and the memory 820 can be communicatively connected through a bus 830.

[0117] The processor 410 can be implemented in a general-purpose CPU (Central Processing Unit), a microprocessor, an application-specific integrated circuit (ASIC), or one or more integrated circuits, etc., for executing related programs to implement the technical solutions provided in the present application.

[0118] The memory 820 can be implemented in the form of a ROM (Read Only Memory), a RAM (Random Access Memory), a static storage device, a dynamic storage device, etc. The memory 820 can store an operating system 821 for controlling operations performed by the electronic device 800, a basic input / output system (BIOS) 822 for controlling low-level operations of the electronic device 800. In addition, a web browser 823, a data storage management system 824, an icon font processing system 825, etc. can also be stored. The icon font processing system 825 described above can be an application program that specifically implements the operations of the above steps in the embodiments of the present application. In summary, when the technical solutions provided by the present application are implemented by software or firmware, the relevant program codes are stored in the memory 820 and are executed by the processor 810.

[0119] The input / output interface 813 is configured to connect an input / output module to realize information input and output. The input / output module can be configured as a component in the device (not shown in the figure) or can be externally connected to the device to provide corresponding functions. The input device can include a keyboard, a mouse, a touch screen, a microphone, various sensors, etc., and the output device can include a display, a speaker, a vibrator, an indicator light, etc.

[0120] The network interface 814 is configured to connect a communication module (not shown in the figure) to realize communication interaction between the device and other devices. The communication module can realize communication through a wired manner (such as USB, network cable, etc.) or through a wireless manner (such as mobile network, WIFI, Bluetooth, etc.).

[0121] The bus 830 includes a path for transmitting information between various components (such as the processor 810, the video display adapter 811, the disk drive 812, the input / output interface 813, the network interface 814, and the memory 820) of the device.

[0122] In addition, the electronic device 800 can also obtain information of the specific obtaining condition from the virtual resource object obtaining condition information database to be used for condition judgment.

[0123] It should be noted that although the above device only shows the processor 810, the video display adapter 811, the disk drive 812, the input / output interface 813, the network interface 818, the memory 820, the bus 830, etc., in the specific implementation process, the device can also include other components necessary for normal execution. In addition, those skilled in the art can understand that the above device can also only contain components necessary for implementing the solutions of the present application, and does not necessarily contain all the components shown in the figure.

[0124] The embodiment of the present application further provides a computer readable storage medium, which stores a computer program, wherein the computer program is arranged to execute the steps in any of the above data management method embodiments when running.

[0125] In an example embodiment, the above computer readable storage medium can include, but is not limited to, a U disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a mobile hard disk, a magnetic disk or an optical disk, and various media that can store computer programs.

[0126] The embodiment of the present application further provides a computer program product, which comprises a computer program, and the computer program is executed by a processor to implement the steps in any of the above data management method embodiments.

[0127] The embodiment of the present application further provides another computer program product, which comprises a non-volatile computer readable storage medium, and the non-volatile computer readable storage medium stores a computer program, and the computer program is executed by a processor to implement the steps in any of the above data management method embodiments.

[0128] The skilled in the art can further realize that the units and algorithm steps of the examples described in combination with the embodiments disclosed herein can be realized in electronic hardware, computer software or combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the components and steps of the examples have been described in the above description in general. Whether the functions are realized in hardware or software depends on the specific application and design constraints of the technical solution. The skilled in the art can use different methods to realize the described functions for each specific application, but such implementation should not be considered beyond the scope of the present application.

[0129] The above has introduced in detail a data management method provided by the present application. The principle and implementation mode of the present application are described by applying specific examples in this paper, and the above example description is only used to help understand the method of the present application and its core idea. It should be pointed out that, for the ordinary skilled in the art, some improvements and modifications can be made to the present application without departing from the principle of the present application, and these improvements and modifications also fall within the protection scope of the present application.

Claims

1. A data management method, characterized in that: Applied to a cache system, the cache system including a shared cache and a private cache, the method comprising: In response to receiving a data access request initiated by a target processor core, obtaining an access data block matching the data access request; According to the access data block and the data distribution characteristics of the cache system, a cache replacement operation is triggered: Determining a target replacement data block based on cached data blocks in a preset cache interval in the shared cache and cached data blocks in the private cache; inserting the access data block into a target insertion position matching the target processor core and deleting the target replacement data block; The step of determining the target replacement data block based on the cached data blocks in the preset cache interval in the shared cache and the cached data blocks in the private cache includes: performing a data block matching operation to select a first cache data block from the cached data blocks within the preset cache interval and compare it with the cached data blocks of the private cache; In response to not detecting that the first cached data block is duplicated with a cached data block in the private cache, determining that the first cached data block is a target replacement data block; In response to detecting that the first cached data block is duplicated with a cached data block in the private cache, repeatedly performing the data block matching operation until all cached data blocks in the preset cache interval are traversed, and detecting whether the first cached data block is a data block with the highest priority in the preset cache interval; In response to detecting that the first cached data block is the data block with the highest priority in the preset cache interval, the first cached data block is determined to be a target replacement data block.

2. The method according to claim 1, characterized in that Method for determining the target insertion position: Obtaining a target program category that matches a currently running program on the target processor core, wherein the program category is determined according to a preset program classification rule; The target insertion position is determined from a plurality of cache insertion positions according to the target program category and a preset mapping relationship table, wherein the mapping relationship table includes a relationship between program categories and the cache insertion positions in the shared cache.

3. The method according to claim 2, characterized in that The program categories include the first category, the second category, the third category, and the fourth category. The program classification rules include: Obtaining a highest non-zero bit position of an access register within the target processor core, the access register being used to record the number of data access requests initiated by the target processor core; searching a hit register in the target processor core for a first bit value that matches the highest non-zero bit position and a second bit value that matches a bit position following the highest non-zero bit position, the hit register being used to record a hit count of the data access request in the target processor core; The program category is determined according to the first bit value and the second bit value.

4. The method according to claim 3, characterized in that The determining the program category according to the first bit value and the second bit value includes: In response to detecting that both the first bit value and the second bit value are first preset values, determining that the target program category is a first category; In response to detecting that the first bit value is the first preset value and the second bit value is the second preset value, determining that the target program category is a second category; In response to detecting that the first bit value is the second preset value and the second bit values ​​are both the first preset value, determining that the target program category is a third category; In response to detecting that both the first bit value and the second bit value are the second preset value, the target program category is determined to be a fourth category.

5. The method according to claim 3, characterized in that The cache insertion position includes a first insertion position, a second insertion position, a third insertion position, and a fourth insertion position. The method for determining the cache insertion position includes: determining a first insertion position according to a first set of connectivity of the shared cache; Determining a second insertion position according to the first set of connectivity, the second set of connectivity of the private cache, and a first preset formula, wherein the first preset formula is L1=X+(YX) / 3, where X represents the second set of connectivity, Y represents the first set of connectivity, and L1 represents the second insertion position; Determining a third insertion position according to the first set of connectivity, the second set of connectivity, and a second preset formula, wherein the first preset formula is L2=Y-(YX) / 3, and L2 represents the third insertion position; A fourth insertion position is determined according to the second set of connectivity degrees.

6. The method according to claim 5, characterized in that The step of determining the target insertion position according to the target program category and a preset mapping relationship table includes: In response to detecting that the program category is the first category, determining the first insertion position as a target insertion position; In response to detecting that the program category is the second category, determining the second insertion position as a target insertion position; In response to detecting that the program category is the third category, determining the third insertion position as a target insertion position; In response to detecting that the program category is the fourth category, the fourth insertion position is determined as a target insertion position.

7. The method according to claim 1, characterized in that The data block matching operation includes: Selecting a first cache data block from the cached data blocks in the preset cache interval according to the order of priority from low to high; Detect whether the first cache data block and the cached data blocks in the private cache are duplicated.

8. The method according to claim 1, characterized in that The data distribution characteristics include cached data blocks and cache occupancy status, and triggering a cache replacement operation based on the accessed data blocks and the data distribution characteristics of the cache system includes: If there is a cached data block matching the accessed data block in the cache system, feeding back the cached data block in response to the data access request; If there is no cached data block matching the accessed data block in the cache system, determining whether to trigger a cache replacement operation is determined according to the cache occupancy status of the shared cache.

9. The method according to claim 8, characterized in that The determining whether to trigger a cache replacement operation according to the cache occupancy status of the shared cache includes: In response to detecting that the cache occupancy state of the shared cache is full, triggering a cache replacement operation; In response to detecting that the cache occupancy state of the shared cache is not full, inserting the access data block into a target insertion position that matches the target processor core.

10. The method according to claim 8, characterized in that If there is a cached data block in the cache system that matches the accessed data block, feeding back the cached data block in response to the data access request includes: If the cached data block that matches the accessed data block belongs to a private cache and belongs to the target processor core, feeding back the cached data block in response to the data access request; If the cached data block matched by the accessed data block belongs to a private cache but belongs to a non-target processor core, setting a data state of the cached data block to an invalid state in the non-target processor core and feeding the cached data block back to the target processor core to respond to the data access request; If the cached data block that matches the accessed data block belongs to a shared cache, the cached data block is fed back to the target processor core to respond to the data access request.

11. An electronic device, characterized in that: include: Memory for storing computer programs; A processor, configured to implement the steps of the data management method according to any one of claims 1 to 10 when executing the computer program.

12. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, wherein the computer program, when executed by a processor, implements the steps of the data management method according to any one of claims 1 to 10.

13. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the data management method according to any one of claims 1 to 10 are implemented.

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