Method for accessing flash memory module and semiconductor package

Abstract

The present invention discloses a method for accessing a flash memory module, wherein the flash memory module includes at least one flash memory chip, each flash memory chip includes a plurality of blocks, each block is implemented by a plurality of word lines, each word line corresponds to K pages, and the method includes: receiving data from a host device; generating virtual data; and writing the data and the accompanying virtual data into a plurality of specific blocks, wherein for each word line of a portion of the word lines of the plurality of word lines of the plurality of specific blocks, the virtual data is written into at least one page of the K pages, and the data from the host device is written into the other pages of the K pages. In addition, the present invention can increase the data stability of the embedded multimedia memory card.

Description

Technical Field

[0001] The present invention relates to a flash memory, and in particular to an embedded Multi-Media-Card (eMMC) comprising a flash memory controller and a flash memory module. Background Art

[0002] Embedded multimedia memory cards are a popular storage component for many electronic devices (e.g., smartphones, tablets, and laptops). Embedded multimedia memory cards in electronic devices are pre-processed in the factory to have boot code, operating system (OS) code, and digital content, so that users can use the electronic device immediately after receiving the product.

[0003] In order to quickly write the boot code, operating system code and digital content into the embedded multimedia memory card, the embedded multimedia memory card is connected to a slot or a tool for data writing, and then the embedded multimedia memory card is mounted on the printed circuit board (PCB) used by the electronic device. Although a wave soldering process can be performed to mount the embedded multimedia memory card on the PCB, the wave soldering process has a relatively high temperature, which may cause the data recorded in the embedded multimedia memory card to be damaged or the data quality to be reduced. Summary of the invention

[0004] Therefore, one object of the present invention is to disclose a method for accessing a flash memory module and a related embedded multimedia memory card, which can increase the data stability of the embedded multimedia memory card to solve the above-mentioned problem.

[0005] According to one embodiment of the present invention, a method for accessing a flash memory module is disclosed, wherein the flash memory module includes at least one flash memory chip, each flash memory chip includes multiple blocks, each block is implemented by multiple word lines, each word line corresponds to K pages, and each word line includes multiple memory cells supporting multiple states, and the method includes: receiving data from a host device; generating dummy data based on the data from the host device; and writing the data and the accompanying dummy data into multiple specific blocks, wherein for each word line of a portion of the multiple word lines of the multiple specific blocks, the dummy data is written to at least one page of the K pages, and the data from the host device is written to the other pages of the K pages.

[0006] According to one embodiment of the present invention, a semiconductor package including a flash memory module and a flash memory controller is disclosed, wherein the flash memory module includes at least one flash memory chip, each flash memory chip includes multiple blocks, each block is implemented by multiple word lines, each word line corresponds to K pages, and each word line includes multiple storage cells supporting multiple states, and the flash memory controller is coupled to the flash memory module and is used to receive data from a host device; generate dummy data based on the data from the host device; and write the data and the accompanying dummy data into multiple specific blocks, wherein for each word line of a portion of the multiple word lines of the multiple specific blocks, the dummy data is written to at least one page of the K pages, and the data from the host device is written to the other pages of the K pages. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 FIG. 4 is a schematic diagram of an electronic device according to an embodiment of the present invention.

[0008] Figure 2 FIG. 4 is a schematic diagram of a three-dimensional NAND (3D NAND) flash memory according to an embodiment of the present invention.

[0009] Figure 3 FIG. 4 is a schematic diagram of multiple states (programming states) of a memory cell in a triple-level cell (TLC) block according to an embodiment of the present invention.

[0010] Figure 4 FIG. 4 is a schematic diagram of a method for accessing a flash memory module according to an embodiment of the present invention.

[0011] Figure 5 Multiple blocks in a flash memory module are shown.

[0012] Figure 6 FIG. 4 is a schematic diagram of multiple states (programming states) of a memory cell in a quad-level cell (QLC) block according to an embodiment of the present invention.

[0013] Figure 7 FIG. 4 is a schematic diagram of a method for accessing a flash memory module according to another embodiment of the present invention.

[0014] The reference numerals are described as follows:

[0015] 10: Electronic devices

[0016] 50: Host device

[0017] 52: Processor

[0018] 54: Power supply circuit

[0019] 100: Storage device

[0020] 110: Flash memory controller

[0021] 112: Microprocessor

[0022] 112C: Programming code

[0023] 112M: Read-only memory

[0024] 114: Control logic circuit

[0025] 116: Random Access Memory

[0026] 118: Transmission interface circuit

[0027] 120: Flash Memory Module

[0028] 122-4~122-N: Flash memory chip

[0029] 132: Encoder

[0030] 134:Decoder

[0031] 136: Randomizer

[0032] 138:De-Randomizer

[0033] PSD(1)~PSD(Ny):Circuit module

[0034] BL(1)~BL(Nx): bit lines

[0035] S(1,1)~S(Nx,Ny): Subcircuit module

[0036] MBLS(1,1)~MBLS(Nx,Ny): upper selection circuit

[0037] BLS(1)~BLS(Ny): Upper selection line

[0038] WL(1,1)~WL(Ny,Nz): word line

[0039] M(1,1,1)~M(Nx,Ny,Nz): storage unit

[0040] MSLS(1,1)~MSLS(Nx,Ny): lower selection circuit

[0041] SLS(1)~SLS(Ny): Lower selection line

[0042] SL(1)~SL(Ny): Source line

[0043] S0~S15: Status

[0044] VR1~VR15: Read voltage

[0045] 400~414,700~718: Steps

[0046] B_1~B_3M: Block DETAILED DESCRIPTION

[0047] Figure 1This is a schematic diagram of an electronic device 10 according to an embodiment of the present invention, wherein the electronic device 10 may include a host device 50 and a storage device 100, the host device 50 may include at least one processor (e.g., one or more processors), which may be generally regarded as a processor 52, and further includes a power supply circuit 54 coupled to the processor 52. The processor 52 is used to control the operation of the host device 50, and the power supply circuit 54 is used to provide power to the processor 52 and the storage device 100, and output one or more driving voltages to the storage device 100. The storage device 100 can be used to provide storage space to the host device 50, and obtain one or more driving voltages from the host device 50 as the power supply of the storage device 100. In this embodiment, the storage device can be an embedded multimedia memory card; and when the embedded multimedia memory card is in the factory, the host device 50 can be a data writing machine for writing the startup code, operating system code, digital content and any other required data into the embedded multimedia memory card; and when the embedded multimedia memory card is embedded in a printed circuit board and placed in an electronic device (such as a smart phone, a tablet computer or any other portable electronic device), the host device 50 can be a processor. According to this embodiment, the storage device 100 may include a flash memory controller 110 and may further include a flash memory module 120, wherein the flash memory controller 110 is used to control the operation of the storage device 100 and access the flash memory module 120, and the flash memory module 120 is used to store information. The flash memory module 120 may include at least one flash memory chip, such as multiple flash memory chips 122-1, 122-2,..., and 122-N, wherein "N" may represent a positive integer greater than 1.

[0048] like Figure 1As shown, the flash memory controller 110 may include a processing circuit (e.g., a microprocessor 112), a storage unit (e.g., a read-only memory (ROM) 112M), a control logic circuit 114, a random-access memory (RAM) 116, and a transmission interface circuit 118, wherein the above elements may be coupled to each other via a bus, and the random-access memory 116 may be connected to the storage device via a static random-access memory (SRAM). The random access memory 116 may be implemented by using a random access memory (RAM, SRAM), but the present invention is not limited thereto. The random access memory 116 may be used to provide internal storage space for the flash memory controller. For example, the random access memory 116 may be used as a buffer memory to buffer data. In addition, the read-only memory 112M of the present embodiment is used to store the program code 112C, and the microprocessor 112 is used to execute the program code 112C to control the access of the flash memory module 120. It should be noted that in some examples, the program code 112C may be stored in the random access memory 116 or any type of memory. In addition, the control logic circuit 114 may be used to control the flash memory module 120, and may include an encoder 132, a decoder 134, a randomizer 136, a de-randomizer 138, and other circuits. The transmission interface circuit 118 may comply with a specific communication standard, such as the Serial Advanced Technology Attachment (Serial ATA or SATA) standard, the Peripheral Component Interconnect (Peripheral Component Interconnect) standard, and the like. The host device 50 may include a corresponding transmission interface circuit that complies with the specific communication standard to communicate between the host device 50 and the storage device 100.

[0049] In this embodiment, the host device 50 can transmit a host command and a corresponding logical address to the flash memory controller 110 to access the storage device 100. The flash memory controller 110 receives the host command and the logical address, and translates the host command into a storage operation command (which can be simply referred to as an operation command), and further controls the flash memory module 120 through the operation command to read, write, and program (programming), etc., a storage unit (such as a data page) having a physical address in the flash memory 120, wherein the physical address corresponds to the logical address. When the flash memory controller 110 performs an erase operation on any flash memory chip 122-n of the multiple flash memory chips 122-1, 122-2, ..., 122-N (where "n" can represent any integer in the interval [1, N]), at least one block of the multiple blocks of the flash memory chip 122-n can be erased, wherein any block of the multiple blocks can include multiple pages (such as data pages), and an access operation (such as reading or writing) can be performed on one or more pages.

[0050] Figure 2 is a schematic diagram of a three-dimensional NAND flash memory according to an embodiment of the present invention. For example, any storage element in at least one of the plurality of flash memory chips 122-1, 122-2, ..., 122-N may be based on Figure 2 The three-dimensional NAND gate flash memory is shown as an implementation, but the present invention is not limited thereto.

[0051] According to this embodiment, the three-dimensional NAND flash memory may include a plurality of memory cells arranged in a three-dimensional structure, for example, (Nx*Ny*Nz) memory cells {{M(1,1,1),…,M(Nx,1,1)},{M(1,2,1),…,M(Nx,2,1)},…,{M(1,Ny,1),…,M(Nx,Ny,1)}},{{M(1,1,2),…,M(Nx,1,2)},{M(1,2,2),…,M(Nx,2,2)},…,{M {{M(1,1,Nz),…,M(Nx,1,Nz)},{M(1,2,Nz),…,M(Nx,2,Nz)},…,{M(1,Ny,Nz),…,M(Nx,Ny,Nz)}}, which are respectively arranged in Nz layers perpendicular to the Z axis and are respectively aligned in three directions corresponding to the X axis, the Y axis and the Z axis, and may further include a plurality of selection circuits (selector For example, (Nx*Ny) upper selector circuits {MBLS(1,1),…,MBLS(Nx,1)}, {MBLS(1,2),…,MBLS(Nx,2)},…, {MBLS(1,Ny),…,MBLS(Nx,Ny)} are arranged in the upper layer of the Nz layers, and (Nx*Ny) lower selector circuits {MSLS(1,1),…,MSLS(Nx,1)}, {MSLS(1,2),…,MSLS(Nx,2)},…, {MSLS(1,Ny),…,MSLS(Nx,Ny)} are arranged in the lower layer of the Nz layers. In addition, the three-dimensional NAND flash memory may include a plurality of bit lines and a plurality of word lines for performing access control. line), for example, the Nx bit lines BL(1), ..., BL(Nx) arranged in the top layer above the upper layer, and the (Ny*Nz) word lines {WL(1,1), WL(2,1), ..., WL(Ny,1)}, {WL(1,2), WL(2,2), ..., WL(Ny,2)}, ..., {WL(1,Nz), WL(2,Nz), ..., WL(Ny,Nz)}, in addition, the three-dimensional NAND flash memory may include a plurality of selection lines for selection control, such as Ny upper selection lines BLS(1), BLS(2), ..., and BLS(Ny) arranged in the upper layer and Ny lower selection lines SLS(1), SLS(2), ..., and SLS(Ny) arranged in the lower layer, and may further include a plurality of source lines to provide reference levels, such as Ny source lines SL(1), SL(2), ..., and SL(Ny) arranged in the bottom layer. ,

[0052] like Figure 2As shown, the three-dimensional NAND flash memory can be divided into Ny circuit modules PS2D(1), PS2D(2), ..., PS2D(Ny) distributed along the Y axis. For better understanding, the circuit modules PS2D(1), PS2D(2), ..., PS2D(Ny) may have some electronic characteristics similar to those of a planar NAND flash memory having a plurality of storage cells arranged in a single layer, and may be respectively regarded as pseudo-2D circuit modules, but the present invention is not limited thereto. In addition, any circuit module PS2D(ny) among the circuit modules PS2D(1), PS2D(2), ..., PS2D(Ny) may include Nx secondary circuit modules. module)S(1,ny),…,S(Nx,ny), where “ny” can represent any integer in the interval [1,Ny]. For example, circuit module PS2D(1) can include Nx sub-circuit modules S(1,1),…,S(Nx,1), circuit module PS2D(2) can include Nx sub-circuit modules S(1,2),…,S(Nx,2),…, and circuit module PS2D(Ny) can include Nx sub-circuit modules S(1,Ny),…,S(Nx,Ny).In the circuit module PS2D(ny), any sub-circuit module S(nx,ny) among the sub-circuit modules S(1,ny), ..., S(Nx,ny) may include Nz storage units M(nx,ny,1), M(nx,ny,2), ..., M(nx,ny,Nz), and may include a set of selection circuits corresponding to the storage units M(nx,ny,1), M(nx,ny,2), ..., M(nx,ny,Nz), such as an upper selection circuit MBLS(nx,ny) and a lower selection circuit MSL S(nx,ny), where "nx" can represent any integer in the interval [1,Nx], and the upper selection circuit MBLS(nx,ny), the lower selection circuit MSLS(nx,ny) and the storage units M(nx,ny,1), M(nx,ny,2), ..., M(nx,ny,Nz) can be implemented by transistors. For example, the upper selection circuit MBLS(nx,ny) and the lower selection circuit MSLS(nx,ny) can be implemented by ordinary transistors without using any floating gates. gate), and any memory cell M(nx,ny,nz) among the memory cells M(nx,ny,1), M(nx,ny,2), ..., M(nx,ny,Nz) can be implemented by a floating gate transistor, wherein "nz" can represent any integer in the interval [1,Nz], but the present invention is not limited thereto. In addition, the upper selection circuits MBLS(1,ny), ..., MBLS(Nx,ny) in the circuit module PS2D(ny) can be selected according to the selection signal on the corresponding selection line BLS(ny), and the lower selection circuits MSLS(1,ny), ..., MSLS(Nx,ny) in the circuit module PS2D(ny) can be selected according to the selection signal on the corresponding selection line SLS(ny).

[0053] In the flash memory module 120, when a block of any one of the flash memory chips 122-1-122-N is used as a single-level cell (SLC) block, each physical page in the block corresponds to a logical page, that is, each storage cell of the physical page is used to store a single bit, and one physical page may include all transistors controlled by a word line (for example, storage cells M(1,1,Nz)-M(Nx,1,Nz) corresponding to word line WL(1,Nz) constitute a physical page); when a block of any one of the flash memory chips 122-1-122-N is used as a multiple-level cell (MLC) block, each physical page in the block corresponds to two logical pages, that is, each storage cell of the physical page is used to store two bits; when a block of any one of the flash memory chips 122-1-122-N is used as a triple-level cell (MLC) block, each physical page in the block corresponds to two logical pages, that is, each storage cell of the physical page is used to store two bits. When the flash memory chip 122-1-122-N is used as a quad-level cell (QLC) block, each physical page in the block corresponds to three logical pages, that is, each storage unit of the physical page is used to store three bits. When the flash memory chip 122-1-122-N is used as a quad-level cell (QLC) block, each physical page in the block corresponds to four logical pages, that is, each storage unit of the physical page is used to store four bits.

[0054] Figure 3 FIG. 1 is a schematic diagram of multiple states (programming states) of a memory cell in a three-layer cell block according to an embodiment of the present invention. Figure 3 As shown, each storage cell can have eight states, and each state represents a different combination of three bits, the three bits are the least significant bit (LSB), the center significant bit (CSB) and the most significant bit (MSB). Figure 3In the illustrated embodiment, when the memory cell is programmed to have state S0, the least significant bit, the middle significant bit, and the most significant bit stored in the memory cell are (1, 1, 1), respectively; when the memory cell is programmed to have state S1, the least significant bit, the middle significant bit, and the most significant bit stored in the memory cell are (1, 1, 0), respectively; when the memory cell is programmed to have state S2, the least significant bit, the middle significant bit, and the most significant bit stored in the memory cell are (1, 0, 0), respectively; when the memory cell is programmed to have state S3, the least significant bit, the middle significant bit, and the most significant bit stored in the memory cell are (0, 0, 0), respectively. 0); when the memory cell is programmed to have state S4, the least significant bit, the middle significant bit, and the most significant bit stored in the memory cell will be (0, 1, 0), respectively; when the memory cell is programmed to have state S5, the least significant bit, the middle significant bit, and the most significant bit stored in the memory cell will be (0, 1, 1), respectively; when the memory cell is programmed to have state S6, the least significant bit, the middle significant bit, and the most significant bit stored in the memory cell will be (0, 0, 1), respectively; and when the memory cell is programmed to have state S7, the least significant bit, the middle significant bit, and the most significant bit stored in the memory cell will be (1, 0, 1), respectively.

[0055] When the flash memory controller 110 wants to read the least significant bit, the flash memory controller 110 can control the flash memory module 120 to apply two read voltages VR3 and VR7 to read the storage unit. If the storage unit is conductive when the read voltage VR7 is applied or the storage unit is non-conductive when the read voltage VR3 is applied, the least significant bit is judged to be "1"; if the storage unit is non-conductive when the read voltage VR7 is applied and conductive when the read voltage VR3 is applied, the least significant bit is judged to be "0". When the flash memory controller 110 wants to read the intermediate valid bit, the flash memory controller 110 can control the flash memory module 120 to apply three read voltages VR2, VR4 and VR6 to read the storage unit. If the storage unit is non-conductive when the read voltage VR2 is applied, the intermediate valid bit is determined to be "1"; if the storage unit is non-conductive when the read voltage VR4 is applied, and is conductive when the read voltage VR2 is applied, the intermediate valid bit is determined to be "0"; if the storage unit is non-conductive when the read voltage VR6 is applied, and is conductive when the read voltage VR4 is applied, the intermediate valid bit is determined to be "1"; and, if the storage unit is conductive when the read voltage VR6 is applied, the intermediate valid bit is determined to be "0". When the flash memory controller 110 wants to read the most significant bit, the flash memory controller 110 can control the flash memory module 120 to apply two read voltages VR1 and VR5 to read the storage unit. If the storage unit is conductive when the read voltage VR5 is applied, or the storage unit is non-conductive when the read voltage VR1 is applied, then the most significant bit is determined to be "1"; if the storage unit is non-conductive when the read voltage VR5 is applied, and if the storage unit is conductive when the read voltage VR1 is applied, then the most significant bit is determined to be "0".

[0056] exist Figure 3 In the illustrated embodiment, the least significant bits of all memory cells on a single word line constitute a least significant bit data page (logical page), the middle significant bits of all memory cells on a single word line constitute a middle significant bit data page (logical page), and the most significant bits of all memory cells on a single word line constitute a most significant bit data page (logical page), that is, each word line of the three-level cell block has three data pages: the least significant bit data page, the middle significant bit data page, and the most significant bit data page.

[0057] It is worth noting that Figure 3 The gray code shown is for illustration only and is not intended to be limiting of the present invention. Any suitable gray code may be applied to the memory device 100, and the read voltages for determining the least significant bit, the middle significant bit, and the most significant bit may vary accordingly.

[0058] like Figure 3 As shown, since the voltage difference between each two adjacent states is very small, the flash memory module 120 may easily encounter data quality problems due to the voltage shifting of these states, especially when the storage device 100 is at a high temperature, such as in the aforementioned wave soldering process. Therefore, in order to increase the data stability of the flash memory module 120, before the storage device 100 is embedded on the printed circuit board and placed in the electronic device, the data will only be written to a single data page or two data pages in each word line so that these states have a larger range. Then, after the storage device 100 is placed in the electronic device and is in a better environment, the flash memory controller 110 can perform a garbage collection operation on the flash memory module 120 to reorganize the data, thereby increasing the data density and releasing storage space.

[0059] Figure 44 is a schematic diagram of a method for accessing a flash memory module according to an embodiment of the present invention. In step 400, the process starts, the storage device 100 is connected to the host device 50, and the host device 50 is ready to write data to the storage device 100. In this embodiment, the storage device 100 is a single semiconductor package, such as an embedded multimedia memory card, that is, the storage device 100 has not been embedded with a printed circuit board and has not been placed in an electronic device. In addition, the host device 50 is a data writing device in a factory. In step 402, the flash memory controller 110 starts to receive data from the host device 50. In step 404, the flash memory controller 110 determines the writing mechanism, that is, the flash memory controller 110 will write the data from the host device 50 to only a single data page of each word line in multiple blocks, only two data pages of each word line in multiple blocks, or multiple blocks. In the present embodiment, the write mechanism may be determined by the data size and the storage capacity of the flash memory module 120, and the write mechanism may be set by an engineer. In the present embodiment, if the data size is less than one-third of the storage capacity of the flash memory module 120, only a single data page in the word line will be used to store the data from the host device 50; if the data size is greater than one-third of the storage capacity of the flash memory module 120 and less than two-thirds of the storage capacity of the flash memory module 120, only two data pages in the word line will be used to store the data from the host device 50; and, if the data size is greater than two-thirds of the storage capacity of the flash memory module 120, three data pages in the word line (i.e., all data pages) will be used to store the data from the host device 50. If the write mechanism indicates that only a single data page in the word line is used to store data from the host device 50 , the process proceeds to step 406 ; if the write mechanism indicates that only two data pages in the word line are used to store data from the host device 50 , the process proceeds to step 410 .

[0060] In step 406, the flash memory controller 110 generates dummy data corresponding to the two data pages in the word line according to the data received from the host device 50. In step 408, for each word line in a plurality of specific blocks for storing data from the host device 50, the dummy data is written to the two data pages, and the data from the host device 50 is written to another data page using only two non-adjacent states in the storage cell, wherein the two non-adjacent states correspond to "0" and "1", respectively. Figure 3For example, data from the host device 50 will be written to the least significant bit data page, and state S0 with "1" and state S5 with "0" can be selected as the above two non-adjacent states. It should be noted that state S0 and state S5 are not limitations of the present invention, and other combinations such as S0 and S6, or S3 and S7, etc. can be selected. At this time, if the received data corresponding to a storage unit has a logic value of "1", the flash memory controller 110 can generate virtual data CSB=1 and MSB=1 to correspond to state S0; and if the received data has a logic value of "0", the flash memory controller 110 can generate virtual data CSB=1 and MSB=1 to correspond to state S5. That is to say, in this embodiment, data from the host device 50 will be written to the LSB data page of the word line of multiple specific blocks, and the virtual data generated by the flash memory controller 110 will be written to the CSB data page and the MSB data page in the word line of the multiple specific blocks.

[0061] In addition, for any specific block among the multiple specific blocks, a logical-to-physical (L2P) mapping table and / or a physical-to-logical (P2L) mapping table can be established to record the mapping relationship between the logical address and the physical address, and the L2P table and / or the P2L table are written to the last data page of the specific block. In the present embodiment, because the virtual data generated by the flash memory controller 110 is written to the CSB data page and the MSB data page of the word line of the multiple specific blocks, only about one-third of the physical addresses in the specific block will correspond to the valid logical address, and about two-thirds of the physical addresses in the specific block will not correspond to the valid logical address.

[0062] In step 410, the flash memory controller 110 generates virtual data corresponding to a single page of word lines based on the data received from the host device 50. In step 412, the virtual data is written to the single page, and the data from the host device 50 is written to the other two pages using only four non-adjacent states, wherein the four states correspond to (1,1), (1,0), (0,0), and (0,1) of the two pages, respectively. Figure 3For example, data from the host device 50 will be written to the LSB data page and the MSB data page, and state S0 corresponding to (LSB=1, MSB=1), state S2 corresponding to (LSB=1, MSB=0), state S4 corresponding to (LSB=0, MSB=0), and state S6 corresponding to (LSB=0, MSB=1) can be selected as the above four states. It should be noted that this is not a limitation of the present invention. At this time, if the received data corresponding to a storage unit has a value (LSB=1, MSB=1), the flash controller 110 can generate virtual data CSB=1 corresponding to state S0; if the received data corresponding to a storage unit has a value (LSB=1, MSB=0), the flash controller 110 can generate virtual data CSB=0 corresponding to state S2; if the received data corresponding to a storage unit has a value (LSB=0, MSB=0), the flash controller 110 can generate virtual data CSB=1 corresponding to state S4; and if the received data corresponding to a storage unit has a value (LSB=0, MSB=1), the flash controller 110 can generate virtual data CSB=0 corresponding to state S6. That is to say, in this embodiment, the data from the host device 50 will be written to the LSB data page and the MSB data page of the word line of multiple specific blocks, and the virtual data generated by the flash controller 110 will be written to the CSB data page of the word line of the multiple specific blocks.

[0063] In addition, for any specific block among the multiple specific blocks, the L2P table and / or the P2L table are written to the last data page of the specific block. In the present embodiment, because the virtual data generated by the flash memory controller 110 is written to the CSB data page of the word line of the multiple specific blocks, only about two-thirds of the physical addresses in the specific block correspond to the valid logical addresses, and about one-third of the physical addresses in the specific block do not correspond to the valid logical addresses.

[0064] Furthermore, if the write mechanism indicates that three data pages (ie, all data pages) of a word line are used to store data from the host device 50, the data is written to the flash memory module 120 using conventional techniques.

[0065] To briefly summarize steps 404 to 412, most or all of the blocks of the flash memory module 120 can be used as three-layer cell blocks with higher data density. However, considering that the memory device 100 may be subjected to high temperature during the manufacturing process, multiple specific blocks used to store data from the host device 50 are used as multi-layer cell blocks or single-layer cell blocks with fewer states and higher data stability to avoid data damage during the manufacturing process. Figure 5 According to an embodiment of the present invention, a plurality of blocks in a flash memory module are illustrated. Figure 5 , it is assumed that the total number of the plurality of blocks is "3*M". If blocks B_1 to B(M-1) as three-layer unit blocks can store all data received from the host device 50, when each specific block is used as a single-layer unit block, the flash memory controller 110 can write the data to multiple specific blocks, such as B_1 to B_(2*M+X), where "X" can be any appropriate value less than M. If blocks B_1 to B(M-1) as three-layer unit blocks are not sufficient to store all data received from the host device 50, but blocks B_1 to B(2*M-1) as three-layer unit blocks can store all data received from the host device 50, then when each specific block is used as a multi-layer unit block, the flash memory controller 110 can write the data to multiple specific blocks, such as B_1 to B_(2*M+X).

[0066] In step 414, after the storage device 100 is placed in the electronic device and the electronic device starts operating, that is, Figure 1 The host device 50 shown in the figure now becomes a processor or a chipset of the electronic device. The flash memory controller 110 performs a garbage collection operation on the flash memory module 120 to move valid data of some of the multiple blocks to a plurality of blank blocks to release the space of the partial blocks, wherein the valid data of some of the specific blocks in the multiple specific blocks are written to all three pages of each word line of the multiple blank blocks to Figure 5 For example, if specific blocks B_1~B_(2*M+X) as single-layer unit blocks store data from the host device 50, then the garbage collection operation can be performed to move the valid data from blocks B_1~B_3 to the blank block B_(3*M-1) as a three-layer unit block, and move the valid data from blocks B_4~B_6 to the blank block B_3*M as a three-layer unit block to increase data density, and blocks B_1~B_6 are erased to release storage space.

[0067] It is worth noting that the purpose of allowing the multiple specific blocks to be used as multi-layer cell blocks or single-layer cell blocks to store data from the host device 50 is to increase the data stability so as to pass through a high-temperature process (such as a wave soldering process), and some of the multiple specific blocks released by the garbage collection operation will be used as three-layer cell blocks for subsequent use. That is to say, after blocks B_1~B_6 are erased to release storage space, blocks B_1~B_6 will be used as three-layer cell blocks to store data from the host device 50 next time. In this embodiment, blocks B_1~B_6 will be used as single-layer cell blocks or multi-layer cell blocks only during the first data write operation.

[0068] In one embodiment, the garbage collection operation may be performed immediately after the user starts the electronic device for the first time. That is, after the user starts the electronic device, the storage device 100 may actively schedule the garbage collection operation to perform the garbage collection operation at an appropriate time.

[0069] In one embodiment, the flash memory controller 110 can actively perform a garbage collection operation even if the quality of the multiple blocks used to store data from the host device 50 is so good that the garbage collection operation does not need to be performed in a normal operation. In other words, because the multiple blocks are intentionally used as single-layer cell blocks or multi-layer cell blocks in steps 404 to 412, the flash memory controller 110 will sequentially rearrange the data so that a portion of the multiple blocks become triple-layer cell blocks with higher data density.

[0070] It is worth noting that the above embodiment can also be applied to a flash memory module 120 having four-layer cell blocks. Figure 6 FIG. 1 is a schematic diagram of multiple states (programming states) of a memory cell in a four-layer cell block according to an embodiment of the present invention. Figure 6 As shown, each memory cell can have sixteen states, and each state represents a different combination of four bits called top bit, upper bit, middle bit, and lower bit, such as Figure 6In the embodiment shown, when the memory cell is programmed to have state S0, the highest bit, upper bit, middle bit and lower bit stored in the memory cell are (1, 1, 1, 1); when the memory cell is programmed to have state S1, the highest bit, upper bit, middle bit and lower bit stored in the memory cell are (1, 1, 1, 0); when the memory cell is programmed to have state S2, the highest bit, upper bit, middle bit and lower bit stored in the memory cell are (1, 0, 1, 0); when the memory cell is programmed to have state S3, the highest bit, upper bit, middle bit and lower bit stored in the memory cell are (1, 0, 0 ,0); when the memory cell is programmed to have state S4, the highest bit, upper bit, middle bit and lower bit stored in the memory cell are (1,0,0,1); when the memory cell is programmed to have state S5, the highest bit, upper bit, middle bit and lower bit stored in the memory cell are (0,0,0,1); when the memory cell is programmed to have state S6, the highest bit, upper bit, middle bit and lower bit stored in the memory cell are (0,0,0,0); when the memory cell is programmed to have state S7, the highest bit, upper bit, middle bit and lower bit stored in the memory cell are (0,0,1,0); When the memory cell is programmed to have state S8, the highest bit, upper bit, middle bit and lower bit stored in the memory cell are (0, 1, 1, 0); when the memory cell is programmed to have state S9, the highest bit, upper bit, middle bit and lower bit stored in the memory cell are (0, 1, 0, 0); when the memory cell is programmed to have state S10, the highest bit, upper bit, middle bit and lower bit stored in the memory cell are (1, 1, 0, 0); when the memory cell is programmed to have state S11, the highest bit, upper bit, middle bit and lower bit stored in the memory cell are (1, 1, 0, 1); When the memory cell is programmed to have state S12, the highest bit, upper bit, middle bit and lower bit stored in the memory cell are (0, 1, 0, 1); when the memory cell is programmed to have state S13, the highest bit, upper bit, middle bit and lower bit stored in the memory cell are (0, 1, 1, 1); when the memory cell is programmed to have state S14, the highest bit, upper bit, middle bit and lower bit stored in the memory cell are (0, 0, 1, 1); and when the memory cell is programmed to have state S15, the highest bit, upper bit, middle bit and lower bit stored in the memory cell are (1, 0, 1, 1).

[0071] In conventional technology, when the flash memory controller 110 needs to read the highest bit, the flash memory controller 110 may control the flash memory module 120 to apply four read voltages VR5, VR10, VR12 and VR15 to read the storage cell; when the flash memory controller 110 needs to read the higher bit, the flash memory controller 110 may control the flash memory module 120 to apply three read voltages VR2, VR8 and VR14 to read the storage cell; when the flash memory controller 110 needs to read the middle bit, the flash memory controller 110 may control the flash memory module 120 to apply four read voltages VR3, VR7, VR9 and VR13 to read the storage cell; and when the flash memory controller 110 needs to read the lower bit, the flash memory controller 110 may control the flash memory module 120 to apply four read voltages VR1, VR4, VR6 and VR11 to read the storage cell.

[0072] Figure 7Schematic diagram of a method for accessing a flash memory module according to another embodiment of the present invention. In step 700, the process starts, the storage device 100 is connected to the host device 50, and the host device 50 is ready to write data to the storage device 100. In this embodiment, the storage device 100 has not yet been embedded with a printed circuit board and has not been placed in an electronic device, and the host device 50 is a data writing device in a factory. In step 702, the flash memory controller 110 starts to receive data from the host device 50. In step 704, the flash memory controller 110 determines a write mechanism, that is, the flash memory controller 110 writes the data from the host device 50 to only a single data page of each word line of multiple blocks, only two data pages of each word line of multiple blocks, only three data pages of each word line of multiple blocks, or four data pages of each word line of multiple blocks (i.e., all data pages). In this embodiment, the write mechanism can be determined by the data The write mechanism can be set by engineers. In the present embodiment, if the size of the data is less than one-fourth of the storage capacity of the flash memory module 120, only a single data page of the word line will be used to store the data from the host device 50; if the size of the data is greater than one-fourth of the storage capacity of the flash memory module 120 and less than two-fourths of the storage capacity of the flash memory module 120, only two data pages of the word line will be used to store the data from the host device 50; if the size of the data is greater than two-fourths of the storage capacity of the flash memory module 120 and less than three-fourths of the storage capacity of the flash memory module 120, only three data pages of the word line will be used to store the data from the host device 50; and if the size of the data is greater than three-fourths of the storage capacity of the flash memory module 120, all four data pages of the word line will be used to store the data from the host device 50. If the write mechanism indicates that only a single data page of the word line will be used to store data from the host device 50, the process enters step 706; if the write mechanism indicates that only two data pages of the word line will be used to store data from the host device 50, the process enters step 710; and if the write mechanism indicates that only three data pages of the word line will be used to store data from the host device 50, the process enters step 714.

[0073] In step 706, the flash controller 110 generates virtual data corresponding to three data pages of the word line according to the data received from the host device 50, and in step 708, for each word line of a plurality of specific blocks for storing data from the host device 50, the virtual data is written to the three pages, and the data from the host device 50 is written to the other one page by using only two non-adjacent states, wherein the two non-adjacent states correspond to "0" and "1", respectively. In step 710, the flash controller 110 generates virtual data corresponding to two data pages of the word line according to the data received from the host device 50, and in step 712, the virtual data is written to the two data pages, and the data from the host device 50 is written to the other two data pages by using only four non-adjacent states. In step 714, the flash controller 110 generates virtual data corresponding to a single data page of the word line according to the data received from the host device 50, and in step 716, the virtual data is written to the single data page, and the data from the host device 50 is written to the other three data pages by using only eight non-adjacent states.

[0074] Furthermore, if the write mechanism indicates that four data pages (ie, all data pages) of a word line are used to store data from the host device 50, the data is written to the flash memory module 120 using conventional techniques.

[0075] To briefly summarize steps 704 to 716, most or all of the blocks of the flash memory module 120 can be used as four-layer cell blocks with higher data density. However, considering that the memory device 100 may be subjected to high temperature during the manufacturing process, multiple specific blocks used to store data from the host device 50 are used as three-layer cell blocks, multi-layer cell blocks, or single-layer cell blocks with fewer states and higher data stability to avoid data damage during the manufacturing process.

[0076] In step 718, after the storage device 100 is placed in the electronic device and the electronic device starts operating, that is, Figure 1 The host device 50 shown now becomes a processor or a chipset of the electronic device, and the flash memory controller 110 performs a garbage collection operation on the flash memory module 120 to move valid data of some blocks among the multiple blocks to multiple blank blocks to free up space in the partial blocks, wherein the valid data of some specific blocks among the multiple specific blocks are written to all four pages of each word line of the multiple blank blocks.

[0077] In brief summary, in the present invention, the embedded multimedia memory card can be controlled to use the blocks of the flash memory module 120 as multi-layer unit blocks or single-layer unit blocks with fewer states and higher data stability. After the embedded multimedia memory card is embedded in the printed circuit board at normal temperature, a garbage collection operation is performed to increase data density and release storage space. Therefore, the process of the embedded multimedia memory card can become very good.

[0078] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A method for accessing a flash memory module, wherein the flash memory module comprises at least one flash memory chip, each flash memory chip comprises a plurality of blocks, each block comprises a plurality of word lines, each word line corresponds to K pages, K is equal to 3 or 4, and each word line comprises a plurality of storage cells supporting a plurality of states, and the method is characterized in that it comprises: (1) receiving data from a host device; (2) determining a ratio between a size of virtual data and the size of the data from the host device with reference to a size of the data and a storage capacity of the flash memory module; (3) generating the virtual data for the host device according to the ratio; (4) writing the data and the accompanying dummy data into a plurality of specific blocks, wherein for each word line of a portion of the plurality of word lines of the plurality of specific blocks, the dummy data is written into at least one page of the K pages, and the data from the host device is written into other pages of the K pages, so that the plurality of specific blocks are used as single-layer cell blocks or multi-layer cell blocks when K is equal to 3, or so that the plurality of specific blocks are used as single-layer cell blocks, multi-layer cell blocks, or triple-layer cell blocks when K is equal to 4; (5) performing a garbage collection operation on the flash memory module to move valid data of a portion of the specific blocks among the plurality of specific blocks to a plurality of blank blocks to release space of the portion of the specific blocks among the plurality of specific blocks; and (6) Writing other data different from the data to all the K pages of each word line of the specific block of the portion, so that the multiple specific blocks are used as three-layer unit blocks when K is equal to 3, or as four-layer unit blocks when K is equal to 4.

2. The method according to claim 1, characterized in that K is equal to three, and the step of writing the data and the accompanying dummy data into the plurality of specific blocks comprises: If the size of the data is less than one third of the storage capacity of the flash memory module, for each word line of the portion of the plurality of word lines of the plurality of specific blocks, the dummy data is written to two pages, and the data from the host device is written to the three pages Another page in as well as If the size of the data is greater than one-third of the storage capacity of the flash memory module and less than two-thirds of the storage capacity of the flash memory module, for each word line of the portion of the multiple word lines of the multiple specific blocks, the virtual data is written to one page, and the data is written from the host device to the other two pages of the three pages.

3. The method according to claim 2, characterized in that Each storage unit supports eight states, and the step of writing the data and the accompanying dummy data into the plurality of specific blocks includes: If the size of the data is less than one third of the storage capacity of the flash memory module, for each word line of the portion of the plurality of word lines of the plurality of specific blocks, the dummy data is written to two pages, and the data from the host device is written to the other page using only two non-adjacent states of the plurality of memory cells; as well as If the size of the data is greater than one-third of the storage capacity of the flash memory module and less than two-thirds of the storage capacity of the flash memory module, for each word line of the portion of the multiple word lines of the multiple specific blocks, the virtual data is written to one page, and only four non-adjacent states are used to write the data from the host device to the other two pages.

4. The method according to claim 1, characterized in that K is equal to four, and the step of writing the data and the accompanying dummy data into the plurality of specific blocks comprises: If the size of the data is less than one quarter of the storage capacity of the flash memory module, for each word line of the portion of the plurality of word lines of the plurality of specific blocks, the dummy data is written to three pages, and the data from the host device is written to another one of the four pages; If the size of the data is greater than one quarter of the storage capacity of the flash memory module and less than two quarters of the storage capacity of the flash memory module, for each word line of the portion of the plurality of word lines of the plurality of specific blocks, the dummy data is written to two pages, and the data from the host device is written to the other two pages of the four pages; as well as If the size of the data is greater than two quarters of the storage capacity of the flash memory module and less than three quarters of the storage capacity of the flash memory module, for each word line of the portion of the multiple word lines of the multiple specific blocks, the virtual data is written to one page, and the data from the host device is written to the other three pages of the four pages.

5. The method according to claim 4, characterized in that Each storage unit supports sixteen states, and the step of writing the data and the accompanying dummy data into the plurality of specific blocks includes: If the size of the data is less than one quarter of the storage capacity of the flash memory module, for each word line of the portion of the plurality of word lines of the plurality of specific blocks, the dummy data is written to three pages, and only two non-adjacent states of the plurality of memory cells are used to write the data from the host device to another one of the four pages; If the size of the data is greater than one quarter of the storage capacity of the flash memory module and less than two quarters of the storage capacity of the flash memory module, for each word line of the portion of the plurality of word lines of the plurality of specific blocks, the dummy data is written to two pages, and the data from the host device is written to the other two pages of the four pages using only four non-adjacent states of the plurality of memory cells; as well as If the size of the data is greater than two quarters and less than three quarters of the storage capacity of the flash memory module, for each word line of the portion of the multiple word lines of the multiple specific blocks, the virtual data is written to one page, and only eight non-adjacent states of the multiple storage cells are used to write the data from the host device to the other three pages of the four pages.

6. The method according to claim 1, characterized in that The method is executed by an embedded multimedia memory card including a flash memory controller and the flash memory module, and steps (1), (3) and (4) of the method are executed before the embedded multimedia memory card is placed in an electronic device.

7. The method according to claim 6, characterized in that Steps (1), (3) and (4) of the method are performed before the embedded multimedia memory card is installed on a printed circuit board applied to the electronic device.

8. The method according to claim 6, characterized in that: After the embedded multimedia memory card is placed in the electronic device and the electronic device starts to operate, performing the garbage collection operation on the flash memory module to move valid data of a portion of the specific blocks among the plurality of specific blocks to the plurality of blank blocks to release space of the portion of the specific blocks among the plurality of specific blocks; The valid data of the specific block of the portion of the specific blocks is written into all the pages of the K pages of each word line of the blank blocks.

9. The method according to claim 8, characterized in that The step of performing the garbage collection operation on the flash memory module to move the valid data of the specific block of the portion of the specific blocks to the plurality of blank blocks comprises: After the embedded multimedia memory card is placed in the electronic device and the electronic device starts operating, even if the quality of the specific blocks in the portion of the multiple specific blocks is so good that the garbage collection operation does not need to be performed in a normal operation of the embedded multimedia memory card, the garbage collection operation is still performed on the flash memory module to move the valid data of the specific blocks in the portion of the multiple specific blocks to the multiple blank blocks.

10. The method according to claim 1, characterized in that The data from the host device includes a startup code, an operating system code and digital content.

11. A storage device, characterized in that: Contains: A flash memory module, wherein the flash memory module includes at least one flash memory chip, each flash memory chip includes a plurality of blocks, each block includes a plurality of word lines, each word line corresponds to K pages, K is equal to 3 or 4, and each word line includes a plurality of storage cells supporting multiple states; and a flash memory controller coupled to the flash memory module, configured to receive data from a host device, generate virtual data, and write the virtual data and the accompanying data into a plurality of specific blocks, wherein a ratio between a size of the virtual data and a size of the data from the host device is determined with reference to the size of the data and a storage capacity of the flash memory module; wherein for each word line of a portion of the plurality of word lines of the plurality of specific blocks, the dummy data is written into at least one page of the K pages, and the data from the host device is written into other pages of the K pages, so that the plurality of specific blocks are used as single-layer cell blocks or multi-layer cell blocks when K is equal to 3, or so that the plurality of specific blocks are used as single-layer cell blocks, multi-layer cell blocks, or triple-layer cell blocks when K is equal to 4; wherein the flash memory controller performs a garbage collection operation on the flash memory module to move valid data of a portion of the specific blocks among the plurality of specific blocks to a plurality of blank blocks to release space of the portion of the specific blocks among the plurality of specific blocks; And writing other data different from the data into all pages of the K pages of each word line of the specific block of the portion, so that the multiple specific blocks are used as three-level unit blocks when K is equal to 3, or as four-level unit blocks when K is equal to 4.

12. The storage device according to claim 11, wherein: K is equal to three; if the size of the data is less than one-third of the storage capacity of the flash memory module, for each word line of the portion of the multiple word lines of the multiple specific blocks, the virtual data is written to two pages, and the data from the host device is written to the other one of the three pages; and if the size of the data is greater than one-third of the storage capacity of the flash memory module and less than two-thirds of the storage capacity of the flash memory module, for each word line of the portion of the multiple word lines of the multiple specific blocks, the virtual data is written to one page, and the data from the host device is written to the other two of the three pages.

13. The storage device according to claim 12, wherein: Each memory cell supports eight states; if the size of the data is less than one-third of the storage capacity of the flash memory module, for each word line of the portion of the multiple word lines of the multiple specific blocks, the virtual data is written to two pages, and only two non-adjacent states of the multiple memory cells are used to write the data from the host device to the other page; and if the size of the data is greater than one-third of the storage capacity of the flash memory module and less than two-thirds of the storage capacity of the flash memory, for each word line of the portion of the multiple word lines of the multiple specific blocks, the virtual data is written to one page, and only four non-adjacent states of the multiple memory cells are used to write the data from the host device to the other two pages.

14. The storage device according to claim 11, wherein: K is equal to four; if the size of the data is less than one-fourth of the storage capacity of the flash memory module, for each of the portion of the multiple word lines of the multiple word lines of the multiple specific blocks, the virtual data is written to three pages, and the data from the host device is written to the other one of the four pages; if the size of the data is greater than one-fourth of the storage capacity of the flash memory module and less than two-fourths of the storage capacity of the flash memory module, for each of the portion of the multiple word lines of the multiple specific blocks, the virtual data is written to two pages, and the data from the host device is written to the other two of the four pages; and if the size of the data is greater than two-fourths of the storage capacity of the flash memory module and less than three-fourths of the storage capacity of the flash memory module, for each of the portion of the multiple word lines of the multiple word lines of the multiple specific blocks, the virtual data is written to one page, and the data from the host device is written to the other three of the four pages.

15. The storage device according to claim 14, wherein: Each memory cell supports sixteen states; if the size of the data is less than one-fourth of the storage capacity of the flash memory module, for each word line of the portion of the word lines of the plurality of specific blocks, the dummy data is written to three pages, and only two non-adjacent states of the plurality of memory cells are used to write the data from the host device to another one of the four pages; if the size of the data is greater than one-fourth of the storage capacity of the flash memory module and less than two-fourths of the storage capacity of the flash memory, for each word line of the portion of the word lines of the plurality of specific blocks, the dummy data is written to three pages, and only two non-adjacent states of the plurality of memory cells are used to write the data from the host device to another one of the four pages. word lines of the multiple word lines of the multiple specific blocks, the dummy data is written to two pages, and only four non-adjacent states of the multiple memory cells are used to write the data from the host device to the other two pages of the four pages; and if the size of the data is greater than two quarters of the storage capacity of the flash memory module and less than three quarters of the storage capacity of the flash memory, for each word line of the portion of the multiple word lines of the multiple specific blocks, the dummy data is written to one page, and only eight non-adjacent states of the multiple memory cells are used to write the data from the host device to the other three pages of the four pages.

16. The storage device according to claim 11, wherein: The storage device is an embedded multimedia memory card, and before the embedded multimedia memory card is placed in an electronic device, the flash memory controller writes the data and the accompanying virtual data into the specific block.

17. The storage device according to claim 16, wherein: After the embedded multimedia memory card is placed in the electronic device and the electronic device starts to operate, the flash memory controller performs the garbage collection operation on the flash memory module to move the valid data of the portion of the specific blocks among the multiple specific blocks to the multiple blank blocks to release the space of the portion of the specific blocks among the multiple specific blocks; wherein the valid data of the portion of the specific blocks among the multiple specific blocks is written to all pages of the K pages of each word line of the multiple blank blocks.

18. The storage device according to claim 16, wherein: After the embedded multimedia memory card is placed in the electronic device and the electronic device starts operating, even if the quality of the specific blocks in the portion of the multiple specific blocks is so good that the garbage collection operation does not need to be performed in a normal operation of the embedded multimedia memory card, the garbage collection operation is still performed on the flash memory module to move the valid data of the specific blocks in the portion of the multiple specific blocks to the multiple blank blocks.

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