Quantum signature nuclear alignment

Abstract

Illustrative embodiments provide a method, system, and computer program product for quantum feature kernel alignment using a hybrid classical-quantum computing system. An embodiment of a method for hybrid classical-quantum decider training includes receiving a training data set. In an embodiment, the method includes selecting, by a first processor, sampled objects from the training set, each object represented by at least one vector. In an embodiment, the method includes applying, by a quantum processor, a set of quantum feature maps to the selected objects, the set of quantum maps corresponding to a set of quantum kernels. In an embodiment, the method includes evaluating, by a quantum processor, a set of parameters of a quantum feature map circuit corresponding to at least one quantum feature map in the set of quantum feature maps.

Description

Technical Field

[0001] The present invention generally relates to quantum classifier training using quantum computing. More specifically, the present invention relates to a system and method for quantum feature kernel alignment for classifier and other quantum decision system training using hybrid classical-quantum computing systems. Background Art

[0002] In the following, unless explicitly distinguished when used, the "Q" prefix in a word or phrase indicates a reference to the word or phrase in the context of quantum computing.

[0003] Molecules and subatomic particles obey the laws of quantum mechanics, a branch of physics that explores how the physical world works at its most fundamental level. At this level, particles behave in strange ways, taking on more than one state at the same time and interacting with other particles that are very far away. Quantum computing exploits these quantum phenomena to process information.

[0004] The computers we commonly use now are called classical computers (also referred to herein as "conventional" computers or conventional nodes, or "CN"). Conventional computers use conventional processors, which are manufactured using semiconductor materials and technologies, semiconductor memories, and magnetic or solid-state storage devices, which is called the von Neumann architecture. In particular, the processors in conventional computers are binary processors, that is, they operate on binary data represented by 1 and 0.

[0005] Quantum processors (q-processors) use the unique properties of entangled quantum bit devices (referred to herein as "qubits") to perform computational tasks. In a specific area where quantum mechanics operates, particles of matter can exist in multiple states, such as "on", "off", and both "on" and "off" at the same time. While binary computing using semiconductor processors is limited to using only on and off states (equivalent to 1 and 0 in binary code), quantum processors use these quantum states of matter to output signals that can be used for data computation.

[0006] Classical computers encode information in bits. Each bit can take on a value of 1 or 0. These 1s and 0s act as switches that ultimately drive the on / off functions of the computer. Quantum computers, on the other hand, are based on qubits, which operate according to two key principles of quantum physics: superposition and entanglement. Superposition means that each qubit can represent a 1 and 0 inference between possible outcomes of an event. Entanglement means that qubits in superposition can be related to each other in a nonclassical way; that is, the state of one qubit (whether it is 1 or 0 or both) can depend on the state of another qubit, and when two qubits are entangled, they contain more information than two separate qubits.

[0007] Using these two principles, qubits operate as information processors, enabling quantum computers to function in a way that allows them to solve certain difficult problems that are intractable using conventional computers.

[0008] In traditional circuits, Boolean logic gates arranged in series manipulate a series of bits. Gate logic techniques for optimizing binary calculations are well known. Circuit optimization software for traditional circuits is intended to improve efficiency and reduce the complexity of traditional circuits. Circuit optimization software for traditional circuits operates in part by breaking down the overall desired behavior of traditional circuits into simpler functions. Traditional circuit optimization software is more easily manipulated and handles simpler functions. Circuit optimization software generates an effective layout of design elements on traditional circuits. Therefore, circuit optimization software for traditional circuits significantly reduces resource requirements, thereby improving efficiency and reducing complexity.

[0009] The illustrative embodiments recognize that in a quantum circuit, quantum gates manipulate qubits to perform quantum computations. A quantum gate is a unitary matrix transformation that acts on a qubit. Due to the superposition and entanglement of qubits, a quantum gate represents a 2n×2n matrix, where n is the number of qubits manipulated by the quantum gate. The illustrative embodiments recognize that because the size of the matrix transformation increases exponentially with the number of qubits, the decomposition of such a matrix transformation quickly becomes too complex to perform manually. For example, a 2-qubit quantum computer requires 4×4 matrix operators to represent a quantum gate. A 10-qubit quantum computer requires 1024×1024 matrix operators to represent a quantum gate. As a result of the exponential increase, manual quantum logic gate matrix transformations quickly become unmanageable as the number of qubits increases.

[0010] Circuit optimization for quantum circuits depends on the chosen functionality, resource requirements, and other design criteria for the quantum circuit. For example, quantum circuits are often optimized to work with a specific device. Summary of the invention

[0011] According to one aspect, a method for hybrid classical-quantum decider training is provided, the method comprising: receiving a training data set; selecting, by a first processor, sampled objects from the training set, each object being represented by at least one vector; applying, by a quantum processor, a quantum feature map set to the selected objects, the quantum map set corresponding to a quantum kernel set; evaluating, by the quantum processor, a parameter set of a quantum feature mapping circuit corresponding to at least one quantum feature map in the quantum feature map set; determining, by the first processor, a new parameter set for the quantum feature mapping circuit; and parameterizing, by the first processor, the quantum feature mapping circuit using the new parameter set.

[0012] According to another aspect, a computer usable program product is provided, comprising one or more computer-readable storage devices, and program instructions stored on at least one of the one or more storage devices, the stored program instructions comprising: program instructions for receiving a training data set; program instructions for selecting, by a first processor, sampled objects from the training set, each object represented by at least one vector; program instructions for applying, by a quantum processor, a set of quantum feature maps to the selected objects, the set of quantum maps corresponding to a set of quantum kernels; program instructions for evaluating, by the quantum processor, a set of parameters for a quantum feature mapping circuit corresponding to at least one quantum feature map in the set of quantum feature maps; program instructions for determining, by the first processor, a new set of parameters for the quantum feature mapping circuit; and program instructions for parameterizing, by the first processor, the quantum feature mapping circuit using the new set of parameters.

[0013] According to another aspect, a computer system is provided, comprising one or more processors, one or more computer-readable memories, one or more computer-readable storage devices, and program instructions for execution stored on at least one of the one or more storage devices, the program instructions being executed by at least one of the one or more processors via at least one of the one or more memories. The stored program instructions include: program instructions for receiving a training data set; program instructions for selecting a sampled object from the training set by a first processor, each object being represented by at least one vector; program instructions for applying a quantum feature map set to the selected object by a quantum processor, the quantum map set corresponding to a quantum kernel set; program instructions for evaluating a parameter set of a quantum feature mapping circuit corresponding to at least one quantum feature map in the quantum feature map set by a quantum processor; program instructions for determining a new parameter set for the quantum feature mapping circuit by the first processor; and program instructions for parameterizing the quantum feature mapping circuit by the first processor using the new parameter set.

[0014] Illustrative embodiments provide a method, system, and computer program product for quantum signature kernel alignment using a hybrid classical-quantum computing system. An embodiment of a method for hybrid classical-quantum decider training includes receiving a training data set. In an embodiment, the method includes selecting, by a first processor, sampled objects from the training set, each object represented by at least one vector.

[0015] In an embodiment, the method comprises applying, by a quantum processor, a set of quantum feature maps to a selected object, the set of quantum maps corresponding to a set of quantum kernels. In an embodiment, the method comprises evaluating, by a quantum processor, a set of parameters of a quantum feature map circuit corresponding to at least one quantum feature map in the set of quantum feature maps.

[0016] In an embodiment, the method comprises determining, by the first processor, a new set of parameters for the quantum signature mapping circuit. In an embodiment, the method comprises parameterizing, by the first processor, the quantum signature mapping circuit using the new set of parameters.

[0017] In an embodiment, the method comprises varying the amplitude of microwave pulses of the quantum processor to parameterize the quantum signature mapping circuit. In an embodiment, the method comprises varying the phase of microwave pulses of the quantum processor to parameterize the quantum signature mapping circuit.

[0018] In an embodiment, the method includes determining that the new set of parameters produces an accurate measurement greater than a predetermined threshold. In an embodiment, the method includes applying the parameterized quantum feature mapping circuit to the selected sampling object to calculate a new output vector.

[0019] In an embodiment, the quantum feature mapping circuit includes a set of single-qubit rotation gates. In an embodiment, a subset of the set of single-qubit rotation gates includes a rotation angle. In an embodiment, the rotation angle corresponds to a new parameter set. In an embodiment, the first processor is a classical processor.

[0020] In an embodiment, the method is embodied in a computer program product comprising one or more computer-readable storage devices and computer-readable program instructions stored on the one or more computer-readable tangible storage devices and executed by one or more processors.

[0021] Embodiments include a computer usable program product. The computer usable program product includes a computer readable storage device and program instructions stored on the storage device.

[0022] An embodiment includes a computer system. The computer system includes a processor, a computer-readable memory, a computer-readable storage device, and program instructions stored on the storage device for execution by the processor via the memory.

[0023] In an embodiment, the program instructions are stored in a computer readable storage device in a data processing system and the program instructions are transmitted over a network from a remote data processing system.

[0024] In an embodiment, program instructions are stored in a computer readable storage device in a server data processing system and the program instructions are downloaded over a network to a remote data processing system for use in a computer readable storage device associated with the remote data processing system.

[0025] According to a preferred embodiment, the present invention provides an improved method for compiling quantum circuits.

[0026] A quantum algorithm represents a set of instructions to be executed on a quantum computer. The illustrative embodiments recognize that a quantum algorithm can be modeled as a quantum circuit. A quantum circuit is a computational model formed by a set of quantum logic gates that execute the steps of a corresponding quantum algorithm.

[0027] In machine learning, the classic support vector machine (SVM) is a supervised learning model associated with a learning algorithm that classifies data into categories. Typically, each of the training example sets is labeled as belonging to a certain category, and the SVM training algorithm builds a model to assign new examples to specific categories. The SVM model represents examples as points mapped into a feature space so that examples of different categories are divided by gaps in the feature space. A feature map refers to a mapping of a set of features representing one or more categories. A feature map is constructed by specifying a function called a kernel that calculates the inner product between each pair of data points in the feature space. Using the SVM algorithm, new input data is mapped into the same feature space, and its category is predicted based on the distance from the new example to the example that represents the category using the feature map. Typically, SVM performs classification by finding a hyperplane that maximizes the boundary between two categories. A hyperplane is a subspace whose dimension is one dimension less than its surrounding space, for example, a three-dimensional space has a two-dimensional hyperplane.

[0028] The illustrative embodiments recognize that a quantum decision system (e.g., a quantum classifier, a quantum regressor, a quantum controller, or a quantum predictor) can be used to analyze input data and make decisions about the input data by a quantum classifier. For example, a quantum classifier (e.g., a quantum support vector machine (QSVM)) can be used to analyze input data and determine discrete classifications of the input data by a quantum processor. A quantum processor is capable of generating feature maps that are traditionally difficult to evaluate. A quantum feature map is constructed by specifying a function called a quantum kernel that calculates the inner product between each pair of data points in a quantum feature space. In other examples, a regressor, a controller, or a predictor can operate on a continuous space entity. A quantum classifier (e.g., a QSVM) implements a classifier using a quantum processor that has the ability to improve the speed of classification of certain input data. The illustrative embodiments recognize that training quantum classifiers and other quantum decision systems typically requires large samples of input data.

[0029] There is a class of problems called optimization problems. An optimization problem is a computational problem to determine the best or optimal solution for a different problem, where the different problem has multiple possible solutions. For example, the different problem can be the famous traveling salesman problem, where a route must be determined between a number of cities so that the traveling salesman covers each of these cities without visiting any of them again. This problem has many possible solutions (routes between cities). An optimization problem related to the traveling salesman problem is to find the shortest route, i.e. the best or optimal route, from a number of possible routes, each of which satisfies the requirements of the traveling salesman problem.

[0030] Configuring an optimization problem to be executed on a computer so that the computer can compute the optimal solution in a finite time is a difficult problem in itself. Until recently, the only computing resources available for performing optimization problems were conventional computers as described herein. Many optimization problems are too difficult or too complex for conventional computers to compute in a finite time using reasonable resources. Typically, in such cases, an approximate solution that can be computed in a reasonable time and using reasonable resources is accepted as a near-optimal solution.

[0031] The advent of quantum computing has raised the possibility of improvements in many areas of computing, including computing of optimization problems. Because quantum computing systems can evaluate many solutions from a solution space at once, the illustrative embodiments recognize that such systems are particularly well suited for solving optimization problems.

[0032] The illustrative embodiments recognize that the kernel determines the geometry of the mapped data in feature space. The illustrative embodiments also recognize that the kernel thus has a core impact on the performance of the machine learning algorithm. The illustrative embodiments recognize that kernel alignment is a currently available technique for classical machine learning algorithms to evaluate the quality of the kernel for a given data set. Kernel alignment measures the degree of consistency between a given kernel of a classical machine learning algorithm and a given learning task. The illustrative embodiments recognize that kernel optimization for a given data set increases the accuracy of the machine learning model. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Preferred embodiments of the present invention will now be described, by way of example only, with reference to the following drawings:

[0034] Figure 1 A block diagram showing a network of data processing systems in which the illustrative embodiments may be implemented;

[0035] Figure 2 shows a block diagram of a data processing system in which the illustrative embodiments may be implemented;

[0036] Figure 3 shows a qubit for a quantum processor according to an illustrative embodiment;

[0037] Figure 4 shows a simplified diagram of a matrix representation of an example universal quantum circuit gate in accordance with an illustrative embodiment;

[0038] Figure 5 shows a block diagram of an example hybrid quantum / classical optimization algorithm for quantum feature kernel alignment using a classical processor and a quantum processor in accordance with an illustrative embodiment;

[0039] Figure 6 shows a block diagram of an example quantum signature mapping circuit for a nuclear family using a hybrid classical-quantum computing system in accordance with an illustrative embodiment;

[0040] Figure 7 shows a block diagram of an example quantum signature mapping circuit for another family of cores using a hybrid classical-quantum computing system in accordance with an illustrative embodiment;

[0041] Figure 8 shows a block diagram of an example quantum signature mapping circuit for another family of cores using a hybrid classical-quantum computing system in accordance with an illustrative embodiment;

[0042] Fig. 9 shows a block diagram of an example quantum signature mapping circuit for another family of cores using a hybrid classical-quantum computing system in accordance with an illustrative embodiment;

[0043] Fig.10 A block diagram showing an example configuration for quantum signature kernel alignment using a hybrid classical-quantum computing system in accordance with an illustrative embodiment;

[0044] Fig.11 shows simulation results of training data of a hybrid classical-quantum system for quantum signature kernel alignment according to a preferred embodiment; and

[0045] Fig.12 A flow chart is shown of an example process for quantum signature kernel alignment using a hybrid classical-quantum computing system in accordance with an illustrative embodiment. DETAILED DESCRIPTION

[0046] The illustrative embodiments used to describe the present invention generally address the above-mentioned problems of using quantum computing to solve computational problems.The illustrative embodiments provide a method and system for quantum signature kernel alignment using a hybrid classical-quantum computing system.

[0047] Embodiments provide a method for quantum feature alignment using a hybrid classical - quantum computing system. Another embodiment provides a program product usable by a conventional or quantum computer, including a computer - readable storage device, and program instructions stored on the storage device, the stored program instructions including a method for quantum feature alignment using a hybrid classical - quantum computing system. The instructions are capable of being executed using a conventional or quantum processor. Another embodiment provides a computer system, including a conventional or quantum processor, a computer - readable memory, and a computer - readable storage device, and program instructions are stored on the storage device to be executed by the processor via the memory, the stored program instructions including a method for quantum feature alignment using a hybrid classical - quantum computing system.

[0048] One or more embodiments provide a hybrid classical and quantum method that co - evolves quantum kernel and classical kernel alignment optimization. In one or more embodiments, a classical computer is used to store a large dataset associated with classification training data and perform kernel alignment optimization, and a quantum computer is used to simultaneously evaluate the quality of the quantum kernel.

[0049] In an embodiment, it is assumed that the QSVM constructs the corresponding correct feature map exactly with the correct quantum kernel. In this embodiment, a finite set of quantum kernels is obtained. In a particular embodiment, the quantum kernel can be based on the circuit description of a quantum circuit. In an embodiment, the classical computer tunes the quantum feature map to the dataset. In an embodiment, the classical computer changes the parameters of the quantum circuit to tune the quantum feature map to the dataset.

[0050] For a fixed α, the SVM objective (F) is equivalent to the kernel alignment γ k : Exemplary embodiments recognize that the support vector weights α are not fixed. Given a kernel k, the support vector weights are chosen to maximize F. Learn the margin - maximizing kernel by maximizing the alignment: Subject to the constraints 0 ≤ α ≤ C, y T α = 0.

[0051] A classical optimization program running on a classical processor learns the margin - maximizing kernel by receiving a training sample set S as input, where the training sample set S: (x i , y i ), i = 1, …, n subject to the parameter box constraint C, the number of steps T, the number of gradient ascent steps M with step size {η t}, a subsampled training set The step size n′ < n. Initialize a random set of kernel parameters, the parameter Random support vector weights α+ =α,α - =α. The optimization procedure executes steps t=1, ...T:

[0052] Generate subsets by randomly sampling from S

[0053] Generate a random vector Δ∈{-1,1} m ;

[0054] Calculating λ + =λ+c SPSA，t Δ and λ - =λ-c SPSA，t Δ, get the constant c SPSA，t ;

[0055] Computing the quantum kernel matrix K on a quantum device + =K(λ + ,S′ t ) and K - =K(λ - ,S′ t );

[0056] Use K + Calculate the gradient g +,t =▽ α F(α +，t ,λ +，t ), using K - Calculate the gradient g -,t =▽ α F(α -，t ,λ -，t ).

[0057] Update α via M-step gradient ascent +,t+1 ←Proj[α +,t +η t g +,t ] and α -,t+1 ←Proj[α -,t +η t g -,t ];

[0058] Using the cost function F(α +，t ,λ +，t ) and F(α -，t ,λ -，t ) Update λ via SPSA optimization.

[0059] The embodiment uses the optimized parameter λ * Calculate the kernel matrix K(λ * , S). The embodiment calculates support vector weights, biases, and support vectors by solving a standard SVM quadratic program.

[0060] In an embodiment, a method optimizes the value of an SVM objective function F. In an embodiment, the method minimizes the value of F with respect to a set of quantum kernel parameters. In an embodiment, the method maximizes the value of F with respect to an alignment. In an embodiment, the method maximizes the alignment of a family of quantum kernels.

[0061] Thus, one or more embodiments provide a system and method for selecting a quantum feature map of a data set. Various embodiments provide a classical / quantum approach where a quantum kernel and a classical kernel alignment function are co-evolved and a quantum computer is used to simultaneously evaluate the quality of the quantum kernel.

[0062] For the sake of clarity of description, and without implying any limitation thereto, some example configurations are used to describe the illustrative embodiments. Based on this disclosure, those skilled in the art will be able to conceive of many changes, adaptations and modifications of the configurations for achieving the described purposes, and these are considered to be within the scope of the illustrative embodiments.

[0063] In addition, simplified diagrams of data processing environments are used in the drawings and illustrative embodiments. In an actual computing environment, there may be additional structures or components not shown or described herein, or structures or components that are different from the structures or components shown but are used for functions similar to those described herein, without departing from the scope of the illustrative embodiments.

[0064] Furthermore, the illustrative embodiments describe specific actual or hypothetical components only as examples. The steps described by the various illustrative embodiments may be adapted to enhance quantum sorting using various components that may be purposefully or repurposed to provide the described functionality within a data processing environment, and such adaptations are considered to be within the scope of the illustrative embodiments.

[0065] The illustrative embodiments describe certain types of steps, applications, classical processors, quantum processors, quantum states, classical feature spaces, quantum feature spaces, classical cores, quantum cores, and data processing environments as examples. Any particular manifestation of these and other similar artifacts is not intended to limit the present disclosure. Any suitable manifestation of these and other similar artifacts may be selected within the scope of the illustrative embodiments.

[0066] The examples in this disclosure are only for clarity of description and are not intended to limit the illustrative embodiments. Any advantages listed herein are only examples and are not intended to limit the illustrative embodiments. Additional or different advantages may be achieved through specific illustrative embodiments. In addition, specific illustrative embodiments may have some, all, or none of the advantages listed above.

[0067] With reference to the accompanying drawings, in particular Figure 1 and Figure 2, these figures are exemplary diagrams of data processing environments in which illustrative embodiments may be implemented. Figure 1 and Figure 2 This is merely an example and is not intended to assert or imply any limitation with regard to the environments in which different embodiments may be implemented. Specific implementations may make many modifications to the illustrated environment based on the following description.

[0068] Figure 1 A block diagram of a data processing system network in which the illustrative embodiments may be implemented is shown. Data processing environment 100 is a network of computers in which the illustrative embodiments may be implemented. Data processing environment 100 includes network 102. Network 102 is a medium for providing communication links between various devices and computers connected together within data processing environment 100. Network 102 may include connections such as wired, wireless communication links, or fiber optic cables.

[0069] Client or server are merely example roles for certain data processing systems connected to network 102 and are not intended to exclude other configurations or roles for these data processing systems. Classical processing system 104 is coupled to network 102. Classical processing system 104 is a classical processing system. Software applications can be executed on any quantum data processing system in data processing environment 100. Figure 1 Any software application executed in the classic processing system 104 described in the can be configured to be executed in another data processing system in a similar manner. Figure 1 Any data or information stored or generated in a conventional processing system 104 in a data processing system may be configured to be stored or generated in a similar manner in another data processing system. A classical data processing system (such as the classical processing system 104) may contain data and may have software applications or software tools that perform classical computing processes on the system.

[0070] Server 106 is coupled to network 102 along with storage unit 108. Storage unit 108 includes database 109, which is configured to store classifier training data as described herein with respect to various embodiments. Server 106 is a conventional data processing system. Quantum processing system 140 is coupled to network 102. Quantum processing system 140 is a quantum data processing system. The software application can be executed on any quantum data processing system in data processing environment 100. Figure 1 Any software application executed in the quantum processing system 140 described in can be configured to execute in another quantum data processing system in a similar manner. Figure 1Any data or information stored or generated in a quantum processing system 140 in a quantum data processing system may be configured to be stored or generated in another quantum data processing system in a similar manner. A quantum data processing system (e.g., quantum processing system 140) may contain data and may have a software application or software tool that performs quantum computing processes on the system.

[0071] Clients 110, 112, and 114 are also coupled to network 102. Conventional data processing systems (such as server 106 or clients 110, 112, or 114) may contain data and may have software applications or software tools that perform conventional computing processes on the systems.

[0072] For example only, and without implying any limitation on such architecture, Figure 1 Certain components that can be used in example implementations of the embodiments are shown. For example, server 106 and clients 110, 112, 114 are depicted as servers and clients only as an example, and do not imply limitation to client-server architectures. As another example, an embodiment can be distributed across several traditional data processing systems, quantum data processing systems, and data networks shown, while another embodiment can be implemented on a single traditional data processing system or a single quantum data processing system within the scope of the illustrative embodiments. Traditional data processing systems 106, 110, 112, and 114 also represent example nodes in clusters, partitions, and other configurations suitable for implementing embodiments.

[0073] Device 132 is an example of a conventional computing device as described herein. For example, device 132 may take the form of a smartphone, a tablet computer, a laptop computer, a fixed or portable form of client 110, a wearable computing device, or any other suitable device. Figure 1 Any software application that is executed in another conventional data processing system as described in can be configured to execute in device 132 in a similar manner. Figure 1 Any data or information stored or generated in another conventional data processing system in may be configured to be stored or generated in device 132 in a similar manner.

[0074] Server 106, storage unit 108, classical processing system 104, quantum processing system 140, clients 110, 112, 114, and device 132 may be coupled to network 102 using wired connections, wireless communication protocols, or other suitable data connections. Clients 110, 112, and 114 may be, for example, personal computers or network computers.

[0075] In the example shown, server 106 may provide data, such as boot files, operating system images, and applications to clients 110, 112, and 114. In this example, clients 110, 112, and 114 may be clients to server 106. Clients 110, 112, 114, or some combination thereof, may include their own data, boot files, operating system images, and applications. Data processing environment 100 may include additional servers, clients, and other devices not shown.

[0076] In the example shown, memory 124 can provide data, such as boot files, operating system images, and applications to classical processor 122. Classical processor 122 can include its own data, boot files, operating system images, and applications. Data processing environment 100 may include additional memory, quantum processors, and other devices not shown. Memory 124 includes application 105, which can be configured to implement one or more classical processor functions described herein for performing quantum signature core alignment on a hybrid classical-quantum computing system according to one or more embodiments.

[0077] In the example shown, memory 144 can provide data, such as boot files, operating system images, and applications to quantum processor 142. Quantum processor 142 can include its own data, boot files, operating system images, and applications. Data processing environment 100 may include additional memory, quantum processors, and other devices not shown. Memory 144 includes applications 146, which can be configured to implement one or more quantum processor functions described herein according to one or more embodiments.

[0078] In the example shown, data processing environment 100 can be the Internet. Network 102 can represent a collection of networks and gateways that use Transmission Control Protocol / Internet Protocol (TCP / IP) and other protocols to communicate with each other. The core of the Internet is the backbone of data communication links between master nodes or host computers, including thousands of commercial, government, educational and other computer systems that send data and messages. Of course, data processing environment 100 can also be implemented as many different types of networks, such as intranets, local area networks (LANs) or wide area networks (WANs). Figure 1 It is intended as an example and not as an architectural limitation to the different illustrative embodiments.

[0079] Among other uses, data processing environment 100 can be used to implement a client-server environment in which exemplary embodiments can be implemented. The client-server environment enables software applications and data to be distributed across a network so that the application works by using the interactivity between a traditional client data processing system and a traditional server data processing system. Data processing environment 100 can also adopt a service-oriented architecture in which interoperable software components distributed across a network can be packaged together as a consistent business application. Data processing environment 100 can also take the form of a cloud, and adopt a cloud computing model of service delivery to achieve convenient, on-demand network access to a shared pool of configurable computing resources (e.g., networks, network bandwidth, servers, processing, memory, storage, applications, virtual machines, and services), which can be quickly supplied and released with minimal management effort or interaction with a service provider.

[0080] refer to Figure 2 , which illustrates a block diagram of a data processing system in which the illustrative embodiments may be implemented. Data processing system 200 is an example of a conventional computer, such as Figure 1 The illustrative embodiments may be implemented using a conventional processing system 104, server 106, clients 110, 112, and 114, or another type of device in which computer usable program code or instructions implementing the processes may be located.

[0081] Data processing system 200 also represents a conventional data processing system or configuration thereof, such as Figure 1 A conventional data processing system 132 in which computer usable program code or instructions implementing the processes of the illustrative embodiments may be located. Data processing system 200 is described as a computer only as an example, but is not limited to such. Other device forms (e.g., Figure 1 An implementation of device 132 in FIG. 1 may modify data processing system 200 (eg, by adding a touch interface) or even remove certain illustrated components from data processing system 200.

[0082] In the illustrated example, data processing system 200 employs a hub architecture, including North Bridge and Memory Controller Hub (NB / MCH) 202 and South Bridge and Input / Output Controller Hub (SB / ICH) 204. Processing unit 206, main memory 208, and graphics processor 210 are coupled to North Bridge and Memory Controller Hub (NB / MCH) 202. Processing unit 206 may include one or more processors and may be implemented using one or more heterogeneous processor systems. Processing unit 206 may be a multi-core processor. In some implementations, graphics processor 210 may be coupled to NB / MCH 202 via an Accelerated Graphics Port (AGP).

[0083] In the example shown, a local area network (LAN) adapter 212 is coupled to the South Bridge and I / O controller hub (SB / ICH) 204. An audio adapter 216, a keyboard and mouse adapter 220, a modem 222, a Read Only Memory (ROM) 224, a Universal Serial Bus (USB) and other ports 232, and a PCI / PCIe device 234 are coupled to the South Bridge and I / O controller hub 204 via a bus 238. A hard disk drive (HDD) or solid-state drive (SSD) 226 and a CD-ROM 230 are coupled to the South Bridge and I / O controller hub 204 via a bus 240. PCI / PCIe devices 234 may include, for example, Ethernet adapters, add-in cards, and PC cards for notebook computers. PCI uses a card bus controller, while PCIe does not. ROM 224 may be, for example, a flash binary input / output system (BIOS). Hard disk drive 226 and CD-ROM 230 may use, for example, an Integrated Drive Electronics (IDE), Serial Advanced Technology Attachment (SATA) interface, or variations such as external-SATA (eSATA) and micro-SATA (mSATA). Super I / O (SIO) device 236 may be coupled to South Bridge and I / O Controller Hub (SB / ICH) 204 via bus 238.

[0084] Memories such as main memory 208, ROM 224, or flash memory (not shown) are some examples of computer usable storage devices. Hard disk drive or solid state drive 226, CD-ROM 230, and other similarly available devices are some examples of computer usable storage devices that include computer usable storage media.

[0085] An operating system runs on processing unit 206. The operating system coordinates and provides Figure 2 The operating system may be a commercially available operating system for any type of computing platform, including but not limited to server systems, personal computers, and mobile devices. Object-oriented or other types of programming systems may operate with the operating system and provide calls to the operating system from programs or applications executing on data processing system 200.

[0086] for operating systems, object-oriented programming systems, and applications or programs (such as Figure 1 The instructions for the application 105 in the example embodiment are located on a storage device (e.g., in the form of code 226A on hard drive 226) and may be loaded into at least one of the one or more memories (e.g., main memory 208) for execution by processing unit 206. The processes of the illustrative embodiments may be performed by processing unit 206 using computer-implemented instructions, which may be located in a memory (e.g., main memory 208, read-only memory 224) or in one or more peripheral devices.

[0087] In addition, in one case, code 226A can be downloaded from remote system 201B via network 201A, where similar code 201C is stored on storage device 201D. In another case, code 226A can be downloaded to remote system 201B via network 201A, where downloaded code 201C is stored on storage device 201D.

[0088] Figure 1-2 The hardware in the may vary depending on the implementation. Figure 1-2 In addition to or in place of the hardware shown Figure 1-2 In addition to the hardware shown in the figure, other internal hardware or peripheral devices (such as flash memory, equivalent non-volatile memory or optical disk drive, etc.) can be used. In addition, the process of the illustrative embodiment can be applied to a multi-processor data processing system.

[0089] In some illustrative examples, data processing system 200 may be a personal digital assistant (PDA), which is typically configured with flash memory to provide non-volatile memory for storing operating system files and / or user-generated data. The bus system may include one or more buses (e.g., a system bus, an I / O bus, and a PCI bus). Of course, the bus system may be implemented using any type of communication structure or architecture that provides data transfer between different components or devices attached to the structure or architecture.

[0090] The communication unit may include one or more devices for sending and receiving data, such as a modem or a network adapter. The memory may be, for example, main memory 208 or a cache (such as the cache found in the north bridge and memory controller hub 202). The processing unit may include one or more processors or CPUs.

[0091] Figure 1-2 The examples shown in and described above are not meant to imply architectural limitations. For example, data processing system 200 may be a tablet computer, laptop computer, or telephone device in addition to taking the form of a mobile device or wearable device.

[0092] Where a computer or data processing system is described as a virtual machine, virtual device, or virtual component, the virtual machine, virtual device, or virtual component operates in the manner of data processing system 200 using virtualized representations of some or all of the components shown in data processing system 200. For example, in the virtual machine, virtual device, or virtual component, processing unit 206 appears as a virtualized instance of all or some of the hardware processing units 206 available in the host data processing system, main memory 208 appears as a virtualized instance of all or a portion of main memory 208 available in the host data processing system, and disk 226 appears as a virtualized instance of all or a portion of disk 226 available in the host data processing system. In this case, the host data processing system is represented by data processing system 200.

[0093] refer to Figure 3 , which shows the use of Figure 1 The qubit 300 is a qubit used in the quantum processor 148 in FIG. 1 . The qubit 300 includes a capacitor structure 302 and a Josephson junction 304. The Josephson junction 304 is formed by separating two thin film superconducting metal layers by a non-superconducting material. When the metal in the superconducting layer becomes superconducting—for example, by lowering the temperature of the metal to a specific low temperature—the electron pairs can tunnel from one superconducting layer through the non-superconducting layer to the other superconducting layer. In the superconducting qubit 300, the Josephson junction 304 with a small inductance is electrically coupled in parallel with the capacitor structure 302 to form a nonlinear resonator.

[0094] refer to Figure 4 , which shows a simplified diagram 400 of a matrix representation of an example universal quantum circuit gate according to an illustrative embodiment. In the example shown, matrix representations and corresponding linear equations for a bit-flip NOT (X) gate, a phase-flip (Z) gate, a Hadamard (H) gate, a phase-shift (T) gate, a controlled NOT (controlled X or CNOT) gate, and a swap gate are shown.

[0095] refer to Figure 5 , which shows a block diagram of an example hybrid quantum / classical optimization algorithm for quantum feature kernel alignment using a classical processor 502 and a quantum processor 504. In this example, the classical processor 502 runs a classical optimization scheme to generate update parameters for the kernel alignment algorithm and sends these update parameters to the quantum processor 504. The quantum processor 504 prepares a set of quantum feature mapping circuits based on the specific combinatorial problem to be solved and the given update parameters. The quantum processor 504 executes the prepared quantum states and evaluates the set of quantum kernel families corresponding to the set of quantum feature mapping circuits. In an embodiment, the set of quantum kernels is from a single family of quantum kernels. The classical processor 502 receives these evaluations from the quantum processor 504 and evaluates the parameters of the set of quantum kernel families to determine whether to update the parameters for the classical optimization scheme.

[0096] If the classical processor 502 determines that the parameters of the quantum feature core alignment optimization problem are to be updated, the classical processor 502 runs the classical optimization scheme using the updated parameters to generate further updated parameters. The classical processor 502 then sends these further updated parameters to the quantum processor 504. Typically, this process is repeated until convergence within an acceptable threshold is obtained.

[0097] refer to Figure 6 , which shows a block diagram of an example quantum feature mapping circuit 600 using a core family of hybrid classical-quantum computing systems according to an illustrative embodiment. In this example, the quantum feature mapping circuit 600 applies a first layer of single-qubit single rotation gates followed by a first diagonal phase gate component. The diagonal phase gate component of the quantum feature mapping circuit 600 computes

[0098] The quantum signature mapping circuit 600 also applies a second layer of single-qubit single rotation gates, followed by a second diagonal phase gate component. The quantum signature mapping circuit also applies a third diagonal phase gate component, followed by a third layer of single-qubit single rotation gates. The quantum signature mapping circuit 600 also applies a fourth diagonal phase gate component, followed by a fourth layer of single-qubit single rotation gates. The quantum signature mapping circuit 600 also applies a measurement layer to the qubit set.

[0099] Thus, an equivalent circuit is obtained to encode both the actual function value of the phase and the Fourier transform value of each basic element. The quantum feature mapping implemented by the quantum feature mapping circuit 600 works to linearly classify the input data into the categories required by the SVM / QSVM because it applies a hyperplane to the "lifted" (e.g., feature-mapped) data. The rotation angle of each layer of single-qubit single rotation gate depends on the optimized kernel parameters.

[0100] refer to Figure 7 , which shows a block diagram of an example quantum signature mapping circuit 700 for another core family using a hybrid classical-quantum computing system according to an illustrative embodiment. In this example, the quantum signature mapping circuit 700 applies a first layer of single-qubit single rotation gates, followed by a first layer of controlled phase gates.

[0101] The quantum signature mapping circuit 700 also applies a second layer of single-qubit single rotation gates, followed by a second layer of controlled phase gates. The quantum signature mapping circuit also applies a third layer of single-qubit single rotation gates. The quantum signature mapping circuit 700 also applies a measurement layer to the qubit set.

[0102] Thus, an equivalent circuit is obtained to encode both the actual function value of the phase and the Fourier transform value of each basic element. The quantum feature mapping implemented by the quantum feature mapping circuit 700 works to linearly classify the input data into the categories required by the SVM / QSVM because it applies a hyperplane to the "lifted" (e.g., feature-mapped) data. The rotation angle of each layer of single-qubit single rotation gate depends on the optimized kernel parameters.

[0103] The quantum feature mapping circuit 700 includes a first portion 702 and a second portion 704. In an embodiment, the first portion 702 is repeated d times, where d is the depth of the quantum feature mapping circuit 700. In an embodiment, the second portion 704 is repeated d times, where d is the depth of the quantum feature mapping circuit 700.

[0104] refer to Figure 8 , which shows a block diagram of an example quantum signature mapping circuit 800 for another nuclear family using a hybrid classical-quantum computing system according to an illustrative embodiment. In this example, the quantum signature mapping circuit 800 applies a first layer of Hadamard gates followed by a first diagonal phase gate component.

[0105] Quantum feature mapping circuit 800 calculates coefficients φ of a classical neural network S. A classical neural network includes a weight set and a bias set. In an embodiment, the quantum kernel family of the quantum feature mapping circuit 800 includes a kernel parameter set optimized in a quantum feature kernel alignment process. In an embodiment, the weight set and the bias set are kernel parameter sets optimized in a quantum feature kernel alignment process. The diagonal phase gate component of the quantum feature mapping circuit 800 calculates

[0106] The quantum feature mapping circuit 800 also applies a second layer of Hadamard gates, followed by a second diagonal phase gate component. The quantum feature mapping circuit also applies a third diagonal phase gate component, followed by a third layer of Hadamard gates. The quantum feature mapping circuit 800 also applies a fourth diagonal phase gate component, followed by a fourth layer of Hadamard gates.

[0107] The quantum feature mapping circuit 800 also applies the measurement layer to the set of qubits. An equivalent circuit is thus obtained to encode both the actual function value of the phase and the Fourier transform value of each basic element. The quantum feature mapping implemented by the quantum feature mapping circuit 800 works to linearly classify the input data into the categories required by the SVM / QSVM because it applies the hyperplane to the "lifted"

[0108] The rotation angle of the single rotation gate of each single qubit layer depends on the optimized kernel parameters.

[0109] refer to Fig. 9 , which shows a block diagram of an example quantum feature mapping circuit 900 for another core family using a hybrid classical-quantum computing system according to an illustrative embodiment. In this example, the quantum feature mapping circuit 900 applies a first layer of single-qubit single rotation gates in a first direction, followed by a second layer of single-qubit single rotation gates in a second direction.

[0110] The quantum signature mapping circuit 900 also applies a first layer of controlled phase gates, followed by a second layer of controlled phase gates. The quantum signature mapping circuit 900 also applies a third layer of single-qubit single rotation gates in the second direction, followed by a fourth layer of single-qubit single rotation gates in the first direction. The quantum signature mapping circuit 900 also applies a measurement layer to the qubit set.

[0111] The quantum feature mapping circuit 900 includes a first portion 902 and a second portion 904. In an embodiment, the first portion 902 is repeated d times, where d is the depth of the quantum feature mapping circuit 900. In an embodiment, the second portion 904 is repeated d times, where d is the depth of the quantum feature mapping circuit 900.

[0112] Thus, an equivalent circuit is obtained to encode both the actual function value of the phase and the Fourier transform value of each basic element. The quantum feature mapping operation implemented by the quantum feature mapping circuit 900 will linearly classify the input data into the categories required by the SVM / QSVM because it applies a hyperplane to the "promoted" (e.g., feature-mapped) data. The rotation angle of each layer of single-qubit single rotation gate depends on the optimized kernel parameters.

[0113] refer to Fig.10 , which shows a block diagram of an example configuration 1000 for quantum signature core alignment using a hybrid classical-quantum computing system, according to an illustrative embodiment. The example embodiment includes a classical processing system 104 and a quantum processing system 140. The classical processing system 104 includes an application 1002. In a particular embodiment, the application 1002 is Figure 1 In an example of an application 105 of the present invention, the application 1002 is configured to receive data 1004. In one or more embodiments, the data 1004 includes one or more training data for training a classifier and input data for classification using the trained classifier. The application 1002 includes a sample selection component 1006, a kernel alignment component 1008, and a quantum parameter update component 1010. The quantum processing system 140 includes a quantum processor 142, a quantum mapping function calculation component 1012, a set of quantum kernel families 1014, and a quantum mapping kernel evaluation component 1016.

[0114] In this embodiment, the sample selection component 1006 is configured to select a sampling of objects from the training data and provide the sampled objects to the quantum processor 142 of the quantum processing system 140. The quantum mapping function calculation component 1012 is configured to apply a set of quantum feature maps corresponding to the set of quantum core families 1014 to the sampled objects configured as input vectors to generate an output vector. The quantum core evaluation component 1016 is configured to determine a quality metric of at least one quantum feature map in the set of quantum feature maps corresponding to the set of quantum core families 1014.

[0115] The kernel alignment component 1008 is configured to use the determined quality metrics and the parameters from the quantum feature mapping circuit to identify the best quality quantum feature mapping circuit corresponding to the data 1004. The quantum parameter update component 1010 is configured to calculate a new set of parameters for the quantum feature mapping circuit and determine whether the current function produces a hybrid classical and quantum classifier with acceptable accuracy. In an embodiment, these parameters are managed by a plurality of variable microwave pulses on the quantum processor 142. In a specific embodiment, the microwave pulses are parameterized by changing the amplitude of the microwave pulses. In a specific embodiment, the microwave pulses are parameterized by changing the phase of the microwave pulses.

[0116] refer to Fig.11 , which shows the simulation results of the training data of the hybrid quantum-classical system for quantum feature kernel alignment. Fig.11 is based on Figure 6 A quantum feature mapping circuit 400 is shown.

[0117] exist Fig.11 In Figure 1, these graphs show the computational cost and alignment of a 2-qubit quantum processor. The alignment graph compares the parameterized kernel used for the quantum feature mapping circuit with the kernel used to generate the training data. The alignment graph shows an alignment of the parameterized kernel close to 100%.

[0118] refer to Fig.12 , which shows a flow chart of an example process 1200 for quantum signature kernel alignment using a hybrid classical-quantum computing system, according to an illustrative embodiment. In block 1202, the classical processor 122 receives a training data set containing training objects associated with one or more classification categories. In a particular embodiment, the objects within the training data are represented by one or more vectors. In block 1204, the classical processor 122 selects a sampling of objects from the training data set. In a particular embodiment, the classical processor 122 selects objects from the training set using random sampling. In one or more particular embodiments, the objects are randomly selected using a classical distance measure.

[0119] In block 1206, the classical processor 122 parameterizes the quantum feature map circuit. In block 1208, the quantum processor 142 applies the quantum feature map set corresponding to the quantum kernel set to the input vector of the sample object to calculate the output vector. In an alternative embodiment, the classical processing system 104 uses simulation to apply the input vector to the quantum feature map to generate the output vector. In block 1210, the quantum processor 142 evaluates the quantum kernel set.

[0120] In box 1212, the classical processor 122 determines a new set of parameters for the quantum feature mapping circuit. In box 1214, the classical processor 122 re-parameterizes the quantum feature mapping circuit with the new set of parameters. In box 1216, the classical processor 122 determines whether the new (updated) quantum feature mapping circuit produces an acceptable level of accuracy, for example, an accurate measurement greater than a predetermined threshold. In an embodiment, the hybrid quantum / classical optimization algorithm 500 optimizes the value of the SVM objective function F. In an embodiment, the classical processor changes the parameter set of the quantum kernel to minimize the SVM objective function F relative to the quantum kernel parameter set. In an embodiment, the hybrid quantum / classical optimization algorithm 500 maximizes the SVM objective function relative to the alignment of the quantum kernel.

[0121] If the new parameter set does not produce a quantum feature map circuit with an acceptable level of accuracy, the process 1200 proceeds to box 1208. In box 1208, the quantum processor 142 determines a new quantum kernel that should be applied. Therefore, parts of the process 1200 are iteratively repeated until an acceptable level of accuracy is obtained. If the classical processor 122 determines in box 1216 that an acceptable level of accuracy is obtained by the updated parameters of the current quantum feature map, the process 1200 ends. Therefore, a trained hybrid classical-quantum classifier is generated. Upon receiving input data that is desired to be classified, the hybrid classical-quantum classifier classifies the received input data to determine the category of the input data.

[0122] Thus, in illustrative embodiments, a computer-implemented method, system or apparatus, and computer program product are provided for quantum space distance assessment for classifiers and other quantum decision systems trained using hybrid classical-quantum computing systems and other related features, functions, or operations. Where an embodiment or a portion of an embodiment is described with respect to a type of device, the computer-implemented method, system or apparatus, computer program product, or a portion thereof, is adapted or configured for use with an appropriate and comparable manifestation of that type of device.

[0123] Where embodiments are described as being implemented in an application, delivery of the application in a "Software as a Service" (SaaS) model is considered to be within the scope of the illustrative embodiments. In the SaaS model, the ability of the application to implement the embodiments is provided to the user by executing the application in a cloud infrastructure. The user can access the application using a variety of client devices through a thin client interface such as a web browser (e.g., web-based email) or other lightweight client applications. The user does not manage or control the underlying cloud infrastructure, including the network, servers, operating system, or storage of the cloud infrastructure. In some cases, the user may not even manage or control the capabilities of the SaaS application. In some other cases, the SaaS implementation of the application may allow limited possible exceptions to user-specific application configuration settings.

[0124] The present invention may be a system, method and / or computer program product at any possible level of technical detail integration. The computer program product may include a computer-readable storage medium having computer-readable program instructions thereon for causing a processor to execute aspects of the present invention.

[0125] A computer-readable storage medium may be a tangible device capable of retaining and storing instructions used by an instruction execution device. A computer-readable storage medium may be, but is not limited to, for example, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. A non-exhaustive list of more specific examples of computer-readable storage media includes the following: a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a static random access memory (SRAM), a portable compact disc read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanical encoding device (e.g., a protruding structure with instructions recorded in a punch card or groove), and any suitable combination of the foregoing. Computer-readable storage media, including but not limited to computer-readable storage devices as used herein, should not be construed as themselves transient signals, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides or other transmission media (e.g., light pulses through fiber optic cables), or electrical signals transmitted through wires.

[0126] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to a corresponding computing / processing device, or downloaded to an external computer or external storage device via a network (e.g., the Internet, a local area network, a wide area network, and / or a wireless network). The network can include copper transmission cables, optical transmission fibers, wireless transmissions, routers, firewalls, switches, gateway computers, and / or edge servers. The network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards the computer-readable program instructions to be stored in a computer-readable storage medium in the corresponding computing / processing device.

[0127] The computer-readable program instructions for performing the operations of the present invention may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state setting data, configuration data of an integrated circuit, or source code or object code written in any combination of one or more programming languages ​​(including object-oriented programming languages, such as Smalltalk, C++, etc.) and procedural programming languages ​​(such as "C" programming language or similar programming languages). The computer-readable program instructions may be fully executed on the user's computer, partially executed, executed as an independent software package, partially executed on the user's computer and partially executed on a remote computer, or executed entirely on a remote computer or server. In the latter case, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected (e.g., via the Internet using an Internet service provider) to an external computer. In some embodiments, in order to perform various aspects of the present invention, an electronic circuit (for example, including a programmable logic circuit, a Field-Programmable Gate Array (FPGA) or a Programmable Logic Array (PLA)) can execute computer-readable program instructions by utilizing state information of the computer-readable program instructions to personalize the electronic circuit.

[0128] Various aspects of the present invention are described herein with reference to the flowcharts and / or block diagrams of the methods, devices (systems) and computer program products according to embodiments of the present invention. It should be understood that each frame of the flowchart and / or block diagram and the combination of frames in the flowchart and / or block diagram can be implemented by computer-readable program instructions.

[0129] These computer-readable program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device to produce a machine, so that instructions executed by the processor of the computer or other programmable data processing device are used to create components for implementing the functions / actions specified in one or more boxes of the flowchart and / or block diagram. These computer-readable program instructions can also be stored in a computer-readable storage medium, which can guide the computer, programmable data processing device, and / or other equipment to operate in a specific manner, so that the computer-readable storage medium in which the instructions are stored includes an artifact, which includes instructions for implementing various aspects of the functions / actions specified in one or more boxes of the flowchart and / or block diagram.

[0130] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device, so that a series of operational steps are performed on the computer, other programmable apparatus, or other device to produce a computer-implemented process, so that the instructions executed on the computer, other programmable apparatus, or other device implement the functions / actions specified in one or more boxes of the flowchart and / or block diagram.

[0131] The flow charts and block diagrams in the accompanying drawings illustrate the architecture, functions and operations of possible implementations of the system, method and computer program product according to various embodiments of the present invention. In this regard, each frame in the flow chart or block diagram may represent a part of a module, segment or instruction, including one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the frame may not occur in the order marked in the figure. For example, two frames shown in succession can actually be executed substantially simultaneously, or these frames can sometimes be executed in reverse order, depending on the functions involved. It will also be noted that each frame illustrated in the block diagram and / or flow chart and the combination of frames in the block diagram and / or flow chart can be implemented by a dedicated hardware-based system that performs a specified function or action or performs a combination of dedicated hardware and computer instructions.

Claims

1. A method for training a hybrid classical-quantum decider, the method comprising: Receive a training dataset; Selecting, by a first processor, sample objects from the training data set, each object being represented by at least one vector; Preparing a plurality of different quantum feature mapping circuits corresponding to a plurality of different quantum core families, wherein each of the plurality of different quantum feature mapping circuits has a respective different arrangement of quantum gates; Identifying a quantum feature mapping circuit that satisfies a threshold level of accuracy from among the prepared plurality of different quantum feature mapping circuits by performing one or more iterations of an optimization algorithm, wherein each iteration comprises: Applying, by a quantum processor, a plurality of quantum feature maps to the selected sample object, the plurality of quantum maps corresponding to a plurality of different quantum nuclear families; evaluating, by a quantum processor, parameters of quantum logic gates of the plurality of different quantum feature mapping circuits, the plurality of different quantum feature mapping circuits respectively corresponding to at least one of the plurality of quantum feature mappings; Determining, by the first processor, a new parameter set for a quantum logic gate of a quantum feature mapping circuit in the plurality of quantum feature mapping circuits; determining, by the first processor, whether a quantum signature mapping circuit having a new set of parameters for quantum logic gates of the quantum signature mapping circuit meets the threshold level of accuracy; and The new set of parameters that satisfies the threshold level of accuracy is used by the first processor to parameterize quantum logic gates of the quantum signature mapping circuit.

2. The method according to claim 1, further comprising: The amplitude of the microwave pulses of the quantum processor is varied to parameterize the quantum signature mapping circuit.

3. The method according to claim 1, further comprising: The phase of the microwave pulses of the quantum processor is varied to parameterize the quantum signature mapping circuit.

4. The method according to claim 1, further comprising: It is determined that the new set of parameters produces an accurate measurement greater than a predetermined threshold.

5. The method according to claim 1, further comprising: The parameterized quantum eigenmapping circuit is applied to the selected sampling object to calculate a new output vector.

6. The method according to claim 1, wherein: The quantum feature mapping circuit includes a set of single quantum bit rotation gates.

7. The method according to claim 6, wherein: A subset of the set of single-qubit rotation gates includes a rotation angle.

8. The method according to claim 7, wherein: The rotation angle corresponds to the new set of parameters.

9. The method according to claim 1, wherein: The first processor is a classic processor.

10. The method according to claim 1, wherein: The parameter set corresponds to the weight set and bias set of the neural network.

11. The method according to claim 1, wherein: The quantum feature mapping circuit includes a set of controlled phase gates.

12. The method according to claim 11, wherein: The set of controlled phase gates includes phase gate angles.

13. The method according to claim 12, wherein: The phase gate angle corresponds to the parameter set.

14. A computer usable program product comprising one or more computer readable storage devices and program instructions stored on at least one of the one or more storage devices, the stored program instructions comprising: Program instructions for receiving a training data set; program instructions for selecting, by a first processor, sampled objects from the training data set, each object being represented by at least one vector; Program instructions for preparing a plurality of different quantum signature mapping circuits corresponding to a plurality of different quantum core families, wherein each quantum signature mapping circuit in the plurality of different quantum signature mapping circuits has a respective different arrangement of quantum gates; Program instructions for identifying a quantum feature mapping circuit that satisfies a threshold level of accuracy from a plurality of prepared different quantum feature mapping circuits by executing one or more iterations of an optimization algorithm, wherein the program instructions for executing each iteration include: program instructions for applying, by a quantum processor, a plurality of quantum feature maps to a selected sample object, the plurality of quantum maps corresponding to a plurality of different quantum nuclear families; Program instructions for evaluating, by a quantum processor, parameters of quantum logic gates of the plurality of different quantum signature mapping circuits, the plurality of different quantum signature mapping circuits corresponding to at least one of the plurality of quantum signature mappings, respectively; program instructions for determining, by the first processor, a new set of parameters for quantum logic gates of a quantum signature mapping circuit in the plurality of quantum signature mapping circuits; program instructions for determining, by the first processor, whether a quantum signature mapping circuit having a new set of parameters for quantum logic gates of the quantum signature mapping circuit meets the threshold level of accuracy; and Program instructions for parameterizing, by the first processor, quantum logic gates of the quantum signature mapping circuit using the new set of parameters that satisfy the threshold level of accuracy.

15. The computer usable program product of claim 14, further comprising: Program instructions for varying the amplitude of microwave pulses of the quantum processor to parameterize the quantum signature mapping circuit.

16. The computer usable program product of claim 14, further comprising: Program instructions for varying the phase of microwave pulses of the quantum processor to parameterize the quantum signature mapping circuit.

17. The computer usable program product of claim 14, further comprising: Program instructions for determining that the new set of parameters produces an accurate measurement greater than a predetermined threshold.

18. The computer usable program product of claim 14, wherein: The computer usable code is stored in a computer readable storage device in the data processing system and wherein the program instructions are transmitted from a remote data processing system over a network.

19. The computer usable program product of claim 14, wherein: The program instructions are stored in a computer readable storage device in a server data processing system and wherein the program instructions are downloaded over a network to a remote data processing system for use in a computer readable storage device associated with the remote data processing system.

20. A computer system comprising one or more processors, one or more computer-readable memories, one or more computer-readable storage devices, and program instructions for execution stored on at least one of the one or more storage devices, the program instructions being executed by at least one of the one or more processors via at least one of the one or more memories, the stored program instructions comprising: Program instructions for receiving a training data set; program instructions for selecting, by a first processor, sampled objects from the training data set, each object being represented by at least one vector; Program instructions for preparing a plurality of different quantum signature mapping circuits corresponding to a plurality of different quantum core families, wherein each quantum signature mapping circuit in the plurality of different quantum signature mapping circuits has a respective different arrangement of quantum gates; Program instructions for identifying a quantum feature mapping circuit that satisfies a threshold level of accuracy from a plurality of prepared different quantum feature mapping circuits by executing one or more iterations of an optimization algorithm, wherein the program instructions for executing each iteration include: program instructions for applying, by a quantum processor, a plurality of quantum feature maps to a selected sample object, the plurality of quantum maps corresponding to a plurality of different quantum nuclear families; Program instructions for evaluating, by a quantum processor, parameters of quantum logic gates of the plurality of different quantum signature mapping circuits, the plurality of different quantum signature mapping circuits corresponding to at least one of the plurality of quantum signature mappings, respectively; program instructions for determining, by the first processor, a new set of parameters for quantum logic gates of a quantum signature mapping circuit in the plurality of quantum signature mapping circuits; program instructions for determining, by the first processor, whether a quantum signature mapping circuit having a new set of parameters for quantum logic gates of the quantum signature mapping circuit meets the threshold level of accuracy; and Program instructions for parameterizing, by the first processor, quantum logic gates of the quantum signature mapping circuit using the new set of parameters that satisfy the threshold level of accuracy.

21. The system of claim 20, wherein: The stored program instructions include: Program instructions for varying the amplitude of microwave pulses of the quantum processor to parameterize the quantum signature mapping circuit.

22. The system of claim 20, wherein: The stored program instructions include: Program instructions for varying the phase of microwave pulses of the quantum processor to parameterize the quantum signature mapping circuit.

23. The system of claim 20, wherein: The stored program instructions include: Program instructions for determining that the new set of parameters produces an accurate measurement greater than a predetermined threshold.

24. The system of claim 20, wherein: The stored program instructions include: Program instructions for applying the parameterized quantum eigenmap circuit to the selected sample object to calculate a new output vector.

25. The system of claim 20, wherein: The quantum feature mapping circuit includes a set of single quantum bit rotation gates.

26. The system of claim 25, wherein: A subset of the set of single-qubit rotation gates includes a rotation angle.

27. The system of claim 26, wherein: The rotation angle corresponds to the new set of parameters.

28. The system of claim 20, wherein: The first processor is a classic processor.

29. The system of claim 20, wherein: The parameter set corresponds to the weight set and bias set of the neural network.

30. The system of claim 20, wherein: The quantum feature mapping circuit includes a set of controlled phase gates.

31. The system of claim 30, wherein: The set of controlled phase gates includes phase gate angles.

32. The system of claim 31, wherein: The phase gate angle corresponds to the parameter set.

33. A computer-readable storage medium comprising a computer program code, which, when executed on a computer, executes the method according to any one of claims 1 to 13.

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