Display and semiconductor memory device

Abstract

The application discloses a display and a semiconductor memory device. The display comprises a power generator, a static storage array and at least one switching device. The static storage array comprises a first sub-storage area and at least one second sub-storage area. The word line of the first sub-storage area continuously receives a working voltage from the power generator. Each switching device is arranged on a path between the power generator and each second sub-storage area. The word line of each second sub-storage area is connected with a switching device. Therefore, the application can reduce the power consumption of SRAM in the screen-off mode.

Description

Technical Field

[0001] This application relates to the field of static storage technology, specifically to a display and a semiconductor storage device. Background Technology

[0002] SRAM (Static Random-Access Memory) is an indispensable and crucial component of electronic systems. Used for temporary storage of data or instructions, SRAM offers advantages such as high speed, low power consumption, and ease of embedded integration, making it the preferred cache component in Central Processing Units (CPUs). In modern high-performance processors, SRAM occupies an increasingly larger portion of the chip area. In the coming years, with the explosive growth of mobile internet, the Internet of Things (IoT), and wearable electronic devices, chip power consumption will face stringent requirements and significant challenges, with SRAM bearing the brunt of these challenges.

[0003] Taking the chip in a display panel as an example, its built-in SRAM is used to store image data. When the display panel screen is updated, the SRAM performs a write operation; when a specific screen is displayed, the SRAM performs a read operation; when the power is turned off to prevent the screen from being displayed, the SRAM is also powered off and all data is lost in order to avoid power consumption caused by leakage current.

[0004] Currently, with the increasing popularity of always-on display functionality in mobile phones and other electronic devices, monitors need to have image display capabilities in always-on mode. In always-on mode, a portion of the monitor panel needs to display information such as time, date, battery status, and notifications. As a result, the SRAM is frequently activated, which not only generates dynamic current but also inevitably produces leakage current due to the inherent properties of SRAM transistors, thus increasing power consumption and affecting battery life.

[0005] The preceding description is intended to provide general background information and does not necessarily constitute prior art. Summary of the Invention

[0006] In view of this, this application provides a display and a semiconductor memory device to solve the problem of high SRAM power consumption in the display during screen-off mode.

[0007] The display provided in this application includes:

[0008] Power generator, which produces the operating voltage;

[0009] A static memory array includes a first sub-memory area and at least a second sub-memory area, wherein the word lines of the first sub-memory area continuously receive operating voltage from a power generator;

[0010] At least one switching device is provided, each switching device is disposed on the path between the power generator and each second sub-memory area, the word line of each second sub-memory area is connected to a switching device, the switching device controls the power generator and the second sub-memory area to be turned on, and when turned on, all static storage cells in the second sub-memory area receive the operating voltage.

[0011] Optionally, the display also includes a power controller connected to a power generator, with the first sub-storage area connected to the power generator via the power controller; each switching device is disposed between the power controller and each second sub-storage area.

[0012] Optionally, during the read / write phase of the static storage array, the power controller switches to a first power supply mode, and the power generator outputs a first operating voltage; during the non-read / write phase, the power controller switches to a second power supply mode, and the power generator outputs a second operating voltage, which is less than the first operating voltage but greater than the minimum voltage required for any sub-storage area to store data.

[0013] Optionally, the non-read / write phase includes the phase in which the display is in one of the following modes: screen-off mode, standby mode, or sleep mode.

[0014] Optionally, the switching device is a transistor, the control terminal of the transistor receives a control signal and turns on, the input terminal receives the operating voltage, and the output terminal is connected to the second sub-memory area.

[0015] Optionally, the control terminal of the switching device is connected to the power generator to receive control signals.

[0016] Optionally, each static memory cell of the static memory array is connected to two bit lines, and the display also includes a boost circuit, a first switch, and a second switch, with each switch connected between the boost circuit and each bit line, and the boost circuit being connected to the control terminal of the switching device.

[0017] Optionally, the boost circuit includes a third switch and a capacitor. The first electrode of the capacitor is connected to two bit lines through the first switch and the second switch, respectively. The third switch is connected between the first electrode of the capacitor and the control terminal of the switching device. The second electrode of the capacitor is grounded.

[0018] This application provides a semiconductor memory device, comprising:

[0019] A static memory array includes a first sub-memory area and at least a second sub-memory area, wherein the word lines of the first sub-memory area continuously receive operating voltage from a power generator;

[0020] At least one switching device is provided, each switching device is disposed on the path between the power generator and each second sub-memory area, the word line of each second sub-memory area is connected to a switching device, the switching device controls the power generator and the second sub-memory area to be turned on, and when turned on, all static storage cells in the second sub-memory area receive the operating voltage.

[0021] Optionally, each static memory cell of the static memory array is connected to two bit lines, and the display also includes a boost circuit, a first switch and a second switch, each switch being connected between the boost circuit and each bit line, and the boost circuit being connected to the control terminal of the switching device.

[0022] Based on the above, the display and semiconductor memory device of this application divide the static memory array into a first sub-memory area and at least one second sub-memory area. The first sub-memory area continuously receives the operating voltage, which is suitable for displaying information in a portion of the display panel area in the screen-off mode. A switching device is provided on the path of the operating voltage received by each second sub-memory area. In the screen-off mode, the switching device is turned off, and the second sub-memory area is powered off, avoiding power consumption in the second sub-memory area due to leakage current, thereby reducing the power consumption of the static memory array. Attached Figure Description

[0023] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the specification, serve to explain the principles of this application. To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the description of the embodiments are briefly introduced below. Obviously, those skilled in the art can obtain other drawings based on these drawings without any creative effort.

[0024] Figure 1 This is a schematic diagram of the storage circuit of a display according to an embodiment of this application;

[0025] Figure 2 This is a schematic diagram of the display interface of the present application in screen-off mode;

[0026] Figure 3 yes Figure 1 The diagram shows an equivalent storage circuit of a display.

[0027] Figure 4 yes Figure 1 The diagram shows an equivalent storage circuit of another display.

[0028] Figure 5 This is an equivalent schematic diagram of the connection between the boost circuit and the static memory cell in this application;

[0029] Figure 6 This is a schematic diagram of the storage circuit of a display according to another embodiment of this application;

[0030] Figure 7 yes Figure 6 The diagram shows an equivalent schematic of the display's storage circuit.

[0031] Figure 8 This is a timing diagram of the display receiving the operating voltage according to this application. Detailed Implementation

[0032] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions of this application are described clearly and completely below with reference to specific embodiments and corresponding drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. Based on the following description, the various embodiments and their technical features can be combined with each other unless otherwise specified.

[0033] Traditional SRAM consists of multiple static memory cells. Word lines control the activation of static memory cells, and bit lines connect stored information (such as image data) to the outside world. In always-on display mode, some areas of the display panel need to display various information such as time, date, battery status, and notifications. At this time, the word line receives the operating voltage and becomes high. All static memory cells connected to the word line will enter the read / write phase. Static memory cells whose bit lines are selected will perform normal read or write operations (hereinafter referred to as read / write operations). Static memory cells that are not selected will perform dummy read / write operations. Although dummy read / write operations do not read or write data, they will still receive the operating voltage and generate power consumption just like normal read / write operations.

[0034] In response to this, this application provides a static memory array and a display having the static memory array, which can reduce the power consumption of SRAM in screen-off mode.

[0035] Please see Figure 1 As shown, the display's storage circuit includes a power generator 11, a static storage array 12, and at least one switching device 13.

[0036] Power generator 11, also known as a memory power generator, is used to generate the voltage required by the static memory array 12 to store image data or other instructions, i.e., the operating voltage VDDM. Power generator 11 can be connected to the power supply of the display and convert the power obtained from the power supply into a voltage suitable for the static memory array 12.

[0037] The static memory array 12 can be an SRAM used to store image data or related instructions for the display during the image display process. The static memory array 12 includes a first sub-memory area 121 and at least one second sub-memory area 122. The first sub-memory area 121 is always connected to the power generator 11 and continuously receives operating voltage from the power generator 11.

[0038] The first sub-storage area 121 can store information that the display needs to show in screen-off mode, including but not limited to... Figure 2 The first sub-storage area 121, which displays various information such as time, date, battery status, and notifications, is always connected to the power generator 11 and is never powered off. Therefore, the stored information will not be lost and can be quickly retrieved and displayed on the monitor.

[0039] Optionally, the display interface of the monitor can be divided into a first panel area and a second panel area. The first panel area is used to display images in the non-read / write stage, and the first sub-storage area is used to store image data of the first panel area in the non-read / write stage and the read / write stage; the second sub-storage area is used to store image data of the second panel area in the non-read / write stage and the read / write stage.

[0040] In other words, there is a correspondence between each sub-storage area of ​​the static storage array 12 and the panel area of ​​the display. The first sub-storage area 121 corresponds to the panel area of ​​the information that needs to be displayed during non-read / write phases (e.g., screen-off mode). Figure 2 There is a correspondence between the panel areas shown by the dashed lines, and there is a correspondence between all the second sub-storage areas 122 and the remaining panel areas. When the display switches from, for example, always-on display mode to normal unlocked display mode, the first sub-storage area 121 is only used to read and write the image data of its corresponding panel area, while the image data of the remaining panel areas are read and written by the corresponding second sub-storage area 122.

[0041] A switching device 13 is provided between each second sub-storage area 122 and the power generator 11 to control the power generator 11 and the second sub-storage area 122, and to transmit the operating voltage generated by the power generator 11 to the second sub-storage area 122 when the power generator 11 is turned on.

[0042] The second sub-storage area 122 is used to store image data from other panel areas (i.e., areas of the display other than the panel areas that need to display information in screen-off mode). In screen-off mode, the switch device 13 is turned off, and the second sub-storage area 122 is de-energized, such as... Figure 3 As shown, when all word lines 12b in any second sub-memory area 122 do not receive operating voltage, all static memory cells 12a in the second sub-memory area 122 will not perform spoof read / write operations and will not generate power consumption, thus reducing the overall power consumption of the static memory array 12.

[0043] Given that there is less image data to be read and written in screen-off mode, the display can be set so that the capacity of the first sub-storage area 121 is less than the sum of the capacities of all the second sub-storage areas 122. For example, the capacity of the first sub-storage area 121 is 1 / 3 of the capacity of all the second sub-storage areas 122, that is, the capacity of the first sub-storage area 121 occupies 25% of the SRAM capacity.

[0044] It should be understood that the capacity ratio of the first sub-storage area 121 and all the second sub-storage areas 122 can be divided according to actual needs in the embodiments of this application, and there is no limitation here.

[0045] Please refer to the implementation details as well. Figure 1 and Figure 3 The static storage array 12 includes a plurality of static storage cells 12a arranged in an array. These static storage cells 12a can be divided into the aforementioned first sub-storage area 121 and a plurality of second sub-storage areas 122. It should be understood that the number of static storage cells 12a included in each sub-storage area is not limited in this application. For example, the first sub-storage area 121 and any second sub-storage area 122 may be provided with an equal number of static storage cells 12a; or, for example, each second sub-storage area 122 may be provided with the same or different numbers of static storage cells 12a. Figure 3 The images shown are merely illustrative examples.

[0046] In the first sub-memory area 121, the word lines 12b of all static memory cells 12a are connected to the power generator 11. In each second sub-memory area 122, the word lines 12b of all static memory cells 12a are connected to a corresponding switching device 13.

[0047] Optionally, the switching device 13 is a transistor, whose control terminal g receives the control signal EN and is turned on, its input terminal s is connected to the power generator 11 and is used to receive the operating voltage VDDM, and its output terminal d is connected to the word line 12b of the second sub-memory area 122.

[0048] In one application scenario, the switching device 13 can be a P-type MOS transistor, with its control terminal g, input terminal s, and output terminal d being the gate, source, and drain, respectively.

[0049] In one implementation, such as Figure 4As shown, the control terminal g of the switching device 13 can be connected to the power generator 11 and receive the control signal EN. At this time, the control signal EN is the operating voltage VDDM applied by the power generator 11 to the second sub-memory area 122. The power generator 11 outputs the operating voltage VDDM to each of the second sub-memory areas 122 through two different lines. Preferably, these two lines can output the operating voltage VDDM simultaneously, thereby reducing the requirements for output timing. The display does not need to set up a timing controller to implement this transmission.

[0050] In another implementation, since the control signal EN is essentially a high-level signal, the control terminal g of the switching device 13 can receive the control signal EN from the bit lines of the static memory array 12. Please refer to... Figure 5 As shown, the display also includes a boost circuit 20.

[0051] The boost circuit 20 is connected to the bit line of the static memory cell 12a. For example... Figure 5 As shown, each static memory cell 12a includes bit line 12c1 and bit line 12c2, which are connected to two inverters H1 and H2 in parallel through transistors M1 and M2, respectively.

[0052] The boost circuit 20 is connected to bit lines 12c1 and 12c2 respectively via a first switch SW1 and a second switch SW2, and is used to recover the charge discharged from the bit lines and apply it to the control terminal g of the switching device 13. The connection point of the boost circuit 20, the first switch SW1, and the second switch SW2 is node Q. Optionally, the boost circuit 20 includes a capacitor C1 and a third switch SW3. The first electrode of capacitor C1 is connected to node Q, and the second electrode is grounded. One end of the third switch SW3 is connected to node Q and the first electrode of capacitor C1, and the other end is connected to the control terminal g of the switching device 13.

[0053] During the read / write phase of static storage unit 12a, one of the first switch SW1 and the second switch SW2 is turned on, the third switch SW3 is turned off, and capacitor C1 is connected in parallel with one of the bit lines, storing the charge of the bit line in capacitor C1. Then, both the first switch SW1 and the second switch SW2 are turned off, the third switch SW3 is turned on, and capacitor C1 outputs a high-level signal, which can be used as a control signal EN and applied to the control terminal g of the switching device 13.

[0054] Based on the boost principle of the boost circuit 20, in one implementation, the boost circuit 20 can be connected to the power generator 11, or applied to each sub-memory area (for example, the boost circuit 20 of each sub-memory area is connected to the input terminal s of the switching device 13), thereby assisting the power generator 11 and helping to reduce the operating voltage generated by the power generator 11 and reduce power consumption.

[0055] When the display is in a non-read / write phase, all word lines 12b in the first sub-memory area 121 continuously receive the operating voltage VDDM generated by the power generator 11. All static memory cells 12a enter the read / write phase, and the selected static memory cell 12a performs normal read or write operations, including displaying information that needs to be displayed in the screen-off mode. However, at this time, the display does not input the control signal EN to the control terminal g of any switching device 13, all switching devices 13 are turned off, and all second sub-memory areas 122 are powered off. No fake read / write operation or normal read / write operation can be performed, and no power consumption is generated. Optionally, the non-read / write phase includes the phase where the display is in any of the screen-off mode, standby mode, or sleep mode.

[0056] It should be understood that not all static storage units 12a in the first sub-storage area 121 are used to store information in the non-read / write stage, such as not all of them are used to store image data in the screen-off mode. Instead, only a portion of the static storage units 12a may be used to perform this storage, and the remaining static storage units 12a may be used as redundant storage space to assist the second sub-storage area 122 in storing other information when the display switches to the read / write stage.

[0057] When the display is in the read / write phase, depending on the size of the data to be stored, the display selects a second sub-storage area 122 with an appropriate capacity and transmits a control signal EN to the control terminal g of the switching device 13 connected to the selected second sub-storage area 122. Only when these switching devices 13 are turned on, the selected second sub-storage area 122 receives the operating voltage VDDM and performs normal read / write operations, while the other second sub-storage areas 122 do not generate power consumption.

[0058] Compared to the traditional SRAM structure, in Figure 3 and Figure 4 In the described embodiment, the static memory array 12 changes the word line connection design of the static memory cells 12a in each sub-memory area, while the static memory array 12 has the same bit line connection design as conventional SRAM.

[0059] Figure 6 This is a schematic diagram of the storage circuit of a display according to another embodiment of this application. Figure 7 yes Figure 6 The diagram shows an equivalent schematic of the display's storage circuit. For ease of description, components with the same names are identified by the same reference numerals. Unlike the foregoing description of the embodiments, the display in this embodiment further includes a power controller 14.

[0060] The power controller 14 is connected to the power generator 11. The first sub-storage area 121 is connected to the power generator 11 through the power controller 14. Each switching device 13 is disposed between the power controller 14 and each second sub-storage area 122 to controllably turn on or off the conductive path between the power controller 14 and the second sub-storage area 122.

[0061] The power controller 14 is equivalent to a power supply mode controller, which is used to control the read and write operations of each sub-memory area under different voltage modes.

[0062] In one implementation, combined Figure 8 As shown below:

[0063] During the read / write phase of the static storage array 12, the power controller 14 switches to the first power supply mode, in which the power generator 11 outputs the first operating voltage.

[0064] During the non-read / write phase of the static storage array 12, the power controller 14 switches to a second power supply mode, in which the power generator 11 outputs a second operating voltage. The second operating voltage is lower than the first operating voltage but higher than the minimum voltage required for any sub-storage area to perform data storage. In other words, during the non-read / write phase, the operating voltage VDDM of the static storage array 12 is reduced to ensure that each sub-storage area can perform normal read / write operations.

[0065] For example, in screen-off mode, the second operating voltage is greater than or equal to the minimum voltage required for any static storage cell 12a in the first sub-storage area 121 to perform normal read / write operations. At this time, since all switching devices 13 are off, the second sub-storage area 122 will not perform read / write operations. Therefore, when setting the value of the second operating voltage, it is not necessary to consider the minimum voltage required for the static storage cell 12a in the second sub-storage area 122 to perform normal read / write operations.

[0066] In the always-on display mode, the ratio of the second operating voltage to the first operating voltage can be between 90% and 100%. In standby or sleep mode, the ratio of the second operating voltage to the first operating voltage can be between 70% and 100%.

[0067] The monitor has settings Figure 5In the scenario shown with boost circuit 20, the boost circuit 20 of each sub-memory area can be connected to the input terminal s of the switching device 13, whereby, during non-read / write phases, the second operating voltage generated by the power generator 11 can be further reduced. The sum of the third voltage output by the boost circuit 20 and the second operating voltage generated by the power generator 11 can be equal to the first operating voltage, or the ratio of the sum of the third voltage and the second operating voltage to the first operating voltage can be between 90% and 100% (or 70% and 100%).

[0068] like Figure 8 As shown in the figure below, traditional SRAM receives the same operating voltage VDDM during both the non-read / write and read / write phases. That is, the operating voltage VDDM of traditional SRAM remains constant and does not change regardless of whether data is being written. However, the embodiments of this application adaptively adjust the operating voltage VDDM of the static storage array 12 at different stages based on the display's current state, ensuring normal information display while reducing power consumption. For example, in scenarios where the display is used in mobile phones or wearable devices such as smartwatches, this helps extend battery life.

[0069] The above description is only a part of the embodiments of this application and does not limit the patent scope of this application. All equivalent structural transformations made using the content of this specification and drawings are similarly included in the patent protection scope of this application.

[0070] Without further restrictions, an element defined by the phrase "comprising a..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. Furthermore, components, features, and elements with the same name in different embodiments may have the same meaning or may have different meanings, the specific meaning of which needs to be determined by its interpretation in that specific embodiment or by further consideration of the context of that specific embodiment.

[0071] Furthermore, although this document uses terms such as "first," "second," and "third" to describe various types of information, this information should not be limited to these terms. These terms are only used to distinguish information of the same type from one another. The singular forms "a," "an," and "the" used herein are intended to also include the plural forms. The terms "or" and "and / or" are interpreted as inclusive, or meaning either one or any combination thereof. Exceptions to this definition only occur when combinations of elements, functions, steps, or operations are inherently mutually exclusive in some way.

Claims

1. A display, characterized in that, The display includes: Power generator, which produces the operating voltage; A static memory array includes a first sub-memory area and at least a second sub-memory area, wherein the word line of the first sub-memory area continuously receives operating voltage from the power generator; At least one switching device is provided, each switching device is disposed on the path between the power generator and each second sub-storage area, the word line of each second sub-storage area is connected to a switching device, the switching device controls the power generator and the second sub-storage area to be turned on, and when turned on, all static storage cells in the second sub-storage area receive the operating voltage; The switching device is a transistor. The control terminal of the transistor receives a control signal and is turned on. The input terminal of the transistor receives a working voltage. The output terminal of the transistor is connected to the second sub-memory area. Each static memory cell of the static memory array is connected to two bit lines. The display also includes a boost circuit, a first switch, and a second switch. The first switch and the second switch are respectively connected between the boost circuit and each bit line. The boost circuit is connected to the control terminal of the switching device.

2. The display according to claim 1, characterized in that, The display also includes a power controller connected to the power generator. The first sub-storage area is connected to the power generator via the power controller; Each switching device is located between the power controller and each second sub-storage area.

3. The display according to claim 2, characterized in that, During the read / write phase of the static storage array, the power controller switches to the first power supply mode, and the power generator outputs the first operating voltage. During the non-read / write phase of the static storage array, the power controller switches to a second power supply mode, and the power generator outputs a second operating voltage. The second operating voltage is less than the first operating voltage but greater than the minimum voltage required for any sub-storage area to store data.

4. The display according to claim 3, characterized in that, The non-read / write phase includes the phase in which the display is in one of the following modes: screen off mode, standby mode, or sleep mode.

5. The display according to claim 1, characterized in that, The control terminal of the switching device is connected to the power generator to receive the control signal.

6. The display according to claim 1, characterized in that, The boost circuit includes a third switch and a capacitor. The first electrode of the capacitor is connected to two bit lines through the first switch and the second switch, respectively. The third switch is connected between the first electrode of the capacitor and the control terminal of the switching device. The second electrode of the capacitor is grounded.

7. A semiconductor memory device, characterized in that, include: A static memory array includes a first sub-memory area and at least a second sub-memory area, wherein the word lines of the first sub-memory area continuously receive operating voltage from a power generator; At least one switching device is provided, each switching device is disposed on the path between the power generator and each second sub-storage area, the word line of each second sub-storage area is connected to a switching device, the switching device controls the power generator and the second sub-storage area to be turned on, and when turned on, all static storage cells in the second sub-storage area receive the operating voltage; Each static memory cell of the static memory array is connected to two bit lines. The semiconductor memory device also includes a boost circuit, a first switch, and a second switch. The first switch and the second switch are respectively connected between the boost circuit and each bit line. The boost circuit is connected to the control terminal of the switching device.

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