Semiconductor device and method for operating semiconductor device

Abstract

A semiconductor device and an operating method of the semiconductor device are described herein. A method of operating a semiconductor device includes: applying a first voltage to a first source selection line coupled to a first source selection transistor of a memory string included in an unselected memory block among memory blocks; floating the first source selection line after the first voltage is applied to the first source selection line; applying a second voltage to a second source selection line coupled to a second source selection transistor of a memory string included in the unselected memory block, the second voltage having a voltage level lower than the first voltage; applying a precharge voltage to a common source line; and applying a programming voltage to a word line coupled to a selected memory cell of a memory string included in a selected memory block among memory blocks.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Korean Patent Application No. 10-2020-0058488, filed on May 15, 2020, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Various embodiments of the present disclosure relate generally to electronic devices, and more particularly to semiconductor devices and methods of operating semiconductor devices. Background Art

[0004] The semiconductor device may include a memory device configured to store data and output the stored data. The memory device may be a volatile memory that loses its stored data in the absence of power. Examples of volatile memory devices may include static random access memory (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), etc. However, the memory device may also be a non-volatile memory device that retains its stored data even without power. Examples of non-volatile memory devices include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, phase change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), ferroelectric RAM (FRAM), etc.

[0005] The memory device may include a memory cell array storing data, peripheral circuits performing various operations such as programming, reading, and erasing operations, and control logic controlling the peripheral circuits. The memory device may include memory cells arranged two-dimensionally or three-dimensionally over a substrate. Summary of the invention

[0006] Various embodiments of the present disclosure are directed to semiconductor devices having improved operating characteristics.

[0007] According to one embodiment, a method for operating a semiconductor device includes memory blocks sharing a common source line, each memory block includes memory strings, and the memory strings each include a first source selection line, a second source selection line, and a memory cell. The method may include: applying a first voltage to a first source selection line coupled to a first source selection transistor of a memory string included in an unselected memory block among the memory blocks; after the first voltage is applied to the first source selection line, floating the first source selection line; applying a second voltage to a second source selection line coupled to a second source selection transistor of a memory string included in the unselected memory block, the second voltage having a voltage level lower than the first voltage; applying a precharge voltage to the common source line; and applying a programming voltage to a word line coupled to a selected memory cell of a memory string included in a selected memory block among the memory blocks.

[0008] According to one embodiment, a method of operating a semiconductor device includes memory blocks sharing a common source line, each memory block includes a memory string coupled between the common source line and a bit line, each memory string includes a first group of source selection transistors, a second group of source selection transistors, and a memory cell, wherein the first group is coupled between the common source line and the second group. The method may include: applying a positive voltage to a first source selection line coupled to a first group of memory strings included in an unselected memory block among the memory blocks; floating the first source selection line after the positive voltage is applied to the first source selection line; applying a voltage for turning off the second group to a second source selection line coupled to a second group of memory cell strings included in the unselected memory block; applying a precharge voltage to the common source line; and applying a programming voltage to a word line coupled to a selected memory cell of a memory string included in a selected memory block among the memory blocks.

[0009] These and other features and advantages of the present invention will be better understood by those skilled in the art from the following drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 is a simplified block diagram illustrating a configuration of a semiconductor device according to an embodiment of the present disclosure;

[0011] Figure 2 is a circuit diagram illustrating a cell array structure of a semiconductor device according to an embodiment of the present disclosure;

[0012] FIG. 3A to FIG. 3C is a diagram illustrating a configuration of a memory string according to an embodiment of the present disclosure;

[0013] FIG. 4A to FIG. 4C is a cross-sectional view of a structure of a semiconductor device according to an embodiment of the present disclosure;

[0014] FIG. 5A to FIG. 5D is a diagram illustrating a method of operating a semiconductor device according to an embodiment of the present disclosure;

[0015] Figure 6 is a diagram illustrating a method of operating a semiconductor device according to an embodiment of the present disclosure;

[0016] Figure 7 is a simplified block diagram illustrating a memory system according to an embodiment of the present disclosure;

[0017] Figure 8 is a simplified block diagram illustrating a memory system according to an embodiment of the present disclosure;

[0018] Fig. 9 is a simplified block diagram illustrating a memory system according to an embodiment of the present disclosure;

[0019] Fig.10 is a simplified block diagram illustrating a memory system according to an embodiment of the present disclosure; and

[0020] Fig.11 is a simplified block diagram illustrating a memory system according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0021] Hereinafter, the specific structural or functional description of various embodiments of the present disclosure is disclosed in this specification. However, the embodiments are not limited to the presented embodiments described in this specification.

[0022] Figure 1 is a simplified block diagram illustrating a configuration of a semiconductor device 100 according to an embodiment of the present disclosure.

[0023] refer to Figure 1 , the semiconductor device 100 may include a cell array 110 and a peripheral circuit 120. The peripheral circuit 120 may include an address decoder circuit 121, a read and write circuit 123, an input / output circuit 124, and a control logic circuit 125. The semiconductor device 100 may be a memory device. The semiconductor device 100 may be a volatile memory device. The semiconductor device 100 may be a non-volatile memory device. For example, in one embodiment, the semiconductor device 100 may be a flash memory device.

[0024] The cell array 110 may be coupled to the address decoder circuit 121 through the row lines RL, and coupled to the read and write circuit 123 through the column lines CL. The row lines RL may be word lines, and the column lines CL may be bit lines. However, the word lines and the bit lines may be determined relative to each other. In other words, the row lines may be bit lines, and the column lines may be word lines.

[0025] The cell array 110 may include one or more planes. Each plane may include multiple memory blocks. Each memory block may include a memory string. In addition, each memory block may include multiple pages.

[0026] The control logic circuit 125 may be coupled to the address decoder circuit 121, the read and write circuit 123, and the input / output circuit 124. The control logic circuit 125 may receive a command CMD and an address ADDR from the input / output circuit 124. The control logic circuit 125 may control the address decoder circuit 121 and the read and write circuit 123 to perform internal operations in response to the received command CMD.

[0027] The address decoder circuit 121 may be coupled to the cell array 110 through the row line RL. For example, the address decoder circuit 121 may be coupled to the cell array 110 through the word line, the dummy word line, the source selection line, and the drain selection line. In addition, the address decoder circuit 121 may be configured to control the row line RL in response to the control logic circuit 125. Therefore, the address decoder circuit 121 may receive the address ADDR from the control logic circuit 125, and select one memory block of the cell array 110 in response to the received address ADDR.

[0028] The programming operation and the reading operation of the semiconductor device 100 may be performed in units of pages. Therefore, during the programming operation and the reading operation, the address ADDR may include a block address and a row address. The address decoder circuit 121 may decode the block address included in the received address ADDR. The address decoder circuit 121 may generate a block selection signal in response to the decoded block address, and select a memory block according to the block selection signal.

[0029] The address decoder circuit 121 may decode a row address included in the received address ADDR and select a page of the selected memory block according to the decoded row address.

[0030] The erase operation of the semiconductor device 100 can be performed in units of memory blocks. Therefore, during the erase operation, the address ADDR may include a block address. The address decoder circuit 121 may decode the block address included in the received address ADDR. The address decoder circuit 121 may select a memory block according to the decoded block address.

[0031] The read and write circuit 123 may be coupled to the cell array 110 through the column lines CL. The read and write circuit 123 may include a page buffer. The page buffer may access the cell array 110 through the column lines CL.

[0032] During a programming operation, the read and write circuit 123 may transmit data DATA received from the input / output circuit 124 to the column line CL, and the memory cells of the selected page may be programmed in response to the transmitted data DATA. The data DATA may be multi-bit data to be programmed into each memory cell. During a read operation, the read and write circuit 123 may read data DATA from the memory cells of the selected page through the column line CL, and may output the read data DATA to the input / output circuit 124. During an erase operation, the read and write circuit 123 may float the column line CL. The programming operation and the erase operation may include a verification operation. The verification operation may be performed in a manner similar to the read operation.

[0033] Figure 2 is a circuit diagram illustrating a cell array structure of a semiconductor device according to an embodiment of the present disclosure.

[0034] refer to Figure 2 , the cell array may include a plurality of memory blocks BLK. The memory blocks BLK may be arranged in a first direction I, a second direction II intersecting the first direction I, or the first direction I and the second direction II. In addition, the memory blocks BLK may be stacked on each other in a third direction III. The memory blocks BLK may share a common source line CSL.

[0035] Each memory block BLK may include a plurality of memory strings MS11 to MS1m and MS21 to MS2m. Each of the memory strings MS11 to MS1m and MS21 to MS2m may extend in a third direction III. The memory cells MC may be stacked on each other in the third direction III, where "m" is an integer of 2 or more.

[0036] The memory block BLK may include memory strings MS11 to MS1m and MS21 to MS2m coupled between the bit lines BL1 to BLm and a common source line CSL. The memory strings MS11 to MS1m and MS21 to MS2m arranged in the second direction II may share the bit lines BL1 to BLm.

[0037] Each of the memory strings MS11 to MS1m and MS21 to MS2m may include at least one source select transistor SST, a plurality of memory cells MC, and at least one drain select transistor DST.

[0038] The source selection transistor SST included in one of the memory strings MS11 to MS1m and MS21 to MS2m may be coupled in series between the memory cell MC and the common source line CSL. The gate electrode of the source selection transistor SST may be coupled to the source selection line SSL. In addition, the source selection transistors SST at the same level may be coupled to the same source selection line SSL or different source selection lines SSL.

[0039] The memory cells MC included in one of the memory strings MS11 to MS1m and MS21 to MS2m may be coupled in series between the source selection transistor SST and the drain selection transistor DST. The gate electrodes of the memory cells MC may be coupled to the word lines WL, and the memory cells MC at the same level may be coupled to the same word line WL. The word line voltage (programming bias, pre-programming bias, and read bias) required for driving may be applied to each word line WL.

[0040] At least one drain selection transistor DST included in one of the memory strings MS11 to MS1m and MS21 to MS2m may be coupled in series between the bit lines BL1 to BLm and the memory cell MC. The gate electrode of the drain selection transistor DST may be coupled to the drain selection line DSL. Among the drain selection transistors DST of the memory strings MS11 to MS1m and MS21 to MS2m arranged in the same row (first direction I), the drain selection transistors DST at the same level may be coupled to the same drain selection line DSL. In addition, the drain selection transistors DST arranged in different rows (first direction I) may be coupled to different drain selection lines DSL.

[0041] Although not in Figure 2 , but each of the memory strings MS11 to MS1m and MS21 to MS2m may include a pipeline transistor. For example, each of the memory strings MS11 to MS1m and MS21 to MS2m may include a plurality of source selection transistors SST coupled in series with each other, a plurality of memory cells MC, at least one pipeline transistor PT, a plurality of memory cells MC, and at least one drain selection transistor DST. In this example, each of the memory strings MS11 to MS1m and MS21 to MS2m may be arranged in a U shape.

[0042] FIG. 3A to FIG. 3C is a diagram illustrating a configuration of a memory string MS according to an embodiment of the present disclosure. For the sake of brevity, descriptions of common contents discussed above are omitted.

[0043] refer to Figure 3A, the memory string MS may include a first source selection transistor SST1 and a second source selection transistor SST2. The first source selection transistor SST1 may be closer to the common source line CSL than the second source selection transistor SST2. More specifically, the first source selection transistor SST1 may be positioned relatively close to the common source line CSL, and the second source selection transistor SST2 may be positioned relatively close to the bit line BL.

[0044] The first source select line SSL1 may be coupled to the first source select transistor SST1. The second source select line SSL2 may be coupled to the second source select transistor SST2. The first source select line SSL1 and the second source select line SSL2 may be electrically isolated from each other and driven independently of each other.

[0045] The memory string MS may further include a third source selection transistor SST3. The third source selection transistor SST3 may be coupled between the first source selection transistor SST1 and the second source selection transistor SST2. A third source selection line SSL3 may be coupled to the third source selection transistor SST3. The third source selection line SSL3 may be electrically isolated from the first source selection line SSL1 and the second source selection line SSL2 and driven independently.

[0046] As described in conjunction with the present embodiment, the memory string MS may include three source selection transistors, i.e., first to third source selection transistors SST1 to SST3. However, the embodiment is not limited thereto. The number of source selection transistors included in the memory string MS may vary. For example, two or more source selection transistors may be included in the memory string MS.

[0047] refer to Figure 3B , the memory string MS may include one or more first source selection transistors SST1 and one or more second source selection transistors SST2. The first source selection transistors SST1 and the second source selection transistors SST2 included in the memory string MS may be divided into a plurality of groups. More specifically, the memory string MS may include a first group GR1 and a second group GR2, the first group GR1 including the first source selection transistor SST1, and the second group GR2 including the second source selection transistor SST2. The number of the first source selection transistors SST1 included in the first group GR1 and the number of the second source selection transistors SST2 included in the second group GR2 may be the same or different.

[0048] The first group GR1 may be closer to the common source line CSL than the second group GR2. The first group GR1 may be coupled between the common source line CSL and the second group GR2.

[0049] The first group GR1 may be coupled to at least one first source select line SSL1, and the second group GR2 may be coupled to at least one second source select line SSL2. The at least one first source select line SSL1 and the at least one second source select line SSL2 may be electrically isolated from each other and driven independently of each other.

[0050] refer to Figure 3C , the memory string MS may further include a third group GR3. The third group GR3 may be coupled between the first group GR1 and the second group GR2. The third group GR3 may include at least one third source selection transistor SST3. The number of first source selection transistors SST1 included in the first group GR1, the number of second source selection transistors SST2 included in the second group GR2, and the number of third source selection transistors SST3 included in the third group GR3 may be the same or different from each other.

[0051] The third group GR3 may be coupled to at least one third source select line SSL3. The at least one third source select line SSL3 may be electrically isolated from the first and second source select lines SSL1 and SSL2 and independently driven.

[0052] As described in conjunction with this embodiment, the memory string MS may include three groups, namely, the first group GR1 to the third group GR3. However, the embodiment is not limited thereto. The number of groups included in the memory string MS may vary. For example, two or more groups may be included in the memory string MS.

[0053] FIG. 4A to FIG. 4C is a cross-sectional view of the structure of a semiconductor device according to an embodiment of the present disclosure. Figure 4A and Figure 4B Conductive lines such as a common source line and a source selection line are mainly illustrated. Figure 4C The diagram mainly shows the conductive lines and the channel structure. However, other components are not shown. FIG. 4A to FIG. 4C is shown in the figure.

[0054] refer to Figure 4A , the semiconductor device may include a common source line 40 , a first memory block MB1 , and a second memory block MB2 .

[0055] The first memory block MB1 may include a first source selection line 41 and a second source selection line 42. The first source selection line 41 may belong to the first group GR1, and the second source selection line 42 may belong to the second group GR2. The second source selection line 42 may be located above the first source selection line 41. The first source selection line 41 may be located between the second source selection line 42 and the common source line 40.

[0056] The second memory block MB2 may include a first source selection line 31 and a second source selection line 32. The first source selection line 31 may belong to the first group GR1, and the second source selection line 32 may belong to the second group GR2. The second source selection line 32 may be located above the first source selection line 31. The first source selection line 31 may be located between the second source selection line 32 and the common source line 40.

[0057] The first source select line 41 of the first memory block MB1 may be electrically isolated from the first source select line 31 of the second memory block MB2 and driven independently. The second source select line 42 of the first memory block MB1 may be electrically isolated from the second source select line 32 of the second memory block MB2 and driven independently.

[0058] refer to Figure 4B , the first memory block MB1 may further include at least one third source selection line 43. The second memory block MB2 may further include at least one third source selection line 33. The third source selection line 43 of the first memory block MB1 may be electrically isolated from the third source selection line 33 of the second memory block MB2 and driven independently.

[0059] Despite Figure 4A and Figure 4B Although not shown in the figure, the first memory block MB1 and the second memory block MB2 may further include word lines, drain selection lines, channel structures, etc. Figure 4C , the semiconductor device may include a common source line CSL, a source selection line SSL, a word line WL, a drain selection line DSL, and a channel structure CH. The source selection line SSL, the word line WL, the drain selection line DSL, and the channel structure CH may be sequentially stacked on the common source line CSL. As described above, the source selection line SSL may include the first source selection line 31 to the third source selection line 33 or the first source selection line 41 to the third source selection line 43.

[0060] The channel structure CH may pass through the source selection line SSL, the word line WL, and the drain selection line DSL in the stacking direction. The channel structure CH may include a channel layer 22, and may further include a memory layer 21 and a core insulation layer 23. The memory layer 21 may be formed to surround the sidewall of the channel layer 22. The memory layer 21 may include at least one of a tunnel insulation layer, a data storage layer, and a barrier layer. The data storage layer may include a floating gate, a charge trapping material, polysilicon, a nitride, a variable resistance material, a phase change material, a nanostructure, etc. The channel layer 22 may refer to a layer forming a channel region of a selection transistor, a memory cell, etc., and may include a semiconductor material, a nanostructure, etc. The channel layer 22 may extend into the common source line CSL.

[0061] According to the above structure of the semiconductor device, the source selection transistor can be located at the intersection between the channel structure CH and the source selection line SSL, the memory cell can be located at the intersection between the channel structure CH and the word line WL, and the drain selection transistor can be located at the intersection between the channel structure CH and the drain selection line DSL.

[0062] The source select line SSL may be positioned adjacent to the common source line CSL. In addition, an insulating layer (not shown) may be interposed between the lowermost source select line SSL and the common source line CSL. Therefore, capacitance may be induced between the lowermost source select line SSL and the common source line CSL.

[0063] FIG. 5A to FIG. 5D is a diagram illustrating a method of operating a semiconductor device according to an embodiment of the present disclosure. FIG. 5A to FIG. 5D Each shows a precharge operation of an unselected memory block among a plurality of memory blocks. The channel region of the memory string in the selected memory block can be precharged with an electric charge through the precharge operation. The precharge operation can be part of the programming operation. The precharge operation can be performed before applying the programming voltage. The following will describe the above reference Figures 2 to 4C Describes the operation of memory blocks and memory strings.

[0064] refer to Figure 5A , in section A, a first voltage V1 may be applied to a first source selection line SSL1 coupled to a first source selection transistor of a memory string included in an unselected memory block. The first voltage V1 may be applied to at least one first source selection line SSL1 coupled to the first group GR1. A second voltage V2 may be applied to a second source selection line SSL2 coupled to a second source selection transistor of the memory string. The second voltage V2 may be applied to a second source selection line SSL2 coupled to the second group GR2. The common source line CSL may be in an initial state and have a ground level.

[0065] The second voltage V2 may have a voltage level lower than the first voltage V1. According to an embodiment, the first voltage V1 may be a positive voltage, and the second voltage V2 may be a ground voltage Vss. In segment A, the second source select transistor may be turned off. Therefore, the memory string may be electrically insulated from the common source line CSL. The first source select transistor may be turned on or off according to the voltage level of the first voltage V1. Even when the first source select transistor is turned on, the memory string may be separated from the common source line CSL because the second source select transistor is turned off.

[0066] In section B, a precharge voltage Vpre may be applied to the common source line CSL. When the first voltage V1 is applied to the first source selection line SSL1 and the second voltage V2 is applied to the second source selection line SSL2, the voltage level of the common source line CSL may increase to a precharge level. The voltage level of the first voltage V1 may be equal to or lower than that of the precharge voltage Vpre.

[0067] The first source selection line SSL1 may be located between the second source selection line SSL2 and the common source line CSL. Therefore, when the voltage level of the common source line CSL increases, the common source line CSL may be affected by the capacitance between the first source selection line SSL1 and the common source line CSL. When the first source selection line SSL1 has a ground level, if the precharge voltage Vpre is applied to the common source line CSL, the voltage level of the common source line CSL may increase slowly due to the capacitance. On the other hand, according to an embodiment, when the first voltage V1 is applied to the first source selection line SSL1, the precharge voltage Vpre may be applied to the common source line CSL. Therefore, the voltage level of the common source line CSL may be quickly increased by the capacitance between the first source selection line SSL1 and the common source line CSL. As a result, the loading time of the common source line CSL may be reduced.

[0068] In section C, the first source select line SSL1 may be floated. When the voltage level of the common source line CSL reaches the precharge level and the channel region of the memory string of the selected memory block is precharged, the first source select line SSL1 may be floated. By floating the first source select line SSL1, power consumption of the semiconductor device may be reduced. The voltage levels of the second source select line SSL2 and the common source line CSL may be maintained.

[0069] According to the above operation, the common source line CSL can be prevented from being slowly charged by the unselected memory block during the precharge operation. Therefore, the charging time of the common source line CSL can be reduced, and the programming time can be reduced.

[0070] Figure 5B Similar to Figure 5A And an embodiment in which the second voltage V2 applied to the second source selection line SSL2 has a positive level is shown. The second voltage V2 may have a voltage level lower than the threshold voltage of the second source selection transistor. According to one embodiment, the first voltage V1 may be a first positive voltage, and the second voltage V2 may be a second positive voltage having a voltage level lower than the first voltage V1.

[0071] Even when the second positive voltage is applied to the second source selection line SSL2, the second source selection transistor may be turned off. Therefore, regardless of the on / off state of the first source selection transistor, the memory string may be electrically isolated from the common source line CSL.

[0072] Figure 5C Similar to Figure 5A or Figure 5B And a modified embodiment is illustrated in which the voltage levels of the first source selection line SSL1 and the second source selection line SSL2 are in accordance with Figure 5A or Figure 5B Different times increase. In segment B, a first voltage V1 may be applied to the first source selection line SSL1, a second voltage V2 may be applied to the second source selection line SSL2, and a precharge voltage Vpre may be applied to the common source line CSL. The second voltage V2 may have a voltage level lower than the first voltage V1. According to one embodiment, the second voltage V2 may be a ground voltage Vss or a positive voltage.

[0073] The first voltage V1 or the second voltage V2 may be applied simultaneously with the precharge voltage Vpre. Alternatively, both the first voltage V1 and the second voltage V2 may be applied simultaneously with the precharge voltage Vpre. As a result, the voltage level of the first source selection line SSL1 or the voltage level of the second source selection line SSL2 may increase simultaneously with the voltage level of the third source selection line SSL3.

[0074] Figure 5D Similar to Figure 5A , Figure 5B or Figure 5C And an embodiment in which the memory string includes a third source select transistor coupled between the first source select transistor and the second source select transistor is shown. In sections A, B, and C, the third source select line SSL3 coupled to the third source select transistor of the memory string included in the unselected memory block may be floated.

[0075] When the first voltage V1 is applied to the first source selection line SSL1, the second voltage V2 is applied to the second source selection line SSL2, and the third source selection line SSL3 is floated, the voltage level of the common source line CSL may be increased to a precharge level. When there is a large difference in the voltage level between the first source selection line SSL1 and the second source selection line SSL2, the semiconductor device may not operate normally, or carriers may move. Therefore, according to an embodiment of the present disclosure, the third source selection line SSL3 between the first source selection line SSL1 and the second source selection line SSL2 may be floated. Since the floated third source selection line SSL3 is used as a buffer therebetween, erroneous operation or unintentional carrier movement may be reduced or avoided.

[0076] Figure 6 is a diagram illustrating a method of operating a semiconductor device. Figure 6 , a programming operation of a selected memory block among a plurality of memory blocks is shown in FIG. The source selection line SSL may correspond to the source selection line SSL as described above with reference to FIG. Figures 1 to 4C The first source selection line SSL1, the second source selection line SSL2 or the third source selection line SSL3 is described.

[0077] At the first time T1, the precharge voltage Vpre may be applied to the common source line CSL.

[0078] At the second time T2, the power supply voltage V DD A power supply voltage V may be applied to a source selection line SSL of a selected memory block among a plurality of memory blocks, and a source selection transistor may be turned on. DD Can be applied to the unselected word line unsel_WL and the selected word line sel_WL, and the memory cell can be turned on. The ground voltage Vss can be applied to the drain selection lines (sel_DSL and unsel_DSL), and the drain selection transistor can be turned off. As a result, the memory string can be electrically coupled to the common source line CSL and separated from the bit line BL. In addition, the channel area of ​​the memory string can be precharged through the common source line CSL.

[0079] At the third time T3, the source selection line SSL, the unselected word line unsel_WL, and the selected word line sel_WL may be discharged. The voltage level of the source selection line SSL may drop to a ground level, and the source selection transistor SST may be turned off. The memory string may be separated from the common source line CSL.

[0080] At the fourth time T4, the power supply voltage V DD may be applied to the selected drain selection line sel_DSL, and the drain selection transistor may be turned on. As a result, the selected memory string may be electrically coupled to the bit line BL.

[0081] At the fifth time T5, the programming voltage Vpgm may be applied to the selected word line sel_WL. After the voltage of the selected word line sel_WL reaches the pass voltage Vpass, the voltage of the selected word line sel_WL may be increased to the programming voltage Vpgm. The pass voltage Vpass may be applied to the unselected word lines WL. As a result, the selected memory cells of the selected memory string may be programmed. In addition, the channel regions of the memory strings where programming is prohibited may be boosted, and programming of these memory strings may be prohibited.

[0082] At a sixth time T6 , the selected word line sel_WL, the unselected word line unsel_WL, and the selected drain select line sel_DSL may be discharged.

[0083] According to the above method, a programming operation including a precharge period and a programming period may be performed. The period between the first time T1 and the third time T3 may be a precharge period, and the period between the fourth time T4 and the sixth time T6 may be a programming period. The period between the first time T1 and the third time T3 may correspond to the period described above with reference to FIG. 5A to FIG. 5C The common source line CSL can be quickly charged by applying the first voltage V1 to the first source selection line SSL1 of the unselected memory block in the precharge period. Therefore, the channel area of ​​the memory string of the selected memory block can be quickly precharged, and the programming speed can be improved.

[0084] Figure 7 is a diagram illustrating a memory system 1000 according to an embodiment of the present disclosure.

[0085] refer to Figure 7 , the memory system 1000 may include a memory device 1200 configured to store data and a memory controller 1100 performing communication between the memory device 1200 and a host 2000 .

[0086] The host 2000 may be a device or system configured to store data in the memory system 1000 or retrieve data from the memory system 1000. The host 2000 may generate requests for various operations and output the generated requests to the memory system 1000. The request may, for example, include a program request for a program operation, a read request for a read operation, and an erase request for an erase operation. The host 2000 may communicate with the memory system 1000 by using at least one interface protocol of a peripheral component interconnect express (PCI-E), an advanced technology attachment (ATA), a serial ATA (SATA), a parallel ATA (PATA), a serial attached SCSI (SAS), a non-volatile memory express (NVMe), a universal serial bus (USB), a multimedia card (MMC), an enhanced small disk interface (ESDI), and an integrated drive electronics device (IDE).

[0087] The host 2000 may include at least one of a computer, a portable digital device, a tablet computer, a digital camera, a digital audio player, a television, a wireless communication device, or a cellular phone. However, embodiments of the disclosed technology are not limited thereto.

[0088] The memory controller 1100 may control the overall operation of the memory system 1000. The memory controller 1100 may control the memory device 1200 in response to a request of the host 2000. The memory controller 1100 may control the memory device 1200 to perform a program operation, a read operation, and an erase operation at the request of the host 2000. Alternatively, in the absence of a request from the host 2000, the memory controller 1100 may perform a background operation for improving the performance of the memory system 1000.

[0089] In order to control the operation of the memory device 1200, the memory controller 1100 may transmit a control signal and a data signal to the memory device 1200. The control signal and the data signal may be transmitted to the memory device 1200 through different input / output lines. The data signal may include a command, an address, or data. The control signal may be used to distinguish a period of an input data signal.

[0090] The memory device 1200 may perform a program operation, a read operation, and an erase operation in response to the control of the memory controller 1100. The memory device 1200 may be a volatile memory that loses data when power is cut off, or a non-volatile memory that may retain data without power. According to one embodiment, the memory device 1200 may be the semiconductor device 100 described above, and the semiconductor device 100 may be a flash memory device.

[0091] Under a request for a program, read, or erase operation from the host 2000, the memory controller 1100 may command the memory device 1200 to perform the operations described above. Figures 1 to 6 The method described herein performs a programming, reading or erasing operation. According to the method, the block size can be reduced and the cell performance characteristics can be ensured.

[0092] Figure 8 is a diagram illustrating a memory system 30000 according to an embodiment of the present disclosure.

[0093] refer to Figure 8 The memory system 30000 may be embodied as a cellular phone, a smart phone, a tablet computer, a personal computer (PC), a personal digital assistant (PDA), or a wireless communication device. The memory system 30000 may include a memory device 2200 and a memory controller 2100 that controls the operation of the memory device 2200.

[0094] The memory controller 2100 may control a data access operation of the memory device 2200 , for example, a program operation, an erase operation, or a read operation of the memory device 2200 , in response to the control of the processor 3100 .

[0095] Data programmed into the memory device 2200 may be output through the display 3200 in response to the control of the memory controller 2100 .

[0096] The radio transceiver 3300 can exchange radio signals through the antenna ANT. For example, the radio transceiver 3300 can change the radio signal received through the antenna ANT into a signal that can be processed by the processor 3100. Therefore, the processor 3100 can process the signal output from the radio transceiver 3300 and transmit the processed signal to the memory controller 2100 or the display 3200. The memory controller 2100 can transmit the signal processed by the processor 3100 to the memory device 2200. In addition, the radio transceiver 3300 can change the signal output from the processor 3100 into a radio signal and output the radio signal to an external device through the antenna ANT. The control signal for controlling the operation of the host or the data to be processed by the processor 3100 can be input through the input device 3400, and the input device 3400 can include an indicating device, such as a touch pad and a computer mouse, a keypad or a keyboard. The processor 3100 may control the operation of the display 3200 so that data output from the memory controller 2100 , data output from the radio transceiver 3300 , or data output from the input device 3400 may be output through the display 3200 .

[0097] According to one embodiment, the memory controller 2100 capable of controlling the operation of the memory device 2200 may be implemented as a part of the processor 3100 , or implemented as a chip separate from the processor 3100 .

[0098] Fig. 9 is a diagram illustrating a memory system 40000 according to an embodiment of the present disclosure.

[0099] refer to Fig. 9 , the memory system 40000 may be embodied as a personal computer (PC), a tablet computer, a netbook, an e-reader, a personal digital assistant (PDA), a portable multimedia player (PMP), an MP3 player, or an MP4 player.

[0100] The memory system 40000 may include a memory device 2200 and a memory controller 2100 that controls a data processing operation of the memory device 2200 .

[0101] The processor 4100 may output data stored in the memory device 2200 through the display 4300 according to data input through the input device 4200. Examples of the input device 4200 may include a pointing device such as a touch pad, a computer mouse, a keypad, or a keyboard.

[0102] The processor 4100 may control the overall operation of the memory system 40000 and control the operation of the memory controller 2100. According to one embodiment, the memory controller 2100 capable of controlling the operation of the memory device 2200 may be implemented as a part of the processor 4100 or as a chip separate from the processor 4100.

[0103] Fig.10 is a diagram illustrating a memory system 50000 according to an embodiment of the present disclosure.

[0104] refer to Fig.10 , the memory system 50000 may be embodied as an image processor, for example, a digital camera, a cellular phone with a digital camera attached, a smart phone with a digital camera attached, or a desktop PC with a digital camera attached.

[0105] The memory system 50000 may include a memory device 2200 and a memory controller 2100 that controls a data processing operation of the memory device 2200 , for example, a program operation, an erase operation, or a read operation.

[0106] The image sensor 5200 of the memory system 50000 may convert an optical image into a digital signal. The converted digital signal may be transmitted to the processor 5100 or the memory controller 2100. In response to the control of the processor 5100, the converted digital signal may be output through the display 5300 or stored in the memory device 2200 through the memory controller 2100. In addition, according to the control of the processor 5100 or the controller 2100, the data stored in the memory device 2200 may be output through the display 5300.

[0107] According to one embodiment, the memory controller 2100 capable of controlling the operation of the memory device 2200 may be formed as a part of the processor 5100 , or formed as a chip separate from the processor 5100 .

[0108] Fig.11 is a diagram illustrating a memory system 70000 according to an embodiment of the present disclosure.

[0109] refer to Fig.11 , the memory system 70000 may include a memory card or a smart card. The memory system 70000 may include a memory device 2200 , a memory controller 2100 , and a card interface 7100 .

[0110] The memory controller 2100 may control data exchange between the memory device 2200 and the card interface 7100. According to one embodiment, the card interface 7100 may be, but is not limited to, a secure digital (SD) card interface or a multimedia card (MMC) interface.

[0111] The card interface 7100 may interface data exchange between the host 60000 and the memory controller 2100 according to the protocol of the host 60000. According to one embodiment, the card interface 7100 may support a universal serial bus (USB) protocol and an inter-chip (IC) USB protocol. The card interface 7100 may refer to hardware capable of supporting the protocol used by the host 60000, software installed in the hardware, or a signal transmission method.

[0112] When the memory system 70000 is connected to the host interface 6200 of the host 60000 (such as a PC, a tablet computer, a digital camera, a digital audio player, a cellular phone, a console video game hardware, or a digital set-top box), the host interface 6200 can perform data communication with the memory device 2200 through the card interface 7100 and the memory controller 2100 in response to the control of the microprocessor 6100.

[0113] According to the embodiments of the present disclosure, a semiconductor device having improved operation characteristics and reliability can be provided.

[0114] In the above-described embodiments, all steps may be selectively executed or skipped. In addition, the steps in each embodiment may not always be executed in a regular order. In addition, the embodiments disclosed in this specification and the accompanying drawings are intended to help those of ordinary skill in the art to more clearly understand the present disclosure, rather than to limit the scope of the present disclosure. That is, those of ordinary skill in the art to which the present disclosure belongs will be able to easily understand that, based on the technical scope of the present disclosure, various modifications are possible. It will be apparent to those skilled in the art that, without departing from the spirit or scope of the present invention, various modifications may be made to the above-described embodiments of the present disclosure. Therefore, it is intended that the embodiments of the present disclosure cover all these modifications, as long as they fall within the scope of the appended claims and their equivalents.

Claims

1. A method of operating a semiconductor device, the semiconductor device comprising memory blocks sharing a common source line, each of the memory blocks comprising memory strings, the memory strings each comprising a first source selection line, a second source selection line, and a memory cell, the method comprising: applying a first voltage to a first source select line coupled to a first source select transistor of a memory string included in an unselected memory block among the memory blocks; applying a precharge voltage to the common source line when the first voltage is applied to the first source selection line; after the first voltage is applied to the first source select line, floating the first source select line; applying a second voltage having a lower voltage level than the first voltage to a second source select line coupled to a second source select transistor of the memory string included in the unselected memory block; and A program voltage is applied to a word line coupled to selected memory cells of a memory string included in a selected memory block among the memory blocks. 2 . The method of claim 1 , wherein the memory string is coupled between the common source line and a bit line, and the first source select transistor is closer to the common source line than the second source select transistor. 3 . The method of claim 1 , wherein when the second voltage is applied, the second source select transistor is turned off. 4 . The method according to claim 1 , wherein the second voltage has a voltage level lower than a threshold voltage of the second source select transistor. The method of claim 1 , wherein the first voltage is a positive voltage, and the second voltage is a ground voltage. The method of claim 1 , wherein the first voltage is a first positive voltage and the second voltage is a second positive voltage. 7 . The method according to claim 1 , wherein a voltage level of the first voltage is equal to or lower than a voltage level of the precharge voltage. 8 . The method of claim 1 , wherein when the first voltage is applied to the first source select line and the second voltage is applied to the second source select line, a level of the common source line is increased to a precharge level.

9. The method according to claim 1, wherein the second voltage is applied when the precharge voltage is applied. 10 . The method of claim 1 , wherein a level of the common source line is increased to a precharge level using capacitance between the first source select line and the common source line. 11 . The method of claim 1 , wherein when the first voltage is applied to the first source select line, the second voltage is applied to the second source select line. 12 . The method of claim 1 , wherein the second voltage is applied to the second source select line when the first source select line is floated. 13 . The method of claim 1 , wherein each of the memory strings further comprises a third source select transistor coupled between the first source select transistor and the second source select transistor.

14. The method according to claim 13, further comprising: A third source selection line coupled to the third source selection transistor is floated.

15. The method according to claim 13, further comprising: When the first voltage is applied to the first source select line and the second voltage is applied to the second source select line, a third source select line coupled to the third source select transistor is floated.

16. The method according to claim 13, further comprising: When the first source select line is floated and the second voltage is applied to the second source select line, a third source select line coupled to the third source select transistor is floated. 17 . The method of claim 1 , wherein a channel region of the memory string included in the selected memory block is precharged using the precharge voltage.

18. A method of operating a semiconductor device, the semiconductor device comprising memory blocks sharing a common source line, each of the memory blocks comprising memory strings coupled between the common source line and a bit line, each of the memory strings comprising a first group of source select transistors, a second group of source select transistors, and memory cells, wherein the first group is coupled between the common source line and the second group, the method comprising: applying a positive voltage to a first source select line coupled to a first group of memory strings included in an unselected memory block among the memory blocks; applying a precharge voltage to the common source line when the positive voltage is applied to the first source selection line; after the positive voltage is applied to the first source select line, floating the first source select line; applying a voltage for turning off the second group to a second source selection line coupled to a second group of memory cell strings included in the unselected memory block; and A program voltage is applied to a word line coupled to selected memory cells of a memory string included in a selected memory block among the memory blocks.

19. A semiconductor device comprising: a common source line; a first memory block including first memory strings coupled between the common source line and a first bit line, each of the first memory strings including a first source select transistor, a second source select transistor, and a memory cell, wherein the first source select transistor is located closer to the common source line than the second source select transistor; a second memory block including second memory strings coupled between the common source line and a second bit line, each of the second memory strings including a third source select transistor, a fourth source select transistor, and a memory cell, wherein the third source select transistor is located closer to the common source line than the fourth source select transistor; a peripheral circuit configured to perform a programming operation on the first memory string and the second memory string; as well as A control logic circuit controls the peripheral circuit to apply a first voltage to a first source selection line coupled to a first source selection transistor of the first memory string when the second memory block is selected, apply a precharge voltage to the common source line when the first voltage is applied to the first source selection line, float the first source selection line after the first voltage is applied to the first source selection line, apply a second voltage to a second source selection line coupled to a second source selection transistor of the first memory string, the second voltage having a voltage level lower than the first voltage, and apply a programming voltage to a word line coupled to a selected memory cell of the second memory string. 20 . The semiconductor device according to claim 19 , wherein the first voltage is a positive voltage, the second voltage has a voltage level lower than a threshold voltage of the second source select transistor, and the first source select line is located between the common source line and the second source select line.

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