semiconductor packages

Abstract

Embodiments of this application provide a semiconductor package, including: a first chip and a second chip arranged side-by-side; a pad located on the lower surface of the first chip adjacent to the second chip; and a trace electrically connected to the pad. In a top view, a first center of the first chip and the pad define a first connection line, and the intersection of the first connection line and the periphery of the pad defines a first boundary region closer to the first center and a second boundary region farther from the first center. The trace does not overlap with the second boundary region. The object of this invention is to provide a semiconductor package to improve the performance of the semiconductor package.

Description

Technical Field

[0001] Embodiments of the present invention relate to semiconductor packages. Background Technology

[0002] In fan-out chip-on-substrate (FOCOS) packaging structures, the underfill material around the fan-out redistribution layer / line layer (RDL) and microbumps / micropads is generally an organic dielectric material. Due to the limitations of current material properties, the protective force of these materials on the line layer weakens after entering the rubber state at high temperatures, and the stress generated by the surrounding structure may damage the line layer. Summary of the Invention

[0003] In view of the problems existing in the related technologies, the purpose of the present invention is to provide a semiconductor package to improve the performance of the semiconductor package.

[0004] Embodiments of this application provide a semiconductor package, including: a first chip and a second chip arranged side by side; a pad located on the lower surface of the first chip adjacent to the second chip; and a trace electrically connected to the pad. In a top view, a first center of the first chip and the pad define a first line, and the intersection of the first line and the periphery of the pad defines a first boundary region closer to the first center and a second boundary region farther from the first center. The trace does not overlap with the second boundary region.

[0005] In some embodiments, the angle between the second line connecting the point in the second boundary region and the second center of the pad and the first line passing through the second center of the pad does not exceed ±30 degrees.

[0006] In some embodiments, the second boundary region is located closer to the outer part of the second chip on the pad, away from the first center of the first chip, compared to the first boundary region.

[0007] In some embodiments, the pad is directly connected to the through hole, which is electrically connected to the trace. In a top view, the through hole is located within the projection range of the pad.

[0008] In some embodiments, in a top view, the first chip has a central horizontal line dividing the first chip into an upper and a lower portion, and traces electrically connected to pads in the upper and lower portions extend from vias toward the central horizontal line.

[0009] In some embodiments, in a top view, the trace extends from the through-hole perpendicular to the center horizontal line.

[0010] In some embodiments, in a top view, the trace extends from the through-hole in a direction perpendicular to the first connecting line.

[0011] In some embodiments, it further includes: pads for connecting traces to vias.

[0012] In some embodiments, in a top view, the diameter of the pad is greater than the diameter of the solder pad, which is greater than the diameter of the via.

[0013] In some embodiments, in a top view, the second center of the pad overlaps with the third center of the via and the fourth center of the pad.

[0014] Embodiments of this application also provide a semiconductor package, including: a first chip and a second chip arranged side by side; a pad located on the lower surface of the first chip adjacent to the second chip; a trace, wherein a pad at the end of the trace is electrically connected to the pad, and in a top view, a first center of the first chip and the pad define a first connection line, and the intersection of the first connection line and the periphery of the pad defines a first boundary region closer to the first center and a second boundary region farther from the first center, wherein the pad overlaps with the second boundary region.

[0015] In some embodiments, the width of the pad at the location where it overlaps with the second boundary region is greater than half the diameter of the pad.

[0016] In some embodiments, the angle between the second line connecting the point in the second boundary region and the second center of the pad and the first line passing through the second center of the pad does not exceed ±30 degrees.

[0017] In some embodiments, the second boundary region is closer to the second chip than the first boundary region.

[0018] In some embodiments, the pads are directly connected to the vias, and the vias are directly connected to the pads. In a top view, the vias are located within the projection range of the pads.

[0019] In some embodiments, in a top view, the third center of the via and the fourth center of the pad do not overlap with the second center of the connector, and the third center of the via and the fourth center of the pad are located between the second center and the second boundary area. In some embodiments, in a top view, the periphery of the pad overlaps with the second boundary area.

[0020] In some embodiments, in a top view, the pads, vias, and solder pads are circular.

[0021] In some embodiments, in a top view, the pad has a first maximum width in the extension direction of the first connection line, and the pad has a second maximum width in a direction perpendicular to the first connection line, wherein the first maximum width is smaller than the second maximum width. In some embodiments, in a top view, the periphery of the pad overlaps with a second boundary region. Attached Figure Description

[0022] The various aspects of the invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industrial practice, the components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the components may be arbitrarily increased or decreased.

[0023] Figures 1 to 5 Schematic diagrams of different embodiments of the semiconductor package of this application are shown. Detailed Implementation

[0024] To better understand the spirit of the embodiments of this application, the following description is based on some preferred embodiments of this application.

[0025] Embodiments of this application will be described in detail below. Throughout this specification, identical or similar components and components having identical or similar functions are indicated by similar reference numerals. The embodiments described herein with reference to the accompanying drawings are illustrative and diagrammatic in nature and are intended to provide a basic understanding of this application. The embodiments of this application should not be construed as limiting this application.

[0026] As used herein, the terms “approximately,” “generally,” “substantially,” and “about” are used to describe and indicate small variations. When used in conjunction with an event or situation, the terms may refer to examples in which the event or situation occurred precisely and examples in which the event or situation occurred very approximately. For example, when used in conjunction with numerical values, the terms may refer to a range of variation less than or equal to ±10% of the numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. For example, if the difference between two values ​​is less than or equal to ±10% of the average of the values ​​(e.g., less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%), then the two values ​​can be considered "substantially" the same.

[0027] In this specification, unless otherwise specified or limited, relative terms such as “central,” “longitudinal,” “lateral,” “front,” “rear,” “right,” “left,” “inner,” “outer,” “lower,” “higher,” “horizontal,” “vertical,” “above,” “below,” “above,” “below,” “top,” “bottom,” and their derivatives (e.g., “horizontally,” “downward,” “upward,” etc.) should be interpreted as referring to the directions described in the discussion or depicted in the accompanying drawings. These relative terms are used for descriptive convenience only and do not require that this application be constructed or operated in a particular orientation.

[0028] Additionally, quantities, ratios, and other numerical values ​​are sometimes presented in range format in this document. It should be understood that such range format is for convenience and brevity and should be interpreted flexibly to include not only the numerical values ​​explicitly specified as range limits, but also all individual numerical values ​​or subranges covered within the range, as if each numerical value and subrange were explicitly specified.

[0029] Furthermore, for ease of description, "first," "second," "third," etc., can be used in this article to distinguish different components of a figure or a series of figures. "First," "second," "third," etc., are not intended to describe the corresponding components.

[0030] Heterogeneous integration of fan-out chip-on-substrate (FOCOS) packaging structures is a key 3D stacking technology currently under development. Its purpose is to provide high-speed interconnects (e.g., fan-out line layer interconnects) for multiple closely connected chips (e.g., chip-to-chip spacing <300μm). However, the extremely fine lines within the fan-out line layer are prone to trace breakage due to large warping or localized large stress.

[0031] The semiconductor package of this application will now be described in detail with reference to the accompanying drawings.

[0032] Simulations revealed that the damage to the circuit layer was caused by excessive stress exerted on the traces of the underlying circuit layer by bumps / pads near the chip's boundary (e.g., application-specific integrated circuit (ASIC) chips, high bandwidth memory (HBM) chips). Figure 1In this embodiment, due to the low rigidity of the filler material 14 between the first chip 10 and the second chip 12, the circuit layer 16 is prone to upward warping (as shown by arrow A). The area of ​​the circuit layer 16 that bears greater stress (as shown by arrow C) is the lower boundary of the via 18 / pad 19 projection area extending radially outward from the center of the first chip 10 and close to the second chip 12. Therefore, if the trace 17 cannot withstand the stress at this location, it will lead to cracking (B). In this embodiment, the via 18 is a microbump, and the via 18 and the pad 19 are interconnected by solder 15. In this embodiment, the circuit layer 16 includes the trace 17 and a polymer layer 20 covering the trace 17. In this embodiment, the linewidth / spacing of the trace 17 in the circuit layer 16 is less than 3μm / 3μm, and the thickness of the circuit layer 16 is less than 5μm.

[0033] An embodiment of this application provides a semiconductor package, including: a first chip 10 and a second chip 12 arranged side by side; a pad 19 located on the lower surface of the first chip 10 adjacent to the second chip 12; and a trace 17 electrically connected to the pad 19.

[0034] See also Figure 2 The image shows the first chip 10 and the pads 19 located at positions P1, P2, and P3 respectively. Figure 2 The right side shows an enlarged view of the pad 19. In the top view, the first center O1 of the first chip 10 and the pad 19 define a first connection line L1. More specifically, the first center O1 of the first chip 10 and the second center O2 of the pad 19 define the first connection line L1. The intersection of the first connection line L1 and the periphery of the pad 19 defines a first boundary region 21 closer to the first center O1 and a second boundary region 22 farther away from the first center O1. The trace 17 does not overlap with the second boundary region 22.

[0035] In some embodiments, the angle θ between the second line connecting the point in the second boundary region 22 and the second center of the pad 19 and the first line L1 passing through the second center O2 does not exceed ±30 degrees. In some embodiments, the second boundary region 22 is located on the outer side of the pad 19 away from the first center O1 of the first chip 10. In some embodiments, the pad 19 is connected to a via 18, which is electrically connected to a trace 17. In a top view, the via 18 is located within the projection range of the pad 19. In some embodiments, in a top view, the first chip 10 has a central horizontal line L3 dividing the first chip into an upper and a lower portion. The trace 17, electrically connected to the pads 19 in the upper and lower portions, extends from the via 18 toward the central horizontal line L3. In some embodiments, in a top view, such as the pad 19 at position P2, the trace 17 extends from the via 18 perpendicular to the central horizontal line L3. In some embodiments, a pad 24 is also included to connect the trace 17 to the via 18. In some embodiments, in a top view, the diameter of the pad 19 is larger than the diameter of the pad 24, which is larger than the diameter of the via 18. In some embodiments, in a top view, the second center O2 of the pad 19 overlaps with the third center O3 of the via and the fourth center O4 of the pad 24. The second boundary region 22 is closer to the second chip 12 than the first boundary region 21.

[0036] Embodiments of this application also provide a semiconductor package, including: a first chip 10 and a second chip 12 arranged side by side; a pad 19 located on the lower surface of the first chip 10 adjacent to the second chip 12; a trace 17, with a pad 24 at the end of the trace 17 electrically connected to the pad 19. In a top view, a first center O1 of the first chip 19 and the pad 19 define a first connection L1. Further, the first center O1 of the first chip 10 and the second center O2 of the pad 19 define the first connection L1. The intersection of the first connection L1 and the periphery of the pad 19 defines a first boundary region 21 closer to the first center O1 and a second boundary region 22 farther away from the first center O1. The pad 24 overlaps with the second boundary region 22.

[0037] like Figure 3 As shown, Figure 3 Shown Figure 2 In some embodiments, the width of the pad 19 located at position P2, where it overlaps with the second boundary region 22, is greater than half the diameter of the pad 19. In some embodiments, in a top view, the third center O3 of the via 18 and the fourth center O4 of the pad 24 do not overlap with the second center O2 of the pad 19, and the third center O3 of the via 18 and the fourth center O4 of the pad 24 are located between the second center O2 and the second boundary region 22. In some embodiments, in a top view, the periphery of the pad 24 overlaps with the second boundary region 22. In some embodiments, in a top view, the pad 19, the via 18, and the pad 24 are circular.

[0038] In some embodiments, such as Figure 4 As shown in the top view, pad 19 has a first maximum width W1 in the extension direction of the first connecting line, and pad 19 has a second maximum width W2 in the direction perpendicular to the first connecting line. The first maximum width W1 is smaller than the second maximum width W2. That is, pad 19 is elliptical, and its major axis is perpendicular to the first connecting line L1 passing through the second center O2. In some embodiments, in the top view, the periphery of the pad overlaps with the second boundary area 22.

[0039] In some embodiments, such as Figure 5 As shown in the top view, the width of the pad 24 increases on the side near the second boundary area 22 until the pad 24 can cover the entire second boundary area 22.

[0040] In embodiments of this application, the traces of the fan-out circuit layer bypass the second boundary region, or overlap the second boundary region with a wider pad (causing the pad to shrink inward; widening the pad width; shifting the center of the pad relative to the center of the pad) to enhance the structural strength of the fan-out circuit layer. This reduces the stress per unit area of ​​the pad / trace, thereby reducing the risk of fan-out circuit layer failure and solving the problems of fan-out circuit layer failure and reliability yield in multi-chip homogeneous / heterogeneous integrated products.

[0041] The foregoing description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Those skilled in the art will readily appreciate that various modifications and variations of the present invention are possible. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present invention are intended to be within the scope of protection of the present invention.

Claims

1. A semiconductor package, characterized in that, include: The first and second chips are arranged side by side; A contact pad is located on the lower surface of the first chip on the side adjacent to the second chip; The trace is electrically connected to the pad. In the top view, the first center of the first chip and the pad define a first line, and the intersection of the first line and the periphery of the pad defines a first boundary area closer to the first center and a second boundary area farther away from the first center. The trace does not overlap with the second boundary area. The pad is connected to the through hole, and the through hole is electrically connected to the trace. In the top view, the first chip has a central horizontal line dividing the first chip into an upper part and a lower part, and the trace electrically connected to the pad in the upper and lower parts extends from the through hole toward the central horizontal line.

2. The semiconductor package according to claim 1, characterized in that, The two endpoints of the second boundary area are respectively connected to the second center of the pad to define the second line and the third line. Compared with the first line passing through the second center of the pad, the second line and the third line are located on opposite sides of the first line, and the angle between the second line and the third line and the first line passing through the second center of the pad does not exceed 30 degrees.

3. The semiconductor package according to claim 2, characterized in that, The second boundary area is closer to the second chip than the first boundary area.

4. The semiconductor package according to claim 1, characterized in that, In the top view, the through hole is located within the projection range of the pad.

5. The semiconductor package according to claim 1, characterized in that, In the top view, the trace extends from the through-hole perpendicular to the center horizontal line.

6. The semiconductor package according to claim 1, characterized in that, In the top view, the trace extends from the through hole in a direction perpendicular to the first connecting line.

7. The semiconductor package according to claim 4, characterized in that, Also includes: The pad connects the trace to the via.

8. The semiconductor package according to claim 7, characterized in that, In the top view, the diameter of the pad is larger than the diameter of the solder pad, and the diameter of the pad is larger than the diameter of the via.

9. The semiconductor package according to claim 7, characterized in that, In the top view, the second center of the pad overlaps with the third center of the via and the fourth center of the pad.

10. A semiconductor package, characterized in that, include: The first and second chips are arranged side by side; A contact pad is located on the lower surface of the first chip on the side adjacent to the second chip; The trace has a pad at its end that is electrically connected to the pad. In the top view, the first center of the first chip and the pad define a first connection line, and the intersection of the first connection line and the periphery of the pad defines a first boundary area closer to the first center and a second boundary area farther away from the first center, and the pad overlaps with the second boundary area; The pads are connected to vias, and the vias are electrically connected to the pads. In the top view, the first chip has a central horizontal line dividing the first chip into an upper part and a lower part, and the traces electrically connected to the pads in the upper and lower parts extend from the vias toward the central horizontal line.

11. The semiconductor package according to claim 10, characterized in that, The width of the pad at the location where it overlaps with the second boundary area is greater than half the diameter of the pad.

12. The semiconductor package according to claim 10, characterized in that, The two endpoints of the second boundary area are respectively connected to the second center of the pad to define a second line and a third line. Compared with the first line passing through the second center of the pad, the second line and the third line are located on opposite sides of the first line, and the angle between the second line and the third line and the first line passing through the second center of the pad does not exceed 30 degrees.

13. The semiconductor package according to claim 12, characterized in that, The second boundary region is closer to the second chip than the first boundary region.

14. The semiconductor package according to claim 10, characterized in that, The pad is connected to the through hole, and the through hole is connected to the pad. In the top view, the through hole is located within the projection range of the pad.

15. The semiconductor package according to claim 14, characterized in that, In the top view, the third center of the through hole and the fourth center of the pad do not overlap with the second center of the connector, and the third center of the through hole and the fourth center of the pad are located between the second center and the second boundary area.

16. The semiconductor package according to claim 15, characterized in that, In the top view, the periphery of the pad overlaps with the second boundary area.

17. The semiconductor package according to claim 16, characterized in that, In the top view, the pads, the vias, and the solder pads are circular.

18. The semiconductor package according to claim 14, characterized in that, In the top view, the pad has a first maximum width in the extension direction of the first connecting line, and the pad has a second maximum width in the direction perpendicular to the first connecting line, wherein the first maximum width is less than the second maximum width.

19. The semiconductor package according to claim 18, characterized in that, In the top view, the periphery of the pad overlaps with the second boundary area.

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