Semiconductor device and method for manufacturing the same

Abstract

A semiconductor device with an improved under-bump metallization layout and a method for forming the same are disclosed. In one embodiment, the semiconductor device includes an IC chip; an interconnect structure coupled to the IC die and including a metallization pattern, the metallization pattern including a via portion extending through a dielectric layer; a second dielectric layer located above the dielectric layer opposite to the IC die; and a second metallization pattern coupled to the metallization pattern and including a line portion located in the dielectric layer and a second via portion extending through the second dielectric layer; and a UBM located above the second metallization pattern and the second dielectric layer, the UBM coupled to the second metallization pattern, a center line of the via portion and a second center line of the second via portion being misaligned with a third center line of the UBM, and the center line and the second center line being on opposite sides of the third center line. Embodiments of the present invention also relate to a semiconductor device and a method for manufacturing the same.

Description

Technical Field

[0001] Embodiments of the present invention relate to a semiconductor device and a method for manufacturing the same. Background Art

[0002] The semiconductor industry has experienced rapid growth due to the continuous improvement of the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). In most cases, iterative reduction of the minimum component size can increase the integration density, so that more components can be integrated into a given area. As the demand for shrinking electronic devices grows, there has been a demand for smaller and more creative semiconductor die packaging technologies. An example of such a packaging system is package-on-package (PoP) technology. In a PoP device, a top semiconductor package is stacked on top of a bottom semiconductor package to provide a high level of integration and component density. PoP technology is generally capable of producing semiconductor devices with enhanced functionality and a small footprint on a printed circuit board (PCB). Summary of the invention

[0003] According to one aspect of an embodiment of the present invention, a semiconductor device is provided, comprising: a first integrated circuit die; an interconnect structure coupled to the first integrated circuit die, the interconnect structure comprising: a first metallization pattern comprising a first through-hole portion extending through a first dielectric layer; a second dielectric layer located above the first dielectric layer relative to the first integrated circuit die; and a second metallization pattern coupled to the first metallization pattern, the second metallization pattern comprising a line portion in the first dielectric layer and a second through-hole portion extending through the second dielectric layer; and an under bump metallization (UBM) above the second metallization pattern and the second dielectric layer, the UBM being coupled to the second metallization pattern, wherein a first center line of the first through-hole portion and a second center line of the second through-hole portion are not aligned with a third center line of the UBM, and wherein the first center line and the second center line are on opposite sides of the third center line.

[0004] According to another aspect of an embodiment of the present invention, a semiconductor device is provided, comprising: an integrated circuit die coupled to an interconnect structure, the interconnect structure comprising: one or more metallization patterns disposed in one or more dielectric layers; a top dielectric layer above the one or more metallization patterns and the one or more dielectric layers; and a top metallization pattern electrically coupled to the one or more metallization patterns, wherein the top metallization pattern comprises a via portion extending through the top dielectric layer, wherein a top surface of the via portion is flush with a top surface of the top dielectric layer; an under bump metallization extending along a top surface of the top dielectric layer and a top surface of the via portion of the top metallization pattern, wherein a first distance is measured between an edge of the under bump metallization layer closest to a centerline of a metal line and an edge of a via portion closest to a centerline of the integrated circuit die, wherein a second distance is measured between an edge of the under bump metallization farthest from the centerline of the integrated circuit die and an edge of the via portion farthest from the centerline of the integrated circuit die, and wherein a first difference between the first distance and the second distance is positive; and a conductive contact coupled to the under bump metallization.

[0005] According to another aspect of an embodiment of the present invention, a method for manufacturing a semiconductor device is provided, comprising: forming an interconnect structure on a first carrier; bonding a first die to the interconnect structure; removing the first carrier from the interconnect structure, wherein, after the first carrier is removed, a first through-hole portion of a first metallization pattern of the interconnect structure opposite to the first die is exposed; and forming a first UBM above and in physical contact with the first through-hole portion, wherein a centerline of the first UBM deviates from a centerline of the first through-hole portion. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Various aspects of the present invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale and are for illustration purposes only. In fact, the dimensions of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figures 1 to 6A and Figures 7 to 9 Cross-sectional views are shown of intermediate steps during a process of forming a packaged component in accordance with some embodiments.

[0008] FIG. 6B to FIG. 6I Cross-sectional and top views of an under bump metallization layout are shown in accordance with some embodiments. DETAILED DESCRIPTION

[0009] The following disclosure provides many different embodiments or examples for realizing different features of the present invention. Specific embodiments or examples of components and arrangements are described below to simplify the present invention. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present invention may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0010] In addition, for ease of description, spacing relation terms such as "below", "beneath", "lower", "above", "upper", etc. may be used herein to describe the relationship of one element or component to another element or component as shown in the figures. In addition to the orientation shown in the figures, the spacing relation terms are intended to encompass different orientations of the device in use or operating processes. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spacing relation descriptors used herein should be interpreted accordingly.

[0011] Various embodiments provide packaged semiconductor devices with improved under-bump metallization (UBM) layouts and methods for forming the same. An interconnect structure including a metallization pattern arranged in a dielectric layer may be formed. The top metallization pattern of the interconnect structure may include a via portion extending through the top dielectric layer of the interconnect structure. The UBM may be formed over the top metallization pattern and the top dielectric layer so that the centerline of the UBM deviates from or is misaligned with the centerline of the via portion of the top metallization pattern. Misaligning the centerline of the UBM with the centerline of the via portion may reduce stress in the surrounding dielectric layer, reduce cracks in the dielectric layer, and reduce device defects.

[0012] Figure 1 An interconnect structure 114 (also referred to as a redistribution structure) is shown formed over the carrier substrate 102 in accordance with some embodiments. Figure 1 In the embodiment, a carrier substrate 102 is provided, and a release layer 104 is formed on the carrier substrate 102. The carrier substrate 102 may be a glass carrier substrate, a ceramic carrier substrate, etc. The carrier substrate 102 may be a wafer, so that a plurality of packages may be formed on the carrier substrate 102 at the same time.

[0013] The release layer 104 can be formed of a polymer-based material that can be removed from the overlying structure to be formed in a subsequent step along with the carrier substrate 102. In some embodiments, the release layer 104 is an epoxy-based thermal release material that loses its adhesive properties when heated, such as a light-to-heat conversion (LTHC) release coating. In other embodiments, the release layer 104 can be an ultraviolet (UV) glue that loses its adhesive properties when exposed to UV light. The release layer 104 can be dispensed and cured in the form of a liquid, can be a laminated film laminated to the carrier substrate 102, or can be the like. The top surface of the release layer 104 can be horizontal and can have a high degree of flatness.

[0014] The interconnect structure 114 is formed on the release layer 104 and the carrier substrate 102. The interconnect structure 114 includes dielectric layers 108 and 112 and metallization patterns 106 and 110. The metallization patterns 106 and 110 may also be referred to as redistribution layers or redistribution lines. The interconnect structure 114 is shown to include four layers of metallization patterns 106 and 110 and five layers of dielectric layers 108 and 112. However, in some embodiments, more or fewer dielectric layers 108 and 112 and metallization patterns 106 and 110 may be formed in the interconnect structure 114. If fewer dielectric layers 108 and 112 and metallization patterns 106 and 110 are to be formed, the steps and processes discussed below may be omitted. If more dielectric layers 108 and 112 and metallization patterns 106 and 110 are to be formed, the steps and processes discussed below may be repeated.

[0015] exist Figure 1 In the embodiment of the present invention, dielectric layer 108 is deposited on release layer 104. In some embodiments, dielectric layer 108 is formed of a photosensitive material such as PBO, polyimide, BCB, etc., which can be patterned using a photolithography mask. Dielectric layer 108 can be formed by spin coating, lamination, chemical vapor deposition (CVD), etc., or a combination thereof. Then, dielectric layer 108 is patterned. Patterning forms openings that expose portions of release layer 104. Patterning can be formed by an acceptable process, such as by exposing dielectric layer 108 to light and developing it when dielectric layer 108 is a photosensitive material, or by etching using anisotropic etching, etc.

[0016] Then form metallization pattern 106.Metallization pattern 106 includes conductive elements extending along the main surface of dielectric layer 108 and extending through dielectric layer 108 to physically contact release layer 104.Metallization pattern 106 can be formed by depositing a seed layer (not shown separately) above dielectric layer 108 and in an opening extending through dielectric layer 108.In some embodiments, the seed layer is a metal layer, which can be a single layer or a composite layer including multiple sublayers formed by different materials.In some embodiments, the seed layer includes a titanium layer and a copper layer above the titanium layer.The seed layer can be formed using, for example, physical vapor deposition (PVD).Then, a photoresist is formed on the seed layer and patterned.A photoresist can be formed by spin coating, etc., and can be exposed for patterning.The pattern of the photoresist corresponds to the metallization pattern 106.Patterning forms an opening through the photoresist to expose the seed layer.Then a conductive material is formed in the opening of the photoresist and on the exposed portion of the seed layer. The conductive material may be formed by plating such as electroplating or chemical plating. The conductive material may include a metal such as copper, titanium, tungsten, aluminum, etc. The combination of the conductive material and the underlying portion of the seed layer forms the metallization pattern 106. The photoresist and the portion of the seed layer where the conductive material is not formed are removed. The photoresist may be removed by an acceptable ashing or stripping process, such as using oxygen plasma, etc. Once the photoresist is removed, the exposed portion of the seed layer is removed, such as by using an acceptable etching process, such as by wet etching or dry etching.

[0017] Then, dielectric layers 112 and metallization patterns 110 are alternately formed over dielectric layers 108 and metallization patterns 106. Dielectric layers 112 may be formed by similar or the same materials and processes as described above for dielectric layers 108. Metallization patterns 110 may be formed by similar or the same materials and processes as described above for metallization patterns 106.

[0018] Then, UBM116 is formed on the topmost dielectric layer 112 and the topmost metallization pattern 110 of the interconnect structure 114. UBM116 can be used for external connection to the interconnect structure 114. UBM116 may include a bump portion extending on and along the main surface of the topmost dielectric layer 112 and a via portion extending through the topmost dielectric layer 112. The via portion may be in physical contact with the topmost metallization pattern 110 and electrically coupled to the topmost metallization pattern 110. UBM116 may be formed by materials and processes similar or identical to those described above for the metallization pattern 106. In some embodiments, UBM116 may have a different size than the metallization patterns 106 and 110.

[0019] exist Figure 2AIn the embodiment of the present invention, the first integrated circuit die 122 and the second integrated circuit die 124 are bonded to the interconnect structure 114 through the conductive connector 118. The conductive connector 118 is formed above the UBM 116. The conductive connector 118 can be a ball grid array (BGA) connector, a solder ball, a metal column, a controlled collapse chip connection (C4) bump, a microbump, a bump formed by chemical nickel plating-chemical palladium immersion gold technology (ENEPIG), etc. The conductive connector 118 can include conductive materials such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, etc. or a combination thereof. In some embodiments, the conductive connector 118 is formed by first forming a solder layer by evaporation, electroplating, printing, solder transfer, solder ball placement, etc. Once the solder layer is formed, reflow can be performed to shape the material into a desired bump shape. In some embodiments, the conductive connector 118 includes a metal column (e.g., a copper column), which can be formed by sputtering, printing, electroplating, chemical plating, CVD, etc. The metal column can be solder-free and have a substantially vertical sidewall. In some embodiments, a metal capping layer is formed on top of the metal pillar. The metal capping layer may include nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, etc. or a combination thereof, and may be formed by a plating process.

[0020] like Figure 2A As shown, a single first integrated circuit die 122 and a single second integrated circuit die 124 can be coupled to the interconnect structure 114. However, any number of first integrated circuit dies 122, second integrated circuit dies 124, and / or other dies (e.g., more than two dies or less than two dies) can be coupled to the interconnect structure 114. Although the first integrated circuit die 122 and the second integrated circuit die 124 are shown as having the same height, the first integrated circuit die 122 and the second integrated circuit die 124 can have varying heights.

[0021] Figure 2BA cross-sectional view of an integrated circuit die is shown, which can be used for a first integrated circuit die 122 and / or a second integrated circuit die 124. The integrated circuit die 122 / 124 will be packaged in a subsequent process to form an integrated circuit package. The integrated circuit chip 122 / 124 can be a logic chip (e.g., a central processing unit (CPU), a graphics processing unit (GPU), a system on a chip (SoC), an application processor (AP), a microcontroller, an application-specific integrated circuit (ASIC) die, etc.), a memory die (e.g., a dynamic random access memory (DRAM) die, a static random access memory (SRAM) die, a high bandwidth memory (HBM)) die, etc.), a power management die (e.g., a power management integrated circuit (PMIC) die), a radio frequency (RF) die, a sensor die, a microelectromechanical system (MEMS) die, a signal processing die (e.g., a digital signal processing (DSP) die, etc.), a front-end die (e.g., an analog front-end (AFE) die), etc. or a combination thereof. In some embodiments, the first integrated circuit die 122 may be a SoC and the second integrated circuit die 124 may be a memory die, such as an HBM die.

[0022] The integrated circuit die 122 / 124 can be formed in a wafer, which can include different device regions that are segmented in subsequent steps to form multiple integrated circuit dies. The integrated circuit die 122 / 124 can be processed according to an applicable manufacturing process to form an integrated circuit. For example, the integrated circuit die 122 / 124 includes a semiconductor substrate 52, such as doped or undoped silicon, or an active layer of a semiconductor on insulator (SOI) substrate. The semiconductor substrate 52 may include other semiconductor materials, such as germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide; alloy semiconductors, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP and / or GaInAsP; or combinations thereof. Other substrates, such as multilayer or gradient substrates, may also be used. The semiconductor substrate 52 has an active surface (e.g., at Figure 2B the upward-facing surface in the middle), sometimes called the front side; and the passive surface (e.g., Figure 2B The downward-facing surface of the middle part of the body is sometimes called the posterior side.

[0023] Device 54 (represented by a transistor) may be formed at an active surface of semiconductor substrate 52. Device 54 may be an active device (e.g., a transistor, a diode, etc.), a capacitor, a resistor, etc. Interlayer dielectric (ILD) 56 is above the active surface of semiconductor substrate 52. ILD 56 surrounds and may cover device 54. ILD 56 may include one or more dielectric layers formed of materials such as phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc.

[0024] Conductive plug 58 extends through ILD56 to electrically couple and physically couple device 54. For example, when device 54 is a transistor, conductive plug 58 can couple the gate and source / drain regions of the transistor. Conductive plug 58 can be formed by tungsten, cobalt, nickel, copper, silver, gold, aluminum, etc. or a combination thereof. Interconnect structure 60 is above ILD56 and conductive plug 58. Interconnect structure 60 interconnects device 54 to form an integrated circuit. Interconnect structure 60 can be formed by a metallization pattern in a dielectric layer on ILD56, for example. The metallization pattern includes metal lines and vias formed in one or more low-k dielectric layers. The metallization pattern of interconnect structure 60 is electrically coupled to device 54 through conductive plug 58.

[0025] The integrated circuit die 122 / 124 also includes a pad 62 connected to the outside, such as an aluminum pad. The pad 62 is on the active side of the integrated circuit die 122 / 124, such as within and / or on the interconnect structure 60. One or more passivation films 64 are on the integrated circuit die 122 / 124, such as on portions of the interconnect structure 60 and the pad 62. An opening extends through the passivation film 64 to the pad 62. A die connector 66, such as a conductive column (e.g., formed of a metal such as copper), extends through the opening in the passivation film 64 and is physically and electrically coupled to a corresponding one of the pads 62. The die connector 66 can be formed, for example, by plating. The die connector 66 electrically couples the individual integrated circuits of the integrated circuit die 122 / 124.

[0026] Alternatively, a solder region (e.g., a solder ball or solder bump) may be provided on the pad 62. The solder ball may be used to perform a chip probe (CP) test on the integrated circuit die 122 / 124. The CP test may be performed on the integrated circuit die 122 / 124 to determine whether the integrated circuit die 122 / 124 is a known good die (KGD). Therefore, only the integrated circuit die 122 / 124 of the KGD is subsequently processed and packaged, while the die that fails the CP test is not packaged. After the test, the solder region may be removed in a subsequent processing step.

[0027] The dielectric layer 68 may (or may not) be on the active side of the integrated circuit die 122 / 124, such as on the passivation film 64 and the die connector 66. The dielectric layer 68 laterally encapsulates the die connector 66, and the dielectric layer 68 laterally interfaces with the integrated circuit die 122 / 124. Initially, the dielectric layer 68 may bury the die connector 66 so that the uppermost surface of the dielectric layer 68 is above the uppermost surface of the die connector 66. In some embodiments where the solder region is disposed on the die connector 66, the dielectric layer 68 may also bury the solder region. Alternatively, the solder region may be removed before the dielectric layer 68 is formed.

[0028] The dielectric layer 68 may be a polymer, such as PBO, polyimide, BCB, etc.; a nitride, such as silicon nitride, etc.; an oxide, such as silicon oxide, PSG, BSG, BPSG, etc.; the like, or a combination thereof. The dielectric layer 68 may be formed, for example, by spin coating, lamination, chemical vapor deposition (CVD), etc. In some embodiments, during the formation of the integrated circuit die 122 / 124, the die connector 66 is exposed through the dielectric layer 68. In some embodiments, the die connector 66 remains buried and is exposed in a subsequent process for packaging the integrated circuit die 122 / 124. Exposing the die connector 66 may remove any solder area that may be present on the die connector 66.

[0029] In some embodiments, the integrated circuit die 122 / 124 is a stacked device including multiple semiconductor substrates 52. For example, the integrated circuit die 122 / 124 may be a memory device such as a hybrid memory cube (HMC) module, a high bandwidth memory (HBM) module including multiple memory dies, etc. In such an embodiment, the integrated circuit die 122 / 124 includes multiple semiconductor substrates 52 interconnected by through substrate vias (TSVs). Each semiconductor substrate 52 may have (or may not have) an interconnect structure 60.

[0030] The first integrated circuit die 122 and the second integrated circuit die 124 may be mechanically and electrically bonded to the interconnect structure 114 through the die connectors 66, the conductive connectors 118, and the UBM 116. The first integrated circuit die 122 and the second integrated circuit die 124 may be placed on the interconnect structure 114, and a reflow process may be performed to reflow the conductive connectors 118 and bond the die connectors 66 to the UBM 116 through the conductive connectors 118.

[0031] exist Figure 3In the embodiment, an underfill 126 is formed between the first integrated circuit die 122 and the second integrated circuit die 124 and the interconnect structure 114, surrounding the UBM 116, the conductive connector 118, and the die connector 66. The underfill 126 can reduce stress and protect the joint caused by the reflow of the conductive connector 118. The underfill 126 can be formed by a capillary flow process after the first integrated circuit die 122 and the second integrated circuit die 124 are attached, or can be formed by a suitable deposition method before the first integrated circuit die 122 and the second integrated circuit die 124 are attached. Figure 3 As shown, the top surface of the underfill 126 can be flush with the top surfaces of the first integrated circuit die 122 and the second integrated circuit die 124. In some embodiments, the top surface of the underfill 126 can be disposed below the top surfaces of the first integrated circuit die 122 and the second integrated circuit die 124. The side surfaces of the underfill material 126 can extend from the side surfaces of the first integrated circuit die 122 and the second integrated circuit die 124 to the top surface of the interconnect structure 114 (e.g., the top surface of the topmost dielectric layer 112).

[0032] exist Figure 4 In the embodiment of the present invention, the encapsulant 128 is formed over the interconnect structure 114 and the bottom filler 126, and surrounds the first integrated circuit die 122, the second integrated circuit die 124, and the bottom filler 126. After formation, the encapsulant 128 seals the first integrated circuit die 122, the second integrated circuit die 124, and the bottom filler 126. The encapsulant 128 can be a molding compound, an epoxy resin, etc. The encapsulant 128 can be applied by compression molding, transfer molding, etc., and can be formed over the interconnect structure 114 so that the first integrated circuit die 122 and / or the second integrated circuit die 124 are buried or covered. In some embodiments, the encapsulant 128 can be further formed in the gap area between the first integrated circuit die 122 and the second integrated circuit die 124. The encapsulant 128 can be applied in a liquid or semi-liquid form and then subsequently cured.

[0033] A planarization process may be performed on the encapsulant 128 to expose the first integrated circuit chip 122 and the second integrated circuit chip 124. The planarization process may also expose the bottom filler 126. The planarization process may remove the material of the first integrated circuit die 122, the second integrated circuit die 124, and / or the bottom filler 126 until the first integrated circuit die 122, the second integrated circuit die 124, and / or the bottom filler 126 are exposed. After the planarization process, within process variations, the top surfaces of the first integrated circuit chip 122, the second integrated circuit chip 124, the bottom filler 126, and the encapsulant 128 may be substantially coplanar (e.g., flush). The planarization process may be, for example, chemical mechanical polishing (CMP), a grinding process, etc. In some embodiments, for example, if the first integrated circuit die 122 and / or the second integrated circuit die 124 are already exposed, planarization may be omitted.

[0034] exist Figure 5 In the embodiment of the present invention, carrier substrate debonding is performed to separate carrier substrate 102 from interconnect structure 114 (or "debonding"), the device is flipped over, and second carrier substrate 150 is bonded to first integrated circuit die 122, second integrated circuit die 124, underfill 126, and encapsulant 128. In some embodiments, debonding includes projecting light such as laser or UV light onto release layer 104 so that release layer 104 decomposes under the heat of the light and carrier substrate 102 can be removed. Figure 5 As shown, after removing the carrier substrate 102 and the release layer 104, the surfaces of the dielectric layer 108 and the metallization pattern 106 can be exposed. The device can be flipped over so that the backsides of the first integrated circuit die 122 and the second integrated circuit die 124 are facing downward.

[0035] The second carrier substrate 150 may be bonded to the first integrated circuit die 122, the second integrated circuit die 124, the bottom fill 126, and the sealant 128 through the second release layer 152. The second carrier substrate 150 may be a glass carrier substrate, a ceramic carrier substrate, or the like. The second carrier substrate 150 may be a wafer so that a plurality of packages may be processed simultaneously on the second carrier substrate 150. The second release layer 152 may be formed of a polymer-based material, which may be removed from the overlying structure to be formed in a subsequent step together with the second carrier substrate 150. In some embodiments, the second release layer 152 is an epoxy-based thermal release material that loses its adhesive properties when heated, such as a light-to-heat conversion (LTHC) release coating. In other embodiments, the second release layer 152 may be an ultraviolet (UV) glue that loses its adhesiveness when exposed to UV light. The second release layer 152 may be dispensed and cured in the form of a liquid, may be a laminated film laminated to the second release layer 152, or may be the like. The top surface of the second release layer 152 may be horizontal and may have a high degree of flatness.

[0036] FIG. 6A to FIG. 6I Various views of the device are shown after forming a UBM 130 over the interconnect structure 114 , in accordance with some embodiments. FIG. 6B to FIG. 6E Shows Fig. 6A The region 132 may be aligned with the sidewalls of the first integrated circuit die 122. Fig. 6F , Figure 6H and Fig.6I Shows Fig. 6A Detailed cross-sectional view of region 131 of FIG. Figure 6C Shows Fig. 6A Detailed top-down view of region 131 of FIG.

[0037] exist FIG. 6A to FIG. 6I 1 , UBM 130 is formed over interconnect structure 114. UBM 130 may be formed on metallization pattern 106, extend along the surface of dielectric layer 108, and be electrically coupled to metallization pattern 106. UBM 130 may be used for external connection to interconnect structure 114. UBM 130 may be formed of materials and processes similar to or the same as those described above for metallization pattern 106. In some embodiments, UBM 130 may have different sizes than metallization patterns 106 and 110 and UBM 116.

[0038] exist 6A to 6HIn the illustrated embodiment, a centerline C1 of the UBM 130 (e.g., a virtual line extending through the center of the UBM 130 ) may be offset or misaligned with a centerline C2 of a via portion of the metallization pattern 106 (e.g., a virtual line extending through the center of the via portion of the metallization pattern 106 ) that extends through the dielectric layer 108 . Fig. 6A and Figure 6B In the illustrated embodiment, the centerline C2 of the through-hole portion of the metallization pattern 106 is arranged farther away from a point P1 aligned with the centerline of the first integrated circuit die 122 than the centerline C1 of the UBM 130. The likelihood of cracks and other defects occurring between the UBM 130, the metallization pattern 106, and the dielectric layer 108 may be greatest at the edge of the first integrated circuit die 122, and may decrease as the distance from the point P1 decreases. On the other hand, as the centerline C1 of the UBM 130 is offset or misaligned from the centerline C2 of the through-hole portion of the metallization pattern 106, the processing window of the UBM 130 decreases. Thus, as the distance from the point P1 increases, the distance that the centerline C1 of the UBM 130 is offset or misaligned from the centerline C2 of the through-hole portion of the metallization pattern 106 increases. For example, as the distance from the point P1 increases, the centerline C1 of the UBM 130 is offset or misaligned from the centerline C2 of the through-hole portion of the metallization pattern 106 increases. Fig. 6A As shown, UBM 130A may be closer to point P1 than UBM 130B. A distance D1 between a center line C1 of UBM 130A and a center line C2 of a through-hole portion of metallization pattern 106 may be smaller than a distance D2 between a center line C1 of UBM 130B and a center line C2 of a through-hole portion of metallization. Distance D1 may be in a range of about 1 μm to about 10 μm, and distance D2 may be in a range of about 5 μm to about 30 μm. This reduces cracks, etc., reduces device defects, improves device performance, and maintains the process window of UBM 130.

[0039] refer to Figure 6B , for the UBM 130A and the metallization pattern 106 closest to the point P1, the inner distance D between the edge of the UBM 130A closest to the point P1 and the edge of the through-hole portion of the metallization pattern 106 closest to the point P1 in1 The outer distance D between the edge of the UBM 130A farthest from the point P1 and the edge of the through-hole portion of the metallization pattern 106 farthest from the point P1 may be greater than out1 As the distances of the UBM 130 and the metallization pattern 106 from the point P1 increase, the difference between the inner distance and the outer distance may increase. For example, for the UBM 130B and the metallization pattern 106 farthest from the point P1, the inner distance D between the edge of the UBM 130B closest to the point P1 and the edge of the through-hole portion of the metallization pattern 106 closest to the point P1 may be greater than or equal to 0. in2The outer distance D between the edge of the UBM 130B farthest from the point P1 and the edge of the through-hole portion of the metallization pattern 106 farthest from the point P1 may be greater than out2 . Distance D in2 and distance D out2 The difference between them can be greater than the distance D in1 and distance D in1 The difference between the inner distance and the outer distance may be in the range of about 3 μm to about 30 μm. Figure 6B As shown, UBM 130 may be evenly distributed across the surface of dielectric layer 108 in region 132 .

[0040] exist Figure 6C In the illustrated embodiment, the inner distance D between the edge of the UBM 130A closest to the point P1 and the edge of the through-hole portion of the metallization pattern 106 closest to the point P1 is in3 The distance D between the edge of the UBM 130A farthest from the point P1 and the edge of the through-hole portion of the metallization pattern 106 farthest from the point P1 may be greater than the distance D between the edge of the UBM 130A farthest from the point P1 out3 For all UBMs 130 and metallization patterns 106, the inner distance D in3 , External distance D out3 The difference between the inner distance and the outer distance may be the same, but the embodiment is not limited thereto. For the UBM 130, the inner distance D is kept constant. in3 , External distance D out3 The difference between the inner distance and the outer distance simplifies layout considerations. The difference between the inner distance and the outer distance can be in the range of about 3 μm to about 30 μm. Figure 6C As shown, UBM 130 may be evenly distributed across the surface of dielectric layer 108 in region 132 .

[0041] exist Fig.6D and Fig. 6E In the embodiment shown, similar to Fig. 6A and Figure 6B In the illustrated embodiment, as the distance of the UBM 130 and the metallization pattern 106 from the point P1 increases, the difference between the inner distance and the outer distance increases. For example, for the UBM 130A and the metallization pattern 106 closest to the point P1, the inner distance D between the edge of the UBM 130A closest to the point P1 and the edge of the through-hole portion of the metallization pattern 106 closest to the point P1 is in4 The outer distance D between the edge of the UBM 130A farthest from the point P1 and the edge of the through-hole portion of the metallization pattern 106 farthest from the point P1 may be greater than out4 .exist Fig.6D, for the UBM 130B and the metallization pattern 106 farthest from the point P1, the inner distance D between the edge of the UBM 130B closest to the point P1 and the edge of the through-hole portion of the metallization pattern 106 closest to the point P1 in5 The distance D between the edge of the UBM 130B farthest from the point P1 and the outer distance D between the through-hole portion of the metallization pattern 106 farthest from the point P1 may be greater than the outer distance D between the edge of the UBM 130B farthest from the point P1 and ... through-hole portion of the metallization pattern 106 out5 . Similarly, in Fig. 6E , for the UBM 130B and the metallization pattern 106 farthest from the point P1, the inner distance D between the edge of the UBM 130B closest to the point P1 and the edge of the through-hole portion of the metallization pattern 106 closest to the point P1 in6 The distance D between the edge of the UBM 130B farthest from the point P1 and the outer distance D between the through-hole portion of the metallization pattern 106 farthest from the point P1 may be greater than the outer distance D between the edge of the UBM 130B farthest from the point P1 and ... through-hole portion of the metallization pattern 106 out6 . Distance D in5 and distance D out5 The difference between them can be greater than the distance D in4 and distance D out4 The difference between the two, and the distance D in6 and distance D out6 The difference between them can be greater than the distance D in4 and distance D out4 The difference between the inner distance and the outer distance may be in the range of about 3 μm to about 30 μm.

[0042] In addition, Fig.6D and Fig. 6E In the illustrated embodiment, the UBMs 130 may be unevenly distributed on the surface of the dielectric layer 108 in the region 132. For example, the UBMs 130 may have a greater density in the peripheral region of the region. In addition to omitting some UBMs 130 in the corner region of the region 132, Fig. 6E The illustrated embodiment can be used with Fig.6D The embodiments shown are identical.

[0043] FIG. 6B to FIG. 6E The illustrated embodiment shows and describes a layout of the UBM 130 and the metallization pattern 106 disposed over the first integrated circuit die 122. In some embodiments, the UBM 130 and the metallization pattern 106 over the second integrated circuit die 124 can have any of the above-described layouts, where the layout is centered around a point P2 aligned with the centerline of the second integrated circuit die 124 instead of the point P1. In some embodiments, the UBM 130 and the metallization pattern 106 over the entire interconnect structure 114 can have any of the above-described layouts, where the layout is centered around a point P3 aligned with the centerline of the interconnect structure 114.

[0044] Both the UBM 130 and the metallization pattern 106 may be formed of a metal, which may have a coefficient of thermal expansion (CTE) that does not match the CTE of the surrounding materials, such as the dielectric layers 108 and 112. Alignment of the centerline C2 of the via portion of the metallization pattern 106 with the centerline C1 of the UBM 130 may induce high stress in the resulting structure, leading to cracks in the dielectric layers 108 and 112. However, by forming the UBM 130 over the metallization pattern 106, the stress in the resulting structure is reduced due to the offset or misalignment of the centerline C1 of the UBM 130 with the centerline C2 of the via portion of the metallization pattern 106, which reduces the likelihood of cracks and reduces device defects.

[0045] exist Fig. 6F and Figure 6G In the illustrated embodiment, the center line C2 of the through hole portion of the metallization pattern 106 and the center line C3 of the through hole portion of the metallization pattern 110 are arranged relative to the center line C1 of the UBM 130. The center line C1 of the UBM 130 and the center line C2 of the through hole portion of the metallization pattern 106 can be the same as described above. Fig. 6A The distance D1 or D2 discussed is the same. The distance D3 between the center line C1 of the UBM 130 and the center line C3 of the through-hole portion of the metallization pattern 110 may be in the range of about 3 μm to about 30 μm. Similar to the distance between the center line C1 of the UBM 130 and the center line C2 of the through-hole portion of the metallization pattern 106, the distance between the center line C1 of the UBM 130 and the center line C3 of the through-hole portion of the metallization pattern 110 may increase as the distance from the point P1 increases; or remain constant as the distance from the point P1 increases. Placing the center lines C2 and C3 on opposite sides of the center line C1 may increase the amount of dielectric material from the dielectric layer 112 between the center lines C2 and C3, which may further reduce stress in the resulting structure and reduce device defects.

[0046] exist Figure 6H In the illustrated embodiment, the center line C3 of the through hole portion of the metallization pattern 110 is aligned with the center line C1 of the UBM 130, and the center line C2 of the through hole portion of the metallization pattern 106 is offset from or misaligned with the center line C1 of the UBM 130 and the center line C3 of the through hole portion of the metallization pattern 110. The distance D5 between the center line C2 of the through hole portion of the metallization pattern 106 and the center line C1 of the UBM 130 and the center line C3 of the through hole portion of the metallization pattern 110 can be the same as described above. Fig. 6A The distance D1 or D2 in question is the same.

[0047] exist Fig.6IIn the illustrated embodiment, UBM130 is replaced by UBM130.i, which includes a through-hole portion extending through dielectric layer 108. The through-hole portion of UBM130.i may be in physical contact with and electrically coupled to metallization pattern 106. The through-hole portion of metallization pattern 106 extending through dielectric layer 108 may be omitted, and the opening may be patterned after debonding carrier substrate 102 and before forming UBM130.i. UBM130.i may be formed of materials and processes similar to or the same as those described above for UBM130. UBM130.i may be formed with a centerline C4 of an upper portion of UBM130.i located above the top, and centerline C4 is offset or misaligned with a centerline C5 of the through-hole portion of UBM130.i located below the top surface of dielectric layer 108. A distance D5 between centerline C4 of the upper portion of UBM130 and centerline C5 of the through-hole portion of UBM130.i may be the same as described above with respect to Fig. 6A The distance D1 or D2 in question is the same.

[0048] Both the UBM 130.i and the metallization pattern 106 may be formed of a metal, which may have a coefficient of thermal expansion (CTE) that does not match the CTE of surrounding materials such as the dielectric layer 108. Aligning the centerline C4 of the upper portion of the UBM 130.i and the centerline C5 of the via portion of the UBM 130.i may induce high stress in the resulting structure, thereby causing cracking of the dielectric layer 108. However, by forming the UBM 130.i so that the centerline C4 of the upper portion of the UBM 130.i is offset or misaligned with the centerline C5 of the via portion of the UBM 130.i, the stress in the resulting structure is reduced, which reduces the possibility of cracking and reduces device defects.

[0049] exist Figure 7In the embodiment of the present invention, a conductive connector 134 is formed above the UBM 130. The conductive connector 134 can be a ball grid array (BGA) connector, a solder ball, a metal column, a controlled collapse chip connection (C4) bump, a microbump, a bump formed by chemical nickel plating chemical palladium immersion gold technology (ENEPIG), etc. The conductive connector 134 can include conductive materials such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, etc. or a combination thereof. In some embodiments, the conductive connector 134 is formed by first forming a solder layer by evaporation, electroplating, printing, solder transfer, ball placement, etc. Once the solder layer is formed, reflow can be performed to shape the material into a desired bump shape. In some embodiments, the conductive connector 134 includes a metal column (such as a copper column), which can be formed by sputtering, printing, electroplating, chemical plating, CVD, etc. The metal column can be solder-free and have a substantially vertical sidewall. In some embodiments, a metal cap layer is formed on the top of the metal column. The metal capping layer may include nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, etc. or a combination thereof, and may be formed by a plating process.

[0050] exist Figure 8 In the embodiment of the present invention, carrier substrate debonding is performed to separate (debond) the second carrier substrate 150 from the first integrated circuit die 122, the second integrated circuit die 124, the underfill 126, and the encapsulant 128, and the device is flipped over. In some embodiments, debonding includes projecting light such as laser or UV light on the second release layer 152 so that the second release layer 152 decomposes under the heat of the light and the second carrier substrate 150 can be removed. Figure 8 As shown, after removing the second carrier substrate 150 and the second release layer 152, the surfaces of the first integrated circuit die 122, the second integrated circuit die 124, the bottom fill 126, and the sealant 128 can be exposed. The back sides of the first integrated circuit chip 122 and the second integrated circuit chip 124 are flipped over so that the back sides of the first integrated circuit chip 122 and the second integrated circuit chip 124 face upward. After removing the second carrier substrate 150 and the second release layer 152, the resulting device can be referred to as a first package assembly 100.

[0051] exist Fig. 9, the substrate 140 is coupled to the first package component 100. The substrate 140 can be made of a semiconductor material such as silicon, germanium, diamond, etc. In some embodiments, composite materials such as silicon germanium, silicon carbide, gallium arsenide, indium arsenide, indium phosphide, silicon germanium carbide, gallium arsenide phosphide, gallium indium phosphide, etc., and combinations thereof, etc. can also be used. In addition, the substrate 140 can be a silicon on insulator (SOI) substrate. Typically, the SOI substrate includes a semiconductor material layer, such as epitaxial silicon, germanium, silicon germanium, SOI, silicon germanium on insulator (SGOI), or a combination thereof. In some embodiments, the substrate 140 can be based on an insulating core, such as a glass fiber reinforced resin core. In some embodiments, the core material can be a glass fiber resin, such as FR4. In some embodiments, the core material can include bismaleimide-triazine (BT) resin, other printed circuit board (PCB) materials, or other films. A stacked film such as Ajinomoto stacked film (ABF) or other stacks can be used for the substrate 140.

[0052] The substrate 140 may include active and passive devices (not shown separately). A variety of devices may be included, such as transistors, capacitors, resistors, combinations thereof, and the like. Any suitable method may be used to form the device. The substrate 140 may also include a metallization layer (not shown). The metallization layer may be formed on top of the active and passive devices and is designed to connect various devices to form a functional circuit. The metallization layer may be formed by alternating layers of a dielectric material (e.g., a low-k dielectric material) and a conductive material (e.g., copper) and have through holes that interconnect the conductive material layers. The metallization layer may be formed by any suitable process (e.g., deposition, inlay, dual inlay, etc.). In some embodiments, the substrate 140 is substantially free of active and passive devices.

[0053] The substrate 140 may include a bonding pad 142 formed on a first surface of the substrate 140 facing the first package component 100. In some embodiments, the bonding pad 142 may be formed by forming a recess (not shown separately) in a dielectric layer (not shown separately) on a first side of the substrate 140. The recess may be formed to allow the bonding pad 142 to be embedded in the dielectric layer. In some embodiments, the recess is omitted and the bonding pad 142 may be formed on the dielectric layer. In some embodiments, the bonding pad 142 includes a thin seed layer (not shown separately) made of copper, titanium, nickel, gold, palladium, etc., or a combination thereof. The conductive material of the bonding pad 142 may be deposited on the thin seed layer. The conductive material may be formed by an electrochemical plating process, a chemical plating process, CVD, atomic layer deposition (ALD), PVD, etc., or a combination thereof. In one embodiment, the conductive material of the bonding pad 142 includes copper, tungsten, aluminum, silver, gold, etc., or a combination thereof.

[0054] In some embodiments, the bonding pad 142 is a UBM that includes three layers of conductive material, such as a titanium layer, a copper layer, and a nickel layer. Other arrangements of materials and layers may be used, such as an arrangement of chromium / chromium-copper alloy / copper / gold, an arrangement of titanium / titanium tungsten / copper, or an arrangement of copper / nickel / gold. Any suitable material or material layer that may be used for the bonding pad 142 is fully intended to be included within the scope of the present application.

[0055] The substrate 140 may be mechanically and electrically bonded to the first package assembly 100 through the bonding pads 142, the conductive connectors 134, and the UBM 130. The substrate 140 may be placed on the first package assembly 100 and the substrate. A reflow process may be performed to reflow the conductive connectors 134 and bond the pads 142 to the UBM 130 through the conductive connectors 134.

[0056] Then, an underfill 144 may be formed between the first package component 100 and the substrate 140, surrounding the bonding pads 142, the UBM 130, and the conductive connectors 134. The underfill 144 may reduce stress and protect the joints caused by the reflowing conductive connectors 134. The underfill 144 may be formed by a capillary flow process after attaching the first package component 100 to the substrate 140, or may be formed by an appropriate deposition method before attaching the first package component 100.

[0057] Embodiments can achieve various advantages. For example, forming a UBM on a metallization pattern such that the centerline of a through-hole portion of the metallization pattern is offset from or misaligned with the centerline of the UBM reduces stress in the resulting structure. This reduces the likelihood of cracks in the surrounding dielectric layer, thereby reducing device defects.

[0058] According to one embodiment, a semiconductor device includes a first integrated circuit die; an interconnect structure coupled to the first integrated circuit die, the interconnect structure including: a first metallization pattern including a first via portion extending through a first dielectric layer; a second dielectric layer located above the first dielectric layer relative to the first integrated circuit die; and a second metallization pattern coupled to the first metallization pattern, the second metallization pattern including a line portion in the first dielectric layer and a second via portion extending through the second dielectric layer; and an under bump metallization (UBM) above the second metallization pattern and the second dielectric layer, the UBM coupled to the second metallization pattern, wherein a first centerline of the first via portion and a second centerline of the second via portion are not aligned with a third centerline of the UBM, wherein the first centerline and the second centerline are on opposite sides of the third centerline. In one embodiment, a conductive bump coupled to the UBM and in physical contact with the UBM is also included. In one embodiment, a second integrated circuit die coupled to the interconnect structure is also included, the first integrated circuit die includes a system on chip, and the second integrated circuit die includes a high bandwidth memory die. In one embodiment, in a first direction parallel to a major surface of the second dielectric layer, a distance between the second center line and the third center line is 3 μm to 30 μm. In one embodiment, the UBM is disposed in a first region, the first region having a boundary aligned with a sidewall of the first integrated circuit die, wherein the third center line is closer to a fourth center line of the first region than the second center line. In one embodiment, a second UBM is further included, wherein the second metallization pattern further includes a third via portion extending through the second dielectric layer, the third via portion being coupled to the second UBM, wherein a fifth center line of the second UBM is disposed further away from the fourth center line of the first region than the third center line of the UBM, wherein a first distance between the second center line and the third center line in the first direction parallel to the major surface of the second dielectric layer is less than a second distance between the fifth center line and the sixth center line of the third via portion in the first direction. In one embodiment, a second UBM is also included, wherein the second metallization pattern further includes a third via portion extending through the second dielectric layer, the third via portion being coupled to the second UBM, wherein a fifth centerline of the second UBM is disposed farther away from a fourth centerline of the first region than a third centerline of the UBM, wherein a first distance between the second centerline and the third centerline in a first direction parallel to a major surface of the second dielectric layer is equal to a second distance between a fifth centerline and a sixth centerline of the third via portion in the first direction.

[0059] According to another embodiment, a semiconductor device includes: an integrated circuit die coupled to an interconnect structure, the interconnect structure including: one or more metallization patterns disposed in one or more dielectric layers; a top dielectric layer over the one or more metallization patterns and the one or more dielectric layers; and a top metallization pattern electrically coupled to the one or more metallization patterns, wherein the top metallization pattern includes a via portion extending through the top dielectric layer, wherein a top surface of the via portion is flush with a top surface of the top dielectric layer; an under bump metallization extending along a top surface of the top dielectric layer and a top surface of the via portion of the top metallization pattern, wherein a first distance is measured between an edge of the under bump metallization layer closest to a centerline of a metal line and an edge of a via portion closest to a centerline of the integrated circuit die, wherein a second distance is measured between an edge of the under bump metallization farthest from the centerline of the integrated circuit die and an edge of the via portion farthest from the centerline of the integrated circuit die, and wherein a first difference between the first distance and the second distance is positive; and a conductive contact coupled to the under bump metallization. In one embodiment, the integrated circuit die includes a system-on-chip die. In one embodiment, it further comprises a second under bump metallization extending along the top surface of the top dielectric layer and the top surface of the second through hole portion of the top metallization pattern, the second under bump metallization further being a distance from the under bump metallization starting from the center line of the integrated circuit chip, wherein a third distance is measured between an edge of the second under bump metallization closest to the center line of the integrated circuit chip and an edge of the second through hole portion closest to the center line of the integrated circuit die, wherein the third distance is greater than the first distance. In one embodiment, it further comprises a second under bump metallization extending along the top surface of the top dielectric layer and the top surface of the second through hole portion of the top metallization pattern, the second under bump metallization being further from the center line of the integrated circuit chip than the under bump metallization, wherein the third distance is measured between an edge of the second under bump metallization closest to the center line of the integrated circuit die and an edge of the second through hole portion closest to the center line of the integrated circuit die, wherein the third distance is equal to the first distance. In one embodiment, it further comprises a plurality of first under bump metallizations, wherein the first under bump metallization comprises the under bump metallization, and wherein the first under bump metallizations are uniformly spaced relative to each other in an area aligned with the sidewalls of the integrated circuit die. In one embodiment, a plurality of first under-bump metallizations are also included, wherein the first under-bump metallizations are disposed in a region aligned with a sidewall of the integrated circuit die, wherein the region includes a first portion surrounded by a second portion, and wherein a density of the first under-bump metallizations in the first portion is less than a density of the first under-bump metallizations in the second portion.In one embodiment, a plurality of first under bump metallizations are further included, wherein the first under bump metallizations are disposed in a region aligned with a sidewall of the integrated circuit die, and wherein the first under bump metallizations are uniformly distributed in the region.

[0060] According to another embodiment, a method includes forming an interconnect structure on a first carrier; bonding a first die to the interconnect structure; removing the first carrier from the interconnect structure, wherein after removing the first carrier, a first through-hole portion of a first metallization pattern of the interconnect structure opposite to the first die is exposed; and forming a first UBM above and in physical contact with the first through-hole portion, wherein a centerline of the first UBM is offset from a centerline of the first through-hole portion. In one embodiment, it also includes: forming a first plurality of UBMs and a second plurality of UBMs surrounding the plurality of first UBMs, wherein a density of the plurality of first UBMs is less than a density of the plurality of second UBMs, and wherein forming the first plurality of UBMs and the second plurality of UBMs includes forming the first UBM. In one embodiment, it also includes forming an underfill between the interconnect structure and each of the first die and the second die, the underfill extending to be flush with the top surface of the first die and the second die. In one embodiment, it also includes: forming an encapsulant around the first die, the second die, and the underfill; and planarizing the encapsulant, the underfill, the first chip, and the second chip. In one embodiment, further comprising forming a second UBM over and in physical contact with a second via portion of the first metallization pattern, wherein a distance between a centerline of the first UBM and a centerline of the first die in a first direction parallel to a major surface of the interconnect structure is less than a distance between a centerline of the second UBM and a centerline of the first die in the first direction, and wherein the centerline of the second UBM is offset from a centerline of the second via by a distance greater than a distance by which the centerline of the first UBM is offset from a centerline of the first via portion. In one embodiment, further comprising forming a second UBM over and in physical contact with a second via portion of the first metallization pattern, wherein a distance between a centerline of the first UBM and a centerline of the first die in a first direction parallel to a major surface of the interconnect structure is less than a distance between a centerline of the second UBM and a centerline of the first die in the first direction, and wherein the centerline of the second UBM is offset from a centerline of the second via by a distance equal to a distance by which the centerline of the first UBM is offset from a centerline of the first via portion.

[0061] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for realizing the same purpose of the embodiments introduced herein and / or realizing the same advantages thereof. Those skilled in the art will also appreciate that such equivalent structures do not deviate from the spirit and scope of the present invention, and they can make various changes, substitutions and changes in the present invention without deviating from the spirit and scope of the present invention.

Claims

1. A semiconductor device, comprising: a first integrated circuit die; an interconnect structure coupled to the first integrated circuit die, the interconnect structure comprising: a first metallization pattern including a first via portion extending through the first dielectric layer; a second dielectric layer located above the first dielectric layer opposite the first integrated circuit die; and a second metallization pattern coupled to the first metallization pattern, the second metallization pattern comprising a line portion in the first dielectric layer and a second via portion extending through the second dielectric layer; and an under bump metallization over the second metallization pattern and the second dielectric layer, the under bump metallization coupled to the second metallization pattern, wherein a first centerline of the first via portion and a second centerline of the second via portion are not aligned with a third centerline of the under bump metallization, wherein the first centerline and the second centerline are on opposite sides of the third centerline, The semiconductor device has a first point aligned with the center line of the first integrated circuit die, and as the distance from the first point increases, the offset or misalignment distance of the third center line of the under-bump metallization and the second center line of the second through-hole portion of the second metallization pattern increases. 2 . The semiconductor device of claim 1 , further comprising a conductive bump coupled to and in physical contact with the under bump metallization.

3. The semiconductor device of claim 1, further comprising a second integrated circuit die coupled to the interconnect structure, the first integrated circuit die comprising a system on a chip, the second integrated circuit die comprising a high bandwidth memory die.

4. The semiconductor device according to claim 1, wherein In a first direction parallel to the main surface of the second dielectric layer, a distance between the second center line and the third center line is 3 μm to 30 μm.

5. The semiconductor device according to claim 1, wherein The under bump metallization is disposed in a first region having a boundary aligned with a sidewall of the first integrated circuit die, wherein the third centerline is closer to a fourth centerline of the first region than the second centerline.

6. The semiconductor device according to claim 5, further comprising a second under bump metallization, wherein The second metallization pattern further includes a third via portion extending through the second dielectric layer, the third via portion coupled to the second under bump metallization, wherein a fifth centerline of the second under bump metallization is disposed farther from the fourth centerline of the first region than the third centerline of the under bump metallization, wherein a first distance between the second centerline and the third centerline in a first direction parallel to a major surface of the second dielectric layer is less than a second distance between the fifth centerline and a sixth centerline of the third via portion in the first direction.

7. The semiconductor device according to claim 5, further comprising a second under bump metallization, wherein The second metallization pattern also includes a third via portion extending through the second dielectric layer, the third via portion coupled to the second under bump metallization, wherein a fifth centerline of the second under bump metallization is disposed farther away from the fourth centerline of the first region than the third centerline of the under bump metallization, wherein a first distance between the second centerline and the third centerline in a first direction parallel to a major surface of the second dielectric layer is equal to a second distance between the fifth centerline and a sixth centerline of the third via portion in the first direction.

8. A semiconductor device comprising: An integrated circuit die coupled to an interconnect structure, the interconnect structure comprising: one or more metallization patterns disposed in one or more dielectric layers; a top dielectric layer over the one or more metallization patterns and the one or more dielectric layers; and a top metallization pattern electrically coupled to the one or more metallization patterns, wherein the top metallization pattern includes a via portion extending through the top dielectric layer, wherein a top surface of the via portion is flush with a top surface of the top dielectric layer; an under bump metallization extending along the top surface of the top dielectric layer and the top surface of the via portion of the top metallization pattern, wherein a first distance is measured between an edge of the under bump metallization closest to a centerline of the integrated circuit die and an edge of the via portion closest to the centerline of the integrated circuit die, wherein a second distance is measured between an edge of the under bump metallization farthest from the centerline of the integrated circuit die and an edge of the via portion farthest from the centerline of the integrated circuit die, and wherein a first difference between the first distance and the second distance is positive; a conductive contact coupled to the under-bump metallization, The semiconductor device has a first point aligned with the centerline of the integrated circuit die, and as the distance from the first point increases, the centerline of the under-bump metallization is offset or misaligned with the centerline of the through-hole portion of the top metallization pattern by an increasing distance.

9. The semiconductor device according to claim 8, wherein: The integrated circuit die comprises a system-on-chip die.

10. The semiconductor device of claim 8 , further comprising a second under bump metallization extending along the top surface of the top dielectric layer and a top surface of a second via portion of the top metallization pattern, the second under bump metallization being further from a centerline of the integrated circuit die than the first under bump metallization, wherein A third distance is measured between an edge of the second under bump metallization closest to the centerline of the integrated circuit die and an edge of the second via portion closest to the centerline of the integrated circuit die, wherein the third distance is greater than the first distance.

11. The semiconductor device of claim 8 , further comprising a second under bump metallization extending along the top surface of the top dielectric layer and a top surface of a second via portion of the top metallization pattern, the second under bump metallization being further from the centerline of the integrated circuit die than the under bump metallization, wherein A third distance is measured between an edge of the second under bump metallization closest to the centerline of the integrated circuit die and an edge of the second via portion closest to the centerline of the integrated circuit die, wherein the third distance is equal to the first distance.

12. The semiconductor device according to claim 8, further comprising a plurality of first under bump metallizations, wherein: The first under bump metallizations include the under bump metallizations, and wherein the first under bump metallizations are evenly spaced relative to each other in a region aligned with a sidewall of the integrated circuit die.

13. The semiconductor device according to claim 8, further comprising a plurality of first under bump metallizations, wherein: The first under bump metallization is disposed in a region aligned with a sidewall of the integrated circuit die, wherein the region includes a first portion surrounded by a second portion, and wherein a density of the first under bump metallization in the first portion is less than a density of the first under bump metallization in the second portion.

14. The semiconductor device according to claim 8, further comprising a plurality of first under bump metallizations, wherein: The first under bump metallization is disposed in a region aligned with a sidewall of the integrated circuit die, and wherein the first under bump metallization is uniformly distributed in the region.

15. A method for manufacturing a semiconductor device, comprising: forming an interconnect structure on a first carrier; bonding a first die to the interconnect structure; removing the first carrier from the interconnect structure, wherein after removing the first carrier, a first through-hole portion of a first metallization pattern of the interconnect structure opposite to the first die is exposed; and forming a first under bump metallization over and in physical contact with the first via portion, wherein a centerline of the first under bump metallization is offset from a centerline of the first via portion, The semiconductor device has a first point aligned with a centerline of the first die, and a centerline of the first under bump metallization is offset or misaligned with a centerline of the first via portion by an increasing distance from the first point.

16. The method according to claim 15, further comprising: Forming a first plurality of under bump metallizations and a second plurality of under bump metallizations surrounding the first plurality of under bump metallizations, wherein a density of the first plurality of under bump metallizations is less than a density of the second plurality of under bump metallizations, and wherein forming the first plurality of under bump metallizations and the second plurality of under bump metallizations includes forming the first under bump metallization. 17 . The method of claim 16 , further comprising forming an underfill between the interconnect structure and each of the first and second dies, the underfill extending to be flush with top surfaces of the first and second dies.

18. The method according to claim 17, further comprising: forming an encapsulant around the first die, the second die, and the underfill; and The encapsulant, the underfill, the first die, and the second die are planarized.

19. The method of claim 15, further comprising forming a second under bump metallization over and in physical contact with a second via portion of the first metallization pattern, wherein A distance between a center line of the first under-bump metallization and a center line of the first die in a first direction parallel to a major surface of the interconnect structure is smaller than a distance between a center line of the second under-bump metallization and the center line of the first die in the first direction, and wherein a distance by which the center line of the second under-bump metallization deviates from a center line of the second through hole is greater than a distance by which the center line of the first under-bump metallization deviates from a center line of the first through hole portion.

20. The method of claim 15, further comprising forming a second under bump metallization over and in physical contact with a second via portion of the first metallization pattern, wherein A distance between a center line of the first under-bump metallization and a center line of the first die in a first direction parallel to a major surface of the interconnect structure is less than a distance between a center line of the second under-bump metallization and a center line of the first die in the first direction, and wherein a distance by which the center line of the second under-bump metallization deviates from a center line of the second through hole is equal to a distance by which the center line of the first under-bump metallization deviates from a center line of the first through hole portion.

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