Semiconductor device and method of manufacturing the same

Abstract

A semiconductor device having contact structures with different configurations and a method of manufacturing the same are disclosed. The semiconductor device includes: a substrate; a fin structure disposed on the substrate; a gate structure disposed on the fin structure; source / drain (S / D) regions disposed adjacent to the gate structure; a contact structure disposed on the S / D regions; and a dipole layer disposed at an interface between a ternary compound layer and the S / D regions. The contact structure includes a ternary compound layer disposed on the S / D regions, a work function metal (WFM) silicide layer disposed on the ternary compound layer, and a contact plug disposed on the WFM silicide layer.

Description

Technical Field

[0001] Embodiments of the present invention relate to semiconductor devices and methods of manufacturing the same. Background Art

[0002] With the progress of semiconductor technology, the demand for higher storage capacity, faster processing systems, higher performance, and lower cost is continuously increasing. To meet these demands, the semiconductor industry continues to scale down the size of semiconductor devices, such as metal-oxide-semiconductor field-effect transistors (MOSFETs) including planar MOSFETs and fin field-effect transistors (finFETs). This scaling down increases the complexity of semiconductor manufacturing processes. Summary of the Invention

[0003] Embodiments of the present invention provide a semiconductor device, including: a substrate; a fin structure disposed on the substrate; a gate structure disposed on the fin structure; a source / drain (S / D) region adjacent to the gate structure; a contact structure disposed on the source / drain region, wherein the contact structure includes a ternary compound layer disposed on the source / drain region, a work function metal (WFM) silicide layer disposed on the ternary compound layer, and a contact plug disposed on the work function metal silicide layer; and a dipole layer disposed at an interface between the ternary compound layer and the source / drain region.

[0004] Another embodiment of the present invention provides a semiconductor device, including: a gate structure disposed on a first fin structure and a second fin structure; a merged source / drain (S / D) region disposed on the first fin structure and the second fin structure; and a contact structure disposed on the merged source / drain region, wherein the contact structure includes a ternary compound cluster disposed on the merged source / drain region, a work function metal (WFM) silicide layer disposed on the ternary compound cluster and the merged source / drain region, and a contact plug disposed on the work function metal silicide layer.

[0005] Yet another embodiment of the present invention provides a method of manufacturing a semiconductor device, including: forming a fin structure on a substrate; forming a source / drain (S / D) region on the fin structure; forming a contact opening in the source / drain region; forming a doped work function metal (nWFM) silicide layer in the contact opening; forming a ternary compound layer between the doped work function metal silicide layer and the source / drain region; and forming a contact plug in the contact opening. Brief Description of the Drawings

[0006] As will be best understood from the following detailed description when read in conjunction with the accompanying drawings.

[0007] Figures 1A to 1I An isometric view and a cross-sectional view of a semiconductor device according to some embodiments are shown.

[0008] Figures 1J to 1L Device characteristics of a semiconductor device having a contact structure according to some embodiments are shown.

[0009] Figures 2A to 2E An isometric view and a cross-sectional view of a semiconductor device according to some embodiments are shown.

[0010] Figures 3A to 3G An isometric view and a cross-sectional view of a semiconductor device according to some embodiments are shown.

[0011] Figures 4A to 4C An isometric view and a cross-sectional view of a semiconductor device according to some embodiments are shown.

[0012] Figure 5 A flowchart of a method for manufacturing a semiconductor device having a contact structure according to some embodiments is shown.

[0013] Figures 6A to 17B Cross-sectional views of a semiconductor device having a contact structure at various stages of a manufacturing process according to some embodiments are shown.

[0014] Exemplary embodiments will now be described with reference to the accompanying drawings. In the drawings, like reference numerals generally denote identical, functionally similar, and / or structurally similar elements. Unless otherwise noted, discussions of elements with the same reference numerals apply to each other. Detailed Description

[0015] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include embodiments where the first component and the second component are formed in direct contact, and may also include embodiments where additional components may be formed between the first component and the second component such that the first component and the second component may not be in direct contact. As used herein, forming a first component on a second component means that the first component is formed in direct contact with the second component. Additionally, the present invention may repeat reference numerals and / or letters in various examples. This repetition itself does not denote a relationship between the embodiments and / or examples discussed herein.

[0016] In addition, for ease of description, spatial relative terms such as "below", "beneath", "lower", "above", "upper", etc. may be used herein to describe the relationship of one element or component to another as shown in the figures. In addition to the orientation shown in the figures, spatial relative terms are intended to encompass different orientations of the device during use or operation. The device may be positioned in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein may be interpreted accordingly.

[0017] Note that references in the specification to "one embodiment", "an embodiment", "example embodiment", "exemplary", etc. mean that the described embodiment may include a particular component, structure, or characteristic, but not every embodiment necessarily includes the particular component, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. In addition, when a particular component, structure, or characteristic is described in connection with an embodiment, implementation of such component, structure, or characteristic in connection with other embodiments is within the knowledge of those skilled in the art, whether or not explicitly described.

[0018] It should be understood that the words or terms herein are for the purpose of description and not limitation, such that the terms or phrases of this specification will be interpreted by those skilled in the relevant art in accordance with the teachings herein.

[0019] In some embodiments, the terms "about" and "substantially" may denote a value of a given quantity that varies within 5% of that value (e.g., ±1%, ±2%, ±3%, ±4%, ±5% of the value). These values are merely examples and are not intended to be limiting. The terms "about" and "substantially" may refer to a percentage of the value that is interpreted by those skilled in the art in accordance with the teachings herein.

[0020] The fin structures disclosed herein may be patterned by any suitable method. For example, one or more lithography processes may be used to pattern the fin structures, and the lithography processes include double patterning processes or multiple patterning processes. Double patterning or multiple patterning processes may combine lithography and self-alignment processes, allowing the creation of patterns with, for example, a pitch smaller than that achievable using a single direct lithography process. For example, a sacrificial layer is formed over the substrate and the sacrificial layer is patterned using a lithography process. A spacer is formed adjacent to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacer may then be used to pattern the fin structures.

[0021] The present invention provides exemplary structures and methods for reducing the contact resistance between the source / drain (S / D) regions of a FET (such as a finFET, a gate-all-around (GAA) FET, etc.) and the S / D contact structure. The contact resistance between the S / D region and the S / D contact structure is proportional to the Schottky barrier height (SBH) between the material of the S / D region and the silicide layer of the S / D contact structure. Reducing the difference between the work function values of the silicide layer and the material of the S / D region can reduce the SBH between the S / D region and the S / D contact structure. In some embodiments, since the S / D regions of NFETs and PFETs are formed of corresponding n-type and p-type materials, the S / D contact structures of NFETs and PFETs are formed of different silicide layers to reduce the contact resistance between the S / D contact structure and the different materials of the S / D region.

[0022] In some embodiments, a dipole layer and / or a ternary compound layer can be formed at the interface between the S / D region and the silicide layer to further reduce the SBH between the S / D region and the S / D contact structure. The dipole layer and / or the ternary compound layer can be formed by doping the silicide layer with a metal having an electronegativity value lower than that of the metal of the silicide layer. The metal dopant can cause the formation of a dipole between the metal dopant and the semiconductor element of the S / D region. The metal dopant can also cause the formation of a ternary compound between the metal dopant, the metal of the silicide layer, and the semiconductor element of the S / D region. The formation of such an interface dipole layer and / or ternary compound layer can reduce the contact resistance of the FET by about 50% to about 70% compared to a FET without an interface dipole layer and / or ternary compound layer, and thus improve the performance of the FET.

[0023] Figure 1A An isometric view of a FET 100 according to some embodiments is shown. According to some embodiments, as Figures 1B to 1I shown, the FET 100 can have different cross-sectional views. Figure 1B 、 Figure 1D 、 Figure 1F and Figure 1H show cross-sectional views of the FET 100 along line A-A, and Figure 1C 、 Figure 1E 、 Figure 1G and Figure 1I show cross-sectional views of the FET 100 along line Figure 1A B-B. Additional structures are not shown in Figure 1A for simplicity. Cross-sectional views are shown for illustrative purposes in Figures 1B to 1I and may not be drawn to scale. Figures 1J to 1K shows the concentration profiles along lines C-C and D-D of Figures 1B to 1I . Unless otherwise specified, elements with the same reference numerals Figures 1A to 1LThe discussions of the components in [the context] apply to each other. In some embodiments, unless otherwise specified, FET 100 can represent an n-type FET 100 (NFET 100) or a p-type FET 100 (PFET 100), and the discussion of FET 100 applies to both NFET 100 and PFET 100.

[0024] Referring Figure 1A , FET 100 can include an array of gate structures 112 disposed on fin structures 106 and an array of S / D regions 110 disposed on portions of the fin structures 106 not covered by the gate structures 112 ( Figure 1A one of the S / D regions 110 visible in [the figure]). FET 100 can also include gate spacers 114, shallow trench isolation (STI) regions 116, an etch stop layer (ESL) 117, and interlayer dielectric (ILD) layers 118A - 118B (for simplicity, ILD layer 118B is not shown in Figure 1A ; shown in Figures 1B to 1E ). ILD layer 118A can be disposed on ESL 117. ESL 117 can be configured to protect the gate structure 112 and / or the S / D regions 110. In some embodiments, the gate spacers 114, STI regions 116, ESL 117, and ILD layers 118A - 118B can include insulating materials such as silicon oxide, silicon nitride (SiN), silicon carbonitride (SiCN), silicon oxynitride (SiOCN), and silicon germanium oxide. In some embodiments, the gate spacers 114 can have a thickness of about 2 nm to about 9 nm to sufficiently electrically isolate the gate structure 112 from adjacent structures.

[0025] FET 100 can be formed on a substrate 104. Other FETs and / or structures (e.g., isolation structures) can be formed on the substrate 104. The substrate 104 can be a semiconductor material such as silicon, germanium (Ge), silicon germanium (SiGe), silicon-on-insulator (SOI) structures, and combinations thereof. Additionally, the substrate 104 can be doped with p-type dopants (e.g., boron, indium, aluminum, or gallium) or n-type dopants (e.g., phosphorus or arsenic). In some embodiments, the fin structures 106 can include a material similar to the substrate 104 and extend along the X-axis.

[0026] Referring Figures 1B to 1C, the FET 100 may include a gate structure 112, S / D regions 110, and an S / D contact structure 120 disposed on the S / D regions 110. The gate structure 112 may be a multi-layer structure. Each gate structure 112 may include an interface oxide (IO) layer 122, a high-k (HK) gate dielectric layer 124 disposed on the IO layer 122, a work function metal (WFM) layer 126 disposed on the HK gate dielectric layer 124, a gate metal fill layer 128 disposed on the WFM layer 126, and a gate capping layer 130 disposed on the HK gate dielectric layer 124, the WFM layer 126, and the gate metal fill layer 128.

[0027] The IO layer 122 may include silicon oxide (SiO2), silicon germanium oxide (SiGeO x ), or germanium oxide (GeO x ). The HK gate dielectric layer 124 may include a high-k dielectric material such as hafnium oxide (HfO2), titanium oxide (TiO2), hafnium zirconium oxide (HfZrO), tantalum oxide (Ta2O3), hafnium silicate (HfSiO4), zirconium oxide (ZrO2), and zirconium silicate (ZrSiO2). For the NFET 100, the WFM layer 126 of the gate structure 112 may include titanium aluminum (TiAl), titanium aluminum carbide (TiAlC), tantalum aluminum (TaAl), tantalum aluminum carbide (TaAlC), Al-doped Ti, Al-doped TiN, Al-doped Ta, Al-doped TaN, other suitable Al-based materials, or combinations thereof. For the PFET 100, the WFM layer 126 of the gate structure 112 may include a Ti-based or Ta-based nitride or alloy substantially free of Al (e.g., Al-free), such as titanium nitride (TiN), titanium silicon nitride (TiSiN), titanium gold (Ti-Au) alloy, titanium copper (Ti-Cu) alloy, tantalum nitride (TaN), tantalum silicon nitride (TaSiN), tantalum gold (Ta-Au) alloy, tantalum copper (Ta-Cu), and combinations thereof. The gate metal fill layer 128 may include a suitable conductive material such as tungsten (W), titanium, silver (Ag), ruthenium (Ru), molybdenum (Mo), copper (Cu), cobalt (Co), Al, iridium (Ir), nickel (Ni), metal alloys, and combinations thereof. In some embodiments, the gate structure 112 may be electrically isolated from the overlying interconnect structure (not shown) by the gate capping layer 130, which may include a nitride layer.

[0028] For the NFET 100, each S / D region 110 may include an epitaxially grown semiconductor material (such as Si) and an n-type dopant (such as phosphorus and other suitable n-type dopants). For the PFET 100, each S / D region 110 may include an epitaxially grown semiconductor material (such as Si or SiGe) and a p-type dopant (such as boron and other suitable p-type dopants).

[0029] The S / D contact structure 120 is disposed on the S / D region 110. In some embodiments, the S / D contact structure 120 may include (i) a WFM silicide layer 132 disposed on the S / D region 110, (ii) a nitride capping layer 136 disposed on the WFM silicide layer 132, (iii) a contact plug 134 disposed on the nitride capping layer 136, (iv) a stack of metal-based liners 135 disposed on the sidewalls of the nitride capping layer 136, and (v) a barrier layer 142 disposed on the stack of metal-based liners 135. The FET 100 further includes a dipole layer 144 at the interface (also referred to herein as "interface 132-110") between the WFM silicide layer 132 and the S / D region 110. In some embodiments, the interface 132-110 may be disposed within the S / D region 110 and may be non-coplanar with the surface 110s of the S / D region 110.

[0030] In some embodiments, the top surface of the WFM silicide layer 132 may be above the surface 110s (as shown in Figures 1B to 1C ), or may be substantially coplanar with the surface 110s (not shown). In some embodiments, as shown in Figure 1C , the WFM silicide layer 132 may form angles A and B with the stack of metal-based liners 135. Angles A and B may be similar or different from each other and may be in the range of about 45 degrees to about 60 degrees. In some embodiments, for the NFET 100, the WFM silicide layer 132 may include a metal or metal silicide having a work function value closer to the conduction band edge energy than the valence band edge energy of the material of the S / D region 110. For example, the work function value of the metal or metal silicide may be less than 4.5 eV (e.g., about 3.5 eV to about 4.4 eV), which may be closer to the conduction band energy (e.g., 4.1 eV for Si) than the valence band energy of the silicon-based material of the S / D region 110 (e.g., 5.2 eV for silicon). In certain embodiments, for the NFET 100, the metal silicide of the WFM silicide layer 132 may include titanium silicide (Ti x Si y ), tantalum silicide (Ta x Si y ), molybdenum silicide (Mo x Si y ), zirconium silicide (Zr x Si y ), hafnium silicide (Hf x Si y ), scandium silicide (Sc x Si y ), yttrium silicide (Y x Si y), terbium silicide (Tb x Si y ), lutetium silicide (Lu x Si y ), erbium silicide (Er x Si y ), ytterbium silicide (Yb x Si y ), europium silicide (Eu x Si y ), thorium silicide (Th x Si y ), or a combination thereof.

[0031] In some embodiments, for PFET 100, the WFM silicide layer 132 may include a metal or metal silicide having a work function value closer to the valence band edge energy than the conduction band edge energy of the material of the S / D region 110. For example, the metal or metal silicide may have a work function value greater than 4.5 eV (e.g., about 4.5 eV to about 5.5 eV), which may be closer to the valence band energy (e.g., 5.2 eV for Si) than the conduction band energy of the Si-based material of the S / D region 110 (e.g., 4.1 eV for Si). In some embodiments, for PFET 100, the metal silicide of the WFM silicide layer 132 may include nickel silicide (Ni x Si y ), cobalt silicide (Co x Si y ), manganese silicide (Mn x Si y ), tungsten silicide (W x Si y ), iron silicide (Fe x Si y ), rhodium silicide (Rh x Si y ), palladium silicide (Pd x Si y ), ruthenium silicide (Ru x Si y ), platinum silicide (Pt x Si y ), iridium silicide (Ir x Si y ), osmium silicide (Os x Si y ), or a combination thereof.

[0032] In some embodiments, the WFM silicide layer 132 may further include a dopant of a transition metal, and the electronegativity value of the dopant of the transition metal is less than the electronegativity value of the metal of the metal silicide included in the WFM silicide layer 132. For example, the dopant may include a transition metal such as zirconium (Zr), hafnium (Hf), ytterbium (Yb), yttrium (Y), erbium (Er), cerium (Ce), scandium (Sc), and combinations thereof. In some embodiments, some of the dopants may diffuse into the S / D regions 110. The dopant may cause the formation of charged dipoles in the dipole layer 144 at the interface 132-110. The dipole layer 144 may include charged dipoles of silicon ions from the S / D regions 110 and transition metal ions of the dopants in the WFM silicide layer 132. For example, when the WFM silicide layer 132 includes a Zr, Hf, Yb, Y, Er, Ce, or Sc dopant, the dipole layer 144 may include Zr-Si, Hf-Si, Yb-Si, Y-Si, Er-Si, Ce-Si, or Sc-Si dipoles.

[0033] The electric field generated by the dipoles in the dipole layer 144 at the interface 132-110 may reduce the SBH between the WFM silicide layer 132 and the S / D regions 110, and thus reduce the contact resistance between the S / D contact structure 120 and the S / D regions 110. Based on the type and concentration of the dipoles in the dipole layer 144 at the interface 132-110, the SBH between the WFM silicide layer 132 and the S / D regions 110 may be reduced by about 35% to 70% compared to the SBH between the WFM silicide layer 132 and the S / D regions 110 without the dipole layer 144. In some embodiments, the SBH may be in the range from about 0.2 eV to about 0.4 eV. The concentration of the dipoles at the interface 132-110 is proportional to the concentration of the dopants in the WFM silicide layer 132 and / or at the interface 132-110. The concentration of the dopants in the WFM silicide layer 132 and / or at the interface 132-110 may be in the range from about 1 atomic percent to about 10 atomic percent. A dopant concentration below this range may not cause the formation of dipoles in the dipole layer 144. On the other hand, if the dopant concentration is higher than this range, the duration and complexity of the doping process increase, and thus the device manufacturing cost increases.

[0034] According to some embodiments, as Figure 1J shown, the dopant concentration may be along Figure 1B and Figure 1CThe line C-C has profiles 146, 148, and / or 150 over the WFM silicide layer 132 and the S / D regions 110. As described in detail below, when the WFM silicide layer 132 is doped with a transition metal (e.g., Zr, Hf, etc.) in a doping process that does not include a high-temperature (e.g., a temperature greater than 500 °C) annealing process, the dopant concentration can have a profile 146 with a peak dopant concentration C1 at the interface 132-110. When the WFM silicide layer 132 is doped with a non-Zr-based transition metal (e.g., Hf, Ce, Er, etc.) in a doping process that does not include a high-temperature annealing process, the dopant concentration can have a profile 148. The thermodynamic stability of the non-Zr-based transition dopant at the interface 132-110 is lower than that of the Zr dopant, which may cause a larger amount of the non-Zr-based transition dopant to diffuse from the interface 132-110 and into the WFM silicide layer 132. As a result, as Figure 1J shown, the peak dopant concentration of the profile 148 can be at a distance D1 (e.g., from about 0.1 nm to about 0.5 nm) from the interface 132-110, and can have a dopant concentration C2 at the interface 132-110, where the dopant concentration C2 is less than the peak dopant concentration C1.

[0035] In some embodiments, as Figure 1J shown, when the doping of the WFM silicide layer 132 includes a high-temperature annealing process, due to the lower thermodynamic stability of the dopant at the interface 132-110, the non-Zr-based dopant can further diffuse into the WFM silicide layer 132 and can have a dopant concentration profile 150. The peak dopant concentration of the profile 150 can be at a distance D2 (e.g., from about 0.2 nm to about 0.8 nm) from the interface 132-110, where the distance D2 is greater than the distance D1, and can have a dopant concentration C3 at the interface 132-110, where the dopant concentration C3 is less than the dopant concentration C2. Since the concentration of the dopant at the interface 132-110 is proportional to the concentration of the dipoles at the interface 132-110, the dipole concentration in the dipole layer 144 of the profile 146 can be greater than the dipole concentration in the dipole layer 144 of the profiles 148 and 150, and the dipole concentration in the dipole layer 144 of the profile 148 can be greater than the dipole concentration in the dipole layer 144 of the profile 150. As a result, the SBH between the WFM silicide layer 132 and the S / D regions 110 of the profile 146 can be lower than the SBH between the WFM silicide layer 132 and the S / D regions 110 of the profiles 148 and 150, and the SBH between the WFM silicide layer 132 and the S / D regions 110 of the profile 148 can be lower than the SBH between the WFM silicide layer 132 and the S / D regions 110 of the profile 150. In some embodiments, along Figures 1B to 1CThe dopant concentration of the line C-C may have distributions 146 and 148, or may have distributions 146 and 150 when the WFM silicide layer 132 is doped with a combination of Zr metal and one or more non-Zr-based transition metals.

[0036] Reference Figures 1B to 1C , the contact plug 134 may include a conductive material such as cobalt (Co), tungsten (W), ruthenium (Ru), iridium (Ir), nickel (Ni), osmium (Os), rhodium (Rh), aluminum (Al), molybdenum (Mo), copper (Cu), zirconium (Zr), tin (Sn), silver (Ag), gold (Au), zinc (Zn), cadmium (Cd), and combinations thereof. The nitride capping layer 136 may be formed to protect the underlying layer (e.g., the WFM silicide layer 132) during subsequent processing of the S / D contact structure 120. The stack of the metal-based liner 135 may include a first liner 138 and a second liner 140. As described in detail below, the first liner 138 may be part of the source layer for forming the WFM silicide layer 132 and may include the metal of the WFM silicide layer 132 or may include an oxide of the metal of the WFM silicide layer 132. As described in detail below, the second liner 140 may be part of the source for doping the WFM silicide layer 132 and may include a transition metal of the dopant in the WFM silicide layer 132 or may include an oxide of the metal of the dopant. In some embodiments, the first liner 138 and / or the second liner 140 may not be present in the stack of the metal-based liner 135, or the stack of the metal-based liner 135 may not be present in the S / D contact structure 120 (as Figures 17A to 17B shown). The barrier layer 142 may include a nitride material and may reduce or prevent oxygen atoms from diffusing from the ILD layers 118A-118B into the contact plug 134 to prevent oxidation of the conductive material of the contact plug 134.

[0037] In some embodiments, when the WFM silicide layer 132 is doped with Zr metal in a doping process including a high-temperature annealing process, the S / D contact structure 120 may have a cross-sectional view as Figures 1D to 1I shown. Figures 1D to 1E A cross-sectional view along the line B-B of Figure 1A is shown, and additional structures are not shown in Figure 1A for simplicity. The S / D contact structure 120 may include a Zr-based ternary compound (ZTC) layer 133 between the WFM silicide layer 132 and the S / D region 110. The Zr dopant of the WFM silicide layer 132 may interact with the Si atoms of the S / D region 110 and the metal atoms of the WFM silicide layer 132 during the high-temperature annealing process to form the ZTC layer 133. The ZTC layer 133 may include zirconium metal silicide (Zr x My Si z ), wherein the metal (M) is the metal of the WFM silicide layer 132. In some embodiments, when the WFM silicide layer 132 comprises Ti x Si y When, the ZTC layer 133 may comprise zirconium titanium silicide (Zr3Ti2Si3). The ZTC layer 133 may cause the formation of a dipole layer 145 at the interface between the ZTC layer 133 and the S / D region 110 (also referred to herein as "interface 133-110"). The dipole layer 145 may comprise Zr-Si dipoles of Zr metal ions from the ZTC layer 133 and silicon ions from the S / D region 110.

[0038] Similar to the dipole layer 144, the electric field generated by the dipole layer 145 at the interface 133-110 may reduce the SBH between the WFM silicide layer 132 and the S / D region 110 by about 35% to about 70%, and thus reduce the contact resistance between the S / D contact structure 120 and the S / D region 110. The concentration of Zr atoms in the ZTC layer 133 may be in the range of about 1 atomic percentage to about 10 atomic percentages. In some embodiments, as Figure 1K shown, the Zr atoms may have a concentration profile 158 along Figures 1D to 1E the line D-D over the WFM silicide layer 132, the ZTC layer 133, and the S / D region 110.

[0039] Figures 1F to 1G Shows Figures 1D to 1E An enlarged view of the S / D region 110, the WFM silicide layer 132, and the ZTC layer 133. In some embodiments, when formed on the S / D region 110 having a (111) crystal orientation (also referred to as a (111) crystal plane) of the surface 110s-110t, the ZTC layer 133 may have a top surface 133s with a (1121) crystal orientation (also referred to as a (1121) crystal plane). The surface 110s may be the top surface of the S / D region 110, and the surface 110t may be the surface that forms an interface with the ZTC layer 133. As Figures 1A to 1E shown, when the semiconductor material of the S / D region 110 is epitaxially grown on the top surface 106s of the fin structure 106 in a bottom-up manner, the surface 110s-110t may have a (111) crystal orientation and not as described in the following reference Figures 3A to 3Cepitaxially grown as a cladding around the fin structure 106 as described above. To have a (111) crystal orientation, the surface 110s can be formed at angles C and D with respect to a horizontal axis (e.g., the X axis), where the angles C and D are in the range of about 50 degrees to about 60 degrees. The angles C and D can be equal to or different from each other. In some embodiments, the surface of the ZTC layer 133 facing the WFM silicide layer 132 and the S / D region 110 can be a non-faceted surface, which is contrary to the ZTC layer 333 described below with reference to Figures 3C to 3G and Figure 4C . Due to the different crystal orientations between the surfaces 110s - 110t and 133s, there can be a lattice mismatch in the range of about 0.5% to about 1% between the S / D region 110 and the ZTC layer 133. In some embodiments, when the S / D region 110 includes Si material and the ZTC layer 133 includes Zr3Ti2Si3, the lattice mismatch can be about 0.7%. For different crystal orientations of the S / D region 110 and the ZTC layer 133, the lattice mismatch can be different, as described below with reference to Figures 3A to 3C . In some embodiments, as shown in Figures 1D to 1G , the interface 133 - 110 can be disposed within the S / D region 110 and is non-coplanar with the surface 110s of the S / D region 110.

[0040] In some embodiments, to sufficiently reduce the SBH between the S / D region 110 and the WFM silicide layer 132 (e.g., the SBH is in the range of about 0.2 eV to about 0.4 eV), the ZTC layer 133 can have a thickness T1 along the Z axis, where the thickness T1 is in the range of about 0.25 nm to about 1 nm, and the WFM silicide layer 132 can have a thickness T2 along the Z axis, where the thickness T2 is in the range of about 2 nm to about 6 nm, and the thickness T2 is greater than the thickness T1. The ratio of T1∶T2 can be in the range of about 1∶2 to about 1∶20 to achieve an SBH in the range of about 0.2 eV to 0.4 eV between the S / D region 110 and the WFM silicide layer 132. The thickness T1 can depend on the concentration of Zr dopant in the WFM silicide layer 132 before forming the ZTC layer 133. The relationship between the thickness T1 and the Zr dopant concentration in the WFM silicide layer can be represented by the graph of Figure 1L . In some embodiments, the thickness T1 can be proportional to the Zr dopant concentration in the WFM silicide layer 132, which is in the range from about 1 atomic percentage to about 10 atomic percentage, and can be independent of the Zr dopant concentration in the WFM silicide layer 132 above 10 atomic percentage. In some embodiments, the top surface 133s of the ZTC layer 133 converges at an angle E, and the angle E can be equal to or less than the angles C and / or D.

[0041] In some embodiments, instead of asFigures 1D to 1G The illustrated ZTC layer 133 is a continuous layer, as Figures 1H to 1I shown, the ZTC layer 133 can be a discontinuous layer. Unless otherwise specified, the discussion of the continuous ZTC layer 133 applies to the discontinuous ZTC layer 133. The discontinuity in the ZTC layer 133 can be caused by the lattice mismatch between the S / D region 110 and the ZTC layer 133. In some embodiments, adjacent portions of the discontinuous ZTC layer 133 can be separated from each other by a distance D3 in the range of about 0.05 nm to about 1 nm to effectively reduce the SBH between the WFM silicide layer 132 and the S / D region 110. In some embodiments, the interface between the WFM silicide layer 132 and the S / D region 110 (also referred to herein as "interface 132-110") (disposed within adjacent portions of the discontinuous ZTC layer 133) can be located at a surface plane below the top surface 133s ( Figures 1H to 1I as shown), or can be coplanar with the top surface 133s (not shown). In some embodiments, the interface between the WFM silicide layer 132 and the ZTC layer 133 (also referred to herein as "interface 132-133") can be located at a surface plane above (as shown in Figures 1D to 1I ) or below (not shown) the surface 110s, or can be coplanar with the surface 110s (not shown).

[0042] Figure 2A An isometric view of a FET 200 according to some embodiments is shown. Unless otherwise specified, the discussion of the FET100 applies to the FET 200. According to some embodiments, as Figures 2B to 2E shown, the FET 200 can have different cross-sectional views. Figures 2B to 2E shows a cross-sectional view of the FET 200 along the line E-E of Figure 2A , with additional structures not shown in Figure 2A for simplicity. A cross-sectional view of Figures 2B to 2E is shown for illustrative purposes and is not drawn to scale. Unless otherwise specified, the discussion of the elements with the same reference numerals in Figures 1A to 1L and Figures 2A to 2E applies to each other.

[0043] Referring to Figure 2A , the FET 200 can have merged S / D regions 210 disposed on the fin structure 106. Unless otherwise specified, the discussion of the S / D region 110 applies to the merged S / D regions 210. Referring to Figure 2B , the FET 200 can include an S / D structure 120 disposed on the merged S / D regions 210. In some embodiments, the top surface of the WFM silicide layer 132 can be above the surface 210s (as shown in Figure 2B) or may be substantially coplanar with surface 210s (not shown). In some embodiments, Figure 2B As shown, the WFM silicide layer 132 can form angles F and G with the stack of metal-based pads 135. Angles F and G can be similar or different from each other and can be in a range of about 135 degrees to about 155 degrees. The dopant of the WFM silicide layer 132 can cause the formation of a dipole layer 144 at the interface between the WFM silicide layer 132 and the merged S / D region 210 (also referred to herein as "interface 132-210"). In some embodiments, the interface 132-210 can be disposed within the S / D region 210 and can be non-coplanar with the surface 210s of the merged S / D region 210. Along Figure 1C The discussion of the dopant concentration profile of line CC applies to Figure 2B Line CC.

[0044] In some embodiments, when the S / D structure 120 includes a ZTC layer 133 disposed on the merged S / D region 210, the S / D contact structure 120 may have a Figure 2C The cross-sectional view shown. Figure 1E The discussion of the dopant concentration profile of line DD applies to Figure 2C Line DD. Figure 2D Shows Figure 2B 1 is an enlarged view of the merged S / D region 210, the WFM silicide layer 132, and the ZTC layer 133. Similar to the S / D region 110, the surfaces 210s-210t of the merged S / D region 210 may have a (111) crystal orientation because the semiconductor material of the merged S / D region 210 is epitaxially grown on the top surface 106s of the fin structure 106 in a bottom-up manner (e.g., Figure 2C As a result, when the ZTC layer 133 is formed on the merged S / D region 210 of the surfaces 210s-210t having the (111) crystal orientation, the ZTC layer 133 may have a top surface 133s having a (1121) crystal orientation. The surface 210s may be the top surface of the S / D region 210, and the surface 210t may be a surface forming an interface with the ZTC layer 133.

[0045] In order to have a (111) crystal orientation, the surface 210s may be formed at angles C and D relative to a horizontal axis (e.g., an X-axis), wherein the angles C and D are in a range of about 50 degrees to about 60 degrees. The angles C and D may be equal to or different from each other. A lattice mismatch of about 0.5% to about 1% may exist between the merged S / D region 210 and the ZTC layer 133. In some embodiments, when the merged S / D region 210 includes a Si material and the ZTC layer 133 includes Zr3Ti2Si3, the lattice mismatch may be about 0.7%. In some embodiments, as Figure 2C andFigure 2D As shown, the interface between the ZTC layer 133 and the merged S / D region 210 (also referred to herein as "interface 133-210") can be disposed within the merged S / D region 210 and can be non-coplanar with the surface 210s of the merged S / D region 210. In some embodiments, instead of as Figure 2C and Figure 2D shown where the ZTC layer 133 is a continuous layer, as Figure 2E shown, the ZTC layer 133 can be a discontinuous layer. Unless otherwise specified, Figure 2C and Figure 2D the discussion of the continuous ZTC layer 133 applies to Figure 2E the discontinuous ZTC layer 133.

[0046] Figure 3A An isometric view of a FET 300 according to some embodiments is shown. Unless otherwise specified, the discussion of the FET100 applies to the FET 300. According to some embodiments, as Figures 3B to 3G shown, the FET 300 can have different cross-sectional views. Figures 3B to 3G Shows a cross-sectional view of the FET 300 along the line F-F of Figure 3A , with additional structures not shown in Figure 3A for simplicity. A cross-sectional view of Figures 3B to 3G is shown for illustrative purposes and may not be drawn to scale. Unless otherwise specified, the discussion of elements with the same reference numerals in Figures 1A to 1L and Figures 3A to 3G applies to each other.

[0047] Referring to Figure 3A , instead of the S / D region 110 grown epitaxially from the bottom up, the FET 300 can have an epitaxially grown S / D region 310 to cover a portion of the fin structure 306 extending over the STI structure 116. Unless otherwise specified, the discussion of the S / D region 110 applies to the S / D region 310. Referring to Figure 3B , the FET 300 can include an S / D structure 120 disposed on the S / D region 310. In some embodiments, the top surface of the WFM silicide layer 132 can be above the surface 310s (as Figure 3B shown) or can be substantially coplanar with the surface 310s (not shown). The dopant in the WFM silicide layer 132 can cause the formation of a dipole layer 144 at the interface between the WFM silicide layer 132 and the S / D region 310 (also referred to herein as "interface 132-310"). In some embodiments, the interface 132-310 can be disposed within the S / D region 310 and can be non-coplanar with the surface 310s. The discussion of the dopant concentration profile along the line C-C of Figure 1C applies toFigure 3B line C-C.

[0048] In some embodiments, when the S / D contact structure 120 includes a ZTC layer 333 between the WFM silicide layer 132 and the S / D region 310, the S / D contact structure 120 may have a cross-sectional view as Figure 3C shown. Unless otherwise specified, the discussion of the ZTC layer 133 applies to the ZTC layer 333. The Zr dopant in the WFM silicide layer 132 may interact with the Si atoms in the S / D region 310 and the metal atoms in the WFM silicide layer 132 during a high-temperature annealing process to form the ZTC layer 333. The ZTC layer 333 may include zirconium metal silicide (Zr x M y Si z ), where the metal (M) is the metal of the WFM silicide layer 132. In some embodiments, when the WFM silicide layer 132 includes Ti x Si y , the ZTC layer 333 may include zirconium titanium silicide (Zr3Ti2Si3). The ZTC layer 333 may cause the formation of a dipole layer 145 at the interface between the ZTC layer 333 and the S / D region 310 (also referred to herein as "interface 333-310") and at the interface between the WFM silicide layer 132 and the S / D region 310. The dipole layer 145 may include Zr-Si dipoles of Zr metal ions from the ZTC layer 333 and silicon ions from the S / D region 310.

[0049] Figures 3D to 3G shows Figure 3C an enlarged view of the S / D region 310, the WFM silicide layer 132, and the ZTC layer 333 within the region 302 of Figures 3A to 3C which has different cross-sectional views of the S / D region 310, the WFM silicide layer 132, and the ZTC layer 333. As Figure 3DAs shown, when formed on the S / D region 310 of the surface 310s - 310t having a (100) or (110) crystal orientation, the ZTC layer 333 can have a faceted surface 333s facing the WFM silicide layer 132 and the S / D region 310. The faceted surface 333s forms an interface with the WFM silicide layer 132 and the S / D region 310. In some embodiments, the faceted surface 333s can have a (0001) crystal orientation (also referred to as the (0001) crystal plane) when formed on the surface 310s - 310t having a (100) crystal orientation (also known as the (100) crystal plane), and can have a (1120) crystal orientation (also referred to as the (1120) crystal plane) when formed on the surface 310s - 310t having a (110) crystal orientation (also known as the (110) crystal plane). Due to the difference in crystal orientation between the surfaces 310s - 310t and 333s, there can be a lattice mismatch in the range of about 1% to about 1.5% between the S / D region 310 and the ZTC layer 333. In some embodiments, when the ZTC layer 333 including Zr3Ti2Si3 is formed on the Si surfaces 310s - 310t having (100) and (110) crystal orientations respectively, the lattice mismatch can be between about 1.2% and about 1.3%.

[0050] In some embodiments, in order to sufficiently reduce the SBH between the S / D region 310 and the WFM silicide layer 132 (e.g., the SBH is in the range of about 0.2 eV to about 0.4 eV), the ZTC layer 333 can have a thickness T3 along the Z - axis, and the thickness T3 is in the range from about 0.1 nm to about 1 nm. Similar to the thickness T1, the thickness T3 can depend on the concentration of Zr dopants in the WFM silicide layer 132 before the formation of the ZTC layer 333 and the relationship between the thickness T3, and the concentration of Zr dopants in the WFM silicide layer can be represented by Figure 1L a graph of. In some embodiments, as Figure 3D shown, the adjacent faceted surfaces 333s facing the WFM silicide layer 132 can form an angle H in the range of about 110 degrees to about 130 degrees. In some embodiments, as Figure 3E shown, the adjacent faceted surfaces 333s facing the WFM silicide layer 132 can form an angle J in the range of about 50 degrees to about 70 degrees.

[0051] In some embodiments, as Figure 3F and Figure 3GAs shown, instead of the ZTC layer 333, ZTC clusters 333 with faceted surfaces 333s can be formed at the interface 333-310. In some embodiments, the ZTC clusters 333 can be separated from each other by a distance in the range of about 0.1 nm to about 2 nm at the interface between the WFM silicide layer 132 and the S / D region 310 (also referred to herein as "interface 132-310"). In some embodiments, as Figure 3F shown, the faceted surface 333s of the ZTC clusters 333 can form an angle K of about 140 degrees to about 160 degrees with the interface 132-310. In some embodiments, as Figure 3G shown, the faceted surface 333s of the ZTC clusters 333 can form an angle L of about 110 degrees to about 130 degrees with the interface 132-310. In some embodiments, the interface 132-310 can be disposed between adjacent ZTC clusters 333. The discussion of the dopant concentration profile along Figure 1E line D-D applies to Figures 3C to 3G line D-D.

[0052] Figure 4A An isometric view of a FET 400 according to some embodiments is shown. Unless otherwise specified, the discussion of FET100 and FET 300 applies to FET 400. According to some embodiments, as Figure 4B and Figure 4C shown, the FET 400 can have different cross-sectional views. Figures 4B to 4C shows a cross-sectional view of the FET 400 along Figure 4A line G-G, with additional structures not shown in Figure 4A for simplicity. A cross-sectional view of Figures 4B to 4C is shown for illustrative purposes and may not be drawn to scale. Unless otherwise specified, the discussion of elements with the same reference numerals in Figures 1A to 1L , Figures 3A to 3G and Figures 4A to 4C applies to each other.

[0053] Referring to Figure 4A , the FET 400 can have an epitaxially grown merged S / D region 410 as a cladding around a portion of the fin structure 306 extending over the STI structure 116. Unless otherwise specified, the discussion of the S / D region 310 applies to the merged S / D region 410. Referring to Figure 4B , the FET 400 can include an S / D structure 120 disposed on the merged S / D region 410. In some embodiments, the top surface of the WFM silicide layer 132 can be above the surface 410s (as Figure 4BThe dopant of the WFM silicide layer 132 may cause the formation of a dipole layer 144 at the interface between the WFM silicide layer 132 and the merged S / D region 410 (also referred to herein as "interface 132-410"). In some embodiments, the interface 132-410 may be disposed within the S / D region 410 and may not be coplanar with the surface 410s. Figure 1C The discussion of the dopant concentration profile of line CC applies to Figure 4B In some embodiments, when the S / D structure 120 includes a ZTC layer 333 or a ZTC cluster 333 disposed on the merged S / D region 410, the S / D contact structure 120 may have a Figure 4C The cross-sectional view shown. Similar to Figure 3C The dipole layer 145 may induce a dipole layer at the interface between the ZTC layer 333 and the S / D region 410 and at the interface between the WFM silicide layer 132 and the S / D region 410 (for simplicity, the dipole layer 145 is shown in FIG. 1 ). Figure 4C (not shown). Along Figure 1E The discussion of the dopant concentration profile of line DD applies to Figure 4C Line DD.

[0054] Figure 5 is a flow chart of an example method 500 for fabricating a FET 100 according to some embodiments. For purposes of illustration, reference will be made to Figures 6A to 17B An example manufacturing process of the FET 100 is shown to describe Figure 5 The operation shown. Figures 6A to 17A and Figures 6B to 17B According to some embodiments, at various stages of manufacturing Figure 1A 1 and 1. A cross-sectional view of FET 100 taken along corresponding lines AA and BB of FIG. 1. Depending on the particular application, the operations may be performed in a different order, or may not be performed at all. It should be noted that method 500 may not result in a complete FET 100. Therefore, it should be understood that additional processes may be provided before, during, and after method 500, and only some of the other processes are briefly described herein. Figures 1A to 1L The same annotation as the element in Figures 6A to 17B Components in .

[0055] In operation 505, a polysilicon structure and S / D regions are formed on the fin structure on the substrate. Figures 6A to 6BAs shown, a polysilicon structure 612 and S / D regions 110 are formed on a fin structure 106, and the fin structure 106 is formed on a substrate 104. During subsequent processing, the polysilicon structure 612 can be replaced in a gate replacement process to form a gate structure 112. After forming the S / D regions 110, an ESL 117 and an ILD layer 118A can be formed to form Figures 6A to 6B the structure of.

[0056] Referring to Figure 5 , in operation 510, the polysilicon structure is replaced with a gate structure. For example, as Figures 7A to 7B shown, the polysilicon structure 612 is replaced with a gate structure 112. In some embodiments, the gate structure 112 can be back-etched to form a gate capping layer 130, as Figures 8A to 8B shown. After forming the gate capping layer 130, an ILD layer 118B can be formed to form Figures 8A to 8B the structure of.

[0057] Referring to Figure 5 , in operation 515, contact openings are formed on the S / D regions. For example, as Figures 9A to 9B shown, contact openings 920 are formed on the S / D regions 110 by etching portions of the ESL 117 and the ILD layers 118A - 118B on the S / D regions 110.

[0058] Referring to Figure 5 , in operation 520, a barrier layer is selectively formed on the sidewalls of the contact openings. For example, as described with respect to Figures 10A to 10B , a barrier layer 142 is selectively formed on the sidewalls of the contact openings 920. The formation of the barrier layer 142 can include operations in the following order: (i) depositing a nitride layer 142 (e.g., SiN) on the Figures 9A to 9B structure of to form the Figures 10A to 10B structure of, and (ii) performing an isotropic etching process to remove portions of the nitride layer 142 from the top surfaces of the ILD layer 118A and the S / D regions 110 to form the Figures 11A to 11B structure of.

[0059] Referring to Figure 5 , in operation 525, a doped WFM silicide layer is formed on the S / D regions. For example, as Figures 13A to 13B shown, a doped WFM silicide layer 132 is formed on the S / D regions 110. The formation of the doped WFM silicide layer 132 can include operations in the following order: (i) performing a cleaning process (e.g., a fluorine-based dry etching process) on the Figures 11A to 11B structure of to remove the native oxide from the top surface of the S / D regions 110, (ii) depositing a dopant source layer 140 on the Figures 11A to 11B cleaned structure of to formFigures 12A to 12B structure, and (iii) depositing a WFM layer 138 on the Figures 12A to 12B structure to form a Figures 13A to 13B structure.

[0060] During deposition of the WFM layer 138, the deposition temperature can cause thermal decomposition of the bottom 140b of the dopant source layer 140 (as Figures 12A to 12B shown), and atoms of the thermally decomposed bottom 140b diffuse into the overlying WFM layer 138 as dopant atoms. In some embodiments, the deposition temperature can cause thermal decomposition of the sidewall surface portion of the dopant source layer 140 facing the WFM layer 138 and diffusion into the overlying WFM layer 138 as dopant atoms. The remaining sidewall portions of the dopant source layer 140 can be oxidized. The dopant atoms can cause the formation of the dipole layer 144 and can have a concentration profile 146 or 148 of cross-line C-C as described with respect to Figure 1J . As Figures 13A to 13B shown, the deposition temperature can also initiate a silicidation reaction between the doped bottom (not shown) of the WFM layer 138 within the contact opening 920 and the S / D region 110 to form a WFM silicide layer 132.

[0061] In some embodiments, deposition of the dopant source layer 140 can include depositing a transition metal using a CVD process or an ALD process in a temperature range of about 300 °C to about 500 °C, the electronegativity value of which is less than that of the metal of the WFM layer 138. In some embodiments, the dopant source layer 140 can include a transition metal such as Zr, Hf, Yb, Y, Er, Ce, Sc, and combinations thereof. To effectively and completely thermally decompose the bottom 140b of the dopant source layer 140, in some embodiments, the dopant source layer 140 can be deposited with a thickness in the range of about 0.05 nm to about 0.5 nm.

[0062] In some embodiments, deposition of the WFM layer 138 can include depositing a metal having a work function value closer to the conduction band edge energy than the valence band edge energy of the material of the S / D region 110 of the NFET 100, or depositing a metal having a work function value closer to the valence band edge energy than the conduction band edge energy of the material of the S / D region 110 of the PFET 100, using a CVD process or an ALD process in a temperature range of about 300 °C to about 500 °C. In some embodiments, for the NFET 100, the WFM layer 138 can include Ti, Ta, Mo, Zr, Hf, Sc, Y, Ho, Tb, Gd, Lu, Dy, Er, Yb, or combinations thereof, and for the PFET 100, the WFM layer 138 can include Ni, Co, Mn, W, Fe, Rh, Pd, Ru, Pt, Ir, Os, or combinations thereof.

[0063] Refer toFigure 5 In operation 530, a high-temperature annealing process is performed. For example, a rapid thermal annealing (RTA) process, a spike annealing process, or a laser annealing process can be used to perform a thermal annealing process on the structure of Figures 13A to 13B in an N2 environment at a temperature range of about 500 °C to about 800 °C for a duration ranging from about 100 nanoseconds to about 100 microseconds. After the thermal annealing process, if the dopant atoms in the WFM silicide layer 132 include non-Zr-based transition metals, the dopant atoms can have a concentration profile 150 across line C-C ( Figures 13A to 13B ), as described with respect to Figures 1A to 1C and Figure 1J . On the other hand, as described with respect to Figures 1D to 1E and Figure 1K , after performing a thermal annealing process on the structure of Figures 13A to 13B , if the dopant atoms include Zr metal, then the structures of Figure 14A and Figure 14B can form a Zr concentration profile 158 across line D-D. The thermal annealing process can improve the quality of the WFM silicide layer 132 and the interface 132-110, and thus reduce the contact resistance between the WFM silicide layer 132 and the S / D regions 110.

[0064] In some embodiments, after forming the WFM silicide layer 132 and before the thermal annealing process, a nitride capping layer (not shown) can be formed on the structure of Figures 13A to 13B . The nitride capping layer can form a nitride capping layer 136 in subsequent processing. The formation of the nitride capping layer can include depositing a metal layer such as Ti and Ta on the structure of Figures 13A to 13B , and performing a nitridation process on the metal layer using ammonia (NH3) gas.

[0065] Referring to Figure 5 , in operation 535, a contact plug is formed within the contact opening. For example, as shown in Figures 15A to 15B , the contact plug 134 is formed within the contact opening 920. The formation of the contact plug 134 can include filling the contact opening 920 in the structure of Figures 13A to 13B with a conductive material, and performing a CMP process to form the structure of Figures 15A to 15B . The CMP process can make the top surface of the contact structure 120 substantially coplanar with the top surface of the ILD layer 118B.

[0066] In some embodiments, the contact opening 920 in the structure of Figures 14A to 14B can be filled (instead of Figures 13A to 13B ), followed by a CMP process to form the structure of Figures 16A to 16BThe structure is used to form the contact plug 134. In some embodiments, before filling the contact opening 920 with a conductive material and performing the CMP process, the stack of the metal-based liner 135 can be removed from Figures 13A to 13B the structure to form Figures 17A to 17B the structure.

[0067] In some embodiments, operations 515-535 can be performed on the S / D regions 210, 310, and 410 (instead of the S / D region 110) of the corresponding FETs 200, 300, and 400 to form Figures 2B to 2C , Figures 3B to 3C and Figures 4B to 4C the structure.

[0068] The present invention provides exemplary structures and methods for reducing the contact resistance between source / drain (S / D) regions (e.g., S / D regions 110, 210, 310, and 410) and S / D contact structures 120 (e.g., S / D contact structure 120) of FETs (e.g., FETs 100, 200, 300, and 400). In some embodiments, a dipole layer (e.g., dipole layers 144 and 145) and / or a ternary compound layer (e.g., ZTC layers 133 and 333) can be formed at the interface between the S / D region and the S / D contact structure to reduce the SBH between the S / D region and the S / D contact structure. The dipole layer and / or the ternary compound layer can be formed by metal-doping the silicide layer of the S / D contact structure with a metal having an electronegativity value lower than that of the silicide layer (e.g., the WFM silicide layer 132). The metal dopant can cause the formation of a dipole between the metal dopant and the semiconductor element of the S / D region. The metal dopant can also cause the formation of a ternary compound between the metal dopant, the metal of the silicide layer, and the semiconductor element of the S / D region. The formation of such an interface dipole layer and / or ternary compound layer can reduce the contact resistance of the FET by about 50% to about 70% compared to an FET without an interface dipole layer and / or ternary compound layer, and thus improve the performance of the FET.

[0069] In some embodiments, a semiconductor device includes: a substrate; a fin structure disposed on the substrate; a gate structure disposed on the fin structure; a source / drain (S / D) region disposed adjacent to the gate structure; a contact structure disposed on the S / D region; and a dipole layer disposed at the interface between the ternary compound layer and the S / D region. The contact structure includes a ternary compound layer disposed on the S / D region, a work function metal (WFM) silicide layer disposed on the ternary compound layer, and a contact plug disposed on the WFM silicide layer.

[0070] In the above semiconductor device, the dipole layer includes dopant atoms of the work function metal silicide layer and semiconductor atoms of the source / drain region.

[0071] In the above semiconductor device, the ternary compound layer includes a zirconium-based ternary compound.

[0072] In the above semiconductor device, a first surface of the source / drain region facing the ternary compound layer includes a (111) crystal orientation, and a second surface of the ternary compound layer facing the work function metal silicide layer includes a non-faceted surface.

[0073] In the above semiconductor device, the ternary compound layer is a discontinuous layer, and a surface of the source / drain region facing the ternary compound layer has a (111) crystal orientation.

[0074] In the above semiconductor device, a first surface of the source / drain region facing the ternary compound layer includes a (100) or (110) crystal orientation, and a second surface of the ternary compound layer facing the work function metal silicide layer includes a faceted surface.

[0075] In the above semiconductor device, the work function metal silicide layer includes a metal dopant, and an electronegativity value of the metal dopant is less than an electronegativity value of a metal in the metal silicide of the work function metal silicide layer.

[0076] In the above semiconductor device, the contact structure further includes a liner along a sidewall of the contact plug, and the liner includes a metal or an oxide of the metal of the dipole layer.

[0077] In the above semiconductor device, the contact structure further includes a liner along a sidewall of the contact plug, and the liner includes a metal or an oxide of the metal of the work function metal silicide layer.

[0078] In the above semiconductor device, the contact structure further includes a capping layer disposed on the work function metal silicide layer.

[0079] In some embodiments, a semiconductor device includes: a gate structure disposed on a first fin structure and a second fin structure; a combined source / drain (S / D) region disposed on the first fin structure and the second fin structure; and a contact structure disposed on the combined S / D region. The contact structure includes a ternary compound cluster disposed on the combined S / D region, a work function metal (WFM) silicide layer disposed on the ternary compound cluster and the combined S / D region, and a contact plug disposed on the WFM silicide layer.

[0080] In the above semiconductor device, the ternary compound cluster includes a zirconium-based ternary compound.

[0081] In the above semiconductor device, the ternary compound cluster includes a faceted surface.

[0082] In the above semiconductor device, the ternary compound clusters are separated from each other by an interface between the work function metal silicide layer and the source / drain region.

[0083] In the above semiconductor device, a dipole layer is further provided at the interface between the work function metal silicide layer and the source / drain region.

[0084] In the above semiconductor device, a dipole layer is further provided at the interface between the ternary compound cluster and the source / drain region.

[0085] In some embodiments, a method includes: forming a fin structure on a substrate; forming source / drain (S / D) regions on the fin structure; forming contact openings in the S / D regions; forming a doped work function metal (nWFM) silicide layer in the contact openings, forming a ternary compound layer between the doped WFM silicide layer and the S / D regions, and forming contact plugs in the contact openings.

[0086] In the above method, forming the doped work function metal silicide layer includes depositing a dopant source layer on the source / drain region, and the dopant source layer includes a metal whose electronegativity value is less than the electronegativity value of the metal in the metal silicide of the doped work function metal silicide layer.

[0087] In the above method, forming the ternary compound layer includes: depositing a zirconium-based dopant source layer on the source / drain region; depositing a work function metal layer on the zirconium-based dopant source layer; and performing an annealing process.

[0088] In the above method, a nitride capping layer is further deposited on the doped work function metal silicide layer.

[0089] The features of several embodiments are outlined above so that those skilled in the art can better understand aspects of the present invention. Those skilled in the art should understand that they can easily use the present invention as a basis to design or modify other processes and structures for implementing the same purposes and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also be aware that such equivalent configurations do not depart from the spirit and scope of the present invention, and various changes, substitutions, and alterations can be made herein without departing from the spirit and scope of the present invention.

Claims

1. A semiconductor device, comprising: Substrate; Fin structure, disposed on the substrate; Gate structure, disposed on the fin structure; Source / drain regions, disposed adjacent to the gate structure; Contact structure, disposed on the source / drain regions, wherein the contact structure includes a ternary compound layer disposed on the source / drain regions, a work function metal silicide layer disposed on the ternary compound layer, and a contact plug disposed on the work function metal silicide layer; and Dipole layer, disposed at the interfaces between the ternary compound layer and the source / drain regions and between the work function metal silicide layer and the source / drain regions, wherein the work function metal silicide layer includes a transition metal dopant, and wherein a peak dopant concentration of the transition metal dopant is spaced apart from the interface where the dipole layer is located.

2. The semiconductor device according to claim 1, wherein, The dipole layer includes dopant atoms of the work function metal silicide layer and semiconductor atoms of the source / drain regions.

3. The semiconductor device according to claim 1, wherein, The ternary compound layer includes a zirconium-based ternary compound.

4. The semiconductor device according to claim 1, wherein, A first surface of the source / drain region facing the ternary compound layer includes a [111] crystal orientation, and wherein a second surface of the ternary compound layer facing the work function metal silicide layer includes a non-faceted surface.

5. The semiconductor device according to claim 1, wherein, The ternary compound layer is a discontinuous layer, and wherein a surface of the source / drain region facing the ternary compound layer has a [111] crystal orientation.

6. The semiconductor device according to claim 1, wherein, A first surface of the source / drain region facing the ternary compound layer includes a [100] or [110] crystal orientation, and wherein a second surface of the ternary compound layer facing the work function metal silicide layer includes a faceted surface.

7. The semiconductor device according to claim 1, wherein, An electronegativity value of the transition metal dopant is less than an electronegativity value of a metal in the metal silicide of the work function metal silicide layer.

8. The semiconductor device according to claim 1, wherein, The contact structure further includes a liner along a sidewall of the contact plug, and wherein the liner includes a metal or an oxide of a metal of the dipole layer.

9. The semiconductor device according to claim 1, wherein, The contact structure further includes a liner along a sidewall of the contact plug, and wherein the liner includes a metal or an oxide of a metal of the work function metal silicide layer.

10. The semiconductor device according to claim 1, wherein, The contact structure further includes a capping layer disposed on the work function metal silicide layer.

11. A semiconductor device, comprising: Gate structure, disposed on a first fin structure and a second fin structure; Combined source / drain regions, disposed on the first fin structure and the second fin structure; and Contact structure, disposed on the combined source / drain regions, wherein the contact structure includes a ternary compound cluster disposed on the combined source / drain regions, a work function metal silicide layer disposed on the ternary compound cluster and the combined source / drain regions, and a contact plug disposed on the work function metal silicide layer, wherein a dipole layer is disposed at the interfaces between the ternary compound cluster and the source / drain regions and between the work function metal silicide layer and the source / drain regions, wherein the work function metal silicide layer includes a transition metal dopant, and wherein a peak dopant concentration of the transition metal dopant is spaced apart from the interface where the dipole layer is located.

12. The semiconductor device according to claim 11, wherein, The ternary compound cluster includes a zirconium-based ternary compound.

13. The semiconductor device according to claim 11, wherein, The ternary compound cluster includes a faceted surface.

14. The semiconductor device according to claim 11, wherein, The ternary compound clusters are separated from each other by an interface between the work function metal silicide layer and the source / drain region.

15. The semiconductor device according to claim 11, wherein, The ternary compound cluster is a discontinuous layer.

16. The semiconductor device according to claim 11, wherein, The surface of the source / drain region facing the ternary compound cluster has a [111] crystal orientation.

17. A method of manufacturing a semiconductor device, comprising: A fin structure is formed on a substrate; Source / drain regions are formed on the fin structure; Contact openings are formed in the source / drain regions; A doped work function metal silicide layer is formed in the contact openings; A ternary compound layer is formed between the doped work function metal silicide layer and the source / drain region; and a contact plug is formed in the contact openings, wherein the doped work function metal silicide layer includes a transition metal dopant, wherein dipole layers are provided at interfaces between the ternary compound layer and the source / drain region and between the doped work function metal silicide layer and the source / drain region, and a peak dopant concentration of the transition metal dopant is spaced apart from the interfaces where the dipole layers are located by a distance.

18. The method according to claim 17, wherein, Forming the doped work function metal silicide layer includes depositing a dopant source layer on the source / drain region.

19. The method according to claim 17, wherein, Forming the ternary compound layer includes: depositing a zirconium-based dopant source layer on the source / drain region; depositing a work function metal silicide layer on the zirconium-based dopant source layer; and performing an annealing process.

20. The method according to claim 17, further comprising depositing a nitride capping layer on the doped work function metal silicide layer.

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