Memory array including memory cell strings and method for forming a memory array

Abstract

The present application relates to a memory array including a string of memory cells and a method for forming the same. A memory array including a string of memory cells includes laterally spaced memory blocks, each of which includes a vertical stack including alternating insulating layers and conductive layers. A channel material string structure of a memory cell extends through the insulating layer and the conductive layer. The channel material string structures each include an upper portion above and joined to a lower portion. Individually, the channel material string structures include at least one external bend surface in a vertical cross-section where the upper and lower portions are joined. Other embodiments including methods are disclosed.

Description

Technical Field

[0001] Embodiments disclosed herein relate to memory arrays and to methods for forming memory arrays. Background Art

[0002] Memory is a type of integrated circuit system and is used in computer systems to store data. Memory can be fabricated as one or more arrays of individual memory cells. Memory cells can be written to or read from using digit lines (which may also be referred to as bit lines, data lines, or sense lines) and access lines (which may also be referred to as word lines). Sense lines can conductively interconnect memory cells along the columns of the array, and access lines can conductively interconnect memory cells along the rows of the array. Each memory cell can be uniquely addressed by a combination of sense lines and access lines.

[0003] Memory cells may be volatile, semi-volatile, or non-volatile. Non-volatile memory cells can store data for a long period of time without power. Non-volatile memory is generally designated as memory having a retention time of at least about 10 years. Volatile memory dissipates and is therefore refreshed / rewritten to maintain data storage. Volatile memory may have a retention time of a few milliseconds or less. In any case, the memory cell is configured to retain or store memory in at least two different selectable states. In a binary system, the state is considered to be "0" or "1". In other systems, at least some individual memory cells may be configured to store information at more than two levels or states.

[0004] Field effect transistors are a type of electronic component that can be used in memory cells. These transistors include a pair of conductive source / drain regions with a semiconducting channel region between them. A conductive gate is adjacent to the channel region and separated from the channel region by a thin gate insulator. Applying a suitable voltage to the gate allows current to flow from one of the source / drain regions to the other through the channel region. When the voltage is removed from the gate, current is greatly prevented from flowing through the channel region. Field effect transistors may also include additional structures, such as a reversibly programmable charge storage region as part of the gate construction between the gate insulator and the conductive gate.

[0005] Flash memory is a type of memory and is used extensively in modern computers and devices. For example, a modern personal computer may have the BIOS stored on a flash memory chip. As another example, it is increasingly common for computers and other devices to utilize flash memory in the form of solid-state drives in place of traditional hard disk drives. As yet another example, flash memory is prevalent in wireless electronic devices because it enables manufacturers to support new communication protocols as they become standardized and to provide the ability to remotely upgrade devices for enhanced features.

[0006] NAND may be the basic architecture of integrated flash memory. A NAND cell device includes at least one selection device coupled in series with a series combination of memory cells (and the series combination is often referred to as a NAND string). The NAND architecture may be configured in a three-dimensional arrangement including vertically stacked memory cells that individually include reversibly programmable vertical transistors. Control circuitry or other circuitry may be formed below the vertically stacked memory cells. Other volatile or non-volatile memory array architectures may also include vertically stacked memory cells that each include a transistor.

[0007] The memory array may be arranged in memory pages, memory blocks, and partial blocks (e.g., sub-blocks), and memory planes, for example, as shown and described in any of U.S. Patent Application Publication Nos. 2015 / 0228651, 2016 / 0267984, and 2017 / 0140833. The memory blocks may at least partially define the longitudinal profiles of individual word lines in individual word line layers of vertically stacked memory cells. Connections to these word lines may occur in a so-called "staircase structure" at the ends or edges of the array of vertically stacked memory cells. The staircase structure includes individual "steps" (alternatively referred to as "steps" or "stairs") that define contact areas for individual word lines, with vertically extending conductive vias contacting the contact areas to provide electrical access to the word lines. Summary of the invention

[0008] In one aspect, the present application provides a method for forming a memory array including a string of memory cells, comprising: forming a lower portion of a stack on a substrate that will include vertically alternating first and second layers, the stack including laterally spaced memory block areas, the material of the first layer having a composition different from that of the material of the second layer; forming pillars in the lower portion, the pillars being horizontally positioned, respectively, wherein individual channel material string structures will be formed, the pillars comprising sacrificial material; forming the vertically alternating first and second layers of an upper portion of the stack above the lower portion and the pillars; forming channel openings into the stack and extending to the individual pillars, respectively; removing the sacrificial material of the pillars through the channel openings to extend the channel openings deeper into the stack; and forming a channel material string structure in the extended channel openings and in the void spaces therein created by the removal.

[0009] In another aspect, the present application provides a method for forming a memory array including a memory cell string, comprising: forming a conductor layer including a conductor material on a substrate; forming a lower portion of a stack including a first layer and a second layer alternating vertically above the conductor layer, the stack including laterally spaced memory block areas, the material of the first layer having a composition different from that of the material of the second layer, the first layer at the bottom including a first sacrificial material; forming pillars in the first layer at the bottom, the pillars being respectively horizontally positioned, wherein individual channel material string structures are to be formed, the pillars including a second sacrificial material; forming the vertically alternating first and second layers of an upper portion of the stack above the lower portion and the pillars; forming channel openings into the stack and extending respectively extending to the individual pillars; removing the second sacrificial material of the pillars through the channel openings to extend the channel openings deeper into the stack; forming a channel material string structure in the extended channel openings and in the void spaces therein produced by the removal; forming horizontally extended grooves into the stack, the horizontally extended grooves respectively extending between the laterally adjacent memory block areas and to the first sacrificial material in the lowermost first layer; isotropically etching the first sacrificial material from the lowermost first layer through the grooves; and forming a conductive material in the lowermost first layer after the isotropic etching, the conductive material directly electrically coupling the channel material of the individual channel material string structure with the conductive material of the conductive layer.

[0010] In yet another aspect, the present application further provides a memory array comprising a memory cell string, comprising: laterally spaced memory blocks, each comprising a vertical stack, the vertical stack comprising alternating insulating layers and conductive layers, a channel material string structure of the memory cell extending through the insulating layers and the conductive layers; and the channel material string structure each comprising an upper portion above and joined to a lower portion, each of the channel material string structures comprising at least one external bending surface in a vertical cross-section where the upper and lower portions are joined. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 is a diagrammatic cross-sectional view of a portion of a substrate during a process according to an embodiment of the present invention and is a cross-sectional view through Figure 2 Intercepted by line 1-1 in.

[0012] Figure 2 It passes through Figure 1 A diagrammatic cross-sectional view taken along line 2-2 in FIG.

[0013] Figures 3 to 10 and 14 to 38 are in the process of some embodiments of the present invention Figure 1 and2 The structure or its parts are shown in cross-section, unfolded, enlarged and / or partial views in sequence.

[0014] Figures 11 to 13 39 to 53 are diagrammatic cross-sectional views of portions of substrates being processed according to some embodiments of the present invention. DETAILED DESCRIPTION

[0015] Embodiments of the present invention encompass methods for forming memory arrays, such as arrays of NAND or other memory cells, which may have at least some peripheral control circuitry under the array (e.g., under-array CMOS). Embodiments of the present invention encompass so-called "gate-last" or "replacement-gate" processes, so-called "gate-first" processes, and other processes, whether present or developed in the future, that are independent of when the transistor gates are formed. Embodiments of the present invention also encompass memory arrays that are independent of the method of manufacture (e.g., NAND architecture). Reference Figures 1 to 53 A first example method embodiment is described, which may be considered a "gate-last" or "replacement-gate" process and which begins with Figure 1 and 2 start.

[0016] Figure 1 and 2 A construction 10 is shown having an array or array region 12 in which vertically extending strings of transistors and / or memory cells are to be formed. Construction 10 includes a base substrate 11 having any one or more of a conductive / conductor / conductive, semiconductive / semiconducting / semiconductive, or insulating / insulator / insulating (i.e., electrically herein) material. Various materials have been vertically formed over base substrate 11. The materials may be Figure 1 and 2 1. The base substrate 11 may be provided with other partially or fully fabricated components of the integrated circuit system somewhere above, around, or within the base substrate 11. Control and / or other peripheral circuitry for operating components within an array of vertically extending strings of memory cells (e.g., array 12) may also be fabricated, and may or may not be completely or partially within an array or sub-array. In addition, multiple sub-arrays may also be fabricated and operated independently, sequentially, or otherwise relative to one another. In this document, a "sub-array" may also be considered an array.

[0017] In some embodiments and as shown, a conductor material 17 (eg, WSi xA conductor layer 16 of conductively doped polysilicon (polysilicon) has been formed over substrate 11. Conductor layer 16 may include portions of control circuitry (e.g., peripheral under-array circuitry and / or a common source line or plate) for controlling read and write access to transistors and / or memory cells to be formed within array 12.

[0018] The lower portion 18L of the stack 18*, when present, has been formed over the substrate 11 and the conductor layer 16 (* is used as a suffix to include all such components designated with the same numerical value that may or may not have other suffixes). The stack 18* will include vertically alternating conductive layers 22* and insulating layers 20*. The example lower portion 18L is shown as including two insulating layers 20* and two conductive layers 22*. More insulating layers 20*, more conductive layers 22*, fewer insulating layers 20*, or fewer conductive layers 22* may be provided alternately in the lower portion 18L (not shown). The conductive layer 22* (alternatively referred to as the first layer) may not include conductive material, and the insulating layer 20* (alternatively referred to as the second layer) may not include insulating material or be insulating when processed in conjunction with the "gate last" or "replacement gate" example method embodiments initially described herein. The example conductive layer 22* includes a first material 26 (e.g., silicon nitride) that may be fully or partially sacrificial. The example insulating layer 20* includes a second material (e.g., 24, 27; such as one or more insulating oxides, including, for example, silicon dioxide) having a different composition than the composition of the first material 26 and may be fully or partially sacrificial. In one embodiment, the lowermost first layer 22z includes a first sacrificial material 77 (e.g., polysilicon or silicon nitride, and may have the same or different composition than the material of the first layer 22* above and / or to be formed above it). In one embodiment, the next lowermost first layer 22x includes conductively doped polysilicon 47.

[0019] An example thickness of each of layers 20* and 22* is 20 to 60 nanometers. In one embodiment and as shown, the lowermost first layer 22z does not directly abut the conductor material 17 of the conductor layer 16, for example where the lowermost second layer 20z is vertically between the conductor material 17 of the conductor layer 16 and the lowermost first layer 22z. Alternatively, the lowermost first layer may directly abut the conductor material of the conductor layer (not shown). In one embodiment, the lowermost second layer 20z directly abuts the top 19 of the conductor material 17 of the conductor layer 16. A silicon nitride layer (not shown) may be between the second material 24 and the first sacrificial material 77, and thus is part of the insulating layer 20z. A silicon nitride layer (not shown) may be between the second material 27 and the first layer material 47, and thus is part of the insulating layer 20x.

[0020] Stack 18* includes laterally spaced memory block regions 58 that will include laterally spaced memory blocks 58 in a finished circuit system configuration. In this document, a "block" generally includes a "sub-block." Memory block regions 58 and resulting memory blocks 58 (not yet shown) may be considered to extend longitudinally and be oriented, for example, along direction 55. Memory block regions 58 may not be discernible at this processing point.

[0021] In one embodiment, horizontally extending lines 13 have been formed in the second-lowest first layer 22x (and in one embodiment, in layer 20x). Lines 13 are respectively between laterally adjacent memory block areas 58. Lines 13 include a second sacrificial material 15 having a different composition than the first sacrificial material 77 in one embodiment. In some embodiments, "second sacrificial material" is simply referred to as "sacrificial material". In some embodiments, the second sacrificial material 15 has a different composition than the first layer material (e.g., 47) formed or to be formed above the first sacrificial material 77 and the second layer material (e.g., 27) formed or to be formed above the first sacrificial material 77. In one embodiment, the second sacrificial material 15 has a different composition than the material 47 of the second-lowest conductive first layer 22x. In one embodiment, the second sacrificial material 15 includes a metallic material, such as elemental tungsten above a thin layer of TiN. In one embodiment, an insulator material 24 (e.g., silicon dioxide) may be formed in a trench before forming material 47, the trench being formed in materials 47 and 27 as shown, and thereby the insulator material being laterally between materials 47 and 15 as shown. Regardless, the wires 13 may taper laterally inward (not shown), moving deeper into the lower stack portion 18L. The wires 13 may be considered to have a bottom surface 59. In one embodiment and as shown, the individual bottom wire surfaces 59 are anywhere above the next-lowest first layer 22z.

[0022] In one embodiment, pillars 60 have been formed in lower portion 18L. Pillars 60 are positioned horizontally (i.e., in x, y coordinates) where individual channel material string structures will be formed. By way of example only and for simplicity, pillars 60 are shown arranged in groups or columns of staggered rows of four and five pillars 60 per row. In one embodiment, pillars 60 include second sacrificial material 15. Pillars 60 may taper radially inward (not shown), moving deeper into lower stack portion 18L. Pillars 60 may be considered to have a bottom surface 64 and an uppermost surface 63. In embodiments where both pillars 60 and wires 13 are formed, they may be formed simultaneously or at different times.

[0023] In one embodiment, the pillar bottom surface 64 and the wire bottom surface 59 are at different depths relative to each other. In one such embodiment, the pillar bottom surface 64 is deeper than the wire bottom surface 59, and in one such latter embodiment, they are in the conductor layer 16 (e.g., directly against the conductor material 17). In one embodiment, the pillar uppermost surface 63 is respectively above the lowermost first layer 22z.

[0024] refer to Figure 3 and 4 , vertically alternating first and second layers 22, 20 of an upper portion 18U of stack 18* have been formed over lower portion 18L (and, when present, wires 13 and / or pillars 60). Example upper portion 18U is shown starting with second layer 20 over lower portion 18L, but this may alternatively start with first layer 22 (not shown). In any event, only a small number of layers 20 and 22 are shown, with upper portion 18U (and thus stack 18*) more likely to include dozens, a hundred, or more, etc. layers 20* and 22*. In addition, other circuitry that may or may not be part of peripheral and / or control circuitry may be between conductor layer 16 and stack 18*. By way of example only, multiple vertically alternating layers of conductive and insulating material of such circuitry may be below lowermost conductive layer 22* and / or above uppermost conductive layer 22*. For example, one or more select gate layers (not shown) may be between conductor layer 16 and lowermost conductive layer 22*, and one or more select gate layers may be above uppermost conductive layer 22*. Alternatively or additionally, at least one of the depicted uppermost and lowermost conductive layers 22* may be a select gate layer.

[0025] A channel opening 25 has been formed (e.g., by etching) through the insulating layer 20 and the conductive layer 22 in the upper portion 18U to the lower portion 18L and to the pillar 60 (when present), respectively. Alternatively, if the pillar 60 is not present, the channel opening 25 may extend to (included in or below) the lowermost first layer 22z. In any case, the channel opening 25 may taper radially inward (not shown), moving deeper into the upper stack portion 18U.

[0026] refer to Figure 5 and 6, pillars 60 (not shown) have been removed (e.g., by isotropic etching) through the trench openings 25, thereby effectively extending the trench openings 25 into the respective void spaces 61 created by the removal of the pillars 60 and to the lowermost first layer 22z. One skilled in the art will be able to select a suitable isotropic etching chemistry that will selectively etch the pillar material 15 relative to other exposed materials. As an example, the tungsten material 15 may be selectively isotropically etched relative to SiO2 and Si3N4 using a mixture of ammonia and hydrogen peroxide or a mixture of sulfuric acid and hydrogen peroxide.

[0027] refer to Figures 7 to 10 , transistor channel material 36 has been formed vertically along the first layer and the second layer in the individual channel openings 25 and the void space 61. The channel material 36 will be directly electrically coupled to the conductive material 17 in the conductor layer 16. The individual memory cells of the formed example memory array may include a gate region (e.g., a control gate region) and a memory structure laterally between the gate region and the channel material. In one such embodiment, the memory structure is formed to include a charge blocking region, a storage material (e.g., a charge storage material), and an insulating charge transfer material. The storage material (e.g., a floating gate material, such as doped or undoped silicon, or a charge trapping material, such as silicon nitride, metal dots, etc.) of the individual memory cells is vertically along the individual charge blocking region. The insulating charge transfer material (e.g., a bandgap engineered structure having a nitrogen-containing material [e.g., silicon nitride] sandwiched between two insulator oxides [e.g., silicon dioxide]) is laterally between the channel material and the storage material. Fig.10 and 11 An embodiment is shown in which charge blocking material 30, storage material 32, and charge transfer material 34 have been formed vertically along insulating layer 20* and conductive layer 22* in individual channel openings 25. Transistor materials 30, 32, and 34 (e.g., memory cell materials) may be formed, for example, by depositing their respective thin layers over stack 18* and within individual channel openings 25, followed by planarization of such transistor materials back to at least the top surface of stack 18*. Channel material 36 and materials 30, 32, and 34 may collectively be considered to include individual channel material string structures 53 extending through first layer 22* and second layer 20* in upper portion 18U to lowermost first layer 22z in lower portion 18L.

[0028] Channel material 36 may be considered to have its lowermost surface 71. In one embodiment, channel material string structure 53 has memory cell materials (e.g., 30, 32, and 34) along it, and wherein a second layer of material (e.g., 24) is horizontally located immediately between channel material string structures 53. Due to the proportions, materials 30, 32, 34, and 36 are Fig.13 and14 30, 32, 34, and 36. An example channel material 36 includes a suitably doped crystalline semiconductor material, such as one or more of silicon, germanium, and so-called III / V semiconductor materials (e.g., GaAs, InP, GaP, and GaN). An example thickness of each of materials 30, 32, 34, and 36 is 25 to 100 angstroms. A stamp etch may be performed to remove materials 30, 32, and 34 from a base (not shown) of channel opening 25 to expose conductor layer 16 so that channel material 36 is directly against conductor material 17 of conductor layer 16. Such a stamp etch may occur individually with respect to each of materials 30, 32, and 34 (as shown), or may occur with respect to only some (not shown). Alternatively and by way of example only, a stamp etch may not be performed, and channel material 36 may be directly electrically coupled to conductor material 17 of conductor layer 16 only through a separate conductive interconnect (not shown). Channel opening 25 is shown including a radially central solid dielectric material 38 (eg, spin-on dielectric, silicon dioxide, and / or silicon nitride). Alternatively and by way of example only, the radially central portion within channel opening 25 may include void space (not shown) and / or be free of solid material (not shown).

[0029] In one embodiment, the channel material string structures 53 can be considered to include upper portions 70 above and joined to lower portions 72, respectively. Figure 8 and 10 The vertical cross section of the embodiment includes at least one external jog surface 75 ( Fig.10 ), wherein the upper portion 70 and the lower portion 72 are joined (i.e., a "bend surface" herein is characterized as an abrupt change in direction [at least 15°] compared to the outer surface of the channel material string structure directly above and below the bend surface). One or more bend surfaces 75 may be formed due to the radially inward taper of the channel opening 25 moving deeper into the upper stack portion 18U compared to the larger uppermost radial extent of the void space 61 left by the removal of the pillar 60 (as shown). Alternatively and / or in addition, for example, as described below, one or more bend surfaces 75 may be formed by a misalignment of the channel opening 25 relative to the previous pillar 60 (in Figures 7 to 10 not shown).

[0030] In one embodiment, at least one outer bend surface 75 is horizontal (as shown) or within 10° of horizontal. The example individual channel material string structures 53 include two bend surfaces 75, and in one embodiment, the individual channel material string structures are vertically inclined relative to each other (each is horizontal in one example and thus each is inclined 90° from vertical).

[0031] Fig.11 An example alternative embodiment configuration 10a is shown. The same reference numerals of the embodiments described above have been used where appropriate, with certain construction differences indicated by the suffix "a" or by different reference numerals. Individual channel material string structures 53a include only one bending surface 75a, such as may occur due to slight misalignment of the channel opening 25 relative to the previous support 60. Any other attributes or aspects as shown and / or described herein with respect to other embodiments may be used.

[0032] Fig.12 An example alternative embodiment configuration 10b is shown. The same reference numerals from the embodiments described above have been used where appropriate, with some construction differences indicated by the suffix "b" or by different reference numerals. Individual channel material string structures 53b include at least one bend surface 75b that is not horizontal (e.g., two bend surfaces 75b are shown, one horizontal and the other non-horizontal). In one embodiment, the non-horizontal bend surface 75b is greater than 10° from horizontal, at least 22.5° from horizontal in one such implementation, and at least 45° from horizontal in one such embodiment (approximately 66° from horizontal is shown, and thus approximately 24° from each of the example extremes; the vertical surface of the channel material string structure 53 is above and below the bend surface 75b). Any other attributes or aspects as shown and / or described herein with respect to other embodiments may be used.

[0033] Fig.13 An example alternative embodiment configuration 10c is shown in which individual channel material string structures 53c include a bent surface 75c (left one) at 45° from horizontal. The same reference numerals from the embodiments described above have been used where appropriate, with some construction differences indicated with a suffix "b" or with different reference numerals. Any other attributes or aspects as shown and / or described herein with respect to other embodiments may be used.

[0034] refer to Fig.14 and 15 , horizontally extended trenches 40 have been formed into the stack 18 * (eg, by anisotropic etching) and are respectively located between laterally adjacent memory block regions 58 and extend to the lines 13 between the memory block regions.

[0035] refer to Fig.16 and 17 , the second sacrificial material 15 (not shown) of the line 13 (not shown) has been removed through the trench 40 (if the material 15 includes tungsten, then by isotropic etching using a mixture of ammonia and hydrogen peroxide or a mixture of sulfuric acid and hydrogen peroxide). An intervening material (not shown) is ultimately formed in the trench 40 and in the void space left by the removal of the second sacrificial material 15 of the line 13.

[0036] Any other attributes or aspects as shown and / or described herein with respect to other embodiments may be used in the embodiments shown and described with reference to the above embodiments.In some embodiments, other and / or additional processing occurs, for example as described below.

[0037] refer to Fig.18 and 19 , trench 40 has optionally been lined with liner material 35 (e.g., 35 is hafnium oxide, aluminum oxide, silicon dioxide, silicon nitride, etc.). Liner material 35 may be partially or completely sacrificial, and is desirably a composition other than the composition of material 24 and material 26. After deposition of liner material 35, the liner material has been substantially removed from the horizontal surfaces, such as by a maskless anisotropic spacer-like etch thereof.

[0038] refer to Fig. 20 and 21 , trench 40 has been extended to conductor material 17 of conductor layer 16 (eg, by etching through materials 27 , 77 , and 24 ).

[0039] refer to Figures 22 to 24 , the first sacrificial material 77 (not shown) has been isotropically etched from the lowermost first layer 22z through the trench 40 (e.g., using liquid or gaseous H3PO4 as the primary etchant, where material 77 is silicon nitride and the other materials exposed include one or more oxides or polysilicon, or using tetramethylammonium hydroxide [TMAH], where material 77 is polysilicon). If the first layer material 26 and the first sacrificial material 77 have the same composition, the sidewalls of the first layer material 26 have been masked by the liner material 35, which prevents the etching of material 26 when etching the first sacrificial material 77.

[0040] In one embodiment, sidewalls of the channel material of the channel material string structure in the lowermost first layer are exposed. Fig.25 and 26An example such subsequent processing is shown where, in one embodiment, material 30 (e.g., silicon dioxide), material 32 (e.g., silicon nitride), and material 34 (e.g., silicon dioxide or a combination of silicon dioxide and silicon nitride) have been etched in layer 20z to expose sidewalls 41 of channel material 36 of channel material string structure 53 in the lowermost first layer 22z. Any of materials 30, 32, and 34 in layer 22z may be considered sacrificial material therein. As an example, consider an embodiment where material 35 is one or more insulating oxides (other than silicon dioxide), materials 47 and 36 are polysilicon, and memory cell materials 30, 32, and 34 are one or more of a silicon dioxide layer and a silicon nitride layer, respectively. In such an example, the depicted construction may be produced by using modified or different chemistries to selectively etch silicon dioxide and silicon nitride sequentially relative to one another. As an example, a solution of 100:1 (by volume) water to HF will selectively etch silicon dioxide relative to silicon nitride, while a solution of 1000:1 (by volume) water to HF will selectively etch silicon nitride relative to silicon dioxide. Thus, and in such an example, such etching chemistries may be used in an alternating manner, where it is desired to achieve the desired etching performance. Fig.25 and 26 The example configuration shown. Those skilled in the art will be able to select other chemistries for etching other different materials, where desired. Fig.25 and 26 The structure shown.

[0041] refer to Fig. 27 and 28 , and in one embodiment, the conductive material 42 has been deposited into the void space left in the lowermost first layer 22z by the removal of the first sacrificial material 77. In one such embodiment, the conductive material 42 directly abuts against the exposed sidewalls 41 of the channel material 36 of the channel material string structure 53 in the lowermost first layer 22z, and in one embodiment, directly abuts against the uppermost surface 19 of the conductor material 17 of the conductor layer 16. This is just one example, whereby the conductive material 42 has been deposited to directly electrically couple the channel material 36 of the individual channel material string structures 53 and the conductor material 17 of the conductor layer 16 together (e.g., through the channel material sidewalls 41). Example conductive materials 42 are conductively doped semiconductor materials (e.g., conductively doped polysilicon) and metal materials. The conductive material 42 may directly abut against the first layer material 47. For example, if a silicon nitride layer (not shown and mentioned above) is between the second material 27 (not shown) and the first layer material 47, the conductive material 42 may not directly abut against the first layer material 47 (not shown). The first layer of material 47 may or may not be in the finished construction, and if so, may be circuit-inactive or circuit-active.

[0042] refer to Fig.29 and30 , conductive material 42 has been removed from trench 40, such as by a timed isotropic or anisotropic etch that may be selectively performed relative to materials 24, 26, 17, and 47. This may result in removal of liner material 35 as shown, or this material may be removed alone. Alternatively, liner material 35 may have been removed earlier (not shown). The reason for removing liner material 35 is to provide access to material 26 in second layer 22 for its removal in the replacement gate process. Etching of conductive material 42 may result in some etching of conductor material 17 when exposed (not shown). Example etching chemistries are anisotropic (HBr) and isotropic (TMAH), where material 42 is conductively doped polysilicon, material 24 is silicon dioxide, and material 26 is silicon dioxide.

[0043] refer to Fig.31 and 32 , an optional selective oxidation has been performed, thereby forming an oxide layer 45 (eg, silicon dioxide).

[0044] refer to Figures 33 to 38 , material 26 (not shown) of conductive layer 22* has been removed, for example, by isotropically etching away through trench 40, ideally selectively relative to other exposed materials (e.g., using liquid or gaseous H3PO4 as the primary etchant, where material 26 is silicon nitride and the other materials include one or more oxides or polysilicon). In an example embodiment, material 26 (not shown) in conductive layer 22* is sacrificial and has been replaced by conductive material 48 and has thereafter been removed from trench 40, thus forming individual conductive lines 29 (e.g., word lines) and vertically extending strings 49 of individual transistors and / or memory cells 56.

[0045] A thin insulating liner (e.g., Al2O3 and not shown) may be formed prior to forming conductive material 48. The approximate location of transistor and / or memory cell 56 is Fig.38 Indicated by brackets in Fig.33 , 35 37, where the transistor and / or memory cell 56 is substantially annular or ring-shaped in the depicted example. Alternatively, the transistor and / or memory cell 56 may not completely surround the individual channel openings 25, so that each channel opening 25 may have two or more vertically extending strings 49 (e.g., multiple transistors and / or memory cells surround the individual channel openings in the individual conductive layers, where there may be multiple word lines per channel opening in the individual conductive layers, and not shown). The conductive material 48 may be viewed as having an end 50 ( Fig.38). In the depicted embodiment, control gate region 52 includes individual portions of individual conductive lines 29. Materials 30, 32, and 34 may be viewed as a memory structure 65 laterally located between control gate region 52 and channel material 36. In one embodiment and as shown with respect to an example "gate last" process, conductive material 48 of conductive layer 22* is formed after forming channel opening 25 and / or trench 40. Alternatively, such as with respect to a "gate first" process, the conductive material of the conductive layer may be formed prior to forming channel opening 25 and / or trench 40 (not shown).

[0046] The charge blocking region (e.g., charge blocking material 30) is between the storage material 32 and the individual control gate region 52. The charge blocking member may have the following functions in the memory cell: in the programming mode, the charge blocking member may prevent charge carriers from flowing from the storage material (e.g., floating gate material, charge trapping material, etc.) to the control gate, and in the erase mode, the charge blocking member may prevent charge carriers from flowing from the control gate into the storage material. Thus, the charge blocking member may be used to block charge migration between the control gate region and the storage material of the individual memory cell. The example charge blocking region as shown includes an insulator material 30. By way of other examples, the charge blocking region may include a lateral (e.g., radially) outer portion of the storage material (e.g., material 32), where this storage material is insulating (e.g., in the absence of any different composition material between the insulating storage material 32 and the conductive material 48). In any case, as an additional example, the interface of the storage material and the conductive material of the control gate may be sufficient to act as a charge blocking region in the absence of any separate composition insulator material 30. Furthermore, the interface of conductive material 48 and material 30 (if present) in conjunction with insulator material 30 may together act as a charge blocking region and alternatively or additionally may act as a lateral outer region of insulating storage material such as silicon nitride material 32. Example material 30 is one or more of hafnium oxide and silicon dioxide.

[0047] In one embodiment and as shown, lowermost surface 71 of channel material 36 of channel material string structure 53 never directly abuts any of conductor materials 17 of conductor layer 16 .

[0048] Interposing material 57 has been formed in trench 40 and in the void space left by the removal of second sacrificial material 15 of line 13, and thereby laterally between and longitudinally along laterally adjacent memory blocks 58. Interposing material 57 may provide lateral electrical isolation (insulation) between laterally adjacent memory blocks. This may include one or more of insulating, semiconductive, and conductive materials, and in any case, may help prevent shorting of conductive layers 22 relative to each other in the finished circuit system construction. Example insulating materials are one or more of SiO2, Si3N4, Al2O3, and undoped polysilicon. Interposing material 57 may include through-array vias (not shown). Some of the material in trench 40 formed prior to forming the material designated as interposing material 57 may remain, and thereby comprise a portion of interposing material 57. In any case, in one embodiment, after forming conductive material 42, at least a majority of interposing material 57 is formed in the trench and void space.

[0049] Any other properties or aspects as shown and / or described herein with respect to other embodiments may be used in the embodiments shown and described with reference to the above embodiments.

[0050] Fig.39 , 40 and 41 respectively show that they can be Fig.11 , 12 and 13 produce example result configurations 10a, 10b, and 10c. Any other attributes or aspects as shown and / or described herein with respect to other embodiments may be used.

[0051] Fig.42 and 43 An example alternative embodiment configuration 10d is shown in process according to an embodiment of the present invention. Like reference numerals from the above embodiments have been used where appropriate, with some configuration differences indicated with a suffix "d" or with different reference numerals. Fig.42 In the processing sequence corresponding to Figure 2 The construction 10d has individual wires 13d having bottom surfaces 59 that are lower than the top 73 of the lowermost first layer 22z. Furthermore, in one such embodiment and as shown, the wires 13d each include laterally opposed protrusions 54 longitudinally along the lowermost first layer 22z. Similar and / or alternative processing to that shown and described above may occur to produce the following: Fig.43 The structure 10d shown (which corresponds in sequence and view to the first described embodiment) Fig.35 Any other attributes or aspects as shown and / or described herein with respect to other embodiments may be used.

[0052] refer to Figures 44 to 48Describing Alternative Methods. Like reference numerals from the embodiments described above have been used where appropriate, with certain construction differences indicated by a suffix "e" or by different reference numerals. Fig.44 In the processing sequence corresponding to Figure 2 Example construction 10e has a conductor material 17 of conductor layer 16 that includes a lower conductor material 44 (eg, WSi) of a different composition than an upper conductor material 43. x 18L). The second layer 20x directly above the lowermost first layer 22z includes an upper conductive material 43 (e.g., n-type or p-type conductive doped polysilicon). The second layer 20x directly above the lowermost first layer 22z includes undoped polysilicon 51 (and second layer material / layers 27 and 24). A silicon nitride layer (not shown) may be between the second material 27 and the undoped polysilicon 51 and is thus part of the insulating layer 20x. A horizontally extended recess 79 has been formed in the lower portion 18L and extends to the conductive layer 16.

[0053] refer to Fig.45 and 46 , the exposed portions of the conductor material 43 and the undoped polysilicon 51 of the conductor layer 16 have been oxidized, thereby forming an insulating oxide 45 (eg, silicon dioxide; for example, longitudinally along what would be line 13e).

[0054] Afterwards, refer to Fig.47 , horizontally extended wires 13e have been formed in recesses 79 and are respectively between laterally adjacent memory block regions 58. The example wires 13e include second sacrificial material 15. In one embodiment, the bottom surface 59 of the individual wires 13e is in the conductor layer 16, and in one such embodiment, is not directly against its conductor material (e.g., due to the presence of insulating oxide 45).

[0055] Similar and / or alternative processing to that shown and described above may occur to produce Fig.48 The structure 10e shown (which corresponds in sequence and view to the first described embodiment) Fig.35 Any other attributes or aspects as shown and / or described herein with respect to other embodiments may be used.

[0056] refer to Figures 49 to 53 Description Reference Figures 44 to 48 Alternatives to the methods shown and described. Like reference numerals from the embodiments described above have been used where appropriate, with certain construction differences indicated by a suffix "f" or by a different reference numeral. Fig.49 and 50 In the processing sequence, the Fig.44 and 46The undoped polysilicon 51 has been recessed laterally (eg, by isotropic etching) to form laterally opposing notches 78 longitudinally along the individual grooves 79. In one embodiment, the laterally opposing notches 78 have also been formed in the conductor material 17 as shown.

[0057] refer to Fig.51 and 52 , horizontally extending wires 13f (including second sacrificial material 15) have been formed in recesses 79 and respectively between laterally adjacent memory blocks 58. Wires 13f respectively include laterally opposing protrusions 66 longitudinally along them in laterally opposing recesses 78. In one embodiment, wires 13f include bottom surfaces 59 in conductor layer 16. In one embodiment where laterally opposing recesses 78 have also been formed in conductor material 43, wires 13f also respectively include laterally opposing protrusions 54 longitudinally along them in laterally opposing recesses 78 in conductor material 43.

[0058] Similar and / or alternative processing to that shown and described above may occur to produce Fig.53 The structure 10f shown (which corresponds in sequence and view to the first described embodiment) Fig.35 Any other attributes or aspects as shown and / or described herein with respect to other embodiments may be used.

[0059] In some embodiments, a method for forming a memory array (e.g., 12) including a string (e.g., 49) of memory cells (e.g., 56) includes forming a lower portion (e.g., 18L) of a stack (e.g., 18*), which will include a vertically alternating first layer (e.g., 22*) and a second layer (e.g., 20*). The stack includes laterally spaced memory blocks (e.g., 58). The material of the first layer has a different composition than the material of the second layer. Pillars (e.g., 60) are formed in the lower portion and are horizontally positioned, respectively, where individual channel material string structures (e.g., 53) are to be formed. The pillars include sacrificial material (e.g., 15). The vertically alternating first and second layers of the upper portion (e.g., 18U) of the stack are formed above the lower portion and the pillars. Channel openings (e.g., 25) are formed into the stack and extend to individual pillars, respectively. The sacrificial material of the pillars is removed by the channel openings to extend the channel openings deeper into the stack. Channel material string structures are formed in the elongated channel openings and in the void spaces therein created by the removal of the pillars.Any other attributes or aspects as shown and / or described herein with respect to other embodiments may be used.

[0060] In some embodiments, a method for forming a memory array (e.g., 12) including a string (e.g., 49) of memory cells (e.g., 56) includes forming a conductor layer (e.g., 16) including a conductor material (e.g., 17) on a substrate (e.g., 11). A lower portion (e.g., 18L) of a stack (e.g., 18*) including a vertically alternating first layer (e.g., 22*) and a second layer (e.g., 20*) is formed above the conductor layer. The stack includes laterally spaced memory blocks (e.g., 58). The material of the first layer has a different composition than the material of the second layer. The lowermost first layer (e.g., 22z) includes a first sacrificial material (e.g., 77). Pillars (e.g., 60) are formed in the lowermost first layer and are horizontally positioned, respectively, where individual channel material string structures (e.g., 53) are to be formed. The pillars include a second sacrificial material (e.g., 15). The vertically alternating first and second layers of the upper portion (e.g., 18U) of the stack are formed above the lower portion and the pillars. Channel openings (e.g., 25) are formed into the stack and extend to individual pillars, respectively. The second sacrificial material of the pillars is removed through the channel openings to extend the channel openings deeper into the stack. A channel material string structure is formed in the extended channel openings and in the void space therein created by removing the pillars. Horizontally extended grooves (e.g., 40) are formed into the stack and extend to the first sacrificial material in the first layer of the lowermost portion, respectively, between the memory blocks that are immediately adjacent in the transverse direction. The first sacrificial material is isotropically etched from the first layer of the lowermost portion through the grooves. After the isotropic etching, a conductive material (e.g., 42) is formed in the first layer of the lowermost portion, which electrically couples the channel material of the individual channel material string structure directly with the conductor material of the conductor layer. Any other attributes or aspects as shown and / or described herein with respect to other embodiments may be used.

[0061] Alternative embodiment configurations may result from the method embodiments described above or otherwise. Regardless, embodiments of the invention encompass memory arrays that are independent of fabrication methods. Nevertheless, such memory arrays may have any of the properties described herein in the method embodiments. Likewise, the method embodiments described above may incorporate, form, and / or have any of the properties described with respect to the device embodiments.

[0062] In one embodiment, a memory array (e.g., 12) including strings (e.g., 49) of memory cells (e.g., 56) includes a conductor layer (e.g., 16) including a conductor material (e.g., 17). The memory array includes laterally spaced memory blocks (e.g., 58) each including a vertical stack (e.g., 18*) including alternating insulating layers (e.g., 20*) and conductive layers (e.g., 22*). Channel material string structures (e.g., 53) of the memory cells extend through the insulating and conductive layers. The channel material string structures each include an upper portion (e.g., 70) above and joined to a lower portion (e.g., 72). Individual channel material string structures include at least one external bend surface (e.g., 75, 75a, 75b, 75c) in a vertical cross-section where the upper and lower portions are joined. Any other attributes or aspects as shown and / or described herein with respect to other embodiments may be used.

[0063] The above-described processing or construction may be viewed as an array of components formed as or within a single stack or single layer of such components, the stack or layer being above or as part of an underlying base substrate (although a single stack / layer may have multiple layers). Control and / or other peripheral circuitry for operating or accessing such components within the array may also be formed at any location as part of the final construction, and in some embodiments may be below the array (e.g., CMOS below the array). In any case, one or more additional such stacks / layers may be provided or fabricated above and / or below the stacks / layers shown in the figures or described above. In addition, the arrays of components may be the same or different in different stacks / layers relative to each other, and different stacks / layers may have the same thickness or different thickness relative to each other. Intervening structures may be disposed between vertically adjacent stacks / layers (e.g., additional circuitry and / or dielectric layers). Also, different stacks / layers may be electrically coupled relative to each other. Multiple stacks / layers may be fabricated individually and sequentially (e.g., one on top of another), or two or more stacks / layers may be fabricated substantially simultaneously.

[0064] The assemblies and structures discussed above can be used in integrated circuits / circuitry systems and can be incorporated in electronic systems. Such electronic systems can be used, for example, in memory modules, device drivers, power modules, communication modems, processor modules, and application-specific modules, and can include multi-layer, multi-chip modules. The electronic system can be any of a wide range of systems such as cameras, wireless devices, displays, chipsets, set-top boxes, games, lighting systems, vehicles, clocks, televisions, cellular phones, personal computers, automobiles, industrial control systems, aircraft, and the like.

[0065] In this document, unless otherwise indicated, "vertical", "higher", "upper", "lower", "top", "top", "bottom", "above", "below", "under", "under", "upward", and "downward" generally refer to the vertical direction. "Horizontal" refers to the general direction along the surface of the main substrate that the substrate can be processed relative to during manufacturing (i.e., within 10 degrees), and vertical is a direction generally orthogonal thereto. Reference to "just horizontal" is a direction along the surface of the main substrate that the substrate can be processed relative to during manufacturing (i.e., not at an angle thereto). In addition, "vertical" and "horizontal" as used herein are generally perpendicular directions relative to each other and are independent of the orientation of the substrate in three-dimensional space. In addition, "vertically extending" and "vertically extending" refer to a direction inclined at least 45° from just horizontal. In addition, with respect to a field effect transistor, "vertically extending", "vertically extending", "horizontally extending", "horizontally extending", etc. are references to the orientation of the channel length of the transistor, and in operation, current flows between the source / drain regions along the orientation. For bipolar junction transistors, "extending vertically", "extending vertically", "extending horizontally", "extending horizontally", etc. are reference to the orientation of the substrate length along which current flows between the emitter and the collector in operation. In some embodiments, any component, feature, and / or region extending vertically extends vertically or within 10° of vertical.

[0066] Furthermore, "directly above," "directly below," and "directly below" require at least some lateral overlap (i.e., horizontally) of the two stated areas / materials / components relative to each other. Moreover, the use of "above" without a preceding "directly" requires only that some portion of the stated area / material / component that is above another stated area / material / component is vertically outward of the other stated area / material / component (i.e., regardless of whether there is any lateral overlap of the two stated areas / materials / components). Similarly, the use of "below" and "beneath" without a preceding "directly" requires only that some portion of the stated area / material / component that is below / beneath another stated area / material / component is vertically inward of the other stated area / material / component (i.e., regardless of whether there is any lateral overlap of the two stated areas / materials / components).

[0067] Any of the materials, regions, and structures described herein may be uniform or non-uniform, and in any case may be continuous or discontinuous over any material overlying it. When one or more example compositions are provided for any material, the material may include, consist essentially of, or consist of such one or more compositions. In addition, unless otherwise stated, each material may be formed using any suitable existing or future developed technology, with atomic layer deposition, chemical vapor deposition, physical vapor deposition, epitaxial growth, diffusion doping, and ion implantation being examples.

[0068] In addition, "thickness" (without a directional adjective in front) used alone is defined as the average straight-line distance perpendicularly passing through a given material or region from the closest surface of an adjacent material or adjacent region with different compositions. In addition, the various materials or regions described herein may have a substantially constant thickness or a variable thickness. If there is a variable thickness, then unless otherwise indicated, the thickness refers to the average thickness, and the material or region will have a certain minimum thickness and a certain maximum thickness due to the variable thickness. As used herein, "different compositions" only require that those parts of the two stated materials or regions that can directly abut against each other are chemically and / or physically different, such as when such materials or regions are not uniform. If the two stated materials or regions do not directly abut against each other, then when such materials or regions are not uniform, "different compositions" only require that those parts of the two stated materials or regions that are closest to each other are chemically and / or physically different. In this document, when the stated materials, regions or structures are in at least some physical contact with each other, the material, region or structure "directly abuts" another material, region or structure. In contrast, “over,” “on,” “adjacent,” “along,” and “against” without being preceded by “directly” encompass “directly against” as well as configurations in which intervening materials, regions, or structures are such that the stated materials, regions, or structures are not in physical contact with each other.

[0069] Herein, region-material-components are "electrically coupled" with respect to one another if, in normal operation, electrical current is able to flow continuously from one region-material-component to another, and the flow occurs primarily through the movement of subatomic positive and / or negative charges when sufficient subatomic positive and / or negative charges are generated. Another electronic component may be between the region-material-components and electrically coupled to the region-material-components. In contrast, when region-material-components are referred to as "directly electrically coupled," there are no intervening electronic components (e.g., no diodes, transistors, resistors, transducers, switches, fuses, etc.) between the directly electrically coupled region-material-components.

[0070] Any use of "rows" and "columns" herein is for convenience in distinguishing one series or orientation of features from another series or orientation of features, and components have been or may be formed along such "rows" and "columns". "Rows" and "columns" are used synonymously with respect to any series of regions, components and / or features, regardless of function. Regardless, rows may be straight and / or curved and / or parallel and / or non-parallel relative to each other, as may columns. Furthermore, rows and columns may intersect at 90° relative to each other, or at one or more other angles (i.e., other than straight angles).

[0071] The composition of any one of the conductive / conductor / conductive materials herein may be a metallic material and / or a conductive doped semiconductive / semiconductive / semiconductive material. "Metallic material" is any one or combination of an elemental metal, any mixture or alloy of two or more elemental metals, and any one or more conductive metal compounds.

[0072] As used herein, any use of "selective" with respect to etching / etching, removing / removal, depositing, forming / formation is such action performed on one stated material relative to another stated material acted upon at a ratio of at least 2:1 by volume. Additionally, any use of selectively depositing, selectively growing, or selectively forming is deposition, growth, or formation of one material relative to another stated material or materials for at least the first 75 angstroms at a ratio of at least 2:1 by volume.

[0073] Unless otherwise indicated, the use of "or" herein includes either and both.

[0074] in conclusion

[0075] In some embodiments, a method for forming a memory array including a memory cell string includes: forming a lower portion of a stack including a vertically alternating first layer and a second layer on a substrate. The stack includes memory blocks spaced laterally apart. The material of the first layer has a composition different from that of the material of the second layer. Pillars are formed in the lower portion and are horizontally positioned, respectively, wherein individual channel material string structures are formed. The pillars include sacrificial material. The vertically alternating first and second layers of the upper portion of the stack are formed above the lower portion and the pillars. Channel openings are formed into the stack and extend to individual pillars, respectively. The sacrificial material of the pillars is removed through the channel openings to extend the channel openings deeper into the stack. The channel material string structure is formed in the extended channel openings and in the void space therein created by the removal.

[0076] In some embodiments, a method for forming a memory array including a memory cell string includes forming a conductor layer including a conductor material on a substrate. A lower portion of a stack including a first layer and a second layer that alternate vertically is formed above the conductor layer. The stack includes memory blocks that are spaced apart laterally. The material of the first layer has a composition different from that of the material of the second layer. The first layer at the bottom includes a first sacrificial material. Pillars are formed in the first layer at the bottom and are horizontally positioned, respectively, where individual channel material string structures are to be formed. Pillars include a second sacrificial material. The first layer and the second layer of the vertically alternating upper portion of the stack are formed above the lower portion and the pillars. Channel openings are formed into the stack and extend to individual pillars, respectively. The second sacrificial material of the pillars is removed through the channel openings to extend the channel openings deeper into the stack. The channel material string structure is formed in the extended channel openings and in the void space therein created by the removal. Horizontally extended trenches are formed into the stack and are respectively between the memory blocks that are adjacent laterally and extend to the first sacrificial material in the first layer at the bottom. The first sacrificial material is isotropically etched from the first layer at the bottom through the trenches. After the isotropic etching, a conductive material is formed in the lowermost first layer, the conductive material directly electrically coupling the channel material of the individual channel material string structures with the conductor material of the conductor layer.

[0077] In some embodiments, a method for forming a memory array including a memory cell string includes forming a conductor layer including a conductor material on a substrate. A lower portion of a stack including a vertically alternating first layer and a second layer is formed above the conductor layer. The stack includes memory blocks spaced laterally apart. The material of the first layer has a composition different from the material of the second layer. The lowermost first layer includes a first sacrificial material. The second lowermost first layer includes conductively doped polysilicon. Horizontally extended lines are formed in the second lowermost first layer, the horizontally extended lines are respectively between laterally adjacent memory blocks. The line includes a second sacrificial material, the second sacrificial material having a composition different from the material of the first layer formed or to be formed above the first sacrificial material, the material of the second layer formed or to be formed above the first sacrificial material, and the material of the second lowermost first layer. The vertically alternating first and second layers of the upper portion of the stack are formed above the lower portion and the line. A channel material string structure is formed, the channel material string structure extending through the first and second layers in the upper portion to the lowermost first layer in the lower portion. Horizontally extended trenches are formed into the stack, the horizontally extended trenches being respectively between laterally adjacent memory blocks and extending to the lines between the memory blocks. The second sacrificial material of the lines is removed through the trenches. Intervening material is formed in the trenches and in the void space left by the removal of the second sacrificial material of the lines.

[0078] In some embodiments, a method for forming a memory array including a memory cell string includes forming a conductor layer including a conductor material on a substrate. A lower portion of a stack including a vertically alternating first layer and a second layer is formed above the conductor layer. The stack includes memory blocks spaced laterally apart. The material of the first layer has a composition different from that of the material of the second layer. The first layer at the bottom includes a first sacrificial material. The second layer material of the second layer directly above the first layer at the bottom includes undoped polysilicon. A horizontally extended groove is formed in the bottom portion and extends to the conductor layer. The exposed portions of the conductor material and the undoped polysilicon of the conductor layer are oxidized. After oxidation, a horizontally extended line is formed in the groove between the memory blocks adjacent to each other laterally. The line includes a second sacrificial material. The vertically alternating first and second layers of the upper portion of the stack are formed above the lower portion and the line. A channel material string structure is formed, which extends through the first and second layers in the upper portion to the first layer at the bottom portion in the lower portion. Horizontally extended trenches are formed into the stack, the horizontally extended trenches being respectively between laterally adjacent memory blocks and extending to the lines between the memory blocks. The second sacrificial material of the lines is removed through the trenches. Intervening material is formed in the trenches and in the void space left by the removal of the second sacrificial material of the lines.

[0079] In some embodiments, a method for forming a memory array including a memory cell string includes forming a conductor layer including a conductor material on a substrate. A lower portion of a stack including a vertically alternating first layer and a second layer is formed above the conductor layer. The stack includes memory blocks spaced laterally apart. The material of the first layer has a composition different from that of the material of the second layer. The first layer of the lowermost portion includes a first sacrificial material. The second layer material of the second layer directly above the first layer of the lowermost portion includes undoped polysilicon. A horizontally extended groove is formed in the lowermost portion and extends to the conductor layer. The undoped polysilicon is laterally recessed to form laterally opposite recesses longitudinally along the individual grooves. After the recessing, horizontally extended lines are formed in the grooves between the memory blocks adjacent to each other laterally. The lines respectively include laterally opposite protrusions longitudinally along them in the laterally opposite recesses. The lines include a second sacrificial material. The vertically alternating first and second layers of the upper portion of the stack are formed above the lower portion and the lines. A channel material string structure is formed, which extends through the first and second layers in the upper portion to the lowermost first layer in the lower portion. Horizontally extended trenches are formed into the stack, the horizontally extended trenches being respectively between laterally adjacent memory blocks and extending to the lines between the memory blocks. The second sacrificial material of the lines is removed through the trenches. Intervening material is formed in the trenches and in the void space left by the removal of the second sacrificial material of the lines.

[0080] In some embodiments, a memory array including strings of memory cells includes laterally spaced memory blocks, each of which includes a vertical stack including alternating insulating layers and conductive layers. Channel material string structures of the memory cells extend through the insulating layers and the conductive layers. The channel material string structures each include an upper portion above and joined to a lower portion. Individual channel material string structures include at least one external bend surface in a vertical cross-section where the upper and lower portions are joined.

[0081] As specified, the subject matter disclosed herein has been described in language more or less specific with respect to structural and methodological features. However, it should be understood that the claims are not limited to the specific features shown and described, as the apparatus disclosed herein includes example embodiments. Therefore, the claims have the full scope as written and should be appropriately interpreted in accordance with the doctrine of equivalents.

Claims

1. A method for forming a memory array including a string of memory cells, comprising: forming a lower portion of a stack of vertically alternating first and second layers on a substrate, the stack including laterally spaced memory blocks, the material of the first layers having a different composition than the material of the second layers; forming pillars in the lower portion, the pillars being respectively horizontally positioned where individual channel material string structures are to be formed, the pillars comprising a sacrificial material; forming the vertically alternating first and second layers of an upper portion of the stack above the lower portion and the struts; forming channel openings into the stack and extending to respective ones of the pillars; removing the sacrificial material of the pillar through the trench opening to extend the trench opening deeper into the stack; forming a string structure of channel material in said extended channel opening and in void spaces therein created by said removing; wherein the channel material string structures each include an upper portion above and joined to a lower portion, each of the channel material string structures including at least one external bending surface in a vertical cross-section where the upper portion and the lower portion are joined; and The at least one outer bending surface is more than 10° from horizontal. The method of claim 1 , wherein the sacrificial material comprises a metallic material. The method of claim 2 , wherein the metallic material comprises elemental tungsten.

4. The method of claim 1, wherein the at least one exterior bending surface is at least 22.5° from horizontal.

5. The method of claim 4, wherein the at least one outer bending surface is at least 45° from horizontal.

6. The method of claim 5, wherein the at least one outer bending surface is at 45° to horizontal.

7. The method of claim 1 including only one external bending surface in the vertical cross-section of the individual channel material string structures.

8. The method of claim 1, including two external bending surfaces in the vertical cross-section in the individual channel material string structures, the two external bending surfaces being differently inclined from vertical relative to each other.

9. The method of claim 8, wherein one of the two outer bending surfaces is horizontal and the other of the two outer bending surfaces is not horizontal.

10. A method for forming a memory array including strings of memory cells, comprising: forming a conductor layer including a conductor material on a substrate; forming above the conductor layer a lower portion of a stack that will include vertically alternating first and second layers, the stack including laterally spaced memory blocks, the first layers having a material having a different composition than the second layers, the lowermost first layer including a first sacrificial material; forming pillars in the lowermost first layer, the pillars being respectively horizontally positioned where individual channel material string structures will be formed, the pillars comprising a second sacrificial material; forming the vertically alternating first and second layers of an upper portion of the stack above the lower portion and the struts; forming channel openings into the stack and extending to respective ones of the pillars; removing the second sacrificial material of the pillar through the trench opening to extend the trench opening deeper into the stack; forming a string structure of channel material in said extended channel opening and in void spaces therein created by said removing; forming horizontally-elongated trenches into the stack, the horizontally-elongated trenches respectively between laterally adjacent memory block regions and extending into the first sacrificial material in the lowermost first layer; isotropically etching the first sacrificial material from the lowermost first layer through the trench; After the isotropic etching, forming a conductive material in the lowermost first layer, the conductive material directly electrically coupling the channel material of the individual channel material string structures with the conductor material of the conductor layer; The channel material string structures each include an upper portion above and joined to a lower portion, each of the channel material string structures including at least one external bend surface in a vertical cross-section where the upper portion and the lower portion join; and The at least one outer bending surface is more than 10° from horizontal.

11. The method of claim 10, wherein the second sacrificial material has a different composition than the first sacrificial material, the first layer of material formed or to be formed over the first sacrificial material, and the second layer of material formed or to be formed over the first sacrificial material.

12. The method of claim 10, including only one external bending surface in the vertical cross-section of the individual channel material string structure.

13. The method of claim 10, wherein the pillars each include an uppermost surface above the lowermost first layer. The method of claim 10 , wherein each of the pillars has a bottom surface in or at a top portion of the conductor layer. The method of claim 14 , wherein the bottom surface directly abuts the conductor material.

16. The method of claim 10, wherein the lowermost first layer does not directly abut the conductor material of the conductor layer during the isotropic etching.

17. The method of claim 10, wherein a lowermost surface of the channel material of the channel material string structure never directly abuts against any of the conductor materials in the conductor layer.

18. The method of claim 10, wherein the conductive material in the lowermost first layer directly abuts against a sidewall of the channel material of the channel material string structure.

19. The method of claim 10, wherein the conductive material in the lowermost first layer directly abuts an uppermost surface of the conductive material of the conductor layer.

20. The method of claim 10, wherein the at least one exterior bending surface is at least 22.5° from horizontal.

21. The method of claim 20, wherein the at least one outer bending surface is at least 45° from horizontal.

22. The method of claim 21, wherein the at least one outer bending surface is at 45° to horizontal.

23. The method of claim 10, including only one external bending surface in the vertical cross-section of the individual channel material string structure.

24. The method of claim 10, including two external bending surfaces in the vertical cross-section in the individual channel material string structures, the two external bending surfaces being differently inclined from vertical relative to each other.

25. The method of claim 24, wherein one of the two outer bending surfaces is horizontal and the other of the two outer bending surfaces is not horizontal.

26. A memory array comprising a string of memory cells, comprising: laterally spaced memory blocks each comprising a vertical stack including insulating and conductive layers alternating above a conductor layer, channel material string structures of memory cells extending through the insulating and conductive layers, channel material of the channel material string structures being directly electrically coupled to conductor material of the conductor layer; and The channel material string structures respectively include an upper portion above a lower portion between the lowest and second lowest portions of the conductive layer and joined to the lower portion, and each of the channel material string structures includes two and only two external bending surfaces between the lowest and second lowest portions of the conductive layer in a vertical cross-section where the upper and lower portions are joined.

27. The memory array of claim 26, wherein at least one of the two outer bending surfaces is horizontal or within 10° of horizontal.

28. The memory array of claim 26 wherein the individual channel material string structures have exterior sidewall surfaces that pass directly through a plurality of the insulating layers and a plurality of the conductive layers in the vertical cross-section above the two exterior bent surfaces.

29. The memory array of claim 26 wherein the other of the two outer bending surfaces is more than 10° from horizontal.

30. The memory array of claim 29 wherein the other of the two outer bending surfaces is at least 22.5° from horizontal.

31. The memory array of claim 30, wherein at least one of the other of the two outer bending surfaces is at least 45° from horizontal.

32. The memory array of claim 26 wherein the two outer bending surfaces are differently inclined from vertical relative to each other.

33. The memory array of claim 32, wherein one of the two outer bending surfaces is horizontal and the other of the two outer bending surfaces is not horizontal.

34. The memory array of claim 26 wherein the two outer bending surfaces are equally inclined from vertical relative to each other.

35. The memory array of claim 34 wherein the two outer bending surfaces are horizontal.

36. The memory array of claim 34 wherein neither of the two outer bending surfaces is horizontal.

37. A memory array comprising a string of memory cells, comprising: laterally spaced memory blocks each comprising a vertical stack including insulating and conductive layers alternating above a conductor layer, channel material string structures of memory cells extending through the insulating and conductive layers, channel material of the channel material string structures being directly electrically coupled to conductor material of the conductor layer; and The channel material string structures respectively include an upper portion above a lower portion between the lowest and the second lowest of the conductive layer and joined to the lower portion, and each of the channel material string structures includes one and only one external bending surface between the lowest and the second lowest in the conductive layer in a vertical cross-section where the upper portion and the lower portion are joined.

38. The memory array of claim 37, wherein the one outer bending surface is horizontal or within 10° of horizontal.

39. The memory array of claim 38, wherein the one outer bending surface is horizontal.

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