A gate drive circuit and method with controllable switching speed

Abstract

The present invention discloses a gate drive circuit with controllable switching speed, which includes a switching transistor, and a main drive circuit coupled to the switching transistor for controlling the gate drive of the switching transistor; a switching speed control circuit coupled to the switching transistor for controlling the switching frequency of the switching transistor; the switching speed control circuit includes a feedback capacitor coupled to the switching transistor; the switching speed control circuit adjusts the gate current of the switching transistor during turn-on and the charging current of the drain-source capacitor of the switching transistor during turn-off by adjusting the capacitance value of the feedback capacitor, thereby controlling the turn-on speed and turn-off speed of the switching transistor. The present invention coordinates the switching speed and switching loss, and has the characteristics of fast response speed, simplicity and reliability.

Description

Technical Field

[0001] The present invention relates to the field of electronic information, and particularly to a gate drive circuit and method with controllable switching speed. Background Art

[0002] A switch mode power supply (SMPS) is a high-frequency power conversion device. Different from a linear power supply, a switch mode power supply uses switching transistors that mostly switch between a fully-on mode (saturation region) and a fully-off mode (cut-off region), both of which have the characteristics of low loss, solving the problems of heat and efficiency. However, the resulting electromagnetic interference (EMI) problems are caused by high drain-source voltage change rate dv / dt and drain-source current change rate di / dt.

[0003] There are many ways to solve the electromagnetic interference problem of a switch mode power supply. An important means is to start from transistor drive and reduce the drain-source voltage change rate dv / dt and drain-source current change rate di / dt at the source. The most common method is to adjust the gate drive resistance Rg, reduce the drive current, and lower the switching speed; another method is to connect a capacitor in parallel with the gate, which can also reduce the turn-on and turn-off speeds.

[0004] In addition, there is also a method of connecting a capacitor in parallel with the output of the switching transistor, such as connecting a capacitor between the drain and source of a MOS transistor; this method can reduce the drain-source voltage change rate dv / dt during turn-off, and has little effect on the drain-source voltage change rate dv / dt during turn-on; this is because the drain-source voltage change rate dv / dt of a MOS transistor during turn-on depends more on the gate parasitic capacitance Cgd. Usually, in order to reduce the switching speed, increasing the gate parasitic capacitance Cgd can effectively slow down the drain-source voltage change rate dv / dt during turn-on and turn-off, but it is easy to cause the problem of cross-conduction between the upper and lower transistors in a half-bridge unit structure, which will increase the switching loss at least and burn out the device at worst, resulting in a serious reduction in reliability.

[0005] Although the traditional method of adjusting the gate drive resistance Rg can reduce the turn-on speed, the price paid is the sacrifice of switching loss. Moreover, changing the gate drive resistance Rg essentially has only one degree of freedom and cannot independently change the drain-source voltage change rate dv / dt and drain-source current change rate di / dt respectively. For example, Figure 1 The conventional gate drive circuit shown is a typical voltage source series resistance drive circuit, that is, a traditional double-pulse circuit, Figure 2 and the corresponding turn-on and turn-off processes are shown.

[0006] As shown in Figure 1 and Figure 2As shown, when the driving signal for turning on comes at the first moment t1, the gate voltage Vgs starts to rise at this time; at the second moment t2, the gate voltage Vgs reaches the turn-on threshold voltage Vth, and the switching transistor Q starts to conduct; due to the parasitic capacitance and the reverse recovery phenomenon of the diode, there is a spike in the drain-source current isd flowing through the switching transistor Q between the second moment t2 and the third moment t3; after the third moment t3, the drain-source current isd is approximately equal to the load current, and the drain-source voltage Vds starts to drop to 0 until it completely drops to 0 at the fourth moment t4. Between the third moment t3 and the fourth moment t4, the gate voltage Vgs is approximately constant, and this voltage at this time is called the Miller plateau voltage Vpl, and all the current provided by the drive flows through the gate parasitic capacitance Cgd. After the fourth moment t4, the gate voltage Vgs continues to rise to the steady state, and the steady state corresponds to the fifth moment t5.

[0007] As shown in the appendix Figure 1 and the appendix Figure 2 As shown, the turn-off process is the opposite of the turn-on process. When the turn-off driving signal comes at the sixth moment t6, the gate voltage Vgs drops. At the seventh moment t7, the gate voltage Vgs is equal to the Miller plateau voltage Vpl. At this time, the drain-source voltage Vds rises, and the current flowing through the gate parasitic capacitance Cgd is equal to the current on the gate driving resistor Rg. At the eighth moment t8, the drain-source voltage Vds rises to the stable voltage, the drain-source current isd starts to drop, and at the same time the gate voltage Vgs also gradually drops until the drain-source current isd drops to 0 at the ninth moment t9, and the gate voltage Vgs is lower than the turn-on threshold. Between the ninth moment t9 and the tenth moment t10, the gate voltage Vgs continues to decrease until it decreases to 0 at the tenth moment t10.

[0008] Adopting the conventional method of increasing the gate driving resistor Rg to alleviate the switching speed will make each of the above processes slower now. As shown in the appendix Figure 3 As shown, in the turn-on process, the dotted line represents the timing corresponding to increasing the gate driving resistor Rg. Since the gate driving resistor Rg increases, the gate charging current from the turn-on threshold to the Miller plateau becomes smaller, and the rate of change of the drain-source current di / dt slows down. Similarly, the current during the Miller plateau period is also limited by the resistor. The rate of change of the drain-source voltage dv / dt across the gate parasitic capacitance Cgd slows down, and the rate of change of the drain-source voltage dv / dt of the output voltage is the same as that of the Miller capacitance voltage.

[0009] However, in practical applications, the conducted common-mode interference sometimes only needs to reduce the rate of change of the drain-source voltage dv / dt. The method of adjusting the gate driving resistor Rg increases the time of the rate of change of the drain-source current di / dt process, brings additional switching losses, and exacerbates the heat dissipation problem. At the same time, this method also increases the turn-on delay time, which also has potential adverse factors on the stability of control. Summary of the Invention

[0010] In view of the deficiencies in the prior art, the present invention provides a gate drive circuit and method with controllable switching speed.

[0011] To solve the above technical problems, the present invention is solved by the following technical solutions:

[0012] The present invention provides a gate drive circuit, including: a switching transistor; a main drive circuit coupled to the switching transistor for controlling the gate drive of the switching transistor; and a switching speed control circuit coupled to the switching transistor for controlling the switching speed of the switching transistor. Wherein, the switching speed control circuit includes a feedback capacitor coupled to the switching transistor; the switching speed control circuit adjusts the gate current of the switching transistor during turn-on and the charging current of the drain-source capacitance of the switching transistor during turn-off by adjusting the capacitance value of the feedback capacitor, thereby controlling the turn-on speed and turn-off speed of the switching transistor.

[0013] Optionally, the switching speed control circuit further includes a first diode and a second diode; the anode of the second diode is coupled to the gate of the switching transistor, the feedback capacitor is coupled between the cathode of the second diode and the drain of the switching transistor; the cathode of the second diode is further coupled to the anode of the first diode, and the cathode of the first diode is coupled to the positive pole of the drive auxiliary power supply.

[0014] Optionally, the main drive circuit includes a gate drive resistor, a pulse drive source, and the auxiliary power supply; the gate drive resistor is coupled between the output terminal of the pulse drive source and the gate of the switching transistor; the gate drive resistor is coupled to the gate of the switching transistor; the ground terminal of the pulse drive source and the ground terminal of the auxiliary power supply are coupled to the source of the switching transistor.

[0015] Optionally, the source of the switching transistor is grounded through a negative voltage.

[0016] Optionally, a first damping resistor or a magnetic bead is electrically connected between the cathode of the second diode and the feedback capacitor, and the common connection of the cathode of the second diode and the first damping resistor is coupled to the anode of the first diode.

[0017] Optionally, a second damping resistor or a magnetic bead is electrically connected between the cathode of the second diode and the feedback capacitor, and the common connection of the feedback capacitor and the second damping resistor is coupled to the anode of the first diode.

[0018] Optionally, a gate turn-off series circuit is connected in parallel across the gate drive resistor; the gate turn-off series circuit includes a gate turn-off resistor and a fourth diode connected in series, the anode of the fourth diode is coupled to the gate of the switching transistor, and the cathode of the fourth diode is coupled to the pulse drive source.

[0019] The present invention also discloses a half-bridge drive circuit, including a first gate drive circuit for driving an upper switching transistor and a second gate drive circuit for driving a lower switching transistor; the first gate drive circuit and the second gate drive circuit are respectively the gate drive circuits as described in any of the foregoing.

[0020] The present invention also discloses a gate drive method for controlling the switching speed of a switching transistor by a gate drive circuit, which is characterized by including the following steps:

[0021] Receiving an on signal;

[0022] The second diode conducts, and the current flowing through the feedback capacitor flows to the drain of the switching transistor.

[0023] In the on Miller plateau stage, the conducting second diode shunts the feedback capacitor from the gate current of the switching transistor, and adjusts the gate current of the switching transistor during turn-on by shunting, so as to control the voltage change of the switching transistor during turn-on, thereby controlling the turn-on speed.

[0024] Receiving an off signal;

[0025] The first diode conducts, and the current flowing through the feedback capacitor flows to the first diode.

[0026] In the off drain-source voltage change stage, the conducting first diode shunts the feedback capacitor from the charging current of the switching transistor, and adjusts the charging current of the drain-source capacitor of the switching transistor during turn-off by shunting, so as to control the voltage change of the switching transistor during turn-off, thereby controlling the turn-off speed.

[0027] Optionally, it further includes: adjusting the turn-on speed and turn-off speed of the switching transistor by adjusting the capacitance value of the feedback capacitor; the larger the capacitance value of the connected feedback capacitor, the slower the turn-on speed and turn-off speed.

[0028] Optionally, it further includes: changing the change rate of the drain-source current of the switching transistor during turn-on by changing the resistance value of the gate drive resistor.

[0029] 1. In the case where the gate drive resistor is fixed, the present invention adjusts the change rate of the drain-source voltage of the switching transistor by adjusting the size of the feedback capacitor, so as to realize the adjustment of the switching speed of the switching transistor.

[0030] 2. The present invention can balance the switching speed and switching loss while reducing the switching speed, so that the losses generated during the turn-on process and turn-off process are not too large.

[0031] 3. The present invention determines the change rate of the drain-source current, i.e., the drain-source current change rate, by adjusting the value of the gate drive resistance. Therefore, this embodiment can independently control the drain-source current change rate and the drain-source voltage change rate of the switching transistor, featuring fast response speed, simplicity, and reliability.

[0032] Additional aspects and advantages of the present invention will be given in part in the following description, become apparent in part from the following description, or be learned through the practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] The drawings described herein are used to provide a further understanding of the present invention, form a part of this application, and the schematic embodiments and descriptions thereof are used to explain the present invention without unduly limiting the present invention. In the drawings:

[0034] Figure 1 A circuit schematic diagram of a conventional gate drive circuit in the background art is shown;

[0035] Figure 2 is a waveform diagram of the turn-on and turn-off processes of the conventional gate drive circuit;

[0036] Figure 3 is a waveform diagram of the turn-on process of the conventional gate drive circuit after increasing the gate drive resistance;

[0037] Figure 4 A circuit schematic diagram of the gate drive circuits of Embodiment 1 and Embodiment 7 of the present invention is shown;

[0038] Figure 5 A schematic diagram of the current flow direction during the turn-on process of the gate drive circuits of Embodiment 1 and Embodiment 7 of the present invention is shown;

[0039] Figure 6 A schematic diagram of the current flow direction during the turn-off process of the gate drive circuits of Embodiment 1 and Embodiment 7 of the present invention is shown;

[0040] Figure 7 A waveform diagram of the turn-on and turn-off processes of the gate drive circuits of Embodiment 1 and Embodiment 7 of the present invention is shown;

[0041] Figure 8 A circuit schematic diagram of the gate drive circuit of Embodiment 2 of the present invention is shown;

[0042] Figure 9 A circuit schematic diagram of the gate drive circuit of Embodiment 3 of the present invention is shown;

[0043] Figure 10 A circuit schematic diagram of the gate drive circuit of Embodiment 4 of the present invention is shown;

[0044] Figure 11Shows the circuit schematic diagram of the gate drive circuit according to the fifth embodiment of the present invention;

[0045] Figure 12 Shows the circuit schematic diagram of the gate drive circuit according to the sixth embodiment of the present invention;

[0046] Figure 13 Shows the step schematic diagram of the gate drive method according to the seventh embodiment of the present invention Detailed implementation manners

[0047] To make the objectives, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are some but not all of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the described embodiments of the present invention without creative efforts shall fall within the scope of protection of the present invention.

[0048] Unless otherwise defined, the technical terms or scientific terms used herein shall have the ordinary meanings understood by those of ordinary skill in the art to which the present invention pertains. The "first", "second" and similar terms used in the specification and claims of this patent application for the present invention do not denote any order, quantity or importance, but are only used to distinguish different components.

[0049] "Coupled" or "connected" in the specification includes both direct connection and indirect connection. Indirect connection is a connection through an intermediate medium, such as a connection through an electrical conduction medium, which may have parasitic inductance or parasitic capacitance; indirect connection may also include a connection through other active devices or passive devices on the basis of achieving the same or similar functional purposes, such as a connection through a circuit or component such as a switch, a follower circuit, etc.

[0050] It should be understood that in Embodiment 1 and Embodiment 7, the reference to the attached Figure 4 and the attached Figure 7 In, the drain-source current ids is represented as isd in the attached Figure 7 In, which is the current reverse of the drain-source current ids.

[0051] Embodiment 1:

[0052] This embodiment discloses a gate drive circuit with controllable switching speed, which can, based on the traditional voltage gate drive circuit, achieve independent control of the drain-source current change rate di / dt and the drain-source voltage change rate dv / dt by adding a small number of devices. That is, it can independently change the drain-source voltage change rate dv / dt while keeping the original drain-source current change rate di / dt unchanged, thereby achieving a better balance between switching speed and switching loss. Among them, the drain-source current change rate di / dt is the change rate of the drain-source current ids; the drain-source voltage change rate dv / dt is the change rate of the drain-source voltage Vds of the switching transistor Q1. The present invention can reduce the switching speed while not overly increasing the switching loss. Among them, the switching speed of the switching transistor Q1 includes the turn-on speed and the turn-off speed.

[0053] In one embodiment, as shown in the appendix Figure 4 the gate drive circuit includes a main drive circuit 200, a switching speed control circuit 100, and a switching transistor Q1. The main drive circuit 200 is coupled to the switching transistor Q1 and is used to control the gate drive of the switching transistor Q1; the switching speed control circuit 100 is coupled to the switching transistor Q1 and is used to control the switching frequency of the switching transistor Q1. In addition, the switching speed control circuit 100 includes a feedback capacitor Cfb coupled to the switching transistor Q1. The switching speed control circuit 100 changes the gate current igs of the switching transistor Q1 during turn-on and the charging current of the drain-source capacitor Cds of the switching transistor Q1 during turn-off by changing the charging direction and capacitance value of the feedback capacitor Cfb, thereby controlling the turn-on speed and turn-off speed of the switching transistor Q1, that is, controlling the switching speed of the switching transistor Q1.

[0054] In one embodiment, as shown in the appendix Figure 4 the switching speed control circuit 100 further includes a first diode D1 and a second diode D2. Among them, the anode of the second diode D2 is coupled to the gate of the switching transistor Q1, the feedback capacitor Cfb is coupled between the cathode of the second diode D2 and the drain of the switching transistor Q1, and at the same time, the cathode of the second diode D2 is also coupled to the anode of the first diode D1, that is, the feedback capacitor Cfb, the anode of the first diode D1, and the cathode of the second diode D2 are commonly electrically connected at one end; the cathode of the first diode D1 is coupled to the positive pole of the driving auxiliary power supply VDD

[0055] In one embodiment, as shown in the appendix Figure 4As shown, the main body drive circuit 200 includes a gate drive resistor Rg, a pulse drive source VPWM, and an auxiliary power supply VDD. The gate drive resistor Rg is coupled between the output terminal of the pulse drive source VPWM and the gate of the switching transistor Q1. At the same time, the gate drive resistor Rg is also coupled to the anode of the second diode D2, that is, the gate drive resistor Rg, the gate of the switching transistor Q1, and the anode of the second diode D2 are commonly electrically connected at one end. The ground terminal of the pulse drive source VPWM and the ground terminal of the auxiliary power supply VDD are coupled to the source of the switching transistor Q1. The main body drive circuit 200 changes the drive current of the switching transistor Q1 by changing the resistance value of the gate drive resistor Rg. In addition, the drain of the switching transistor Q1 is connected to the DC power supply Vdc. The gate drive circuit of this embodiment includes a third diode D3 and a load (the load of this embodiment uses an inductor L). The anode of the third diode D3 is coupled to the drain of the switching transistor Q1, and the cathode of the third diode D3 is coupled to the positive electrode of the DC power supply Vdc. The inductor L is connected in parallel across the third diode D3.

[0056] During the turn-on process of the switching transistor Q1, the working mode is as shown in the Figure 5 equivalent circuit diagram and the Figure 7 working waveform diagram of the Figure 5 , and the current path is as shown by the dotted line in the Figure 7 . Among them, the solid line in the

[0057] is the turn-on and turn-off process of this embodiment, and the dotted line part at the same time coordinate as the solid line is the schematic of the turn-on and turn-off process of the traditional double-pulse circuit for reference. The turn-on process includes a first turn-on stage, a second turn-on stage, and a third turn-on stage.

[0058] Second turn-on stage: During the Miller plateau stage from the third moment T3 to the fourth moment T4, the second diode D2 conducts. Since the feedback current ifb of the feedback capacitor Cfb changes according to the formula: ifb = Cfb × (dv1 / dt), where "dv1 / dt" in the formula is the change rate of the feedback voltage across the feedback capacitor Cfb (i.e., the change rate of the feedback voltage Vfb), "Cfb" in the formula refers to the capacitance value of the feedback capacitor Cfb, and "ifb" in the formula refers to the magnitude of the feedback current ifb. The circuit where the second diode D2 is located provides the feedback current ifb for the feedback capacitor Cfb, enabling the change rate dv1 / dt of the feedback voltage on the feedback capacitor Cfb to obtain the feedback current ifb required for its change. Since part of the current flowing through the gate drive resistor Rg is drawn away by the feedback capacitor Cfb, the gate current igs that should originally be provided to the switching transistor Q1 decreases, resulting in a reduced turn-on speed of the switching transistor Q1. Among them, the capacitance value of the feedback capacitor Cfb determines the amount of current drawn from the gate of the switching transistor Q1; feedback capacitors Cfb with different capacitance values draw different amounts of current from the gate of the switching transistor Q1. Therefore, when the gate drive resistor Rg is fixed, adjusting the capacitance value of the feedback capacitor Cfb can adjust the magnitude of the feedback current ifb obtained by the feedback capacitor Cfb, thereby adjusting the magnitude of the gate current igs obtained by the switching transistor Q1, and thus can adjust the change rate dv / dt of the drain-source voltage of the switching transistor Q1, achieving the purpose of adjusting the turn-on speed of the switching transistor Q1.

[0059] Meanwhile, since the feedback current ifb flowing through the feedback capacitor Cfb during the second turn-on stage also flows through the switching transistor Q1, that is, it flows from the drain of the switching transistor Q1 through the switching transistor Q1, the turn-on current of the switching transistor Q1 is increased, ultimately resulting in an increase in turn-on loss, which is equivalent to adding the gate parasitic capacitance Cgd of the switching transistor Q1.

[0060] Third turn-on stage: During the stage from the fourth moment T4 to the fifth moment T5, the drive current provided by the pulse drive source VPWM is mainly used to charge the gate parasitic capacitance Cgd of the switching transistor Q1. Since the gate-source capacitance Cgs of the switching transistor Q1 is much larger than the feedback capacitor Cfb, this stage process has no difference from the traditional drive method.

[0061] During the turn-off process of the switching transistor Q1, the working mode is as shown in the equivalent circuit diagram attached Figure 6 and the working waveform diagram attached Figure 7 . The current path is as shown by the dotted arrows in the attachment Figure 6 and includes the first turn-off stage, the second turn-off stage, and the third turn-off stage.

[0062] The first turn-off stage: During the stage from the sixth moment T6 to the seventh moment T7, the working mode of the gate drive circuit of this embodiment is no different from the conventional drive. Therefore, during this stage, the rate of change of the drain-source current di / dt of the switching transistor Q1 can be determined by adjusting the value of the gate drive resistor Rg.

[0063] The second turn-off stage: During the Miller plateau stage from the seventh moment T7 to the eighth moment T8, the first diode D1 conducts. According to the formula for the change in the feedback current ifb of the feedback capacitor Cfb, the circuit where the first diode D1 is located provides the feedback current ifb to the feedback capacitor Cfb, so that the rate of change of the feedback voltage dv1 / dt on the feedback capacitor Cfb obtains the feedback current ifb required for its change. Since part of the charging current flowing through the switching transistor Q1 is drawn away by the feedback capacitor Cfb, the charging current that should originally be provided to the drain-source capacitor Cds of the switching transistor Q1 decreases, reducing the turn-off speed of the switching transistor Q1. Among them, the capacitance value of the feedback capacitor Cfb determines the magnitude of the current drawn from the charging current of the drain-source capacitor Cds of the switching transistor Q1; for feedback capacitors Cfb with different capacitance values, the magnitudes of the currents drawn from the charging current of the drain-source capacitor Cds of the switching transistor Q1 are different. Therefore, when the gate drive resistor Rg is fixed, adjusting the capacitance value of the feedback capacitor Cfb can adjust the magnitude of the feedback current ifb obtained by the feedback capacitor Cfb, thereby adjusting the magnitude of the charging current obtained by the switching transistor Q1, and thus the rate of change of the drain-source voltage dv / dt of the switching transistor Q1 can be adjusted, achieving the purpose of adjusting the turn-off speed of the switching transistor Q1.

[0064] At the same time, since the charging current flowing through the switching transistor Q1 is shunted by the feedback capacitor Cfb, the turn-off loss of the switching transistor Q1 is reduced at this time, which is equivalent to increasing the drain-source capacitor Cds of the switching transistor Q1.

[0065] Therefore, during the turn-on process of the switching transistor Q1, the influence of the feedback capacitor Cfb drawing current on the switching transistor Q1 is equivalent to increasing the gate parasitic capacitance Cgd of the switching transistor Q1; during the turn-off process of the switching transistor Q1, the influence of the feedback capacitor Cfb drawing current on the switching transistor Q1 is equivalent to increasing the drain-source capacitor Cds of the switching transistor Q1. Therefore, the increased turn-on loss in the second turn-on stage and the reduced turn-off loss in this stage partially offset each other, so that when the turn-on speed and the turn-off speed are reduced, the switching loss will not be too large, and finally the balance between the switching speed and the switching loss is achieved.

[0066] The third turn-off stage: During the stage from the eighth moment T8 to the tenth moment T10, the feedback voltage Vfb across the feedback capacitor Cfb remains unchanged. At this time, the circuit where the feedback capacitor Cfb is located is equivalent to an open circuit. Therefore, this stage process is no different from the traditional drive method.

[0067] In summary, in this embodiment, with the gate drive resistor Rg fixed, the value of the feedback capacitor Cfb is adjusted to change the magnitude of the obtained feedback current ifb, thereby adjusting the magnitude of the gate current igs obtained by the switching transistor Q1 during the turn-on process of the switching transistor Q1, achieving the adjustment of the speed of the switching transistor Q1 and reducing the turn-on speed; and being able to adjust the magnitude of the charging current obtained by the switching transistor Q1 during the turn-off process of the switching transistor Q1, achieving the adjustment of the turn-off speed of the switching transistor Q1 and reducing the turn-off speed.

[0068] This embodiment can balance the switching speed and switching loss by reducing the turn-on speed and turn-off speed while preventing the losses generated during the turn-on and turn-off processes from being too large.

[0069] In this embodiment, by adjusting the resistance value of the gate drive resistor Rg, the change rate of the drain-source current ids, that is, the drain-source current change rate di / dt, is determined. Therefore, this embodiment can independently control the drain-source current change rate di / dt and the drain-source voltage change rate dv / dt of the switching transistor Q1, featuring a fast response speed, simplicity, and reliability.

[0070] Embodiment Two:

[0071] In this embodiment, in the field of high-power applications, since the gate threshold voltage decreases as the temperature rises, in order to further improve the driving reliability of the gate drive circuit, based on Embodiment One, a negative turn-off voltage is connected between the source of the switching transistor Q1 and the grounded terminal of the pulse drive source VPWM. That is, a negative voltage less than 0 is connected to the source of the switching transistor Q1 as the turn-off voltage Voffset, which can improve the turn-off reliability of the circuit. The gate drive circuit in Embodiment One can be compatible with the application scenarios of this embodiment. The reference circuit of this embodiment is as shown in the appendix Figure 8 as follows.

[0072] Embodiment Three:

[0073] Based on Embodiment One, in this embodiment, a damping resistor or a bead is electrically connected between the cathode of the second diode D2 and the feedback capacitor Cfb, and the common connection of the cathode of the second diode D2 and the first damping resistor R1 (or bead) is coupled to the anode of the first diode D1. The reference circuit of this embodiment is as shown in the appendix Figure 9 as follows.

[0074] Embodiment Four:

[0075] Based on Embodiment One, in this embodiment, a damping resistor or a bead is electrically connected between the cathode of the second diode D2 and the feedback capacitor Cfb, and the common connection of the feedback capacitor Cfb and the second damping resistor R2 (or bead) is coupled to the anode of the first diode D1. The reference circuit of this embodiment is as shown in the appendix Figure 10 as follows.

[0076] During the turn-on process of the gate drive circuit, the current in the loop where the feedback capacitor Cfb is located changes rapidly, which is likely to cause gate oscillation. Therefore, the circuit designs of Embodiment 3 or Embodiment 4 can absorb high-frequency oscillation and reduce the harm caused by gate oscillation.

[0077] Embodiment 5:

[0078] Based on Embodiment 1, a gate turn-off series circuit is connected in parallel across the gate drive resistor Rg in this embodiment. The gate turn-off series circuit includes a gate turn-off resistor Roff and a fourth diode D4 connected in series. The anode of the fourth diode D4 is coupled to the gate of the switching transistor Q1, and the cathode of the fourth diode D4 is coupled to the pulse drive source VPWM. The reference circuit of this embodiment is as shown in the appendix. Figure 11 As shown. By adding a design of a gate turn-off resistor Roff in this embodiment, the turn-on and turn-off parameters can be independently adjusted, so that the turn-on and turn-off speeds can be independently adjusted.

[0079] Embodiment 6:

[0080] This embodiment discloses a half-bridge drive circuit, which adopts the structure of the gate drive circuit in Embodiment 1 and forms the half-bridge drive circuit of this embodiment by coupling two gate drive circuits. As shown in the appendix, this embodiment includes a first gate drive circuit and a second gate drive circuit coupled to each other; the drain of the upper switching transistor Q2 of the first gate drive circuit, the ground terminal of the first pulse drive source VPWM1, and the ground terminal of the first auxiliary power supply VDD1 are coupled to each other to form a first common terminal, and the first common terminal is coupled to the source of the lower switching transistor Q3 of the second gate drive circuit. Figure 12 As shown, this embodiment includes a first gate drive circuit and a second gate drive circuit coupled to each other; the drain of the upper switching transistor Q2 of the first gate drive circuit, the ground terminal of the first pulse drive source VPWM1, and the ground terminal of the first auxiliary power supply VDD1 are coupled to each other to form a first common terminal, and the first common terminal is coupled to the source of the lower switching transistor Q3 of the second gate drive circuit.

[0081] Both the first gate drive circuit and the second gate drive circuit have the advantage that while the turn-on speed and turn-off speed are reduced, the switching loss is not too large, that is, they both have the advantage of balancing the switching speed and the switching loss. Therefore, the half-bridge drive circuit of this embodiment has the characteristics of fast response speed and less interference, that is, it has the characteristic of balancing the response speed and anti-interference.

[0082] The first gate drive circuit of this embodiment can reduce the gate current of the upper switching transistor Q2 through the first feedback capacitor Cfb1 during the turn-on stage of the upper switching transistor Q2, reduce the switching speed, which is equivalent to increasing the gate parasitic capacitance of the upper switching transistor Q2; and reduce the charging current of the upper switching transistor Q2 through the first feedback capacitor Cfb1 during the turn-off stage of the upper switching transistor Q2, reduce the turn-off speed, which is equivalent to increasing the drain-source capacitance of the upper switching transistor Q1. The second gate drive circuit has the same characteristics, so it will not be elaborated. Therefore, this embodiment can avoid the risk of cross-conduction between the upper and lower transistors of the half-bridge drive circuit while reducing the switching speed of the switching transistor, and improve the circuit reliability.

[0083] In other embodiments of the half-bridge drive circuit, the first gate drive circuit and the second gate drive circuit may also adopt the gate drive circuits of Embodiment 2, Embodiment 3, Embodiment 4 or Embodiment 5.

[0084] This embodiment also discloses a motor system, which includes a motor and at least one half-bridge drive circuit as introduced in this embodiment.

[0085] Embodiment 7:

[0086] This embodiment discloses a gate drive method with controllable switching speed, which is applied to the gate drive circuit of Embodiment 1. Refer to the circuit diagram shown in the appendix Figure 4 and the schematic diagram of the turn-on and turn-off processes shown in the appendix Figure 7 shown.

[0087] This embodiment includes the steps shown in the appendix Figure 13 shown. It should be understood that the order of the steps in this embodiment is only one order of the present invention, and there may be other arrangements in other embodiments.

[0088] Step S01: When the pulse drive source VPWM drives the turn-on signal to come at the first moment T1, the gate drive circuit receives the turn-on signal.

[0089] The gate voltage Vgs of the switching transistor Q1 starts to rise. At the second moment T2, the gate voltage Vgs reaches the turn-on threshold voltage Vth, and the switching transistor Q1 starts to conduct, and the drain-source current ids starts to rise. Due to the influence of the drain-source capacitance Cds of the switching transistor Q1 and the reverse recovery phenomenon of the parasitic diode, there is a spike in the drain-source current ids flowing through the switching transistor Q1 between the second moment T2 and the third moment T3.

[0090] During the process from the first moment T1 to the third moment T3, by selecting a gate drive resistor Rg with an appropriate resistance value to meet the change rate of the drain-source current di / dt required for the turn-on of the switching transistor Q1, where the change rate of the drain-source current di / dt is the change rate of the drain-source current ids flowing through the drain-source capacitance Cds of the switching transistor Q1.

[0091] Step S02: The second diode D2 conducts, and the current flowing through the feedback capacitor Cfb flows to the drain of the switching transistor Q1.

[0092] Under the action of the turn-on signal, the current direction of the switching speed control circuit 100 is as shown in the appendix Figure 5 shown.

[0093] The turn-on signal is the drive current provided by the pulse drive source VPWM. At this time, the drive current flows from the anode to the cathode of the second diode D2 after passing through the gate drive resistor Rg. The second diode D2 conducts, and the first diode D1 turns off. The conducting second diode D2 causes a part of the drive current that should originally flow to the gate of the switching transistor Q1 to flow to the feedback capacitor Cfb.

[0094] Step S03: During the turn-on Miller plateau stage, the conducting second diode D2 shunts the feedback capacitor Cfb from the gate current igs of the switching transistor Q1, thereby adjusting the gate current igs of the switching transistor Q1 during turn-on to control the voltage change of the switching transistor Q1 during turn-on, and thus controlling the turn-on speed of the switching transistor Q1. The larger the capacitance value of the connected feedback capacitor Cfb, the slower the turn-on speed of the switching transistor Q1.

[0095] At the third moment T3, the drain-source current ids is approximately equal to the load current IL, and the drain-source voltage Vds of the switching transistor Q1 starts to decrease, and at the fourth moment T4, the drain-source voltage Vds drops to zero. Among them, as shown in the appendix Figure 4 As shown, the load current IL refers to the current flowing through the inductor L. In addition, during the process from the third moment T3 to the fourth moment T4, the gate voltage Vgs rises to the Miller plateau voltage Vpl and remains approximately unchanged. Therefore, this is the Miller plateau stage. During this stage, the drive current provided by the pulse drive source VPWM flows through the gate drive resistor Rg and then to the gate of the switching transistor Q1. Since the conducting second diode D2 causes a part of the drive current that should originally flow to the gate of the switching transistor Q1 to flow to the feedback capacitor Cfb, the feedback current ifb required for the change of the feedback voltage change rate dv1 / dt on the feedback capacitor Cfb is obtained. Therefore, the gate current igs that should originally be provided to the switching transistor Q1 decreases, resulting in a reduction in the turn-on speed of the switching transistor Q1.

[0096] Among them, for feedback capacitors Cfb with different capacitance values, the magnitudes of the drive currents extracted from the gate of the switching transistor Q1 are different. Therefore, when the gate drive resistor Rg is fixed, adjusting the size of the feedback capacitor Cfb can adjust the magnitude of the gate current igs obtained by the switching transistor Q1, thereby adjusting the drain-source voltage change rate dv / dt, achieving the purpose of adjusting the turn-on speed of the switching transistor Q1.

[0097] At the fourth moment T4, the gate voltage Vgs continues to rise and rises to the steady state at the fifth moment T5. During this stage, the drive current provided by the pulse drive source VPWM is mainly used to charge the gate parasitic capacitance Cgd of the switching transistor Q1. Since the gate-source capacitance Cgs of the switching transistor Q1 is much larger than the feedback capacitor Cfb, this stage process has no difference from the traditional drive method.

[0098] Step S04: At the sixth moment T6, the pulse drive source VPWM drives the arrival of the turn-off signal, and the gate drive circuit receives the turn-off signal.

[0099] The gate voltage Vgs of the switching transistor Q1 begins to decrease. During the process from the sixth moment T6 to the seventh moment T7, by selecting a gate drive resistor Rg with an appropriate resistance value, the rate of change of the drain-source current di / dt required for the turn-on of the switching transistor Q1 is satisfied.

[0100] Step S05: The first diode D1 conducts, and the current flowing through the feedback capacitor Cfb flows towards the first diode D1.

[0101] Under the action of the turn-off signal, the current direction of the switching speed control circuit 100 is as shown in the appendix Figure 6 as shown.

[0102] The turn-off signal is the drive current provided by the pulse drive source VPWM. Since the turn-off signal and the turn-on signal are in opposite directions, the drive current direction at this time turns off the second diode D2 and turns on the first diode D1. The turned-on first diode D1 diverts a part of the charging current that should originally flow to the switching transistor Q1 to the feedback capacitor Cfb.

[0103] Step S06: In the changing stage of the drain-source voltage during turn-off, the turned-on first diode D1 diverts the feedback capacitor Cfb from the charging current of the switching transistor Q1. By controlling the charging current of the drain-source capacitor Cds of the switching transistor Q1 during turn-off, the voltage change of the switching transistor Q1 during turn-off is controlled, thereby controlling the turn-off speed. The larger the capacitance value of the connected feedback capacitor Cfb, the slower the turn-off speed.

[0104] At the seventh moment T7, the gate voltage Vgs drops to the Miller plateau voltage Vpl, and at this time the drain-source voltage Vds begins to rise. During this process, since the turned-on first diode D1 diverts a part of the charging current that should originally flow to the switching transistor Q1 to the feedback capacitor Cfb, the feedback current ifb required for the change of the feedback voltage change rate dv1 / dt on the feedback capacitor Cfb is obtained. Since a part of the charging current flowing through the switching transistor Q1 is drawn away by the feedback capacitor Cfb, the charging current that should originally be provided to the drain-source capacitor Cds of the switching transistor Q1 decreases, reducing the turn-off speed of the switching transistor Q1. When the gate drive resistor Rg is fixed, adjusting the capacitance value of the feedback capacitor Cfb can adjust the magnitude of the charging current obtained by the switching transistor Q1, thereby adjusting the drain-source voltage change rate dv / dt to achieve the purpose of adjusting the turn-off speed of the switching transistor Q1.

[0105] At the eighth moment T8, the drain-source voltage Vds rises to a stable voltage, the drain-source current ids begins to decrease, and at the same time the gate voltage Vgs also begins to decrease. At the ninth moment T9, the drain-source current ids decreases to zero, and at this time the gate voltage Vgs is lower than the turn-on threshold voltage Vth. From the ninth moment T9 to the tenth moment T10, the gate voltage Vgs continues to decrease and drops to zero at the tenth moment T10. During the stage from the eighth moment T8 to the tenth moment T10, the feedback voltage Vfb across the feedback capacitor Cfb remains unchanged. At this time, the line where the feedback capacitor Cfb is located is equivalent to an open circuit. Therefore, this stage process has no difference from the traditional driving method.

[0106] In summary, in this embodiment, when the gate driving resistance Rg is fixed, the rate of change of the drain-source voltage dv / dt of the switching tube is adjusted by adjusting the size of the feedback capacitor Cfb, so as to realize the adjustment of the switching speed of the switching tube Q1.

[0107] In addition, this embodiment can, while reducing the switching speed, prevent the losses generated during the turn-on process and the turn-off process from being too large, so as to achieve a balance between the switching speed and the switching loss.

[0108] In this embodiment, the rate of change of the drain-source current ids, that is, the rate of change of the drain-source current di / dt, is determined by adjusting the value of the gate driving resistance Rg. Therefore, this embodiment can independently control the rate of change of the drain-source current di / dt and the rate of change of the drain-source voltage dv / dt of the switching tube Q1. It has the characteristics of fast response speed, simplicity and reliability.

[0109] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit them. Although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements on some of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

[0110] In short, the above are only the preferred embodiments of the present invention, and all equivalent changes and modifications made according to the scope of the patent application of the present invention shall fall within the scope of the patent of the present invention.

Claims

1. A gate drive circuit, characterized in that, it includes: a switching transistor; a main drive circuit coupled to the switching transistor for controlling the gate drive of the switching transistor; and a switching speed control circuit coupled to the switching transistor for controlling the switching speed of the switching transistor; wherein, the switching speed control circuit includes a feedback capacitor coupled to the switching transistor; the switching speed control circuit adjusts the charging direction and capacitance value of the feedback capacitor to adjust the gate current of the switching transistor when it is turned on, and to adjust the charging current of the drain-source capacitor of the switching transistor when it is turned off, thereby controlling the turn-on speed and turn-off speed of the switching transistor.

2. A gate drive circuit according to claim 1, characterized in that, the switching speed control circuit further includes a first diode and a second diode; the anode of the second diode is coupled to the gate of the switching transistor, and the feedback capacitor is coupled between the cathode of the second diode and the drain of the switching transistor; the cathode of the second diode is further coupled to the anode of the first diode, and the cathode of the first diode is coupled to the positive pole of the auxiliary power supply.

3. A gate drive circuit according to claim 2, characterized in that, the main drive circuit includes a gate drive resistor, a pulse drive source and the auxiliary power supply; the gate drive resistor is coupled between the output terminal of the pulse drive source and the gate of the switching transistor; the gate drive resistor is coupled to the gate of the switching transistor; the ground terminal of the pulse drive source and the ground terminal of the auxiliary power supply are coupled to the source of the switching transistor.

4. A gate drive circuit according to claim 3, characterized in that, the source of the switching transistor is grounded through a negative voltage.

5. A gate drive circuit according to claim 3, characterized in that, a first damping resistor or a bead is electrically connected between the cathode of the second diode and the feedback capacitor, and the common connection of the cathode of the second diode and the first damping resistor is coupled to the anode of the first diode.

6. A gate drive circuit according to claim 3, characterized in that, a second damping resistor or a bead is electrically connected between the cathode of the second diode and the feedback capacitor, and the common connection of the feedback capacitor and the second damping resistor is coupled to the anode of the first diode.

7. A gate drive circuit according to claim 3, characterized in that, a gate turn-off series circuit is connected in parallel across the two ends of the gate drive resistor; the gate turn-off series circuit includes a gate turn-off resistor and a fourth diode connected in series, the anode of the fourth diode is coupled to the gate of the switching transistor, and the cathode of the fourth diode is coupled to the pulse drive source.

8. A half-bridge drive circuit, characterized in that, it includes a first gate drive circuit for driving an upper switching transistor and a second gate drive circuit for driving a lower switching transistor; the first gate drive circuit and the second gate drive circuit are respectively the gate drive circuit according to any one of claims 1-7.

9. A gate drive method for controlling the switching speed of a switching transistor by a gate drive circuit, characterized in that, it includes the following steps: Receive an enabling signal; The second diode conducts, and the current flowing through the feedback capacitor flows to the drain of the switching transistor; During the enabling Miller plateau phase, the conducting second diode shunts the feedback capacitor from the gate current of the switching transistor. By shunting, the gate current of the switching transistor during enabling is adjusted, thereby controlling the voltage change of the switching transistor during enabling, and thus controlling the enabling speed; Receive a disabling signal; The first diode conducts, and the current flowing through the feedback capacitor flows to the first diode; During the drain-source voltage change phase of disabling, the conducting first diode shunts the feedback capacitor from the charging current of the switching transistor. By shunting, the charging current of the drain-source capacitor of the switching transistor during disabling is adjusted, thereby controlling the voltage change of the switching transistor during disabling, and thus controlling the disabling speed.

10. The gate driving method according to claim 9, characterized in that it further includes: Adjusting the enabling speed and disabling speed of the switching transistor by adjusting the capacitance value of the feedback capacitor; The larger the capacitance value of the connected feedback capacitor, the slower the enabling speed and disabling speed.

11. The gate driving method according to claim 10, characterized in that it further includes: Changing the rate of change of the drain-source current of the switching transistor during enabling by changing the resistance value of the gate driving resistor.

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