Frequency detector for measuring and tuning the frequency of a controlled oscillator

Abstract

A frequency detector (200) and a method thereof for measuring and tuning the frequency of a controlled oscillator are disclosed. The frequency detector (200) includes: a pulse generator (210) for generating sampling pulses; a sampling circuit system (220) for sampling the output state of the controlled oscillator (180); and a digital processing unit (230). The sampling circuit system (220) is configured to subsample the output state of the controlled oscillator (180) at two or more sampling frequencies, all of which are lower than the frequency of the controlled oscillator. The digital processing unit (230) is configured to calculate the frequency offset of the oscillator based on the sampled states, and to generate a control signal based on the frequency offset to tune the frequency of the oscillator.

Description

Technical Field

[0001] The embodiments described herein relate to frequency detectors for measuring and tuning the frequency of a controlled oscillator. In particular, they relate to frequency detectors with sub-sampling frequency detection, frequency generation circuitry systems including the frequency detectors, and electronic devices (such as receivers, transmitters, and transceivers) including the frequency generation circuitry systems. Background Technology

[0002] In wireless communication systems, there is a strong trend towards supporting devices with ultra-low power consumption. These devices can be small sensor nodes where batteries should last for many years, or devices that use energy harvesting to achieve battery-free operation. When a wireless communication system needs to communicate with such a device, a receiver must be operated within the device. To achieve a finite response time, the receiver must be operated periodically. Therefore, the receiver's power consumption must be limited. Thus, special ultra-low power receivers, known as wake-up receivers, are often used. These wake-up receivers have limited performance; they can only detect the presence of a wake-up request. When such a request is present, a higher-performance and higher-power master receiver is activated to receive the actual communication data.

[0003] To achieve ultra-low power consumption, such as below 100 uW, the wake-up receiver is based on amplitude detection of the on / off keying signal. This avoids the need for power-intensive phase-locked loops (PLLs) to generate accurate local oscillator (LO) signals. However, only moderate filtering can be implemented before amplitude detection, and noise immunity is essentially limited to what can be achieved with the correlation of a pseudo-random noise (PN) sequence.

[0004] Due to the limited amount of filtering before amplitude detection, the wake-up receiver is highly susceptible to interference. All interference and noise entering the amplitude detector will mask the desired signal, which modulates amplitude within the same frequency range as the wake-up request signal. It should be understood that "same frequency" does not mean the interference only exists on the same frequency channel. Instead, due to the limited ability to filter out signals with frequencies adjacent to the wake-up signal, it should be understood that signals transmitted in adjacent channels and even at potentially greater distances will effectively have the same detrimental effect as co-channel interference. To effectively filter out adjacent interference, frequency generation in the wake-up receiver must be highly accurate, thus consuming significant energy. Furthermore, the amplitude detector is highly nonlinear, thus producing a very small output signal for weak input signals. Assuming the amplitude detector has a quadratic characteristic for small input signals, this means that for every 10 dB decrease in the input signal level, the signal-to-noise ratio drops by 20 dB, which quickly becomes very detrimental when the detector input is already moderately interfered with. Therefore, more filtering before amplitude detection is necessary to achieve a wake-up receiver with high interference immunity; however, this increases power consumption. Summary of the Invention

[0005] Therefore, the purpose of the embodiments herein is to provide a frequency generation circuit system with improved performance in terms of accuracy and power consumption.

[0006] According to one aspect of the embodiments herein, this objective is achieved by a frequency detector for measuring and tuning the frequency of a controlled oscillator. The frequency detector includes: a pulse generator for generating sampling pulses; a sampling circuit system for sampling the output state of the controlled oscillator; and a digital processing unit. The sampling circuit system is configured to subsample the output state of the controlled oscillator at two or more sampling frequencies, all of which are lower than the frequency of the controlled oscillator. The digital processing unit is configured to calculate the frequency offset of the oscillator based on the sampled states and generate a control signal based on the frequency offset to tune the frequency of the oscillator.

[0007] According to one aspect of the embodiments herein, this objective is achieved by a frequency detector for measuring and tuning the frequency of a controlled oscillator. The frequency detector includes: a pulse generator for generating sampling pulses; a multi-stage frequency divider connected to the output of the controlled oscillator; a sampling circuit system for sampling the output state from each stage of the frequency divider; and a digital processing unit. The sampling circuit system is configured to subsample the output state of the frequency divider at a sampling frequency lower than the frequency of the controlled oscillator. The digital processing unit is configured to calculate the frequency offset of the oscillator based on the sampled states and to generate a control signal based on the frequency offset to tune the frequency of the oscillator.

[0008] According to one aspect of the embodiments herein, this objective is achieved by a method for measuring and tuning the frequency of a controlled oscillator. The method includes: subsampling the states of the controlled oscillator at a sampling frequency lower than the frequency of the controlled oscillator; calculating the state difference between each adjacent sampled state pair; estimating a frequency offset based on the state difference; generating a control signal based on the frequency offset; and tuning the frequency of the controlled oscillator based on the control signal.

[0009] The embodiments described herein provide techniques for digital frequency measurement, calibration, and locking of oscillator frequencies for ultra-low-power devices, such as wake-up receivers, where conventional PLLs are too power-intensive. Frequency detection is based on subsampling of the controlled oscillator state. Therefore, the sampled pulses can be generated by a relatively low-frequency PLL, for example, a PLL operating at a frequency more than an order of magnitude lower than the oscillator's radio frequency (RF). Thus, these PLLs can have very low power compared to RF PLLs. Subsampling introduces aliasing problems, so different oscillator frequencies will generate the same subsampled signal. To resolve the aliasing problem, multiple sampling frequencies, all lower than the oscillator frequency, can be used without employing a high RF sampling frequency. Another approach to resolve the aliasing problem is to temporarily operate the RF divider connected to the controlled oscillator and sample its state. This will also eliminate aliasing within the oscillator's tuning range. The simplest possible divider can be used, such as a cascaded divider-by-two circuit with minimal power overhead. Furthermore, the divider can be used only for a short period, for example, during oscillator startup or coarse tuning to save power.

[0010] The oscillator frequency can be estimated by filtering or averaging the sampled state difference of the oscillator, which can be calculated as the sampled phase state difference of the oscillator and / or divider. Therefore, this technique is digital, providing digital frequency estimation and offering a high degree of flexibility in algorithms used for oscillator frequency calibration and tuning. By combining sampling results from several sampling frequencies, or alternatively by temporarily operating a simple divider and sampling its state, the aliasing-free frequency range of the sampling technique can extend beyond the amplitude of the highest sampling frequency. This technique can be used in fully digital frequency-locked loops (ADFLL) or for oscillator frequency calibration.

[0011] According to the embodiments described herein, the frequency detector described above is used to implement a frequency generation circuit system for tuning and locking a controlled oscillator.

[0012] Therefore, the frequency generation circuit system is based on subsampling of the controlled oscillator state, which eliminates the need for power-intensive frequency dividers and PLLs that operate continuously across the entire RF. Compared to conventional frequency generation circuit systems using PLLs, the frequency generation circuit system according to the embodiments herein can be implemented with sufficient accuracy and significantly lower power consumption. Frequency accuracy will be superior to that of a self-excited oscillator, and the bandwidth of the receiver using the frequency generation circuit system can be effectively limited by a filter after the down-conversion mixer. The amount of noise and interference reaching the amplitude detector at the receiver will be limited. The digital implementation also provides a high degree of flexibility in algorithms and operating modes.

[0013] According to the embodiments described herein, an electronic device, such as a wake-up receiver, is implemented using the frequency generation circuit system described above. Due to the more accurate yet still ultra-low-power local frequency generation circuit system, the selectivity and sensitivity of the wake-up receiver can be improved, which is achieved by using narrower-band filtering after the down-conversion mixer. Therefore, the main advantage is improved performance and interference immunity of the wake-up receiver with limited power overhead.

[0014] Therefore, the embodiments described herein provide a frequency generation circuit system with improved performance in terms of accuracy and power consumption. Attached Figure Description

[0015] Examples of embodiments described herein are described in more detail with reference to the accompanying drawings, in which:

[0016] Figure 1 This is a schematic block diagram of a receiver that can implement the frequency detector according to the embodiments herein.

[0017] Figure 2 This is a schematic block diagram of a frequency detector according to one embodiment of this document.

[0018] Figure 3 This is a schematic block diagram of a frequency detector according to one embodiment of this document;

[0019] Figure 4 This is a flowchart illustrating a method for measuring and tuning the frequency of a controlled oscillator according to an embodiment of this document;

[0020] Figure 5 The following is shown according to this article: Figure 2 Simulation results of the frequency detector in the illustrated embodiment;

[0021] Figure 6 The following is shown according to this article: Figure 3 Simulation results of the frequency detector in the illustrated embodiment;

[0022] Figure 7 Simulation results for synchronous and asynchronous frequency dividers are shown.

[0023] Figure 8 This is a block diagram illustrating a frequency detector according to one embodiment of the present document;

[0024] Figure 9 This is a block diagram illustrating a frequency generation circuit system according to an embodiment of the present invention;

[0025] Figure 10 This is a block diagram illustrating an electronic device in which a frequency generation circuit system according to embodiments of this document can be implemented. Detailed Implementation

[0026] Figure 1 A receiver 100 in which a frequency detector according to an embodiment of this document can be implemented is shown.

[0027] Receiver 100 includes an input matching network 110 for matching the input impedance of the antenna with the input impedance of mixer 120. Mixer 120 converts the received RF signal into an intermediate frequency (IF) signal. Receiver 100 also includes an IF amplifier 130, an envelope detector 140, a bandpass filter 150, a baseband amplifier 160, and a comparator 170 for amplifying the IF signal.

[0028] Receiver 100 also includes a controlled oscillator 180 to generate a local oscillator signal for mixer 120. A frequency detector 190, according to embodiments herein, is implemented in receiver 100 for measuring and tuning the frequency of the controlled oscillator 180.

[0029] Figure 2 A frequency detector 200 according to one embodiment of this document is shown.

[0030] The frequency detector 200 includes: a pulse generator (pulse generator 210) for generating sampling pulses, a sampling circuit system 220 for sampling the output state of the controlled oscillator 180, and a digital processing unit (digital block 230) for processing the sampled state.

[0031] The sampling circuit system 220 is configured to subsample the output state of the controlled oscillator at two or more sampling frequencies, all of which are lower than the frequency of the controlled oscillator. The sampling circuit system 220 can sample the output state of the controlled oscillator at different outputs indicated by LO1, LO2, LO3.

[0032] The sampling circuit system 220 can be configured to subsample the output state of the controlled oscillator 180 at a first frequency during a first time period, and to subsample the output state of the controlled oscillator 180 at a second frequency during a second time period.

[0033] According to some embodiments herein, the sampling circuit system 220 may include two or more sampling circuits to simultaneously subsample the output state of the controlled oscillator 180 at two or more sampling frequencies.

[0034] The sampled state is input to the digital processing unit 230. The digital processing unit 230 is configured to calculate the frequency offset of the oscillator based on the sampled state, and generate a control signal based on the frequency offset to tune the frequency of the controlled oscillator 180.

[0035] Figure 3 A frequency detector 300 according to another embodiment of this document is shown.

[0036] The frequency detector 300 includes a pulse generator (pulser 310) for generating sampling pulses, a sampling circuit system 320, and a digital processing unit (digital block 330). The frequency detector 300 also includes a multi-stage frequency divider 340 connected to the output of the controlled oscillator 180. In this embodiment, the sampling circuit system 320 samples the output state from each stage of the frequency divider 340 and is configured to subsample the output state of the frequency divider 340 at a sampling frequency lower than the frequency of the controlled oscillator. The digital processing unit 330 is configured to calculate the frequency offset of the oscillator based on the sampled states and generate a control signal based on the frequency offset to tune the frequency of the controlled oscillator 180.

[0037] Reference Figure 4 This describes a method for measuring and tuning the frequency of a controlled oscillator, performed in frequency detectors 200 and 300. The method includes the following actions.

[0038] Action 410

[0039] The sampling circuit systems 220 and 320 subsample the state of the controlled oscillator 180 at a sampling frequency lower than that of the controlled oscillator.

[0040] To eliminate the need for power-intensive frequency dividers operating at full RF frequencies, frequency sensing is based on subsampling of the oscillator state. Unfortunately, subsampling introduces aliasing problems, resulting in different oscillator frequencies generating the same subsampled signal.

[0041] In order to distinguish between oscillator frequencies of signals that have been subsampled by the same frequency, subsampling can be performed at different sampling frequencies. Therefore, the sampling circuit system 220 can be configured to subsample the output state of the controlled oscillator at two or more sampling frequencies, and all sampling frequencies are lower than the frequency of the controlled oscillator.

[0042] An alternative method using different sampling frequencies is to resolve the aliasing problem by temporarily operating the RF divider 340 and sampling its state, such as... Figure 3 As shown. The simplest possible frequency divider can be used, such as a cascaded divider-2 circuit. This results in minimal power consumption, especially since the frequency divider 340 can only be used for a short period of time.

[0043] The sampling frequency can be generated, for example, in pulse generators 210 and 310 using a relatively low-frequency PLL, which operates at a frequency more than an order of magnitude lower than that of the RF. Therefore, these PLLs have very low power compared to RF PLLs.

[0044] Action 420

[0045] After the oscillator state is sampled and digitized, the sampled state is input to digital processing units 230 and 330. In digital processing units 230 and 330, the state difference between each adjacent sampled state pair is calculated.

[0046] For ring oscillators, this can be achieved by sampling the digital state, with 1 bit per circuit node or per stage. The state change from the previous sample is then calculated, providing a measurement of the instantaneous frequency shift of the nearest harmonic from the sampling frequency. Note that the number of this nearest harmonic is unknown, therefore the absolute frequency is ambiguous, which introduces aliasing problems. By performing frequency measurements with different sampling frequencies, different oscillator frequencies can be uniquely distinguished over a wider frequency range compared to using a single sampling frequency of the same amplitude.

[0047] To illustrate the principles and steps or actions of frequency detection according to the embodiments herein, methods such as... have been used... Figure 2 and Figure 3 The controlled oscillator 180 shown was used to simulate a wake-up receiver operating in the 2.45 GHz ISM band.

[0048] Then, the controlled oscillator 180 will cycle through six different digital states 101, 001, 011, 010, 110, and 100 at outputs LO1, LO2, and LO3. The controlled oscillator 180 will complete one cycle through these six states in 1 / 2.45 GHz = 408 ps, with each state lasting 408 ps / 6 = 68 ps. Simulation results are available in... Figure 5 The states are shown in the diagram. In this case, the total number of states is 6.

[0049] The first three state curves are the output states LO1, LO2, and LO3 of each stage of the controlled oscillator 180. Then, the sampled digital states at different outputs of the controlled oscillator 180 (in...) Figure 3The samples (indicated by "Sampl_LO1", "Sampl_LO2", and "Sampl_LO3") are used to evaluate the offset frequency of the harmonic from the nearest sampled frequency. This is achieved by calculating the state difference. This calculation can be performed by converting each sampled state into a state number based on its position in the state sequence and subtracting the previous state number from the current state number.

[0050] For example, the first step could be to convert the six states into state numbers ranging from 0 to 5 based on their positions in the state sequence, such as... Figure 5 The term "state" is used to indicate this. For example, the oscillator output cycles through different digital states: "101, 001, 011, 010, 110, 100". Figure 5 The states are assigned numbers 0 through 5. State "100" is assigned number 5, and state 101 is assigned number 0. Then, the previous sample state number is subtracted from the current sample state number. The result of the subtraction is... Figure 5 The difference is indicated by "State_diff". If there is no state change, the state difference will be zero, and this result indicates that the oscillator frequency is equal to the harmonic of the sampling frequency. If the difference is 1, the oscillator phase is advanced by one state, indicating that the oscillator frequency is 1 / 6 of the sampling frequency harmonic. If the difference is -1, the oscillator frequency is 1 / 6 of the sampling frequency harmonic, and so on.

[0051] If the state difference is equal to 3 or -3, it's impossible to determine whether the oscillator frequency is higher or lower than the nearest harmonic by half the sampling frequency, because it lies in the middle of the two harmonics, thus it's lower than one but higher than the other. However, this is only temporary; the average state difference over a period of time will be biased to one side. That is, the average state difference can represent the frequency offset from a certain harmonic of the sampling frequency. The average will also provide increased accuracy in frequency estimation.

[0052] Therefore, according to some embodiments of this article, the method may also include averaging the state differences over a period of time.

[0053] Similar to the ambiguous states described above, there may be some erroneous state differences. These erroneous state differences, compared to other state differences, provide oscillator frequency offsets from different harmonics of the sampling frequency. These ambiguous or erroneous state differences need to be corrected or skipped before calculating the average.

[0054] According to some embodiments of this article, the method may also include correcting some state differences such that all state differences represent frequency offsets from the same harmonic of the sampling frequency.

[0055] There are two error correction possibilities. First, let's introduce the terms "average" and "initial average" and explain the difference between them. The "initial average" is the average of the state differences of the first few samples in the initial sampling period, while the "average" is the average of the state differences of all samples throughout the entire sampling period.

[0056] The purpose of this embodiment is to calculate the average of the sampled state differences and to subtract the oscillator frequency from this average to correct it. To correct erroneous samples, the idea is to average the state differences over the first few sample periods to obtain an "initial average," and then, based on this "initial average," decide whether to retain or reject a sample. Simultaneously, all samples over the entire sampling period are averaged to obtain an overall "average" (which differs from the "initial average").

[0057] One method for correcting or skipping state differences is to compare each new state difference with the "initial average". If it differs from the "initial average" by + / - 1, it is skipped or not counted. That is, skipped state differences are those that are not included in the range [initial average - 1, initial average + 1], otherwise, the state difference is retained and counted in the "average". For example, if the initial average is 0, the retained values ​​are state differences in the range [-1, 1].

[0058] If the next state difference is correct, then the erroneous state difference can be corrected. For example, with an initial average of 1, if the previous state number is 0, the current erroneous state number is 2, and the next correct state number is 2, then the state difference is first 2 and then 0. When both state differences 2 and 0 are retained, the average is 1. The resulting average is the same as in the case where there are two correct state differences that are both equal to 1, where the correct state numbers would be 0, 1, and 2.

[0059] Note that omitting certain samples from the "average" may also introduce errors, leading to a decrease in the accuracy of frequency detection.

[0060] Another way to correct or skip state differences is to set the state difference to zero or to correct it by adding or subtracting a state number. For example, you could simply set a fuzzy state difference of + / -3 to zero so that other samples determine the sign when calculating the initial average. Once the sign is known, you can set the sign of the state difference to a value of 3.

[0061] Another issue is wrap-around. For example, moving from state 5 to state 0 results in a state difference of -5, when it should be 1, because state 5 precedes state 0 by one state. Furthermore, moving from state 0 to state 5 results in a state difference of 5, when it should be -1. To address this, state differences less than -6 / 2 = -3 (the negative of the total number of states, 6 divided by 2) should be added by 6, while state differences greater than 6 / 2 = 3 (the total number of states, 6 divided by 2) should be subtracted by 6. In other words, some state differences need to be compensated for wrap-around.

[0062] Therefore, according to some embodiments of this document, the method may also include surrounding some state differences by: if the state difference is greater than the total number of states divided by 2, subtracting a number representing the total number of states from the state difference; or if the state difference is less than a negative number of the total number of states divided by 2, adding a number representing the total number of states to the state difference.

[0063] The second error correction method could be to retain state differences that will be automatically corrected by subsequent state differences. That is, retain state differences that fall within the range of [initial average - N, initial average + N], where N can be greater than 1, but N has a maximum value subject to wrapping: Nmax = Max_state_difference - |Initial_Average|, where |Initial_Average| is the absolute value of the initial average, and Max_state_difference is the maximum state difference equal to the total number of states divided by 2. For example, when sampling the output of a three-stage ring oscillator, the total number of states is 6, and Max_state_difference is 3; when sampling an M-divider, the total number of states is M, and Max_state_difference = M / 2. When N exceeds this maximum value, the first or second state difference will be wrapped, resulting in -6 or +6 being added to the average, thus adding an error.

[0064] Skipped state differences are those not included in the range [initial average - Max_state_difference + |initial average|, initial average + Max_state_difference - |initial average|]. For example, for an initial average of 0, the range is [-3, 3]. State differences within this range but not within [initial average + 1, initial average - 1] (i.e., [-1, 1]) are retained errors because the next state difference will correct them, except in the case where the second state difference is also an error.

[0065] For example, for an initial average of 2, the range of state differences retained is [1, 3]. The example below illustrates a case where error state differences outside the range [initial average - Max_state_difference + |initial average|, initial average + Max_state_difference - |initial average|] are averaged. Compared to the case where the average would have a value of 2 in the case of correct states (i.e., 0, 2, 4), if the previous state number is 0, the current error state number is 4, and the next correct state number is 4, the state difference is initially -2 because the state difference +4 is wrapped around to -2, and then the state difference is 0, resulting in an average of -1.

[0066] To further include more previously skipped state differences—those that are not within the range of [initial average - Max_state_difference + |initial_Average|, initial average + Max_state_difference - |initial_Average|]—a increment of -6 can be added if the state difference is positive, and +6 if it is negative, or + / -M if there are M states, and the value is retained if it is still within the range. This compensates for the loop, thus avoiding skipping state differences with respect to harmonics that differ from the average state difference.

[0067] The corrected state difference is Figure 5 The term "Corr_State_diff" is used to indicate this.

[0068] To obtain higher frequency detection resolution, the obtained correction state difference is then averaged to obtain the result. Figure 5 The average state difference is indicated by "State_diff_avrg". Assuming averaging over 1 µs without uncorrected errors, the phase error will be a maximum of 1 / 3 of a period, or 120 degrees, corresponding to 0.33 MHz, within 1 µs. On average, the absolute frequency error will be approximately 1 / 2 of that frequency, or 160 kHz. Longer averaging times result in lower frequency errors but slower computation. Adding more phase to the oscillator or using an analog-to-digital converter that provides higher resolution will also reduce frequency errors. For wake-up receiver applications, the frequency error resulting from 160 kHz quantization is acceptable.

[0069] Action 430

[0070] Digital processing units 230 and 330 estimate frequency shift based on state difference.

[0071] These state differences, representing the frequency offset samples, are then filtered or averaged and used to estimate the oscillator offset frequency.

[0072] Digital processing units 230 and 330 can use a lookup table to estimate the frequency offset, which contains a list of state differences with the corresponding frequency offset.

[0073] The frequency offset can also be calculated by multiplying the sum of the state differences by a constant. This constant can be determined based on the sampling frequency and the time period for averaging the state differences.

[0074] Action 440

[0075] Digital processing units 230 and 330 generate control signals based on frequency offset.

[0076] Then, use the control signal to lock the loop or calibrate the oscillator.

[0077] Action 450

[0078] Digital processing units 230 and 330 tune the frequency of the controlled oscillator based on control signals.

[0079] Frequency ambiguity is a troublesome problem in all sampling systems. As discussed above, the method according to the embodiments of this paper addresses this problem by using multiple sampling frequencies. This can be used because the oscillator's output signal has a slowly changing frequency. Therefore, the oscillator is first measured with one sampling frequency, then with another, assuming the oscillator's frequency is substantially the same across the two sampling periods. Assume the oscillator frequency is 2.450 GHz, and it is first sampled at 98 MHz, producing a zero-offset frequency from the 25th harmonic. It is then sampled at 70 MHz, also producing a zero-offset frequency, but now from the 35th harmonic. The adjacent frequencies at which zero-offset frequencies are also produced at both sampling frequencies are 490 MHz away from 2.450 GHz. Unless the oscillator's tuning range is higher than 490 MHz, no aliasing problem will occur when using these sampling frequencies. Note that aliasing is also not observed when the tuning range is less than 960 MHz and centered at 2.45 GHz.

[0080] If the power consumption of a minimal RF divider is tolerable, switching between two different sampling frequencies can be avoided. Then, a single sampling frequency can be used by dividing the oscillator output by, for example, 8 (e.g., ...). Figure 3 (As shown) to resolve sampling frequency aliasing. Thus, when using the output state of the sampled divider, the frequency range between two samples aliased is multiplied by 8. Therefore, using only a single sampling frequency of 100 MHz will produce an 800 MHz alias-free oscillator frequency detection range.

[0081] Figure 6 Simulation results for the frequency detector 300 are shown. The first three state curves, Div1, Div2, and Div3, represent the output states after division by 2, 4, and 8, respectively. The three sampled outputs of the frequency divider (i.e., divided by 2, 4, and 8) are shown in... Figure 5 These are indicated by "Sampl_Div1", "Sampl_Div2", and "Sampl_Div3" respectively. The three sampled outputs of the frequency divider will cycle through eight states, numbered from 0 to 7. Figure 6 In this context, "state" is used to indicate this. Similarly, for the oscillator's output, the state difference is calculated by subtracting the current state from the previous state. The subtraction result is in... Figure 6 The term "State_diff" is used to indicate this. Then, "State_diff" is corrected by considering wraparound. This corrected state difference is... Figure 6 The quantization error is indicated by "Corr_State_diff" and then filtered or averaged to obtain high-frequency detection resolution. In this case, the quantization error will be a maximum of 4 cycles. Then, if the state difference is averaged over 4 µs, the maximum frequency error is 1 MHz.

[0082] For example, if you want to lock the RF oscillator frequency to 2.45 GHz using a sampling frequency of 100 MHz, the offset frequency should be equal to 6.25 MHz, since 2.45 GHz divided by 8 is 306.25 MHz. Therefore, the adjacent aliasing frequencies are 1.65 GHz and 3.25 GHz, because frequencies divided by 8 are 206.25 MHz and 406.25 MHz. These adjacent aliasing frequencies are far enough from 2.45 GHz to be outside the oscillator's frequency tuning range, which should cover the band where process, voltage, and temperature (PVT) variations exist. Process variations can then be corrected for using a memory that reuses the same oscillator control signal or word the next time the same frequency is generated, or interpolation can be used between previously generated frequencies stored in a table. This can be used to reduce the time required to change the local oscillator frequency.

[0083] To achieve the lowest power consumption, an asynchronous frequency divider can be used. Unfortunately, such a divider has a delay between the signal transitions representing its state. Directly sampling these signals at certain sampling moments can lead to erroneous state observations, which can corrupt frequency detection. One solution is to use a synchronous frequency divider or counter. Figure 7 As shown, the output switching of the synchronous frequency divider all occurs at the same time, which solves the problem, but at the cost of higher power consumption.

[0084] The power consumption of the synchronous divider for the 2.45 GHz clock is 8.5 µW.

[0085] The power consumption of the asynchronous frequency divider for a 2.45 GHz clock is 4.4 µW.

[0086] Another solution could be to use delay units to synchronize the output of the asynchronous frequency divider. However, if these delay units are used for the frequency divider output, their power consumption may be high, and the power reduction advantage relative to synchronous frequency dividers may be limited. To further reduce power consumption, one could... Figure 8 The diagram illustrates the use of a delay unit to delay the sampled signal. This sampled signal frequency is 100 MHz, significantly lower than the three outputs of the divider (1.2 GHz, 600 MHz, and 300 MHz), resulting in minimal power consumption. The delay unit is tuned to match the timing delays between the different asynchronous divider outputs.

[0087] To further reduce power consumption, the frequency divider can be turned off after the frequency-locked loop stabilizes. The oscillator output is then sampled instead to improve frequency accuracy and reduce power consumption. The frequency-locked loop can then track and compensate for oscillator frequency variations caused by changes in power supply voltage and temperature.

[0088] Generating a sampling clock using a low-frequency PLL is feasible because dividers in this frequency range can be implemented with extremely low power consumption in modern silicon technology. For example, a 10-stage divider chain operating at 32 MHz has been reported in 28 nm FDSOI technology with a power consumption of 28 nW.

[0089] Figure 9 A frequency generation circuit system 900 according to an embodiment of this document is shown. For example... Figure 2 , Figure 3 and Figure 8 As shown, the frequency generation circuit system 900 includes a controlled oscillator 910 and frequency detectors FD 200, 300, 800 according to embodiments herein. The controlled oscillator 910 may be a multi-stage ring oscillator, and the sampling circuit system is configured to subsample the state of the ring oscillator at the output of each stage.

[0090] As described above, the sampling circuit system SC 920 in the frequency detectors 200, 300, and 800 may include two or more sampling circuits SC1 and SC2, and simultaneously subsample the state of the controlled oscillator 910 at the output of the controlled oscillator at two or more sampling frequencies f1 and f2. Sampling pulses with different frequencies can be generated by the pulse generation circuit PG 930.

[0091] Frequency detectors 200, 300, and 800 can subsample the state of the controlled oscillator 910 one at a time at two sampling frequencies f1 and f2 at the output of the controlled oscillator 910.

[0092] Frequency detectors 200, 300, and 800 can subsample the state of the controlled oscillator at the output of the Div 940 multi-stage frequency divider connected to the controlled oscillator 910.

[0093] Frequency detection and calibration of the controlled oscillator 910 can be performed discontinuously or periodically. Based on the estimated frequency offset, subsampling can be performed alternately between subsampling the output of the multi-stage frequency divider 940 connected to the controlled oscillator 910 and subsampling the output of the controlled oscillator 910.

[0094] The digital processing unit (DPU) 950 processes the sampled state, calculates the frequency offset of the controlled oscillator 910 based on the sampled state, and generates a control signal based on the frequency offset to tune the frequency of the controlled oscillator 910.

[0095] Frequency detectors 200, 300, 800 and frequency generation circuit system 900 can be used in various integrated circuits, electronic circuits, devices or apparatuses. Figure 10 A block diagram of an electronic device 1000 is shown. The electronic device 1000 includes a frequency generation circuit system FGC 900, which includes frequency detectors FD 200, 300, and 800 according to embodiments herein. The electronic device 1000 may be a receiver, transmitter, or transceiver. The electronic device 1000 may include other units, of which a memory 1020 and a processing unit 1030 are shown.

[0096] In summary, the embodiments described herein provide a technique for digital frequency measurement, calibration, and locking of a local oscillator frequency in an ultra-low power wake-up receiver, where conventional PLLs would be too power-intensive. A lower frequency PLL is used to provide accurate sampling pulses. Frequency measurement is then based on subsampling of the oscillator's state. Multiple sampling frequencies can be used to resolve aliasing issues without employing high sampling frequencies. Alternatively, a simple RF divider, such as dividing by 8, can be used temporarily. This will also eliminate aliasing within the oscillator's tuning range. The oscillator frequency is estimated by filtering or averaging frequency samples, which are calculated as the phase state difference of the oscillator and / or divider. This technique can be used for all-digital frequency-locked loops (ADFLLs) or for oscillator frequency calibration. The digital implementation offers high flexibility in terms of algorithms and operating modes.

[0097] Those skilled in the art will understand that the frequency detectors 200, 300, 800 and the frequency generation circuit system 900 according to the embodiments herein can be implemented using any semiconductor technology, such as bipolar, NMOS, PMOS, CMOS or microelectromechanical systems (MEMS) technology.

[0098] The word “including” or “contains” as used in this text should be interpreted as non-restrictive, meaning “consisting of at least…”.

[0099] The embodiments described herein are not limited to the preferred embodiments described above. Various alternatives, modifications, and equivalents may be used. Therefore, the above embodiments should not be considered as limiting the scope of the invention, which is defined by the appended claims.

Claims

1. A frequency detector (200) for measuring and tuning the frequency of a controlled oscillator (180), comprising: Pulse generator (210) is used to generate sampling pulses; A sampling circuit system (220) is used to sample the output state of the controlled oscillator (180); as well as Digital processing unit (230); wherein, The sampling circuit system (220) is configured to subsample the output state of the controlled oscillator (180) at two or more sampling frequencies, and all sampling frequencies are lower than the frequency of the controlled oscillator. The digital processing unit (230) is configured to calculate the frequency offset of the oscillator based on the sampled state, and to generate a control signal based on the frequency offset to tune the frequency of the oscillator; The sampling circuit system (220) includes two or more sampling circuits configured to simultaneously subsample the output state of the controlled oscillator at different sampling frequencies.

2. The frequency detector (200) according to claim 1, wherein, The sampling circuit system (220) is configured to: subsample the output state of the controlled oscillator at a first frequency during a first time period, and subsample the output state of the controlled oscillator at a second frequency during a second time period.

3. A frequency detector (300) for measuring and tuning the frequency of a controlled oscillator, comprising: A pulse generator (310) is used to generate sampling pulses; A multi-stage frequency divider (340) is connected to the output of the controlled oscillator; A sampling circuit system (320) is used to sample the output state from each stage of the frequency divider; as well as Digital processing unit (330); wherein, The sampling circuit system (320) is configured to subsample the output state of the frequency divider at a sampling frequency lower than that of the controlled oscillator; The digital processing unit (330) is configured to calculate the frequency offset of the oscillator based on the sampled state, and to generate a control signal based on the frequency offset to tune the frequency of the oscillator; The sampling circuit system (220) includes two or more sampling circuits configured to simultaneously subsample the output state of the controlled oscillator at different sampling frequencies.

4. The frequency detector (300) according to claim 3, wherein, The sampling circuit system is also configured to subsample the output state of the controlled oscillator.

5. A frequency generation circuit system (900) comprising a controlled oscillator (180) and a frequency detector (200, 300) according to any one of claims 1 to 4.

6. The frequency generation circuit system (900) according to claim 5, wherein, The controlled oscillator (180) is a multi-stage ring oscillator, and the sampling circuit system (320) is configured to subsample the state of the ring oscillator at the output of each stage.

7. An electronic device (1000) comprising a frequency generation circuit system (900) according to any one of claims 5 to 6.

8. The electronic device (1000) according to claim 7, comprising: Receiver, transmitter, transceiver.

9. A method for measuring and tuning the frequency of a controlled oscillator, comprising: The state of the controlled oscillator is subsampled at a sampling frequency lower than the frequency of the controlled oscillator (410). Calculate the state difference between adjacent sampled state pairs (420); Based on the state difference, estimate the (430) frequency shift; Based on the frequency offset, a (440) control signal is generated; as well as Based on the control signal, the frequency of the controlled oscillator is tuned (450). The subsampling of the state of the controlled oscillator includes: simultaneously subsampling the output of the controlled oscillator at two sampling frequencies.

10. The method according to claim 9, wherein, Subsampling the state of the controlled oscillator includes subsampling the output of the controlled oscillator one at a time at two sampling frequencies.

11. The method according to claim 9, wherein, The output of the controlled oscillator is connected to a multi-stage frequency divider, wherein subsampling the state of the controlled oscillator includes subsampling the output of the multi-stage frequency divider connected to the controlled oscillator.

12. The method according to claim 9, wherein, Calculating the state difference between each pair of adjacent states includes: Based on the position of each sampled state in the state sequence, each sampled state is converted into a state number; and Subtract the previous state number from the current state number.

13. The method of claim 9, further comprising: To navigate around some state differences, follow these steps: If the state difference is greater than the total number of states divided by 2, then subtract the number representing the total number of states from the state difference; or If the state difference is less than a negative number equal to the total number of states divided by 2, then the number representing the total number of states is added to the state difference.

14. The method of claim 9, further comprising: Correct or skip some of the aforementioned state differences.

15. The method of claim 9, further comprising: The initial average value of the state difference is obtained by averaging the state differences of the first few samples over the same period.

16. The method of claim 15, further comprising: Based on comparing the state differences with the initial average value, some of the state differences are skipped.

17. The method according to claim 16, wherein, The skipped state differences are those state differences that are less than the initial average minus 1 and greater than the initial average plus 1.

18. The method according to claim 16, wherein, The skipped state differences are those that are not included in the range [initial average - Max_state_difference + |initial average|, initial average + Max_state_difference - |initial average|], where Max_state_difference is the maximum value among the state differences, and |initial average| is the absolute value of the initial average.

19. The method of claim 9, further comprising: The average state difference is obtained by averaging the state differences over a period of time.

20. The method according to claim 9, wherein, A lookup table is used to perform frequency offset estimation based on the state difference, the lookup table containing a list of state difference averages with corresponding frequency offsets.

21. The method according to claim 9, wherein, Frequency offset is estimated based on the state differences by multiplying the sum of the state differences by a constant, wherein the constant is determined based on the sampling frequency and the time period used to average the state differences.

22. The method of claim 9, wherein, The method is executed periodically.

23. The method according to any one of claims 9 to 22, wherein, Based on the estimated frequency offset, subsampling is performed alternately between subsampling the output of the multi-stage frequency divider connected to the controlled oscillator and subsampling the output of the controlled oscillator.

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