Data processing method, processing device, electronic device and storage medium

Abstract

The present disclosure provides a data processing method. The method includes generating a random number with a preset value interval for the first target cache data when accessing the first target cache data stored in the first cache area of ​​the cache space, wherein the cache space also includes a second cache area and a third cache area, and the historical call frequencies of the cache data stored in the first cache area, the second cache area, and the third cache area increase in sequence; determining the movement probability when the first target cache data is called; and when the random number is less than or equal to the movement probability, moving the first target cache data to the head of the third cache area. The present disclosure also provides a data processing device, an electronic device, a storage medium, and a computer program product.

Description

Technical Field

[0001] The present disclosure relates to the technical field of computer technology, and more specifically, to a data processing method, a processing device, an electronic device, a storage medium, and a computer program product. Background Art

[0002] MySQL is a relational database management system that stores data in different tables instead of placing all data in a large warehouse, which can increase the speed of data processing and improve the flexibility of data management. LRU cache is a common cache technology used to achieve the interaction between internal database data and external data.

[0003] In the process of implementing the concept of the present disclosure, the inventors found that there are at least the following problems in the related art: when the access frequency is not high, the cache system has the problem of performance jitter. Summary of the invention

[0004] In view of this, the present disclosure provides a data processing method, a processing device, an electronic device, a storage medium, and a computer program product.

[0005] One aspect of the present disclosure provides a data processing method, comprising:

[0006] In the case of accessing first target cache data stored in a first cache area of ​​the cache space, generating a random number with a value of a preset value interval for the first target cache data, wherein the cache space further includes a second cache area and a third cache area, and the historical call frequencies of the cache data stored in the first cache area, the second cache area, and the third cache area are increased in sequence;

[0007] determining a movement probability when the first target cache data is called; and

[0008] When the random number is less than or equal to the move probability, the first target cache data is moved to the head of the third cache area.

[0009] According to an embodiment of the present disclosure, the data processing method further includes:

[0010] When the random number is greater than the movement probability, the storage location of the first target cache data is kept unchanged.

[0011] According to an embodiment of the present disclosure, determining the movement probability when the first target cache data is called includes:

[0012] Obtaining a loading time and an access time of the first target cache data, wherein the loading time is used to represent a time when the first target cache data is loaded into the cache space, and the access time is used to represent a time when the first target cache data is accessed after being loaded into the cache space;

[0013] Obtaining the number of times the first target cache data is accessed within a time period from the loading time to the access time; and

[0014] The movement probability is determined according to the loading time, the access time and the number of accesses.

[0015] According to an embodiment of the present disclosure, obtaining the number of times the first target cache data is accessed within a time period from the loading time to the access time includes:

[0016] determining a first counter for recording access information of the first target cache data; and

[0017] The first counter is used to determine the number of accesses.

[0018] According to an embodiment of the present disclosure, the data processing method further includes:

[0019] When accessing second target cache data stored in the second cache area, the second target cache data is moved to the head of the first cache area.

[0020] According to an embodiment of the present disclosure, the data processing method further includes:

[0021] When the current time reaches the predefined time, the cached data cached at the tail of the third cache area is removed.

[0022] According to an embodiment of the present disclosure, the data processing method further includes:

[0023] Determining third target cache data that needs to be removed;

[0024] determining a second counter for recording access information of the third target cache data; and

[0025] The third target cache data and the access information thereof are removed from the second counter.

[0026] Another aspect of the present disclosure provides a data processing device, comprising:

[0027] a generating module, configured to generate a random number having a value within a preset value interval for first target cache data when accessing first target cache data stored in a first cache area of ​​a cache space, wherein the cache space further includes a second cache area and a third cache area, and the historical calling frequencies of the cache data stored in the first cache area, the second cache area, and the third cache area are increased in sequence;

[0028] A first determining module, configured to determine a movement probability when the first target cache data is called; and

[0029] The first moving module is configured to move the first target cache data to the head of the third cache area when the random number is less than or equal to the moving probability.

[0030] Another aspect of the present disclosure provides a computer system, including: one or more processors; and a memory for storing one or more programs, wherein when the one or more programs are executed by the one or more processors, the one or more processors implement the method as described above.

[0031] Another aspect of the present disclosure provides a computer-readable storage medium having computer-executable instructions stored thereon, which are used to implement the method described above when the instructions are executed.

[0032] Another aspect of the present disclosure provides a computer program product, which includes computer executable instructions, and when the instructions are executed, are used to implement the method as described above.

[0033] According to an embodiment of the present disclosure, when accessing the first target cache data in the first cache area stored in the cache space, a random number with a value in a preset numerical range is generated for the first target cache data. Then, the movement probability when the first target cache data is called is determined, and when the random number is less than or equal to the movement probability, the first target cache data is moved to the head of the third cache area. Since the result of whether the first target cache data is moved is determined based on the random number generated for the first target cache data and the movement probability when the first target cache data is called, the problem of performance jitter caused by mistakenly loading data from the first target cache area to the third cache area in non-high-speed scenarios is solved to a certain extent. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] The above and other objects, features and advantages of the present disclosure will become more apparent through the following description of the embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0035] Figure 1An exemplary system architecture to which the data processing method according to an embodiment of the present disclosure can be applied is schematically shown.

[0036] Figure 2 The flowchart of the data processing method according to the embodiment of the present disclosure is schematically shown.

[0037] Figure 3 The flowchart of a data processing method according to another embodiment of the present disclosure is schematically shown.

[0038] Figure 4 The block diagram schematically shows a data processing device according to an embodiment of the present disclosure.

[0039] Figure 5 A block diagram of a computer system suitable for implementing the method described above according to an embodiment of the present disclosure is schematically shown. DETAILED DESCRIPTION

[0040] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the present disclosure. In the following detailed description, for ease of explanation, many specific details are set forth to provide a comprehensive understanding of the embodiments of the present disclosure. However, it is apparent that one or more embodiments may also be implemented without these specific details. In addition, in the following description, descriptions of known structures and technologies are omitted to avoid unnecessary confusion of the concepts of the present disclosure.

[0041] The terms used herein are only for describing specific embodiments and are not intended to limit the present disclosure. The terms "comprise", "include", etc. used herein indicate the existence of the features, steps, operations and / or components, but do not exclude the existence or addition of one or more other features, steps, operations or components.

[0042] All terms (including technical and scientific terms) used herein have the meanings commonly understood by those skilled in the art, unless otherwise defined. It should be noted that the terms used herein should be interpreted as having a meaning consistent with the context of this specification, and should not be interpreted in an idealized or overly rigid manner.

[0043] In the case of using expressions such as "at least one of A, B, and C, etc.", it should generally be interpreted in accordance with the meaning of the expression generally understood by those skilled in the art (for example, "a system having at least one of A, B, and C" should include but is not limited to a system having A alone, B alone, C alone, A and B, A and C, B and C, and / or A, B, C, etc.). In the case of using expressions such as "at least one of A, B, or C, etc.", it should generally be interpreted in accordance with the meaning of the expression generally understood by those skilled in the art (for example, "a system having at least one of A, B, or C" should include but is not limited to a system having A alone, B alone, C alone, A and B, A and C, B and C, and / or A, B, C, etc.).

[0044] MySQL is a relational database management system that stores data in different tables instead of placing all data in a large warehouse, which can increase the speed of data processing and improve the flexibility of data management. LRU cache is a common cache technology used to achieve the interaction between internal database data and external data.

[0045] In the MySQL LRU cache, there are cold data areas and hot data areas. If the data in the cold data area has survived in the cold data area for more than a preset time (such as 1 second), it will be directly loaded into the head of the hot data area when it is accessed again. This strategy may be suitable in the high-speed access scenario of MySQL, but in some environments with low access frequency, this strategy will cause serious performance jitter, that is, the data in the cold data area is loaded into the hot data area, and the entire list is frequently moved and deleted.

[0046] In the process of implementing the concept of the present disclosure, the inventors found that there are at least the following problems in the related art: when the access frequency is not high-speed, the cold data area may be mistakenly loaded into the hot data area, causing system performance jitter.

[0047] The embodiments of the present disclosure provide a data processing method and a data processing device. The data processing method includes generating a random number with a value in a preset numerical range for the first target cache data when accessing the first target cache data stored in the first cache area of ​​the cache space, wherein the cache space also includes a second cache area and a third cache area, and the historical call frequencies of the cache data stored in the first cache area, the second cache area, and the third cache area increase in sequence; determining the movement probability when the first target cache data is called; and moving the first target cache data to the head of the third cache area when the random number is less than or equal to the movement probability.

[0048] Figure 1 The exemplary system architecture 100 to which the data processing method according to the embodiment of the present disclosure can be applied is schematically shown. It should be noted that: Figure 1 What is shown is merely an example of a system architecture to which the embodiments of the present disclosure can be applied, in order to help those skilled in the art understand the technical content of the present disclosure, but it does not mean that the embodiments of the present disclosure cannot be used in other devices, systems, environments or scenarios.

[0049] like Figure 1 As shown, the system architecture 100 according to this embodiment may include terminal devices 101, 102, 103, a network 104 and a server 105. The network 104 is used to provide a medium for communication links between the terminal devices 101, 102, 103 and the server 105. The network 104 may include various connection types, such as wired and / or wireless communication links, etc.

[0050] Users can use terminal devices 101, 102, 103 to interact with server 105 through network 104 to receive or send messages, etc. Various communication client applications can be installed on terminal devices 101, 102, 103, such as shopping applications, web browser applications, search applications, instant messaging tools, email clients and / or social platform software, etc. (only as examples).

[0051] The terminal devices 101 , 102 , and 103 may be various electronic devices having a display screen and supporting web browsing, including but not limited to smart phones, tablet computers, laptop computers, and desktop computers.

[0052] The server 105 may be a server that provides various services, such as a background management server (only an example) that provides support for websites browsed by users using the terminal devices 101, 102, and 103. The background management server may analyze and process the received data such as user requests, and feed back the processing results (such as web pages, information, or data obtained or generated according to user requests) to the terminal device.

[0053] It should be noted that the data processing method provided in the embodiment of the present disclosure can generally be executed by the server 105. Accordingly, the data processing device provided in the embodiment of the present disclosure can generally be set in the server 105. The data processing method provided in the embodiment of the present disclosure can also be executed by a server or server cluster that is different from the server 105 and can communicate with the terminal devices 101, 102, 103 and / or the server 105. Accordingly, the data processing device provided in the embodiment of the present disclosure can also be set in a server or server cluster that is different from the server 105 and can communicate with the terminal devices 101, 102, 103 and / or the server 105. Alternatively, the data processing method provided in the embodiment of the present disclosure can also be executed by the terminal devices 101, 102, or 103, or can also be executed by other terminal devices different from the terminal devices 101, 102, or 103. Accordingly, the data processing device provided in the embodiment of the present disclosure can also be set in the terminal devices 101, 102, or 103, or can be set in other terminal devices different from the terminal devices 101, 102, or 103.

[0054] For example, the data to be processed may be originally stored in the server 105, or may be stored in an external storage device and may be imported into the server 105. The server 105 may then locally execute the data processing method provided by the embodiment of the present disclosure.

[0055] It should be understood that Figure 1 The number of terminal devices, networks and servers in the embodiment is only for illustration. Any number of terminal devices, networks and servers may be provided according to implementation requirements.

[0056] Figure 2 The flowchart of the data processing method according to the embodiment of the present disclosure is schematically shown.

[0057] like Figure 2 As shown, the method includes operations S201 to S203.

[0058] In operation S201, when accessing first target cache data stored in a first cache area of ​​a cache space, a random number having a value in a preset value range is generated for the first target cache data. The cache space also includes a second cache area and a third cache area, and the historical call frequencies of the cache data stored in the first cache area, the second cache area, and the third cache area increase in sequence.

[0059] According to an embodiment of the present disclosure, the first cache area may include, for example, a cold data area, which may include, for example, cache data with an access frequency lower than a first preset threshold or cache data loaded for the first time. The second cache area may include, for example, a hot data area, which may include, for example, cache data with an access frequency higher than a second preset threshold. The third cache area may include, for example, a hot data area, which may include, for example, cache data with an access frequency higher than a third preset threshold. It should be noted that the access frequency of the cache data in the third cache area is higher than that of the cache data in the second cache area, and the cache data in the second cache area may generally also include data shifted from the third cache area.

[0060] According to an embodiment of the present disclosure, the preset numerical range may include, for example, a numerical range between any two numbers, and the random number may include, for example, any number in the numerical range. For example, the numerical range may be, for example, a numerical range from 0 to 1, and the random number may be, for example, any number in the numerical range from 0 to 1. Selecting the numerical range from 0 to 1 can facilitate comparison with the movement probability.

[0061] It should be noted that the selection of the above numerical range is only an illustrative embodiment. According to specific implementation requirements, any numerical range may be selected, for example, a numerical range of 0 to 10 or a numerical range of 0 to 100, etc.

[0062] In operation S202 , a move probability when the first target cache data is called is determined.

[0063] According to an embodiment of the present disclosure, the movement probability may, for example, include a movement probability determined by a loading time, an access time, and a number of accesses. The loading time may, for example, include a time characterizing that the first target cache data is loaded into the cache space. The access time may, for example, include a time characterizing that the first target cache data is accessed after being loaded into the cache space. The number of accesses may, for example, include the number of times the first target cache data is accessed within a time period from the loading time to the access time. It should be noted that the above embodiments are only illustrative embodiments, and according to actual needs, the movement probability may be determined by other methods that can be thought of by those skilled in the art.

[0064] In operation S203 , when the random number is less than or equal to the move probability, the first target cache data is moved to the head of the third cache area.

[0065] According to an embodiment of the present disclosure, the head of the third cache area may include, for example, the front end of the third cache area at this time. After the first target cache data is moved to the head of the third cache area, the other cache data are sequentially moved backward by one cache area unit position. Each cache area may be composed of, for example, multiple cache area units.

[0066] According to an embodiment of the present disclosure, when accessing the first target cache data in the first cache area stored in the cache space, a random number with a value in a preset numerical range is generated for the first target cache data. Then, the movement probability when the first target cache data is called is determined, and when the random number is less than or equal to the movement probability, the first target cache data is moved to the head of the third cache area. Since the result of whether the first target cache data is moved is determined based on the random number generated for the first target cache data and the movement probability when the first target cache data is called, the problem of performance jitter caused by mistakenly loading data from the first target cache area to the third cache area in non-high-speed scenarios is solved to a certain extent.

[0067] According to an embodiment of the present disclosure, the data processing method further includes: when the random number is greater than the movement probability, keeping the storage location of the first target cache data unchanged.

[0068] According to an embodiment of the present disclosure, the movement probability may include any reasonable probability distribution, for example. Since the result of whether the first target cache data is moved is determined based on the random number generated for the first target cache data and the movement probability when the first target cache data is called, the problem of performance jitter caused by mistakenly loading data in the first target cache area to the third cache area in a non-high-speed scenario is solved to a certain extent.

[0069] According to an embodiment of the present disclosure, determining the movement probability when the first target cache data is called includes: obtaining the loading time and access time of the first target cache data. The loading time is used to characterize the time when the first target cache data is loaded into the cache space, and the access time is used to characterize the time when the first target cache data is accessed after being loaded into the cache space. Obtain the number of times the first target cache data is accessed within the time period from the loading time to the access time. Determine the movement probability based on the loading time, the access time, and the number of times it is accessed.

[0070] According to an embodiment of the present disclosure, the loading time and the access time may be, for example, in milliseconds, which can increase the accuracy of calculation. Specifically, the loading time and the access time may also be in other time units.

[0071] According to an embodiment of the present disclosure, the movement probability may be represented by P(load, visits), for example. The calculation method of P(load, visits) may be as shown in formula (1), for example.

[0072]

[0073] Among them, cur is the access time; load is the loading time; visits is the number of visits.

[0074] According to an embodiment of the present disclosure, obtaining the number of accesses of the first target cache data in a time period from the loading time to the access time includes: determining a first counter for recording access information of the first target cache data. The first counter is used to determine the number of accesses.

[0075] According to an embodiment of the present disclosure, the first counter may include, for example, a counter that can simultaneously record the loading time, access time, and access count of multiple cache data.

[0076] According to an embodiment of the present disclosure, the number of accesses may be counted, for example, by a counter, or the number of accesses may also be counted by other tools, which is not limited in the embodiment of the present disclosure.

[0077] According to an embodiment of the present disclosure, the data processing method further includes: when accessing second target cache data stored in the second cache area, moving the second target cache data to the head of the first cache area.

[0078] According to an embodiment of the present disclosure, the data processing method further includes: when the current time reaches a predefined time, removing the cached data cached at the end of the third cache area.

[0079] According to the embodiments of the present disclosure, the predefined time may be determined, for example, by a background timer task, or may be determined by a method that can achieve the same technical effect, such as setting a cache cleanup cycle, etc. The embodiments of the present disclosure do not limit the method for determining the predefined time.

[0080] According to the embodiments of the present disclosure, by periodically removing the cache data at the tail of the third cache area, the cache data with the lowest access frequency can be periodically cleared, thereby releasing the cache resources of the system.

[0081] According to an embodiment of the present disclosure, the data processing method further includes: determining the third target cache data to be removed, determining a second counter for recording access information of the third target cache data, and removing the third target cache data and its access information from the second counter.

[0082] According to an embodiment of the present disclosure, the second counter may include, for example, a counter that can simultaneously record the loading time, access time, and access count of multiple cache data.

[0083] According to an embodiment of the present disclosure, for example, the system may automatically determine cache data in a cold data area that needs to be deleted, and while deleting the cache data, statistical data associated with the cache data in a counter may be deleted.

[0084] Figure 3The flowchart of a data processing method according to another embodiment of the present disclosure is schematically shown.

[0085] like Figure 3 As shown, the cache area of ​​the method includes a hot data area 310 , a warm data area 320 and a cold data area 330 .

[0086] In this embodiment, the hot data area 310 is composed of one cache area unit, the hot data area 320 is composed of three cache area units, and the cold data area 330 is composed of four cache area units.

[0087] The historical call frequency of the cache data stored in the hot data area 310, the hot data area 320 and the cold data area 330 is reduced in sequence. When new target cache data 331 needs to be added to the cache data and the cache space is full. At this time, the system can delete the cache data 332 at the tail of the cold data area 330 and delete the cache data 332 from the counter. Then, the target cache data 331 is stored at the front end of the cold data area 330.

[0088] Figure 4 The block diagram schematically shows a data processing device according to an embodiment of the present disclosure.

[0089] like Figure 4 As shown, the data processing device 400 includes a generating module 401 , a first determining module 402 and a first moving module 403 .

[0090] Generation module 401 is used to generate a random number with a value in a preset numerical range for the first target cache data when accessing the first target cache data in the first cache area stored in the cache space, wherein the cache space also includes a second cache area and a third cache area, and the historical call frequencies of the cache data stored in the first cache area, the second cache area and the third cache area increase successively.

[0091] The first determining module 402 is used to determine the movement probability when the first target cache data is called.

[0092] The first moving module 403 is configured to move the first target cache data to the head of the third cache area when the random number is less than or equal to the moving probability.

[0093] According to an embodiment of the present disclosure, the data processing device 400 further includes a processing module.

[0094] The processing module is used to keep the storage location of the first target cache data unchanged when the random number is greater than the movement probability.

[0095] According to an embodiment of the present disclosure, the first determining module 402 includes a first acquiring unit, a second acquiring unit and a determining unit.

[0096] The first acquisition unit is used to acquire the loading time and access time of the first target cache data, wherein the loading time is used to represent the time when the first target cache data is loaded into the cache space, and the access time is used to represent the time when the first target cache data is accessed after being loaded into the cache space.

[0097] The second acquisition unit is used to acquire the number of times the first target cache data is accessed within a time period from the loading time to the access time.

[0098] The determination unit is used to determine the movement probability according to the loading time, the access time and the number of accesses.

[0099] According to an embodiment of the present disclosure, the first acquiring unit includes a first determining subunit and a second determining subunit.

[0100] The first determining subunit is used to determine a first counter for recording access information of the first target cache data.

[0101] The second determining subunit is used to determine the number of accesses using the first counter.

[0102] According to an embodiment of the present disclosure, the data processing device 400 further includes a moving module.

[0103] The moving module is used to move the second target cache data stored in the second cache area to the head of the first cache area when accessing the second target cache data.

[0104] According to an embodiment of the present disclosure, the data processing device 400 further includes a first removing module.

[0105] The first removing module is used to remove the cache data cached at the end of the third cache area when the current time reaches a predefined time.

[0106] According to an embodiment of the present disclosure, the data processing device 400 further includes a second determining module, a third determining module and a second removing module.

[0107] The second determining module is used to determine the third target cache data that needs to be removed.

[0108] The third determining module is used to determine a second counter for recording access information of third target cache data.

[0109] The second removing module is used to remove the third target cache data and the access information thereof from the second counter.

[0110] According to the embodiments of the present invention, any one or more of the modules, submodules, units, and subunits, or at least part of the functions of any one of them can be implemented in one module. According to the embodiments of the present invention, any one or more of the modules, submodules, units, and subunits can be split into multiple modules for implementation. According to the embodiments of the present invention, any one or more of the modules, submodules, units, and subunits can be at least partially implemented as hardware circuits, such as field programmable gate arrays (FPGAs), programmable logic arrays (PLAs), systems on chips, systems on substrates, systems on packages, application specific integrated circuits (ASICs), or can be implemented by hardware or firmware in any other reasonable way of integrating or packaging the circuit, or implemented in any one of the three implementation methods of software, hardware, and firmware, or in any appropriate combination of any of them. Alternatively, according to the embodiments of the present invention, one or more of the modules, submodules, units, and subunits can be at least partially implemented as computer program modules, and when the computer program modules are run, the corresponding functions can be performed.

[0111] For example, any multiple of the generation module 401, the first determination module 402 and the first movement module 403 can be combined in one module / unit / subunit for implementation, or any one of the modules / units / subunits can be split into multiple modules / units / subunits. Alternatively, at least part of the functions of one or more of these modules / units / subunits can be combined with at least part of the functions of other modules / units / subunits and implemented in one module / unit / subunit. According to an embodiment of the present disclosure, at least one of the generation module 401, the first determination module 402 and the first movement module 403 can be at least partially implemented as a hardware circuit, such as a field programmable gate array (FPGA), a programmable logic array (PLA), a system on a chip, a system on a substrate, a system on a package, an application specific integrated circuit (ASIC), or can be implemented by hardware or firmware such as any other reasonable way of integrating or packaging the circuit, or by any one of the three implementation methods of software, hardware and firmware or by a suitable combination of any of them. Alternatively, at least one of the generating module 401, the first determining module 402 and the first moving module 403 may be at least partially implemented as a computer program module, and when the computer program module is executed, a corresponding function may be performed.

[0112] It should be noted that the data processing device part in the embodiments of the present disclosure corresponds to the data processing method part in the embodiments of the present disclosure. The description of the data processing device part specifically refers to the data processing method part, which will not be repeated here.

[0113] Figure 5A block diagram of a computer system suitable for implementing the method described above according to an embodiment of the present disclosure is schematically shown. Figure 5 The computer system shown is only an example and should not bring any limitation to the functions and scope of use of the embodiments of the present disclosure.

[0114] like Figure 5 As shown, the computer system 500 according to the embodiment of the present disclosure includes a processor 501, which can perform various appropriate actions and processes according to the program stored in the read-only memory (ROM) 502 or the program loaded from the storage part 508 to the random access memory (RAM) 503. The processor 501 may include, for example, a general-purpose microprocessor (such as a CPU), an instruction set processor and / or a related chipset and / or a special-purpose microprocessor (for example, an application-specific integrated circuit (ASIC)), etc. The processor 501 may also include an onboard memory for caching purposes. The processor 501 may include a single processing unit or multiple processing units for performing different actions of the method flow according to the embodiment of the present disclosure.

[0115] In RAM503, various programs and data required for the operation of system 500 are stored. Processor 501, ROM502 and RAM503 are connected to each other through bus 504. Processor 501 performs various operations of the method flow according to the embodiment of the present disclosure by executing the program in ROM 502 and / or RAM503. It should be noted that the program can also be stored in one or more memories other than ROM502 and RAM503. Processor 501 can also perform various operations of the method flow according to the embodiment of the present disclosure by executing the program stored in the one or more memories.

[0116] According to an embodiment of the present disclosure, the system 500 may further include an input / output (I / O) interface 505, which is also connected to the bus 504. The system 500 may further include one or more of the following components connected to the I / O interface 505: an input section 506 including a keyboard, a mouse, etc.; an output section 507 including a cathode ray tube (CRT), a liquid crystal display (LCD), etc., and a speaker, etc.; a storage section 508 including a hard disk, etc.; and a communication section 509 including a network interface card such as a LAN card, a modem, etc. The communication section 509 performs communication processing via a network such as the Internet. A drive 510 is also connected to the I / O interface 505 as needed. A removable medium 511, such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, etc., is installed on the drive 510 as needed, so that a computer program read therefrom is installed into the storage section 508 as needed.

[0117] According to an embodiment of the present disclosure, the method flow according to an embodiment of the present disclosure can be implemented as a computer software program. For example, an embodiment of the present disclosure includes a computer program product, which includes a computer program carried on a computer-readable storage medium, and the computer program contains a program code for executing the method shown in the flowchart. In such an embodiment, the computer program can be downloaded and installed from the network through the communication part 509, and / or installed from the removable medium 511. When the computer program is executed by the processor 501, the above-mentioned functions defined in the system of the embodiment of the present disclosure are executed. According to an embodiment of the present disclosure, the system, equipment, device, module, unit, etc. described above can be implemented by a computer program module.

[0118] The present disclosure also provides a computer-readable storage medium, which may be included in the device / apparatus / system described in the above embodiments; or may exist independently without being assembled into the device / apparatus / system. The above computer-readable storage medium carries one or more programs, and when the above one or more programs are executed, the method according to the embodiment of the present disclosure is implemented.

[0119] According to an embodiment of the present disclosure, the computer-readable storage medium may be a non-volatile computer-readable storage medium. For example, it may include, but is not limited to: a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination thereof. In the present disclosure, a computer-readable storage medium may be any tangible medium containing or storing a program that may be used by or in combination with an instruction execution system, apparatus, or device.

[0120] For example, according to an embodiment of the present disclosure, the computer-readable storage medium may include the ROM 502 and / or the RAM 503 described above and / or one or more memories other than the ROM 502 and the RAM 503 .

[0121] The embodiments of the present disclosure also include a computer program product, which includes a computer program, which contains program code for executing the method provided by the embodiments of the present disclosure. When the computer program product runs on an electronic device, the program code is used to enable the electronic device to implement the data processing method provided by the embodiments of the present disclosure.

[0122] When the computer program is executed by the processor 501, the above functions defined in the system / device of the embodiment of the present disclosure are executed. According to the embodiment of the present disclosure, the system, device, module, unit, etc. described above can be implemented by a computer program module.

[0123] In one embodiment, the computer program may rely on tangible storage media such as optical storage devices, magnetic storage devices, etc. In another embodiment, the computer program may also be transmitted and distributed in the form of signals on a network medium, and downloaded and installed through the communication part 509, and / or installed from the removable medium 511. The program code contained in the computer program may be transmitted using any appropriate network medium, including but not limited to: wireless, wired, etc., or any suitable combination of the above.

[0124] According to an embodiment of the present disclosure, the program code for executing the computer program provided by the embodiment of the present disclosure can be written in any combination of one or more programming languages. Specifically, these computing programs can be implemented using high-level process and / or object-oriented programming languages, and / or assembly / machine languages. Programming languages ​​include, but are not limited to, Java, C++, python, "C" language or similar programming languages. The program code can be executed entirely on the user computing device, partially on the user device, partially on the remote computing device, or entirely on the remote computing device or server. In the case of a remote computing device, the remote computing device can be connected to the user computing device through any type of network, including a local area network (LAN) or a wide area network (WAN), or can be connected to an external computing device (for example, using an Internet service provider to connect through the Internet).

[0125] The flowcharts and block diagrams in the accompanying drawings illustrate the possible architecture, functions and operations of the systems, methods and computer program products according to various embodiments of the present disclosure. In this regard, each box in the flowchart or block diagram may represent a module, a program segment, or a part of a code, and the above-mentioned module, program segment, or a part of the code contains one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box may also occur in an order different from that marked in the accompanying drawings. For example, two boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram or flowchart, and the combination of boxes in the block diagram or flowchart, can be implemented with a dedicated hardware-based system that performs the specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions. It can be understood by those skilled in the art that the features recorded in the various embodiments and / or claims of the present disclosure can be combined and / or combined in a variety of ways, even if such a combination or combination is not explicitly recorded in the present disclosure. In particular, without departing from the spirit and teaching of the present disclosure, the features described in the various embodiments and / or claims of the present disclosure may be combined and / or combined in a variety of ways. All of these combinations and / or combinations fall within the scope of the present disclosure.

[0126] The embodiments of the present disclosure are described above. However, these embodiments are only for illustrative purposes and are not intended to limit the scope of the present disclosure. Although the embodiments are described above separately, this does not mean that the measures in the various embodiments cannot be used in combination to advantage. The scope of the present disclosure is defined by the attached claims and their equivalents. Without departing from the scope of the present disclosure, those skilled in the art may make a variety of substitutions and modifications, which should all fall within the scope of the present disclosure.

Claims

1. A data processing method, comprising: In the case of accessing first target cache data stored in a first cache area of ​​the cache space, generating a random number with a value of a preset value interval for the first target cache data, wherein the cache space further includes a second cache area and a third cache area, and the historical call frequencies of the cache data stored in the first cache area, the second cache area, and the third cache area are increased in sequence; Determine a movement probability when the first target cache data is called, wherein the movement probability is determined according to a loading time, an access time, and a number of accesses, the loading time being used to characterize a time when the first target cache data is loaded into the cache space, and the access time being used to characterize a time when the first target cache data is accessed after being loaded into the cache space; and When the random number is less than or equal to the move probability, the first target cache data is moved to the head of the third cache area.

2. The method according to claim 1, further comprising: When the random number is greater than the movement probability, the storage location of the first target cache data is kept unchanged.

3. The method according to claim 1, wherein: Determining the movement probability when the first target cache data is called includes: Obtaining the loading time and access time of the first target cache data; Obtaining the number of times the first target cache data is accessed within a time period from the loading time to the access time; and The movement probability is determined according to the loading time, the access time and the number of accesses.

4. The method according to claim 3, wherein: Obtaining the number of times the first target cache data is accessed within a time period from the loading time to the access time includes: determining a first counter for recording access information of the first target cache data; and The first counter is used to determine the number of accesses.

5. The method according to claim 1, further comprising: When accessing second target cache data stored in the second cache area, the second target cache data is moved to the head of the first cache area.

6. The method according to claim 1, further comprising: When the current time reaches the predefined time, the cached data cached at the tail of the third cache area is removed.

7. The method according to claim 1, further comprising: Determining third target cache data that needs to be removed; Determine a second counter for recording access information of the third target cache data; as well as The third target cache data and the access information thereof are removed from the second counter.

8. A data processing device, comprising: a generating module, configured to generate a random number having a value within a preset value interval for first target cache data when accessing first target cache data stored in a first cache area of ​​a cache space, wherein the cache space further includes a second cache area and a third cache area, and the historical calling frequencies of the cache data stored in the first cache area, the second cache area, and the third cache area are increased in sequence; a first determining module, configured to determine a movement probability when the first target cache data is called, wherein the movement probability is determined according to a loading time, an access time, and a number of accesses, wherein the loading time is used to characterize a time when the first target cache data is loaded into the cache space, and the access time is used to characterize a time when the first target cache data is accessed after being loaded into the cache space; and The first moving module is configured to move the first target cache data to the head of the third cache area when the random number is less than or equal to the moving probability.

9. A computer system comprising: one or more processors; a memory for storing one or more programs, When the one or more programs are executed by the one or more processors, the one or more processors implement the method according to any one of claims 1 to 7.

10. A computer-readable storage medium having executable instructions stored thereon, which, when executed by a processor, enables the processor to implement the method according to any one of claims 1 to 7.

11. A computer program product comprising computer executable instructions, which when executed are used to implement the method of any one of claims 1 to 7.

Images