Semiconductor memory device and method of operating the same

Abstract

The present application discloses a semiconductor memory device and a method for operating the semiconductor memory device. A semiconductor memory device includes a memory cell array, a peripheral circuit, a current sensing circuit and a control logic. The memory cell array includes a plurality of memory cells. The peripheral circuit performs a programming operation on a selected memory cell connected to a selected word line among the plurality of memory cells. The current sensing circuit generates a pass signal or a fail signal by performing a current sensing operation on the selected memory cell. The control logic receives the pass signal or the fail signal and controls the operation of the peripheral circuit and the current sensing circuit. The control logic controls the current sensing circuit and the peripheral circuit to perform a current sensing operation and an operation of applying a programming pulse to the selected word line based on the programming progress state of the selected memory cell.

Description

Technical Field

[0001] The present disclosure relates to electronic devices, and more particularly, to a semiconductor memory device and a method of operating the semiconductor memory device. Background Art

[0002] The memory device may be formed in a two-dimensional structure in which strings are arranged horizontally on a semiconductor substrate or in a three-dimensional structure in which strings are vertically stacked on a semiconductor substrate. A three-dimensional memory device is a memory device designed to address the integration limitations of a two-dimensional memory device and may include a plurality of memory cells vertically stacked on a semiconductor substrate. Summary of the invention

[0003] A semiconductor memory device according to an embodiment of the present disclosure may include a memory cell array, a peripheral circuit, a current sensing circuit, and a control logic. The memory cell array may include a plurality of memory cells. The peripheral circuit may perform a programming operation on a selected memory cell connected to a selected word line among the plurality of memory cells. The current sensing circuit may generate a pass signal or a fail signal by performing a current sensing operation on the selected memory cell. The control logic may receive a pass signal or a fail signal and control the operation of the peripheral circuit and the current sensing circuit. The control logic may control the current sensing circuit and the peripheral circuit to perform a current sensing operation and an operation of applying a programming pulse to the selected word line based on the programming progress state of the selected memory cell.

[0004] According to a method of operating a semiconductor memory device according to another embodiment of the present disclosure, a selected memory cell is programmed. The method may include the following steps: applying a programming pulse to a selected word line connected to the selected memory cell; applying a verification voltage to the selected word line; and performing a current sensing operation and an operation of applying a programming pulse based on a programming progress state of the selected memory cell. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figure 1 is a block diagram illustrating a semiconductor memory device according to an embodiment of the present disclosure.

[0006] Figure 2 It is shown Figure 1 FIG. 1 is a diagram of an embodiment of a memory cell array.

[0007] Figure 3 It is shown Figure 2 A circuit diagram of any memory block BLKa among the memory blocks BLK1 to BLKz.

[0008] Figure 4 It is shown Figure 2 A circuit diagram of another embodiment of any one memory block BLKb among the memory blocks BLK1 to BLKz is shown.

[0009] Figure 5 It is shown Figure 1 1 is a circuit diagram of an embodiment of any one memory block BLKc of the memory blocks BLK1 to BLKz included in the memory cell array 110 of FIG.

[0010] Figure 6 is a diagram schematically illustrating a page buffer according to an example of an embodiment.

[0011] Figure 7 is a block diagram showing a memory cell array, a read / write circuit, and a current sensing circuit of a semiconductor memory device.

[0012] Figure 8 is a graph showing target programming states for a three-level cell.

[0013] Fig. 9 is a diagram for describing a program operation according to an embodiment of the present disclosure.

[0014] Fig.10 is a flowchart illustrating a programming method according to another embodiment of the present disclosure.

[0015] Fig.11 It is shown Fig.10 Flow chart of an example of an implementation of step S150.

[0016] Fig.12 is a flowchart showing an implementation of step S250.

[0017] Fig.13 is a flowchart showing an implementation of step S270.

[0018] Fig.14 It shows reference Figures 11 to 13 A diagram describing the programming method.

[0019] Fig.15 It is shown Fig.10 Flow chart of another implementation of step S150.

[0020] Fig.16 It shows reference Fig.15 A diagram describing the programming method.

[0021] Fig.17 It is shown that Figure 1 A block diagram of an embodiment of a memory system of a semiconductor memory device.

[0022] Fig.18 It is shown Fig.17 A block diagram of an application example of a memory system.

[0023] Fig.19It is shown including reference Fig.18 A block diagram of a computing system that describes a memory system. DETAILED DESCRIPTION

[0024] Only the specific structure or functional description of the implementation of the concept disclosed in this specification or application is shown to describe the implementation of the concept according to the present disclosure. The implementation of the concept according to the present disclosure can be implemented in various forms, and the description is not limited to the implementation described in this specification or application.

[0025] Embodiments of the present disclosure may provide a semiconductor memory device having improved programming speed and stability.

[0026] Another embodiment of the present disclosure may provide an operating method of a semiconductor memory device having improved programming speed and stability.

[0027] Figure 1 is a block diagram illustrating a semiconductor memory device according to an embodiment of the present disclosure.

[0028] Reference Figure 1 , the semiconductor memory device 100 includes a memory cell array 110, an address decoder 120, a read / write circuit 130, a control logic 140, a voltage generator 150, and a current sensing circuit 160. The control logic 140 may be implemented as hardware, software, or a combination of hardware and software. For example, the control logic 140 may be a control logic circuit operating according to an algorithm and / or a processor executing a control logic code.

[0029] The memory cell array 110 includes a plurality of memory blocks BLK1 to BLKz. The plurality of memory blocks BLK1 to BLKz are connected to the address decoder 120 through word lines WL. The plurality of memory blocks BLK1 to BLKz are connected to the read / write circuit 130 through bit lines BL1 to BLm. Each of the plurality of memory blocks BLK1 to BLKz includes a plurality of memory cells. As an embodiment, the plurality of memory cells are nonvolatile memory cells and may be configured by nonvolatile memory cells having a vertical channel structure. The memory cell array 110 may be configured as a memory cell array of a two-dimensional structure. According to an embodiment, the memory cell array 110 may be configured as a memory cell array of a three-dimensional structure. In addition, each of the plurality of memory cells included in the memory cell array may store at least one bit of data. In an embodiment, each of the plurality of memory cells included in the memory cell array 110 may be a single-level cell (SLC) storing one bit of data. In another embodiment, each of the plurality of memory cells included in the memory cell array 110 may be a multi-level cell (MLC) storing two bits of data. In another embodiment, each of the plurality of memory cells included in the memory cell array 110 may be a three-level cell storing three-bit data. In another embodiment, each of the plurality of memory cells included in the memory cell array 110 may be a four-level cell storing four-bit data. According to an embodiment, the memory cell array 110 may include a plurality of memory cells each storing five or more bits of data.

[0030] The address decoder 120 is connected to the memory cell array 110 through word lines WL. The address decoder 120 is configured to operate in response to the control of the control logic 140. The address decoder 120 receives an address through an input / output buffer (not shown) within the semiconductor memory device 100.

[0031] The address decoder 120 is configured to decode a block address among the received addresses. The address decoder 120 selects at least one memory block according to the decoded block address. In addition, the address decoder 120 applies the read voltage Vread generated in the voltage generator 150 to the selected word line of the selected memory block during the read voltage application operation during the read operation, and applies the pass voltage Vpass to the remaining unselected word lines. In addition, during the program verification operation, the address decoder 120 applies the verification voltage generated in the voltage generator 150 to the selected word line of the selected memory block, and applies the pass voltage Vpass to the remaining unselected word lines.

[0032] The address decoder 120 may be configured to decode a column address in the received address and send the decoded column address to the read / write circuit 130 .

[0033] The read operation and programming operation of the semiconductor memory device 100 are performed in units of pages. The address received when requesting a read operation and a programming operation includes a block address, a row address, and a column address. The address decoder 120 selects a memory block and a word line according to the block address and the row address. The column address is decoded by the address decoder 120 and provided to the read / write circuit 130. In this specification, the memory cell connected to a word line may be referred to as a "physical page".

[0034] The read-write circuit 130 includes a plurality of page buffers PB1 to PBm. The read-write circuit 130 may operate as a "read circuit" during a read operation of the memory cell array 110, and may operate as a "write circuit" during a write operation of the memory cell array 110. The plurality of page buffers PB1 to PBm are connected to the memory cell array 110 through bit lines BL1 to BLm. During a read operation and a program verification operation, in order to sense the threshold voltage of a memory cell, the plurality of page buffers PB1 to PBm sense the change in the amount of current flowing according to the programming state of the corresponding memory cell through a sensing node while continuously supplying a sensing current to the bit line connected to the memory cell, and latch the sensed change as sensing data. The read-write circuit 130 operates in response to a page buffer control signal output from the control logic 140. In this specification, a write operation of a write circuit may be used as the same meaning as a programming operation on a selected memory cell.

[0035] During a read operation, the read / write circuit 130 senses data of a memory cell, temporarily stores the read data, and outputs the data DATA to an input / output buffer (not shown) of the semiconductor memory device 100. As an example of an implementation, the read / write circuit 130 may include a column selection circuit, etc., in addition to a page buffer (or a page register).

[0036] The control logic 140 is connected to the address decoder 120, the read / write circuit 130, the voltage generator 150, and the current sensing circuit 160. The control logic 140 receives the command CMD and the control signal CTRL through the input / output buffer (not shown) of the semiconductor memory device 100. The control logic 140 is configured to control the overall operation of the semiconductor memory device 100 in response to the control signal CTRL. In addition, the control logic 140 outputs a control signal for adjusting the precharge potential level of the sensing node of the plurality of page buffers PB1 to PBm. The control logic 140 can control the read / write circuit 130 to perform a read operation of the memory cell array 110.

[0037] Furthermore, in response to a pass signal PASS or a fail signal FAIL received from the current sensing circuit 160 , the control logic 140 may determine whether a verification operation on a specific target program state passes or fails.

[0038] The voltage generator 150 generates a read voltage Vread and a pass voltage Vpass during a read operation in response to a control signal output from the control logic 140. In order to generate a plurality of voltages having various voltage levels, the voltage generator 150 may include a plurality of pumping capacitors receiving an internal power supply voltage, and generate the plurality of voltages by selectively enabling the plurality of pumping capacitors in response to the control of the control logic 140.

[0039] The current sensing circuit 160 may generate a reference current in response to an enable bit VRY_BTI<#> received from the control logic 140 during a verification operation, and may output a pass signal PASS or a fail signal FAIL by comparing a reference voltage generated by the reference current with a sensing voltage VPB received from page buffers PB1 to PBm included in the read / write circuit 130.

[0040] For example, the current sensing circuit 160 may determine whether the verification operation corresponding to a specific target program state is completed by comparing a voltage generated according to a value of a bit line sensing latch included in each of the page buffers PB1 to PBm with a reference voltage generated by a reference current. The bit line sensing latch included in each of the page buffers PB1 to PBm will be referred to later. Figure 6 describe.

[0041] The address decoder 120, the read / write circuit 130, and the voltage generator 150 may be used as a “peripheral circuit” that performs read, write, and erase operations on the memory cell array 110. The peripheral circuit performs read, write, and erase operations on the memory cell array 110 based on the control of the control logic 140.

[0042] Figure 2 It is shown Figure 1 FIG. 1 is a diagram of an embodiment of a memory cell array.

[0043] Reference Figure 2 , the memory cell array 110 includes a plurality of memory blocks BLK1 to BLKz. Each memory block may have a three-dimensional structure. Each memory block includes a plurality of memory cells stacked on a substrate. In this way, the plurality of memory cells are arranged along the +X direction, the +Y direction, and the +Z direction. Figure 3 and Figure 4 The structure of each memory block is described in more detail.

[0044] Figure 3 It is shown Figure 2 A circuit diagram of any memory block BLKa among the memory blocks BLK1 to BLKz.

[0045] Reference Figure 3, the memory block BLKa includes a plurality of cell strings CS11 to CS1m and CS21 to CS2m. As an embodiment, each of the plurality of cell strings CS11 to CS1m and CS21 to CS2m may be formed in a "U" shape. In the memory block BLKa, m cell strings are arranged in a row direction (ie, +X direction). Figure 3 In FIG. 1 , two cell strings are arranged in the column direction (ie, +Y direction). However, this is for convenience of description, and it can be understood that three or more cell strings may be arranged in the column direction.

[0046] Each of the plurality of cell strings CS11 to CS1m and CS21 to CS2m includes at least one source select transistor SST, first to nth memory cells MC1 to MCn, a pipe transistor PT, and at least one drain select transistor DST.

[0047] Each of the selection transistors SST and DST and the memory cells MC1 to MCn may have a similar structure. As an embodiment, each of the selection transistors SST and DST and the memory cells MC1 to MCn may include a channel layer, a tunneling insulating film, a charge storage film, and a blocking insulating film. As an embodiment, a column for providing a channel layer may be provided in each cell string. As an embodiment, a column for providing at least one of a channel layer, a tunneling insulating film, a charge storage film, and a blocking insulating film may be provided in each cell string.

[0048] The source selection transistor SST of each cell string is connected between the common source line CSL and the memory cells MC1 to MCp.

[0049] As an embodiment, source selection transistors of cell strings arranged in the same row are connected to a source selection line extending in the row direction, and source selection transistors of cell strings arranged in different rows are connected to different source selection lines. Figure 3 In the embodiment, source selection transistors of the cell strings CS11 to CS1m of the first row are connected to the first source selection line SSL1. Source selection transistors of the cell strings CS21 to CS2m of the second row are connected to the second source selection line SSL2.

[0050] As another embodiment, source selection transistors of the cell strings CS11 to CS1m and CS21 to CS2m may be commonly connected to one source selection line.

[0051] The first to n-th memory cells MC1 to MCn of each cell string are connected between a source select transistor SST and a drain select transistor DST.

[0052] The first to nth memory cells MC1 to MCn may be divided into the first to pth memory cells MC1 and the (p+1)th memory cells MCp+1 to the nth memory cells MCn. The first to pth memory cells MC1 to MCp are sequentially arranged in a direction opposite to the +Z direction and are connected in series between the source selection transistor SST and the tube transistor PT. The (p+1)th memory cells MCp+1 to the nth memory cells MCn are sequentially arranged in the +Z direction and are connected in series between the tube transistor PT and the drain selection transistor DST. The first to pth memory cells MC1 and the (p+1)th memory cells MCp+1 to the nth memory cells MCn are connected to each other through the tube transistor PT. The gates of the first to nth memory cells MC1 to MCn of each cell string are respectively connected to the first to nth word lines WL1 to WLn.

[0053] The gate of the tube transistor PT of each cell string is connected to the pipeline PL.

[0054] The drain selection transistors DST of each cell string are connected between the corresponding bit line and the memory cells MCp+1 to MCn. The cell strings arranged in the row direction are connected to the drain selection lines extending in the row direction. The drain selection transistors of the cell strings CS11 to CS1m of the first row are connected to the first drain selection line DSL1. The drain selection transistors of the cell strings CS21 to CS2m of the second row are connected to the second drain selection line DSL2.

[0055] The cell strings arranged in the column direction are connected to the bit lines extending in the column direction. Figure 4 In the embodiment, the cell strings CS11 and CS21 of the first column are connected to the first bit line BL1. The cell strings CS1m and CS2m of the mth column are connected to the mth bit line BLm.

[0056] Memory cells connected to the same word line in the cell strings arranged in the row direction configure one page. For example, memory cells connected to the first word line WL1 among the cell strings CS11 to CS1m of the first row configure one page. Memory cells connected to the first word line WL1 among the cell strings CS21 to CS2m of the second row configure another page. Cell strings arranged in one row direction can be selected by selecting any one of the drain selection lines DSL1 and DSL2. One page of the selected cell string can be selected by selecting any one of the word lines WL1 to WLn.

[0057] As another embodiment, even bit lines and odd bit lines may be provided instead of the first to mth bit lines BL1 to BLm. In addition, even-numbered cell strings among the cell strings CS11 to CS1m or CS21 to CS2m arranged in the row direction may be connected to even bit lines, respectively, and odd-numbered cell strings among the cell strings CS11 to CS1m or CS21 to CS2m arranged in the row direction may be connected to odd bit lines, respectively.

[0058] As an embodiment, at least one of the first to nth memory cells MC1 to MCn may be used as a dummy memory cell. For example, at least one dummy memory cell is provided to reduce the electric field between the source select transistor SST and the memory cells MC1 to MCp. Alternatively, at least one dummy memory cell is provided to reduce the electric field between the drain select transistor DST and the memory cells MCp+1 to MCn. As more dummy memory cells are provided, the reliability of the operation of the memory block BLKa improves, however, the size of the memory block BLKa increases. As fewer memory cells are provided, the size of the memory block BLKa may be reduced, however, the reliability of the operation of the memory block BLKa may be reduced.

[0059] In order to effectively control at least one dummy memory cell, each dummy memory cell may have a desired threshold voltage. Before or after the erase operation of the memory block BLKa, a programming operation for all or part of the dummy memory cells may be performed. When an erase operation is performed after the programming operation is performed, the dummy memory cells may have a desired threshold voltage by controlling the voltage applied to the dummy word line connected to each dummy memory cell.

[0060] Figure 4 It is shown Figure 2 A circuit diagram of another embodiment of any one memory block BLKb among the memory blocks BLK1 to BLKz is shown.

[0061] Reference Figure 4 , the memory block BLKb includes a plurality of cell strings CS11' to CS1m' and CS21' to CS2m'. Each of the plurality of cell strings CS11' to CS1m' and CS21' to CS2m' extends along the +Z direction. Each of the plurality of cell strings CS11' to CS1m' and CS21' to CS2m' includes at least one source selection transistor SST, first to nth memory cells MC1 to MCn, and at least one drain selection transistor DST stacked on a substrate (not shown) below the memory block BLK1'.

[0062] The source selection transistors SST of each cell string are connected between a common source line CSL and memory cells MC1 to MCn. The source selection transistors of the cell strings arranged in the same row are connected to the same source selection line. The source selection transistors of the cell strings CS11' to CS1m' arranged in the first row are connected to the first source selection line SSL1. The source selection transistors of the cell strings CS21' to CS2m' arranged in the second row are connected to the second source selection line SSL2. As another embodiment, the source selection transistors of the cell strings CS11' to CS1m' and CS21' to CS2m' may be connected together to one source selection line.

[0063] The first to nth memory cells MC1 to MCn of each cell string are connected in series between the source selection transistor SST and the drain selection transistor DST. Gates of the first to nth memory cells MC1 to MCn are connected to the first to nth word lines WL1 to WLn, respectively.

[0064] The drain selection transistors DST of each cell string are connected between the corresponding bit line and the memory cells MC1 to MCn. The drain selection transistors of the cell strings arranged in the row direction are connected to the drain selection lines extending in the row direction. The drain selection transistors of the cell strings CS11' to CS1m' of the first row are connected to the first drain selection line DSL1. The drain selection transistors of the cell strings CS21' to CS2m' of the second row are connected to the second drain selection line DSL2.

[0065] As a result, in addition to excluding the tube transistor PT from each cell string, Figure 4 The memory block BLKb has Figure 3 The equivalent circuit of the storage block BLKa is similar.

[0066] As another embodiment, even bit lines and odd bit lines may be provided instead of the first to mth bit lines BL1 to BLm. In addition, even-numbered cell strings among the cell strings CS11' to CS1m' or CS21' to CS2m' arranged in the row direction may be connected to the even bit lines, respectively, and odd-numbered cell strings among the cell strings CS11' to CS1m' or CS21' to CS2m' arranged in the row direction may be connected to the odd bit lines, respectively.

[0067] As an embodiment, at least one of the first memory cell MC1 to the nth memory cell MCn may be used as a dummy memory cell. For example, at least one dummy memory cell is provided to reduce the electric field between the source selection transistor SST and the memory cells MC1 to MCn. Alternatively, at least one dummy memory cell is provided to reduce the electric field between the drain selection transistor DST and the memory cells MC1 to MCn. As more dummy memory cells are provided, the reliability of the operation of the memory block BLKb is improved, however, the size of the memory block BLKb is increased. As fewer memory cells are provided, the size of the memory block BLKb may be reduced, however, the reliability of the operation of the memory block BLKb may be reduced.

[0068] In order to effectively control at least one dummy memory cell, each dummy memory cell may have a desired threshold voltage. Before or after the erase operation for the memory block BLKb, a programming operation for all or part of the dummy memory cells may be performed. When the erase operation is performed after the programming operation is performed, the dummy memory cells may have a desired threshold voltage by controlling the voltage applied to the dummy word line connected to each dummy memory cell.

[0069] Figure 5 It is shown that the Figure 1 1 is a circuit diagram of an embodiment of any one memory block BLKc among the memory blocks BLK1 to BLKz in the memory cell array 110 of FIG.

[0070] Reference Figure 5 , the memory block BKLc includes a plurality of cell strings CS1 to CSm. The plurality of cell strings CS1 to CSm may be connected to a plurality of bit lines BL1 to BLm, respectively. Each of the cell strings CS1 to CSm includes at least one source selection transistor SST, first to nth memory cells MC1 to MCn, and at least one drain selection transistor DST.

[0071] Each of the selection transistors SST and DST and the memory cells MC1 to MCn may have a similar structure. As an embodiment, each of the selection transistors SST and DST and the memory cells MC1 to MCn may include a channel layer, a tunneling insulating film, a charge storage film, and a blocking insulating film. As an embodiment, a column for providing a channel layer may be provided in each cell string. As an embodiment, a column for providing at least one of a channel layer, a tunneling insulating film, a charge storage film, and a blocking insulating film may be provided in each cell string.

[0072] The source selection transistor SST of each cell string is connected between the common source line CSL and the memory cells MC1 to MCn.

[0073] The first to n-th memory cells MC1 to MCn of each cell string are connected between a source select transistor SST and a drain select transistor DST.

[0074] The drain selection transistor DST of each cell string is connected between the corresponding bit line and the memory cells MC1 to MCn.

[0075] Memory cells connected to the same word line configure one page. Cell strings CS1 to CSm may be selected by selecting a drain selection line DSL. One page among the selected cell strings may be selected by selecting any one of word lines WL1 to WLn.

[0076] As another embodiment, even and odd bit lines may be provided instead of the first to mth bit lines BL1 to BLm. Even-numbered cell strings among the cell strings CS1 to CSm may be connected to the even bit lines, and odd-numbered cell strings may be connected to the odd bit lines, respectively.

[0077] As described above, memory cells connected to one word line configure one physical page. Figure 5 In the example of , among the memory cells belonging to the memory block BLKc, m memory cells connected to any one of the plurality of word lines WL1 to WLn configure one physical page.

[0078] like Figures 2 to 4 As shown, the memory cell array 110 of the semiconductor memory device 100 may be arranged in a three-dimensional structure, but may also be arranged in a Figure 5 As shown, the two-dimensional structure is configured.

[0079] Figure 6 is a diagram schematically illustrating a page buffer 131 according to an example of an embodiment.

[0080] During a read operation or a program verification operation, data stored in a memory cell or a threshold voltage of a memory cell is sensed through the bit line BL. The page buffer 131 may include a bit line sense latch BSLAT; 1314 for storing the sensing result. In addition, the bit line sense latch 1314 may be used to determine a program enable voltage or a program inhibit voltage applied to the bit line BL during a program execution operation.

[0081] The page buffer 131 may include a plurality of data latches 1311, 1312, and 1313 for storing externally input program data during a program operation. Figure 6In the illustrated embodiment, the page buffer 131 can store 3-bit data. In this case, the data latch LAT1 or 1311 can store the most significant bit (MSB), the data latch LAT2 or 1312 can store the center significant bit (CSB), and the data latch LAT3 or 1313 can store the least significant bit (LSB). The data latches 1311, 1312, and 1313 can maintain the stored programming data until the programming of the memory cell is completed.

[0082] In addition, the cache latch CSLAT; 1315 may receive data read from a memory cell during a read operation from the bit line sense latch 1314 and output the data to the outside of the page buffer 131 through a data output line Data_out.

[0083] In addition, the page buffer 131 may include a bit line connection transistor 1316 that controls the connection between the bit line BL and the bit line sense latch 1314 and between the data latches 1311, 1312, and 1313 and the cache latch 1315. The bit line connection transistor 1316 is controlled by a bit line connection signal PB_SENSE. For example, when reading data from a memory cell, the bit line connection transistor 1316 is turned on to electrically connect the bit line BL and the bit line sense latch 1314. In addition, when the data stored in the bit line sense latch 1314 is sent to the cache latch 1315, the bit line connection transistor 1316 may be turned off.

[0084] In the verification process during the programming operation of the memory cell, a value indicating whether the threshold voltage of the memory cell connected to the corresponding bit line BL is greater than the verification voltage corresponding to the target state may be stored in the bit line sense latch 1314. For example, when the threshold voltage of the memory cell connected to the bit line BL is less than the verification voltage corresponding to the target state, a value of "0" may be stored in the bit line sense latch 1314. While the value "0" is stored in the bit line sense latch 1314, when a programming pulse is applied, a program enable voltage is applied to the bit line BL. In addition, as the programming process proceeds, when the threshold voltage of the memory cell connected to the bit line BL is greater than the verification voltage corresponding to the target state, a value of "1" may be stored in the bit line sense latch 1314. When the value "1" is stored in the bit line sense latch 1314, the value of the bit line sense latch 1314 is maintained as "1" in a subsequent programming loop, and when a programming pulse is applied, a program inhibit voltage is applied to the bit line BL. Furthermore, since the threshold voltage of the memory cell corresponding to the erase state E does not need to be increased, the bit line sense latch 1314 of the page buffer 131 connected to the memory cell corresponding to the erase state E may have a value of '1' from the start of programming.

[0085] Therefore, whether the memory cell connected to the bit line BL of the page buffer 131 is programmed to the target program state can be determined by the value of the bit line sense latch 1314. The current sensing circuit 160 performs a current sensing operation based on the value stored in the bit line sense latch 1314 of the page buffer 131. Therefore, the current sensing circuit 160 can determine whether the verification operation corresponding to a specific target program state is completed.

[0086] Figure 7 is a block diagram showing a memory cell array, a read / write circuit, and a current sensing circuit of a semiconductor memory device.

[0087] Reference Figure 7 According to an embodiment, the memory cell array 110 of the semiconductor memory device 100 may include a plurality of memory blocks. Figure 7 Although not shown, according to another embodiment of the present disclosure, a memory cell array of a semiconductor memory device may include a plurality of planes, and each plane may include a plurality of memory blocks.

[0088] A plurality of memory blocks included in the memory cell array 110 may be connected to the read / write circuit 130 through the bit lines BLs. In addition, the read / write circuit 130 may be connected to the current sensing circuit 160.

[0089] When an i-th memory block BLKi is selected as a program target, the semiconductor memory device 100 may perform a program operation on the selected i-th memory block BLKi.

[0090] While performing a programming operation on the i-th memory block BLKi, the current sensing circuit 160 may output a pass signal PASS or a fail signal FAIL for a verification operation of the memory cells included in the i-th memory block BLKi by comparing a reference voltage generated by a reference current with a sensing voltage VPB received from a page buffer included in the write circuit 130. As described above, the operation of outputting a pass signal PASS or a fail signal FAIL for a specific programming state of the memory cells based on the sensing voltage VPB by the current sensing circuit 160 may be referred to as a “current sensing operation”. This will be referred to later. Figure 8 Current sensing operations for specific programming states are described.

[0091] According to the present disclosure, a programming pulse may be applied to a selected word line of a selected i-th storage block BLKi by the read-write circuit 130. In addition, while the programming pulse is applied to the selected word line, the current sensing circuit 160 may perform a current sensing operation. In an embodiment, in order to reduce the programming time, the current sensing operation and the operation of applying the programming pulse to the selected word line may be performed simultaneously. In another embodiment, the current sensing operation and the operation of applying the programming pulse may be performed at different times. The words "simultaneously" and "simultaneously" used herein for occurrence mean that the occurrence is performed at overlapping time intervals. For example, if the first occurrence is performed within a first time interval and the second occurrence is performed simultaneously within a second time interval, the first interval and the second interval overlap at least partially with each other, so that there is a time when both the first occurrence and the second occurrence are performed.

[0092] Figure 8 is a graph showing target programming states for a three-level cell.

[0093] Reference Figure 8 , a three-level cell (TLC) has a total of eight threshold voltage states. The threshold voltage states of the TLC include an erase state E and a first target programming state P1 to a seventh target programming state P7. The erase state E and the first target programming state P1 to the seventh target programming state P7 have corresponding bit codes. Various bit codes can be provided to the erase state E and the first target programming state P1 to the seventh target programming state P7 as needed.

[0094] The respective threshold voltage states can be distinguished based on the first to seventh read voltages R1 to R7. In addition, the first to seventh verification voltages VR1 to VR7 can be used to determine whether programming of memory cells corresponding to respective target program states of a program operation is completed.

[0095] For example, the second verification voltage VR2 is applied to the word line to verify the memory cells corresponding to the second target program state P2 among the memory cells included in the selected physical page. At this time, the memory cells corresponding to the second program state P2 can be verified by Figure 6 1314 is distinguished by the data latches 1311, 1312 and 1313 shown. For example, when the bit code corresponding to the second target programming state is "101", the memory cells connected to the page buffers whose values ​​"1", "0" and "1" are stored in the data latches 1311, 1312 and 1313, respectively, are memory cells to be programmed to the second target programming state P2. Among the memory cells to be programmed to the second target programming state P2, the memory cells whose values ​​of the bit line sense latch 1314 are "0" are memory cells that have not yet been programmed to the second target programming state P2, and the memory cells whose values ​​of the bit line sense latch 1314 are "1" are memory cells that have been programmed to the second target programming state P2.

[0096] The second verification voltage VR2 is applied to the word line and the bit line BL is sensed, and when the threshold voltage of the memory cell is less than the second verification voltage VR2, the value of the bit line sense latch 1314 maintains "0". On the other hand, when the threshold voltage of the memory cell is greater than the second verification voltage VR2, the value of the bit line sense latch 1314 becomes "1". When the value of the bit line sense latch 1314 becomes "1", a program inhibition voltage is applied to the bit line BL connected to the corresponding memory cell in a subsequent programming loop. Therefore, even if a programming pulse is applied to the word line, the threshold voltage of the corresponding memory cell does not increase any more.

[0097] As described above, the operation of changing the value of the bit line sense latch 1314 corresponding to the second verification voltage VR2 is performed separately for the memory cells to be programmed to the second target program state P2. Whether programming is completed for the memory cells to be programmed to the second target program state P2 (i.e., determination of verification pass / fail) is determined by Figure 1 and Figure 7 The current sensing circuit 160 performs.

[0098] exist Figure 1 In the example of , the current sensing circuit 160 determines whether the verification passes or fails by comparing a reference voltage based on a reference current corresponding to the number of memory cells to be programmed to the second target programming state P2 with a sensing voltage VPB based on a sensing current corresponding to the number of memory cells whose threshold voltages are greater than the verification voltage VR2 among the memory cells to be programmed to the second target programming state P2. That is, the current sensing circuit 160 determines whether the verification of the second target programming state P2 passes or fails by comparing the sensing voltage VPB determined according to the number of memory cells whose values ​​are "1" stored in the bit line sense latch BSLAT among the memory cells to be programmed to the second target programming state P2 with the reference voltage.

[0099] As described above, the current sensing circuit can determine verification pass / fail for a specific target programming state (e.g., P2). As described above, among multiple target programming states, the operation of determining verification pass / fail for a specific target programming state can be referred to as a "current sensing operation".

[0100] although Figure 8, but this is an example, and the plurality of memory cells included in the semiconductor memory device according to the embodiment of the present disclosure may be multi-level cells (MLC). In another embodiment, the plurality of memory cells included in the semiconductor memory device according to the embodiment of the present disclosure may be quad-level cells. Hereinafter, the present disclosure will be described with the programming operation of the three-level cell as the center. However, the present disclosure is not limited thereto, and the present disclosure may also be applied to the programming of quad-level cells or memory cells storing five bits or more of data.

[0101] Fig. 9 is a diagram for describing a program operation according to an embodiment of the present disclosure.

[0102] Reference Fig. 9 , showing a voltage applied to a selected word line and a current sensing operation performed by a current sensing circuit while a programming operation is in progress. Fig. 9 The programming operation shown includes a total of N programming loops.

[0103] The first programming pulse VP1 is applied to the word line selected in the first programming loop. Thereafter, the first verification voltage VR1 is applied to the word line selected for the verification operation. The reason why only the first verification voltage VR1 is applied in the first programming loop is that, as a result of performing the first programming loop, the possibility of the existence of memory cells programmed to the second target programming state P2 or higher than the second target programming state P2 is very low. After applying the first verification voltage VR1, the value of the bit line sense latch 1314 of the page buffer connected to the memory cells whose threshold voltage is higher than the first verification voltage VR1 among the memory cells to be programmed to the first target programming state P1 may be changed to "1". On the other hand, the value of the bit line sense latch 1314 of the page buffer connected to the memory cells whose threshold voltage is lower than the first verification voltage VR1 among the memory cells to be programmed to the first target programming state P1 may be maintained at "0".

[0104] After applying the first verification voltage VR1, a current sensing operation CSC1 for the first target program state P1 is performed Since only some of the memory cells to be programmed to the first target program state P1 are programmed, verification for the first target program state P1 fails (CSC1-Fail).

[0105] In addition, while performing the current sensing operation CSC1 for the first target programming state P1, the second programming pulse VP2 may be applied to the selected word line. That is, the second programming loop may be started together with the current sensing operation CSC1 for the first target programming state P1. As described above, the current sensing operation of the first programming loop and the operation of applying the programming pulse of the second programming loop are performed simultaneously in order to reduce the entire programming time. The programming speed may be improved by performing the current sensing operation of the first programming loop and the operation of applying the programming pulse of the second programming loop simultaneously.

[0106] After applying the second programming pulse VP2, the first verification voltage VR1 and the second verification voltage VR2 are applied to the selected word line. As the first verification voltage VR1 and the second verification voltage VR2 are applied, the value of the bit line sense latch 1314 of the page buffer connected to the memory cell to be programmed to the first target programming state P1 and the second target programming state P2, in which the programming is completed, may be changed to "1". On the other hand, the value of the bit line sense latch 1314 of the page buffer connected to the memory cell to be programmed to the first target programming state P1 and the second target programming state P2, in which the programming is not completed, may be maintained at "0".

[0107] The verification voltage applied in each programming loop can be appropriately selected. Fig. 9 In the embodiment, the second verification voltage VR2 is applied from the second programming loop, but according to the embodiment, the second verification voltage VR2 may be applied from the first programming loop or may be applied from the third programming loop.

[0108] After applying the verification voltages VR1 and VR2, the current sensing operation CSC1 for the first target program state P1 is performed again. Fig. 9 In the example of , although the second program pulse VP2 is applied, the program operation on the first target program state P1 is not completed. Therefore, verification for the first target program state P1 fails (CSC1-Fail) in the second program loop.

[0109] While performing the current sensing operation CSC1 for the first target programming state P1, the third programming pulse VP3 may be applied to the selected word line. That is, the third programming loop may start together with the current sensing operation CSC1 for the first target programming state P1. After applying the third programming pulse VP3, the first to third verification voltages VR1 to VR3 are applied to the selected word line. As the first to third verification voltages VR1 to VR3 are applied, the value of the bit line sense latch 1314 of the page buffer connected to the memory cell to be programmed to the first to third target programming states P1 to P3, where programming is completed, may be changed to "1". On the other hand, the value of the bit line sense latch 1314 of the page buffer connected to the memory cell to be programmed to the first to third target programming states P1 to P3, where programming is not completed, may be maintained at "0".

[0110] After applying the verification voltages VR1, VR2, and VR3, the current sensing operation CSC1 for the first target program state P1 is performed again. Fig. 9 In the example of FIG. 1 , the program operation for the first target program state P1 is completed in the third program loop. Therefore, verification for the first target program state P1 passes (CSC1-Pass) in the third program loop.

[0111] While performing the current sensing operation CSC1 for the first target program state P1, the fourth program pulse VP4 may be applied to the selected word line. That is, the fourth programming loop may start with the current sensing operation CSC1 for the first target program state P1. After applying the fourth programming pulse VP4, verification voltages VR2, VR3, and VR4 are applied. Since the verification for the first target program state P1 is passed in the third programming loop, the first verification voltage VR1 may not be applied in the fourth programming loop.

[0112] As the second to fourth verification voltages VR2 to VR4 are applied, the value of the bit line sense latch 1314 of the page buffer connected to the memory cells to be programmed into the second to fourth target program states P2 to P4, in which programming is completed, may be changed to "1". On the other hand, the value of the bit line sense latch 1314 of the page buffer connected to the memory cells to be programmed into the second to fourth target program states P2 to P4, in which programming is not completed, may be maintained at "0".

[0113] Since verification is passed as a result of the current sensing operation CSC1 for the first target program state P1 in the third program loop, the current sensing operation CSC2 for the second target program state P2 is performed in the fourth program loop. Fig. 9In the example of , the program operation for the second target program state P2 is not completed in the fourth program loop. Therefore, verification for the second target program state P2 fails in the fourth program loop (CSC1-Fail).

[0114] Thereafter, as a result of the current sensing operation CSC2 for the second target program state in the fifth program loop, verification is passed. Such a program loop is repeatedly performed. Descriptions of the sixth to (N-3)th programs are omitted.

[0115] In the (N-2)th programming loop, the current sensing operation CSC7 for the seventh target programming state P7 fails. While the current sensing operation CSC7 for the seventh target programming state P7 is performed, the (N-1)th programming pulse VP(N-1) may be applied to the selected word line. That is, the (N-1)th programming loop may start with the current sensing operation CSC7 for the seventh target programming state P7.

[0116] After applying the (N-1)th programming pulse VP(N-1), the seventh verification voltage VR7 is applied to the selected word line. As the seventh verification voltage VR7 is applied, the value of the bit line sense latch 1314 of the page buffer connected to the memory cell to be programmed to the seventh target programming state P7, which has completed programming, may be changed to "1". On the other hand, the value of the bit line sense latch 1314 of the page buffer connected to the memory cell to be programmed to the seventh target programming state P7, which has not completed programming, may be maintained at "0".

[0117] After the seventh verification voltage VR7 is applied, the current sensing operation CSC7 for the seventh target program state P7 is performed again. In addition, the Nth program pulse VPN is applied to the selected word line together with the current sensing operation CSC7 for the seventh target program state P7.

[0118] exist Fig. 9 In the example of , the programming operation for the seventh target programming state P7 is completed in the (N-1)th programming loop. Therefore, the verification for the seventh target programming state P7 passes (CSC7-Pass) in the (N-1)th programming loop. Therefore, the programming operation ends.

[0119] As described above, since the current sensing operation of the (N-1)th programming loop and the application of the Nth programming pulse are performed simultaneously, the Nth programming pulse VPN becomes an unnecessarily applied programming pulse. Since the time required to apply the programming pulse is relatively longer than the time required to perform the current sensing operation, the programming time may be unnecessarily increased due to the application of the Nth programming pulse VPN that does not need to be applied. In addition, due to the unnecessary application of the Nth programming pulse VPN again, an over-programming phenomenon in which the threshold voltage of some of the memory cells to be programmed to the seventh target programming state P7 is too high may occur. This may be a factor that hinders the stability of the programming operation of the semiconductor memory device.

[0120] According to a programming method according to another embodiment of the present disclosure, a current sensing operation and a programming pulse applying operation are performed based on a programming progress state. That is, the current sensing operation and the programming pulse applying operation are performed simultaneously or sequentially according to the programming progress state. Fig. 9 As shown, at the time point when the verification of the last target program state P7 is passed, the unnecessary Nth program pulse VPN can be prevented from being applied. Therefore, the program speed of the semiconductor memory device can be improved, and the stability of the program operation can also be improved.

[0121] Fig.10 is a flowchart showing a programming method according to another embodiment of the present disclosure. Fig.10 According to another embodiment of the present disclosure, a programming method includes: applying a programming pulse to a selected word line (S110); applying a verification voltage to the selected word line (S130); performing a current sensing operation and applying a programming pulse based on a programming progress state of a selected memory cell (S150); and determining whether programming is completed (S170).

[0122] In step S110, a program pulse is applied to the selected word line.In step S110, a first program pulse of a first program loop may be applied.

[0123] In step S130, a verification voltage is applied to the selected word line. In step S130, a verification voltage including at least a first verification voltage may be applied to the selected word line.

[0124] In step S150, a current sensing operation and an operation of applying a programming pulse may be performed based on the programming progress state of the memory cells connected to the selected word line. For example, at the beginning of the programming progress, the current sensing operation and the operation of applying a programming pulse may be performed simultaneously to shorten the entire programming time. However, as the programming progress proceeds or in the second half of the programming progress, the current sensing operation and the operation of applying a programming pulse may be performed sequentially to prevent unnecessary programming pulses from being applied to the selected word line.

[0125] For example, when the programming progress state (programming progress) of the selected memory cell corresponds to the "first state (first stage)", the current sensing operation and the operation of applying the programming pulse may be performed simultaneously. The first state may correspond to an early stage of the programming operation, including the first programming loop among a plurality of programming loops. On the other hand, when the programming progress state of the selected memory cell corresponds to the "second state (second stage)" occurring after the first state, the current sensing operation and the operation of applying the programming pulse may be performed sequentially. The second state may correspond to the final stage of the programming operation, including the last loop among a plurality of programming loops immediately before the programming is completed.

[0126] Will refer to Fig.11 and Fig.15 An example of implementation of step S150 is described.

[0127] In step S170, it is determined whether the programming is completed. As a result of performing step S150, when verification passes for all target program states (S170: Yes), the programming operation may end because the programming is successfully completed. As a result of performing step S150, when verification fails for at least some target program states, the method may proceed to step S150 again, and the programming loop may be repeatedly performed.

[0128] Fig.11 It is shown Fig.10 Flow chart of an example of an implementation of step S150.

[0129] Reference Fig.11 , first, check the state of the programming that has passed the verification (S210). In step S210, the state of the programming of the target for performing the current current sensing operation can be determined by checking the programming state that has passed the verification so far. For example, when the verification of the first target programming state P1 to the third target programming state P3 among the first target programming state P1 to the seventh target programming state P7 passes, it may be necessary to perform a current sensing operation CSC4 on the fourth target programming state P4. As another example, when the verification of the first target programming state P1 to the sixth target programming state P6 among the first target programming state P1 to the seventh target programming state P7 passes, it may be necessary to perform a current sensing operation CSC7 on the seventh target programming state P7 as the last programming state. In this specification, "last programming state" refers to the target programming state corresponding to the highest threshold voltage among multiple target programming states P1 to P7, that is, the seventh target programming state P7.

[0130] In step S230, it is determined whether the current sensing operation corresponds to the last programming state. As described above, when the verification of the first target programming state P1 to the third target programming state P3 among the first target programming state P1 to the seventh target programming state P7 passes, since the current sensing operation corresponds to the fourth target programming state P4, the current sensing operation does not correspond to the last programming state (S230: No). As another example, when the verification of the first target programming state P1 to the sixth target programming state P6 among the first target programming state P1 to the seventh target programming state P7 passes, it is necessary to perform a current sensing operation CSC7 on the seventh target programming state P7 as the last programming state, and the current sensing operation corresponds to the last programming state (S230: Yes). That is, in Fig.11 In an embodiment, when the current sensing operation does not correspond to the last programming state, the programming progress state (programming progress) may correspond to the above-mentioned “first state (first stage)”. On the other hand, when the current sensing operation corresponds to the last programming state, the programming progress state may correspond to the above-mentioned “second state (second stage)”.

[0131] When the current sensing operation corresponds to the last programming state (S230: Yes), this means that the programming operation enters the final stage. Therefore, in this case, the current sensing operation and the operation of applying the programming pulse (S250) are sequentially performed. Therefore, when the verification of the current sensing operation CSC7 corresponding to the last programming state (e.g., P7) passes, it is possible to prevent unnecessary programming pulses from being applied to the selected word line. The detailed implementation of step S250 will be referred to later. Fig.12 describe.

[0132] When the current sensing operation does not correspond to the final programming state (S230: No), this means that the programming operation has not yet entered the final stage. Therefore, in this case, the current sensing operation and the operation of applying the programming pulse (S270) are performed simultaneously. Therefore, the entire programming time can be shortened. The detailed implementation of step S270 will be referred to later. Fig.13 describe.

[0133] After executing step S250 or step S270, the method proceeds to Fig.10 Therefore, when the programming is completed according to the execution of step S250 or step S270 (S170: Yes), the entire programming operation ends. When the programming is not completed according to the execution of step S250 or step S270 (S170: No), the method proceeds to step S150 and performs a subsequent programming loop.

[0134] like Fig.11As shown, according to a programming method of a semiconductor memory device according to another embodiment of the present disclosure, by checking the state of the programming that has passed the verification, the current sensing operation and the operation of applying the programming pulse are performed sequentially or simultaneously according to whether the current sensing operation corresponds to the final programming state. Therefore, when the programming operation enters the final stage, the current sensing operation and the operation of applying the programming pulse are performed sequentially to prevent the application of unnecessary programming pulses. When the programming operation has not yet entered the final stage, the current sensing operation and the operation of applying the programming pulse are performed simultaneously to reduce the programming time. Therefore, the overall programming speed can be improved, and the stability of the programming operation can also be improved.

[0135] Fig.12 is a flowchart showing an implementation of step S250. That is, Fig.12 A flowchart illustrating an embodiment of an operation of sequentially performing a current sensing operation and an operation of applying a program pulse when the current sensing operation corresponds to a last programmed state as a result of the determination of step S230 is shown.

[0136] Reference Fig.12 First, a current sensing operation is performed (S251). Since the current sensing operation is performed when the current sensing operation corresponds to the last programming state as a result of the determination of step S230, Fig.12 Therefore, a current sensing operation CSC7 on the seventh target program state P7 may be performed in step S251.

[0137] Thereafter, in step S253, it is determined whether verification of the seventh target program state P7 fails. When verification passes for the seventh target program state P7 (S253: No), the method proceeds to step S170 to determine whether programming is completed. Since verification of the seventh target program state P7 passes, this means that programming is completed (S170: Yes), so the programming operation can end.

[0138] When verification fails for the seventh target program state P7 (S253: Yes), a subsequent program loop may need to be performed. Therefore, a program pulse is applied to the selected word line (S255), and a verification voltage is applied to the selected word line (S257). In step S257, a seventh verification voltage VR7 may be applied to the selected word line.

[0139] Thereafter, the method proceeds to step S251 again to perform a current sensing operation and performs step S253. This process is repeated until verification of the seventh target program state P7 passes (S253: No).

[0140] Reference Fig.12, after first performing the current sensing operation (S251), it may be determined whether verification fails (S253), and when verification fails (S253: Yes), a subsequent programming pulse may be applied to the selected word line (S255). That is, the current sensing operation and the operation of applying the programming pulse are performed sequentially. Therefore, when the verification of the seventh target programming state P7 passes, the method proceeds directly to step S170 to end the programming operation, and no unnecessary programming pulses are applied.

[0141] Fig.13 is a flowchart showing an implementation of step S270. That is, Fig.13 A flowchart illustrating an embodiment in which, when the current sensing operation does not correspond to the last programmed state as a result of the determination of step S230 , the current sensing operation and the operation of applying a program pulse are simultaneously performed is shown.

[0142] Reference Fig.13 , a current sensing operation is performed (S271), and at the same time, a programming pulse is applied to the selected word line (S273). Since the current sensing operation does not correspond to the last programmed state as a result of the determination of step S230, the current sensing operation is performed Fig.13 Therefore, in step S271, a current sensing operation of any one of the first to sixth target program states P1 to P6 may be performed. For example, a current sensing operation CSC3 of the third target program state P3 may be performed.

[0143] Thereafter, in step S275, for example, it is determined whether verification of the third target program state P3 fails. When verification passes for the third target program state P3 (S275: No), the method proceeds to step S170 to determine whether programming is completed. Even if verification of the third target program state P3 passes, since verification of the fourth to seventh target program states P4 to P7 fails, the method may proceed to step S150 again to perform a subsequent programming loop. In this case, a current sensing operation CSC4 for the fourth target program state P4 may be performed.

[0144] When verification fails for the third target program state P3 (S275: Yes), a subsequent program loop may need to be performed. Therefore, a verification voltage is applied to the selected word line (S277). In step S277, for example, a verification voltage including at least a third verification voltage VR3 may be applied to the selected word line.

[0145] Thereafter, the method proceeds to step S271 and step S273 again to perform a current sensing operation and a program pulse applying operation, respectively, and performs step S275. This process is repeated, for example, until verification of the third target program state P3 passes (S275: No).

[0146] Reference Fig.13 , a current sensing operation (S271) and an operation of applying a programming pulse to a selected word line (S273) are performed simultaneously. Thereafter, it may be determined whether verification has failed (S275), and when verification has failed (S275: Yes), a verification voltage may be applied to the selected word line (S277). That is, the current sensing operation and the operation of applying a programming pulse are performed simultaneously. That is, when the current sensing operation for the first target programming state P1 to the sixth target programming state P6 is performed, the operation of applying a programming pulse belonging to a subsequent programming loop may be performed simultaneously, thereby reducing the entire programming time.

[0147] Fig.14 It shows reference Figures 11 to 13 A diagram describing the programming method. Fig.14 , according to Fig. 9 The program operation is performed in the same manner as shown until the verification is passed as a result of the current sensing operation CSC6 for the sixth target program state P6. That is, since the first to (N-4)th program loops are performed in accordance with the same Fig. 9 The programming operation is performed in the same manner as shown, so repeated description will be omitted.

[0148] exist Fig.14 In the first programming cycle, applying the first programming pulse VP1 corresponds to Fig.10 In step S110, applying a first verification voltage VR1 corresponds to Fig.10 Thereafter, the step of performing the current sensing operation CSC1 on the first target program state P1 belongs to Fig.10 Step S150.

[0149] While the first to (N-4)th program loops are repeatedly executed, since Fig.11 As a result of the determination of step S230, the current sensing operation does not correspond to the last programming state (S230: No), so the method proceeds to step S270. In step S270, the current sensing operation and the operation of applying a programming pulse are performed simultaneously. That is, while performing the first to (N-4)th programming loops, the current sensing operation (S271) and the operation of applying a programming pulse (S273) are performed simultaneously, and then it is determined whether verification fails (S275).

[0150] exist Fig.14 In the (N-4)th programming loop, a current sensing operation CSC6 for the sixth target program state P6 is performed. At the same time, the (N-3)th programming pulse VP(N-3) is applied to the selected word line. Fig.14, since verification is passed as a result of performing the current sensing operation CSC6 on the sixth target program state P6 in the (N-4)th program loop, the target of the current sensing operation is now the seventh target program state P7 as the last program state. Fig.11 As a result of the determination of step S230, the current sensing operation corresponds to the last programming state (S230: Yes), and the method proceeds to step S250. In step S250, the current sensing operation and the operation of applying the programming pulse are sequentially performed. That is, from the (N-3)th programming loop, the current sensing operation (CSC7) and the subsequent operation of applying the programming pulse are sequentially performed. When verification passes as a result of the current sensing operation CSC7 for the seventh target programming state P7, the programming operation ends without the subsequent operation of applying the programming pulse.

[0151] That is, after applying the verification voltage VR7 in the (N-1)th programming loop, the current sensing operation CSC7 (S251) for the seventh target program state P7 is performed, and since the verification passes (S253: No), the method proceeds to step S170 to determine that the programming is completed, and the entire programming operation ends. Fig. 9 In addition to the embodiments shown, according to Fig.14 In the programming method shown, the unnecessary Nth programming pulse VPN is not applied.

[0152] Fig.15 It is shown Fig.10 Flow chart of another implementation of step S150.

[0153] Reference Fig.15 , check the number of programming pulses CNT applied to the selected word line PGM (S310). The number CNT of programming pulses applied to the selected word line PGM is the number of times a programming pulse is applied to the selected word line after the programming operation of the memory cells connected to the selected word line starts, and corresponds to the number of programming loops. For example, when programming pulses are applied up to the fifth programming pulse as a result of the execution of step S310, the number of applied programming pulses CNT checked is PGM It can be five.

[0154] Thereafter, in step S330, the number of program pulses CNT PGM With a predetermined threshold number N TH Compare. Threshold number N TH It can be determined by experiments. For example, when the entire programming operation is completed when the programming pulse is applied 20 times on average as a result of repeated experiments, the threshold number N TH can be determined to be a slightly smaller value. For example, the threshold number N THIt may be determined as 18 or 19. However, this is an example, and another value may be determined as the threshold number N as needed. TH The word "predetermined" as used herein with respect to a parameter (e.g., a predetermined threshold amount) means that the value of the parameter is determined before the parameter is used in a process or algorithm. For some embodiments, the value of the parameter is determined before the process or algorithm begins. In other embodiments, the value of the parameter is determined during the process or algorithm but before the parameter is used in the process or algorithm.

[0155] exist Fig.15 In the embodiment, when the number of programming pulses CNT PGM Less than the threshold number N TH , the programming progress state (programming progress) may correspond to the above-mentioned “first state (first stage)”. On the other hand, when the number of applied programming pulses CNT PGM Equal to or greater than the threshold number N TH , the programming progress state may correspond to the above-mentioned “second state (first stage)”.

[0156] When the number of programming pulses CNT PGM Equal to or greater than the threshold number N TH When (S330: Yes), this means that the programming operation enters the final stage. Therefore, in this case, the current sensing operation and the operation of applying the programming pulse are sequentially performed (S350). Therefore, it is possible to prevent unnecessary programming pulses from being applied to the selected word line in the final stage of the programming operation. Fig.12 The illustrated embodiment configures step S350.

[0157] When the number of programming pulses CNT PGM Less than the threshold number N TH When (S330: No), this means that the programming operation has not yet entered the final stage. Therefore, in this case, the current sensing operation and the operation of applying the programming pulse (S370) are performed simultaneously. Therefore, the entire programming time can be shortened. Fig.13 The illustrated implementation configures step S370.

[0158] After executing step S350 or step S370, the method proceeds to Fig.10 Therefore, when the programming is completed according to the execution of step S350 or step S370 (S170: Yes), the entire programming operation ends. When the programming is not completed according to the execution of step S350 or step S370 (S170: No), the method proceeds to step S150 to perform a subsequent programming loop.

[0159] like Fig.15As shown, according to a programming method of a semiconductor memory device according to another embodiment of the present disclosure, the number CNT of programming pulses applied to the currently selected word line is checked. PGM , and according to the number of programming pulses applied CNT PGM Is it less than the threshold number N? TH , the current sensing operation and the operation of applying the programming pulse are performed sequentially or simultaneously. Therefore, when the programming operation enters the final stage, the current sensing operation and the operation of applying the programming pulse are performed sequentially to prevent the application of unnecessary programming pulses. When the programming operation has not yet entered the final stage, the current sensing operation and the operation of applying the programming pulse are performed simultaneously to reduce the programming time. Therefore, the overall programming speed can be improved, and the stability of the programming operation can also be improved.

[0160] Fig.16 It shows reference Fig.15 A diagram describing the programming method.

[0161] Reference Fig.16 , when the number of programming pulses applied is less than the threshold N TH When, according to Fig. 9 That is, since the programming operation is performed in the same manner as shown in FIG. Fig. 9 The programming operation is performed in the same manner as shown until the first to the (N TH -1) programming loop, so repeated description will be omitted.

[0162] exist Fig.16 In the first programming cycle, applying the first programming pulse VP1 corresponds to Fig.10 In step S110, applying a first verification voltage VR1 corresponds to Fig.10 Thereafter, the step of performing the current sensing operation CSC1 on the first target program state P1 belongs to Fig.10 Step S150.

[0163] In repeatedly performing the first to (N TH -1) While programming the loop, as Fig.15 As a result of the determination of step S330, the number CNT of programming pulses applied to the selected word line PGM Less than the threshold number N TH (S330: No), so the method proceeds to step S370. In step S370, the current sensing operation and the operation of applying the programming pulse are performed simultaneously. That is, after performing the first to the (N TH -1) While the program loop is in progress, a current sensing operation (S271) and an operation of applying a program pulse (S273) are simultaneously performed, and then it is determined whether verification fails (S275).

[0164] exist Fig.16 In the (N TH -1) In the programming loop, a current sensing operation CSC6 is performed on the sixth target program state P6. At the same time, the (N)th programming pulse VPN TH is applied to the selected word line. Therefore, since the number CNT of program pulses applied to the selected word line is PGM Equal to the threshold number N TH (S330: Yes), so the method proceeds to step S350. Therefore, in step S350, the current sensing operation and the operation of applying the programming pulse are sequentially performed. That is, from the Nth programming loop, the current sensing operation CSC7 and the subsequent operation of applying the programming pulse are sequentially performed. When the verification is passed as a result of the current sensing operation CSC7 for the seventh target programming state P7, the programming operation ends without the subsequent operation of applying the programming pulse.

[0165] That is, in the (N TH +3) After applying the verification voltage VR7 in the programming loop, a current sensing operation CSC7 (S251) is performed on the seventh target programming state P7. Since the verification passes (S253: No), the method proceeds to step S170 to determine that the programming is completed, and the entire programming operation ends. Therefore, unlike Fig. 9 The embodiment shown, according to Fig.16 The programming method shown does not impose unnecessary TH +4) Programming pulse.

[0166] Fig.17 It is shown that Figure 1 1 is a block diagram of an embodiment of a memory system 1000 of a semiconductor memory device.

[0167] Reference Fig.17 , the memory system 1000 includes a semiconductor memory device 100 and a controller 1100. The semiconductor memory device 100 may be a reference Figure 1 Hereinafter, repeated descriptions are omitted.

[0168] The controller 1100 is connected to the host Host and the semiconductor memory device 100. The controller 1100 is configured to access the semiconductor memory device 100 in response to a request from the host Host. For example, the controller 1100 is configured to control a read operation, a write operation, an erase operation, and a background operation of the semiconductor memory device 100. The controller 1100 is configured to provide an interface between the semiconductor memory device 100 and the host Host. The controller 1100 is configured to drive firmware for controlling the semiconductor memory device 100.

[0169] The controller 1100 includes a random access memory (RAM) 1110, a processing unit 1120, a host interface 1130, a memory interface 1140, and an error correction block 1150. The RAM 1110 is used as any one of an operation memory of the processing unit 1120, a cache memory between the semiconductor memory device 100 and the host Host, and a buffer memory between the semiconductor memory device 100 and the host Host. The processing unit 1120 controls the overall operation of the controller 1100. In addition, the controller 1100 may temporarily store programming data provided from the host Host during a write operation.

[0170] The host interface 1130 includes a protocol for performing data exchange between the host Host and the controller 1100. As an example of an implementation, the controller 1100 is configured to communicate with the host Host through at least one of various interface protocols such as a universal serial bus (USB) protocol, a multimedia card (MMC) protocol, a peripheral component interconnect (PCI) protocol, a high-speed PCI (PCI-E) protocol, an advanced technology attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer system interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, and a proprietary protocol.

[0171] The memory interface 1140 interfaces with the semiconductor memory device 100. For example, the memory interface includes a NAND interface or a NOR interface.

[0172] The error correction block 1150 is configured to detect and correct errors of data received from the semiconductor memory device 100 using an error correction code (ECC). The processing unit 1120 may control a read voltage according to an error detection result of the error correction block 1150, and control the semiconductor memory device 100 to perform re-reading. As an example of an implementation, the error correction block may be provided as a component of the controller 1100.

[0173] The controller 1100 and the semiconductor memory device 100 may be integrated into one semiconductor device. As an example of an implementation, the controller 1100 and the semiconductor memory device 100 may be integrated into one semiconductor device to configure a memory card. For example, the controller 1100 and the semiconductor memory device 100 may be integrated into one semiconductor device to form a memory card such as a PC card (Personal Computer Memory Card International Association (PCMCIA)), a Compact Flash card (CF), a Smart Media Card (SM or SMC), a Memory Stick, a Multimedia Card (MMC, RS-MMC or MMCmicro), an SD card (SD, miniSD, microSD or SDHC), and a Universal Flash Storage (UFS).

[0174] The controller 1100 and the semiconductor memory device 100 may be integrated into one semiconductor device to form a semiconductor drive (solid state drive (SSD)). The semiconductor drive (SSD) includes a storage device configured to store data in a semiconductor memory. When the memory system 1000 is used as a semiconductor drive (SSD), the operation speed of the host Host connected to the memory system 1000 is greatly improved.

[0175] As another example, the memory system 1000 is provided as one of various components of an electronic device such as a computer, an ultra mobile PC (UMPC), a workstation, a netbook, a personal digital assistant (PDA), a portable computer, a web tablet computer, a wireless phone, a mobile phone, a smart phone, an e-book, a portable multimedia player (PMP), a portable game console, a navigation device, a black box, a digital camera, a 3D TV, a digital audio recorder, a digital audio player, a digital image recorder, a digital image player, a digital video recorder, and a digital video player, a device capable of sending and receiving information in a wireless environment, one of various electronic devices configuring a home network, one of various electronic devices configuring a computer network, one of various electronic devices configuring a telematics network, an RFID device, or one of various components configuring a computing system.

[0176] As an example of an implementation, the semiconductor memory device 100 or the memory system 1000 may be installed as various types of packages. For example, the semiconductor memory device 100 or the memory system 1000 may be packaged and installed in a method such as a stacked package (PoP), a ball grid array (BGA), a chip scale package (CSP), a plastic chip carrier with leads (PLCC), a plastic dual in-line package (PDIP), a waffle wafer package, a wafer form wafer, a chip on board (COB), a ceramic dual in-line package (CERDIP), a plastic metric quad flat package (MQFP), a thin quad flat package (TQFP), a small outline package (SOIC), a shrink small outline package (SSOP), a thin small outline package (TSOP), a system in package (SIP), a multi-chip package (MCP), a wafer-level manufacturing package (WFP), or a wafer-level processing stacked package (WSP).

[0177] Fig.18 It is shown Fig.17 A block diagram of an application example of a memory system.

[0178] Reference Fig.18 , the memory system 2000 includes a semiconductor memory device 2100 and a controller 2200. The semiconductor memory device 2100 includes a plurality of semiconductor memory chips. The plurality of semiconductor memory chips are divided into a plurality of groups.

[0179] exist Fig.18 In the embodiment, the plurality of groups communicate with the controller 2200 through the first channel CH1 to the kth channel CHk respectively. Figure 1 One of the described semiconductor memory devices 100 is similarly configured and operates.

[0180] Each group is configured to communicate with the controller 2200 through a common channel. The controller 2200 and the reference Fig.17 The described controller 1100 is similarly configured, and is configured to control a plurality of memory chips of the semiconductor memory device 2100 through a plurality of channels CH1 to CHk.

[0181] Fig.19 It is shown including reference Fig.18 A block diagram of a computing system that describes a memory system.

[0182] The computing system 3000 includes a central processing device 3100 , a random access memory (RAM) 3200 , a user interface 3300 , a power supply 3400 , a system bus 3500 , and a memory system 2000 .

[0183] The memory system 2000 is electrically connected to the central processing device 3100, the RAM 3200, the user interface 3300, and the power supply 3400 through the system bus 3500. Data provided through the user interface 3300 or processed by the central processing device 3100 is stored in the memory system 2000.

[0184] exist Fig.19 In the embodiment, the semiconductor memory device 2100 is connected to the system bus 3500 through the controller 2200. However, the semiconductor memory device 2100 may be configured to be directly connected to the system bus 3500. At this time, the function of the controller 2200 is performed by the central processing unit 3100 and the RAM 3200.

[0185] exist Fig.19 References are provided in Fig.18 However, the memory system 2000 may be configured as described with reference to Fig.17 As an example of an implementation, the computing system 3000 may be configured to include a memory system 1000 described above. Fig.17 and Fig.18 Both memory systems 1000 and 2000 are described.

[0186] The embodiments of the present disclosure disclosed in this specification and the accompanying drawings are only examples for describing the technical content of the present disclosure and facilitating understanding of the present disclosure, rather than limiting the scope of the present disclosure. It is obvious to those skilled in the art that, in addition to the embodiments disclosed herein, other modifications based on the technical spirit of the present disclosure may be made.

[0187] CROSS-REFERENCE TO RELATED APPLICATIONS

[0188] This application claims the benefit of Korean Patent Application No. 10-2020-0060007, filed on May 19, 2020, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.

Claims

1. A semiconductor memory device, comprising: a memory cell array, the memory cell array comprising a plurality of memory cells; a peripheral circuit configured to perform a program operation on a selected memory cell connected to a selected word line among the plurality of memory cells; a current sensing circuit configured to generate a pass signal or a fail signal by performing a current sensing operation on the selected memory cell; as well as a control logic configured to receive the pass signal or the fail signal and control operations of the peripheral circuit and the current sensing circuit, wherein the control logic controls the current sensing circuit and the peripheral circuit to perform the current sensing operation and the operation of applying a programming pulse to the selected word line based on the programming progress state of the selected memory cell, wherein, when the program progress state of the selected memory cell corresponds to a first state as the start of the program operation, the control logic controls the current sensing circuit and the peripheral circuit to simultaneously perform the current sensing operation and the operation of applying the program pulse to the selected word line, and When the programming progress state of the selected memory cell corresponds to a second state occurring after the first state, the control logic controls the current sensing circuit and the peripheral circuit to sequentially perform the current sensing operation and the operation of applying the programming pulse to the selected word line.

2. The semiconductor memory device according to claim 1, wherein The selected memory cell is programmed to any one of a plurality of target programming states, and When the current sensing operation to be performed corresponds to any one of the remaining target programming states among the multiple target programming states except the last programming state, the control logic controls the current sensing circuit and the peripheral circuit to simultaneously perform the current sensing operation and the operation of applying the programming pulse to the selected word line.

3. The semiconductor memory device according to claim 1, wherein: When the number of program pulses applied to the selected word line is less than a predetermined threshold number, the control logic controls the current sensing circuit and the peripheral circuit to simultaneously perform the current sensing operation and the operation of applying the program pulses to the selected word line.

4. The semiconductor memory device according to claim 1, wherein: The selected memory cell is programmed to any one of a plurality of target programming states, and When the current sensing operation to be performed corresponds to a last programming state among the plurality of target programming states, the control logic controls the current sensing circuit to perform the current sensing operation and then controls the peripheral circuit to perform an operation of applying the programming pulse to the selected word line.

5. The semiconductor memory device according to claim 1, wherein: When the number of program pulses applied to the selected word line is equal to or greater than a predetermined threshold number, the control logic controls the current sensing circuit to perform the current sensing operation and then controls the peripheral circuit to perform the operation of applying the program pulses to the selected word line.

6. The semiconductor memory device according to claim 1, wherein: The peripheral circuit comprises: an address decoder configured to decode the selected word line among a plurality of word lines connected to the memory cell array and transfer a program voltage and a verification voltage to the selected word line; and A read / write circuit is connected to the memory cell array through a plurality of bit lines and is configured to transmit a program enable voltage or a program inhibit voltage to each of the plurality of bit lines.

7. A method of operating a semiconductor memory device to program a selected memory cell, the method comprising the steps of: applying a programming pulse to a selected word line connected to the selected memory cell; applying a verify voltage to the selected word line; as well as performing a current sensing operation and an operation of applying a program pulse based on a program progress state of the selected memory cell, wherein, when the program progress state of the selected memory cell corresponds to a first state as the start of a program operation, the current sensing operation and the operation of applying the program pulse to the selected word line are simultaneously performed, and When the program progress state of the selected memory cell corresponds to a second state occurring after the first state, the current sensing operation and the operation of applying the program pulse to the selected word line are sequentially performed.

8. The method according to claim 7, wherein: The selected memory cell is programmed to any one of a plurality of target programming states, and The step of performing the current sensing operation and the operation of applying the program pulse based on the program progress state of the selected memory cell includes the following steps: checking a verification-passed programming state among the plurality of target programming states; and When the current sensing operation to be performed corresponds to any one of remaining target program states except a last program state among the plurality of target program states, the current sensing operation and the operation of applying the program pulse to the selected word line are simultaneously performed.

9. The method according to claim 7, wherein: The step of performing the current sensing operation and the operation of applying the program pulse based on the program progress state of the selected memory cell includes the following steps: checking the number of programming pulses applied to the selected word line; and When the number of the program pulses is less than a predetermined threshold number, the current sensing operation and the operation of applying the program pulses to the selected word line are simultaneously performed.

10. The method according to claim 7, wherein: When the program progress state of the selected memory cell corresponds to the first state, performing the current sensing operation and applying the program pulse to the selected word line includes the following steps: performing the current sensing operation; applying the program pulse to the selected word line in a period at least partially overlapping with a period in which the current sensing operation is performed; and As a result of the current sensing operation, it is determined whether the verification fails or passes.

11. The method according to claim 7, wherein: The selected memory cell is programmed to any one of a plurality of target programming states, and The step of performing the current sensing operation and the operation of applying the program pulse based on the program progress state of the selected memory cell includes the following steps: checking a verification-passed programming state among the plurality of target programming states; and When the current sensing operation to be performed corresponds to a last program state among the plurality of target program states, the current sensing operation and the operation of applying the program pulse to the selected word line are sequentially performed.

12. The method according to claim 7, wherein: The step of performing the current sensing operation and the operation of applying the program pulse based on the program progress state of the selected memory cell includes the following steps: checking the number of programming pulses applied to the selected word line; and When the number of the program pulses is equal to or greater than a predetermined threshold number, the current sensing operation and the operation of applying the program pulses to the selected word line are sequentially performed.

13. The method according to claim 7, wherein: When the program progress state of the selected memory cell corresponds to a second state occurring after the first state, performing the current sensing operation and applying the program pulse to the selected word line includes the following steps: performing the current sensing operation; determining whether verification has failed or passed as a result of the current sensing operation; and When the verification fails, the program pulse is applied to the selected word line.

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