Encapsulated multi-chip semiconductor device

Abstract

A semiconductor package is provided, including a first connection structure, a first semiconductor chip on an upper surface of the first connection structure, a first molding layer on the upper surface of the first connection structure and surrounding the first semiconductor chip, a first bonding pad on the first semiconductor chip, a first bonding insulating layer on the first semiconductor chip and the first molding layer and surrounding the first bonding pad, a second bonding pad directly contacting the first bonding pad, a second bonding insulating layer surrounding the second bonding pad, and a second semiconductor chip on the second bonding pad and the second bonding insulating layer.

Description

[0001] This application claims the benefit of Korean Patent Application No. 10-2020-0059328, filed on May 18, 2020, the disclosure of which is incorporated herein by reference. Technical Field

[0002] The inventive concept relates to packaged semiconductor devices, and more specifically, to packaged multi-chip semiconductor devices. Background Technology

[0003] There is a constant demand for high-performance and compact electronic devices. As a result, semiconductor packages comprising multiple semiconductor chips have been developed. For example, multiple semiconductor chips can be stacked vertically, thereby reducing the layout area of ​​the semiconductor package and providing multifunctional and / or high-performance semiconductor packages. Summary of the Invention

[0004] The inventive concept provides an integrated circuit package and a method for manufacturing the integrated circuit package, in which multiple semiconductor chips are connected by bonding without any bumps (e.g., solder balls).

[0005] According to one aspect of the inventive concept, a packaged semiconductor device is provided, the packaged semiconductor device comprising: a first connection structure; a first semiconductor chip; a first molding layer located on an upper surface of the first connection structure and surrounding the first semiconductor chip; a first bonding pad located on the first semiconductor chip; a first bonding insulating layer located on the first semiconductor chip and the first molding layer and surrounding the first bonding pad; a second bonding pad in direct contact with the first bonding pad; a second bonding insulating layer surrounding the second bonding pad; and a second semiconductor chip located on the second bonding pad and the second bonding insulating layer.

[0006] According to another aspect of the inventive concept, a packaged semiconductor device is provided, the packaged semiconductor device comprising: a redistribution structure; solder bumps located on a lower surface of the redistribution structure; and a first semiconductor chip positioned on an upper surface of the redistribution structure. The first semiconductor chip includes: a substrate; a lower chip pad located on the lower surface of the substrate; an upper chip pad located on the upper surface of the substrate; and a through-substrate via (TSV) extending between the lower chip pad and the upper chip pad by penetrating the substrate. A first molding layer is also provided, positioned on the upper surface of the redistribution structure and at least partially surrounding the first semiconductor chip. A first bonding pad is disposed on the upper chip pad of the first semiconductor chip. A first bonding insulating layer is provided, positioned on the upper surface of the first semiconductor chip and the upper surface of the first molding layer (and at least partially surrounding the first bonding pad). A second bonding pad is provided, directly contacting the first bonding pad. A second bonding insulating layer is provided, directly contacting the first bonding insulating layer and surrounding the second bonding pad. Furthermore, a second semiconductor chip is disposed on the second bonding pad and the second bonding insulating layer.

[0007] According to another aspect of the inventive concept, a packaged semiconductor device is provided, the packaged semiconductor device comprising: a connection structure; a first semiconductor chip located on an upper surface of the connection structure; a first bonding pad located on the first semiconductor chip; a first bonding insulating layer positioned on the first semiconductor chip and at least partially surrounding the first bonding pad; a second bonding pad in direct contact with the first bonding pad; and a second bonding insulating layer at least partially surrounding the second bonding pad. A second semiconductor chip is further disposed on the second bonding pad and the second bonding insulating layer. A first molding layer is provided, the first molding layer being positioned on the second bonding insulating layer and at least partially surrounding the second semiconductor chip.

[0008] According to another aspect of the inventive concept, a packaged semiconductor device is provided, the packaged semiconductor device comprising: a package substrate; an interposer located on the package substrate; a first bonding pad and a second bonding pad located on the interposer; and a first bonding insulating layer positioned on the interposer and at least partially surrounding the first bonding pad and the second bonding pad. A third bonding pad and a fourth bonding pad are also provided, the third bonding pad directly contacting the first bonding pad and the fourth bonding pad directly contacting the second bonding pad. A second bonding insulating layer is provided, at least partially surrounding the third bonding pad and the fourth bonding pad. A first semiconductor chip is disposed on the second bonding insulating layer and the third bonding pad, and a second semiconductor chip is disposed on the second bonding insulating layer and the fourth bonding pad. A molding layer is provided, the molding layer being positioned on the second bonding insulating layer and at least partially surrounding the first semiconductor chip and the second semiconductor chip. Attached Figure Description

[0009] Exemplary embodiments of the inventive concept will become clearer from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0010] Figure 1 This is a cross-sectional view of a packaged semiconductor device according to an embodiment of the inventive concept;

[0011] Figure 2 yes Figure 1 A magnified view of region A;

[0012] Figure 3A and Figure 3B yes Figure 1 A magnified view of the modified area A;

[0013] Figure 4 This is a cross-sectional view of a packaged semiconductor device according to an embodiment of the inventive concept;

[0014] Figure 5 yes Figure 4 A magnified view of region B;

[0015] Figure 6 This is a cross-sectional view of a packaged semiconductor device according to an embodiment of the inventive concept;

[0016] Figure 7 This is a cross-sectional view of a packaged semiconductor device according to an embodiment of the inventive concept;

[0017] Figure 8 This is a cross-sectional view of a packaged semiconductor device according to an embodiment of the inventive concept;

[0018] Figure 9 This is a cross-sectional view of a packaged semiconductor device according to an embodiment of the inventive concept;

[0019] Figure 10 This is a cross-sectional view of a packaged semiconductor device according to an embodiment of the inventive concept;

[0020] Figure 11 This is a cross-sectional view of a packaged semiconductor device according to an embodiment of the inventive concept;

[0021] Figure 12 This is a cross-sectional view of a packaged semiconductor device according to an embodiment of the inventive concept;

[0022] Figure 13 This is a cross-sectional view of a packaged semiconductor device according to an embodiment of the inventive concept;

[0023] Figure 14 This is a cross-sectional view of a packaged semiconductor device according to an embodiment of the inventive concept;

[0024] Figure 15This is a cross-sectional view of a packaged semiconductor device according to an embodiment of the inventive concept;

[0025] Figure 16 This is a cross-sectional view of a packaged semiconductor device according to an embodiment of the inventive concept;

[0026] Figures 17A to 17H This is a cross-sectional view illustrating a method for manufacturing a packaged semiconductor device according to an embodiment of the inventive concept;

[0027] Figures 18A to 18D This is a cross-sectional view illustrating a method for manufacturing a packaged semiconductor device according to an embodiment of the inventive concept;

[0028] Figure 19 This is a cross-sectional view illustrating a method for manufacturing a packaged semiconductor device according to an embodiment of the inventive concept;

[0029] Figure 20A and Figure 20B This is a cross-sectional view illustrating a method for manufacturing a semiconductor package according to an embodiment of the inventive concept;

[0030] Figure 21 This is a cross-sectional view illustrating a method for manufacturing a semiconductor package according to an embodiment of the inventive concept;

[0031] Figure 22 This is a cross-sectional view illustrating a method for manufacturing a semiconductor package according to an embodiment of the inventive concept;

[0032] Figure 23 This is a cross-sectional view illustrating a method for manufacturing a semiconductor package according to an embodiment of the inventive concept;

[0033] Figure 24 This is a cross-sectional view illustrating a method for manufacturing a semiconductor package according to an embodiment of the inventive concept; and

[0034] Figure 25A and Figure 25B This is a cross-sectional view illustrating a method for manufacturing a semiconductor package according to an embodiment of the inventive concept. Detailed Implementation

[0035] Figure 1 This is a cross-sectional view of a semiconductor package 100 according to an embodiment of the inventive concept. Figure 2 yes Figure 1 A magnified view of region A. Figure 3A and Figure 3B yes Figure 1 A magnified view of the modified area A.

[0036] Reference Figure 1 , Figure 2 , Figure 3A and Figure 3BThe semiconductor package 100 may include a first connection structure 130, a first semiconductor chip 140 located on the upper surface of the first connection structure 130, a first molding layer MD1 at least partially surrounding the first semiconductor chip 140, a first bonding pad (or "pad") BP1 located on the first semiconductor chip 140, a first bonding insulating layer BO1 located on the first semiconductor chip 140 and the first molding layer MD1, a second bonding pad BP2 in direct contact with the first bonding pad BP1, a second bonding insulating layer BO2 at least partially surrounding the second bonding pad BP2, and a second semiconductor chip 150 located on the second bonding pad BP2 and the second bonding insulating layer BO2.

[0037] According to some embodiments, the semiconductor package 100 may further include an external connection terminal 110 located on the lower surface of the first connection structure 130. According to some embodiments, the semiconductor package 100 may further include a terminal pad 120 located between the first connection structure 130 and the external connection terminal 110. According to some embodiments, the semiconductor package 100 may further include a connection member CP penetrating the first molding layer MD1. According to some embodiments, the semiconductor package 100 may further include a third bonding pad BP3 located on the connection member CP and a fourth bonding pad BP4 in direct contact with the third bonding pad BP3.

[0038] The first connection structure 130 can connect the first semiconductor chip 140 and the second semiconductor chip 150 to the external connection terminal 110. According to some embodiments, the first connection structure 130 can be a redistribution structure. According to another embodiment, the first connection structure 130 can be an interposer or a printed circuit board (PCB). According to some embodiments where the first connection structure 130 is a redistribution structure, the first connection structure 130 can be the last structure of a redistribution layer (RDL). In other words, the first connection structure 130 can be formed on the first semiconductor chip 140 after the first semiconductor chip 140 is arranged on a carrier (not shown).

[0039] The first connection structure 130 may include, for example, a first insulating layer 132O located on the lower surface of the first molding layer MD1, a first conductive via 132V penetrating the first insulating layer 132O, a first conductive pattern 132L located on the lower surface of the first insulating layer 132O and contacting the first conductive via 132V, a second insulating layer 131O located on the lower surface of the first insulating layer 132O and the lower surface of the first conductive pattern 132L, a second conductive via 131V contacting the first conductive pattern 132L by penetrating the second insulating layer 131O, and a second conductive pattern 131L located on the lower surface of the second insulating layer 131O and contacting the second conductive via 131V. Although in Figure 1The first connection structure 130 includes two layers corresponding to two layers: a first conductive pattern 132L and a second conductive pattern 131L, and a first insulating layer 132O and a second insulating layer 131O. However, the first connection structure 130 may include more conductive pattern layers and more insulating layers. According to some embodiments, the first conductive via 132V and the first conductive pattern 132L may be integrally formed with each other. Similarly, the second conductive via 131V and the second conductive pattern 131L may be integrally formed with each other. According to some embodiments, the terminal pad 120 may contact the second conductive pattern 131L. The connection member CP may contact the first conductive via 132V, and the second chip pad 144B of the first semiconductor chip 140 may contact other first conductive vias 132V. The first conductive via 132V, the first conductive pattern 132L, the second conductive via 131V, and the second conductive pattern 131L may form an electrical path.

[0040] According to some embodiments, the first insulating layer 132O and the second insulating layer 131O may include insulating materials, such as silicon oxide, silicon nitride, or combinations thereof. The first conductive via 132V, the first conductive pattern 132L, the second conductive via 131V, and the second conductive pattern 131L may include conductive materials, such as metallic materials including copper (Cu), silver (Ag), gold (Au), tungsten (W), aluminum (Al), titanium (Ti), tantalum (Ta), or combinations thereof.

[0041] The first semiconductor chip 140 may be located on the upper surface of the first connection structure 130. The first semiconductor chip 140 may include a substrate 141 and a semiconductor device 142 located on the substrate 141. The upper surface of the substrate 141 on which the semiconductor device 142 is formed may be referred to as the effective surface, and the lower surface of the substrate 141 on which the semiconductor device 142 is not formed may be referred to as the ineffective surface. The second semiconductor chip 150 may include a substrate 151 and a semiconductor device 152 located on the substrate 151. The lower surface of the substrate 151 on which the semiconductor device 152 is formed may be referred to as the effective surface, and the upper surface of the substrate 151 on which the semiconductor device 152 is not formed may be referred to as the ineffective surface.

[0042] Each of substrates 141 and 151 may include a semiconductor material, such as a Group IV, Group III and V, or Group II and VI semiconductor material. Group IV semiconductor materials may include, for example, silicon (Si), germanium (Ge), or Si-Ge. Group III and V semiconductor materials may include, for example, gallium arsenide (GaAs), indium phosphide (InP), gallium phosphide (GaP), indium arsenide (InAs), indium antimonide (InSb), or indium gallium arsenide (InGaAs). Group II and VI semiconductor materials may include, for example, zinc telluride (ZnTe) or cadmium sulfide (CdS).

[0043] Each of semiconductor devices 142 and 152 may include, for example, a memory device and / or a logic device. For example, the memory device may be dynamic random access memory (DRAM), static random access memory (SRAM), flash memory, electrically erasable and programmable read-only memory (EEPROM), phase-change random access memory (PRAM), magnetic random access memory (MRAM), resistive random access memory (RRAM), or combinations thereof. The logic device may be, for example, a central processing unit (CPU), a graphics processing unit (GPU), a controller, an application-specific integrated circuit (ASIC), an application processor (AP), or combinations thereof.

[0044] According to some embodiments, the first semiconductor chip 140 may further include a through-substrate via (TSV) penetrating the substrate 141. According to some embodiments, the first semiconductor chip 140 may further include a first chip pad 144A located on the upper surface of the substrate 141 and a second chip pad 144B located on the lower surface of the substrate 141. According to some embodiments, the first semiconductor chip 140 may further include a first chip insulating layer 143A located on the upper surface of the substrate 141 and a second chip insulating layer 143B located on the lower surface of the substrate 141. The first chip pad 144A may be located between the TSV 145 and the first bonding pad BP1. The second chip pad 144B may be located between the TSV 145 and the first connection structure 130. In other words, the TSV 145 may extend between the first chip pad 144A and the second chip pad 144B. The first chip insulating layer 143A may at least partially surround the first chip pad 144A, and the second chip insulating layer 143B may at least partially surround the second chip pad 144B. The first chip pad 144A may be referred to as the upper chip pad, and the second chip pad 144B may be referred to as the lower chip pad. According to some embodiments, the second semiconductor chip 150 also includes a chip pad located between the semiconductor device 152 and the second bonding pad BP2 and / or between the semiconductor device 152 and the fourth bonding pad BP4.

[0045] The first chip pad 144A, the second chip pad 144B, and TSV 145 may include conductive materials, such as metallic materials including copper (Cu), silver (Ag), gold (Au), tungsten (W), aluminum (Al), titanium (Ti), tantalum (Ta), or combinations thereof. The first chip insulating layer 143A and the second chip insulating layer 143B may include insulating materials, such as silicon oxide, silicon nitride, polymers, or combinations thereof.

[0046] The second semiconductor chip 150 can be connected to the first semiconductor chip 140 via the second bonding pad BP2 and the first bonding pad BP1. The second semiconductor chip 150 can also be connected to the first connection structure 130 via the first semiconductor chip 140. For example, the second semiconductor chip 150 can be connected to the first connection structure 130 via the second bonding pad BP2, the first bonding pad BP1, the first chip pad 144A, TSV 145, and the second chip pad 144B. According to some embodiments, the second semiconductor chip 150 can be connected to the first connection structure 130 via a connection member CP instead of the first semiconductor chip 140. For example, the second semiconductor chip 150 can be connected to the first connection structure 130 via the fourth bonding pad BP4, the third bonding pad BP3, and the connection member CP.

[0047] The first molding layer MD1 may be located on the upper surface of the first connection structure 130 and may at least partially surround the first semiconductor chip 140. The first molding layer MD1 may withstand temperatures of about 300°C or higher, may have a coefficient of thermal expansion of about 10 ppm / °C or less, and may include a material with good adhesion to the first bonding insulating layer BO1. The first molding layer MD1 may include, for example, an organic insulating material, including epoxy resin, silicone resin, or combinations thereof. The first molding layer MD1 may include, for example, epoxy molding compound (EMC). According to some embodiments, the side surface of the first molding layer MD1 may be coplanar with the side surface of the second semiconductor chip 150. Two coplanar surfaces may refer to two surfaces on the same plane. According to some embodiments, the side surface of the first molding layer MD1 may be coplanar with the side surface of the first connection structure 130.

[0048] The connecting member CP may extend between the first connecting structure 130 and the third bonding pad BP3. The connecting member CP may provide an electrical path between the second semiconductor chip 150 and the first connecting structure 130. The connecting member CP may include, for example, a metallic material (including copper (Cu), silver (Ag), gold (Au), tungsten (W), aluminum (Al), titanium (Ti), tantalum (Ta), lead (Pb), tin (Sn), or combinations thereof). Although in Figure 1 Each connecting member CP has a column shape, but each connecting member CP can have any shape including a bump shape.

[0049] A first bonding pad BP1 may be located on a first chip pad 144A of a first semiconductor chip 140. A third bonding pad BP3 may be located on a connecting member CP. A first bonding insulating layer BO1 may at least partially surround the first bonding pad BP1 and the third bonding pad BP3. The first bonding insulating layer BO1 may be located on a first molding layer MD1 and the first semiconductor chip 140. A second bonding pad BP2 and a fourth bonding pad BP4 may be located on the lower surface of a second semiconductor chip 150. A second bonding insulating layer BO2 may at least partially surround the second bonding pad BP2 and the fourth bonding pad BP4. The first bonding pad BP1 may directly contact the second bonding pad BP2, and the third bonding pad BP3 may directly contact the fourth bonding pad BP4. According to some embodiments, the second bonding insulating layer BO2 may directly contact the first bonding insulating layer BO1.

[0050] According to the inventive concept, since there is direct contact between the first bonding pad BP1 and the second bonding pad BP2 and no bumps between the first semiconductor chip 140 and the second semiconductor chip 150, the second semiconductor chip 150 can be connected to the first semiconductor chip 140 without any bumps (e.g., solder balls). Therefore, because a polymer layer with low thermal conductivity, located between the first semiconductor chip 140 and the second semiconductor chip 150 and surrounding the bumps, is not required, the semiconductor package 100 can have improved thermal conductivity. Because relatively large bumps are not required, first bonding pads BP1 to fourth bonding pads BP4 with small size and small pitch can be used, and therefore the semiconductor package 100 can have improved integration and increased speed.

[0051] The first bonding pads BP1 to the fourth bonding pads BP4 may comprise conductive materials, such as metallic materials including copper (Cu), silver (Ag), gold (Au), tungsten (W), aluminum (Al), titanium (Ti), tantalum (Ta), or combinations thereof. The first bonding insulating layer BO1 and the second bonding insulating layer BO2 may comprise inorganic insulating materials, such as silicon oxide, silicon nitride, silicon carbonitride, silicon oxynitride, or combinations thereof.

[0052] According to some embodiments, such as Figure 2 As shown, the first bonding pad BP1 can be aligned with the first chip pad 144A of the first semiconductor chip 140. The first bonding pad BP1 can be aligned with the second bonding pad BP2. However, according to other embodiments, such as Figure 3A As shown, the first chip pad BP1 may be misaligned with the first chip pad 144A of the first semiconductor chip 140. For example... Figure 3B As shown, the second bonding pad BP2 may be misaligned with the first bonding pad BP1. The alignment error between the first bonding pad BP1 and the second bonding pad BP2 may be, for example, within about 100 nm.

[0053] External connection terminal 110 may be located on the lower surface of terminal pad 120. External connection terminal 110 may be used to connect semiconductor package 100 to the outside of semiconductor package 100. According to some embodiments, external connection terminal 110 may be a solder bump. External connection terminal 110 may include, for example, a conductive material, including tin (Sn), lead (Pb), copper (Cu), silver (Ag), or combinations thereof.

[0054] Terminal pad 120 may be located on the lower surface of the first connection structure 130 and may contact the external connection terminal 110. Terminal pad 120 may be referred to as lower bump metal (UBM). Terminal pad 120 may include a metallic material, such as copper (Cu), nickel (Ni), silver (Ag), chromium (Cr), titanium (Ti), or palladium (Pd).

[0055] Figure 4 This is a cross-sectional view of a semiconductor package 100A according to an embodiment of the inventive concept. Figure 5 yes Figure 4 A magnified view of region B. Now, a description will follow. Figure 1 Semiconductor package 100 and Figure 4 and Figure 5 Differences between semiconductor packages 100A. (Refer to...) Figure 4 and Figure 5 The first bonding insulating layer BO1 may not contact the second bonding insulating layer BO2. In other words, the first bonding insulating layer BO1 can be separated from the second bonding insulating layer BO2. For example, the first bonding pad BP1 may protrude upward from the upper surface of the first bonding insulating layer BO1, and the second bonding pad BP2 may protrude downward from the lower surface of the second bonding insulating layer BO2. Therefore, even when the first bonding pad BP1 contacts the second bonding pad BP2, the first bonding insulating layer BO1 can be separated from the second bonding insulating layer BO2. According to some embodiments, a portion of the first bonding insulating layer BO1 and a portion of the second bonding insulating layer BO2 may contact each other, and the remaining portions of the first bonding insulating layer BO1 and the remaining portions of the second bonding insulating layer BO2 may be separated from each other.

[0056] Figure 6 This is a cross-sectional view of a semiconductor package 100B according to an embodiment of the inventive concept. It will now be described... Figure 1 Semiconductor package 100 and Figure 6 Differences between semiconductor packages 100B. (Refer to...) Figure 6 In the first semiconductor chip 140, the semiconductor device 142 may be located on the lower surface of the substrate 141. In other words, the effective surface of the substrate 141 may be the lower surface of the substrate 141, and the ineffective surface of the substrate 141 may be the upper surface of the substrate 141.

[0057] Figure 7 This is a cross-sectional view of a semiconductor package 100C according to an embodiment of the inventive concept. It will now be described. Figure 1 Semiconductor package 100 and Figure 7 Differences between semiconductor package 100C. (Refer to...) Figure 7 The semiconductor package 100C may include a first connection structure 130C instead of Figure 1 The first connection structure 130C may be an RDL first structure. In other words, after forming the first connection structure 130C, a first semiconductor chip 140 may be disposed on the first connection structure 130C. The first connection structure 130C may include, for example, a first insulating layer 132OC located on the lower surface of the first molding layer MD1, a first conductive pattern 132LC located between the first insulating layer 132OC and the first molding layer MD1, a first conductive via 132VC penetrating the first insulating layer 132OC and contacting the first conductive pattern 132LC, a second insulating layer 131OC located on the lower surface of the first insulating layer 132OC, a second conductive pattern 131LC located between the second insulating layer 131OC and the first insulating layer 132OC and contacting the first conductive via 132VC, and a second conductive via 131VC penetrating the second insulating layer 131OC and contacting the second conductive pattern 131LC. According to some embodiments, the first conductive pattern 132LC and the first conductive via 132VC may be integrally formed with each other. According to some embodiments, the second conductive pattern 131LC and the second conductive via 131VC can be integrally formed with each other. According to some embodiments, the terminal pad 120 can contact the second conductive via 131VC. The connecting member CP can contact the first conductive pattern 132LC, and the second chip pad 144B of the first semiconductor chip 140 can contact other first conductive patterns 132LC. Although in Figure 7 The first connection structure 130C includes two layers corresponding to two layers: a first conductive pattern 132LC and a second conductive pattern 131LC, and a first insulating layer 132OC and a second insulating layer 131OC. However, the first connection structure 130C may include more conductive pattern layers and more insulating layers.

[0058] Figure 8 This is a cross-sectional view of a semiconductor package 100D according to an embodiment of the inventive concept. It will now be described... Figure 7 Semiconductor package 100C and Figure 8 Differences between 100D semiconductor packages. (Refer to...) Figure 8The semiconductor package 100D may further include a second connection structure 160. The second connection structure 160 may be located between the first molding layer MD1 and the first bonding insulating layer BO1, and between the first semiconductor chip 140 and the first bonding insulating layer BO1. The second connection structure 160 can connect the first semiconductor chip 140 to the first bonding pad BP1. The second connection structure 160 can connect the connecting member CP to the third bonding pad BP3. In other words, the second semiconductor chip 150 can be connected to the first semiconductor chip 140 and the connecting member CP via the second connection structure 160. The second connection structure 160 may be a redistributed structure. Figure 8 In one embodiment, the second connection structure 160 has an RDL last structure (the second connection structure 160 is formed on the first semiconductor chip 140 after the first semiconductor chip 140 is disposed). However, according to another embodiment, the second connection structure 160 may have an RDL first structure (the first semiconductor chip 140 is disposed on the second connection structure 160 after the second connection structure 160 is formed).

[0059] The second connection structure 160 may include, for example, a first insulating layer 161O located on the first molding layer MD1, the first semiconductor chip 140, and the connection member CP; a first conductive via 161V penetrating the first insulating layer 161O; a first conductive pattern 161L located on the first insulating layer 161O and contacting the first conductive via 161V; a second insulating layer 162O located on the first insulating layer 161O and the first conductive pattern 161L; a second conductive via 162V penetrating the second insulating layer 162O and contacting the first conductive pattern 161L; and a second conductive pattern 162L located on the second insulating layer 162O and contacting the second conductive via 162V. Although in Figure 8 The second connection structure 160 includes two layers corresponding to two layers: a first conductive pattern 161L and a second conductive pattern 162L, and a first insulating layer 161O and a second insulating layer 162O. However, the second connection structure 160 may include more conductive pattern layers and more insulating layers. According to some embodiments, the first conductive via 161V and the first conductive pattern 161L may be integrally formed with each other. According to some embodiments, the second conductive via 162V and the second conductive pattern 162L may be integrally formed with each other. According to some embodiments, the first chip pad 144A of the first semiconductor chip 140 may contact some of the first conductive vias 161V, and the connection member CP may contact other first conductive vias 161V. According to some embodiments, the first bonding pad BP1 may contact some of the second conductive patterns 162L, and the third bonding pad BP3 may contact other second conductive patterns 162L. The first conductive via 161V, the first conductive pattern 161L, the second conductive via 162V, and the second conductive pattern 162L may form an electrical path.

[0060] According to some embodiments, the first insulating layer 161O and the second insulating layer 162O may include insulating materials, such as silicon oxide, silicon nitride, or combinations thereof. The first conductive via 161V, the first conductive pattern 161L, the second conductive via 162V, and the second conductive pattern 162L may include conductive materials, such as metallic materials including copper (Cu), silver (Ag), gold (Au), tungsten (W), aluminum (Al), titanium (Ti), tantalum (Ta), or combinations thereof.

[0061] Figure 9 This is a cross-sectional view of a semiconductor package 100E according to an embodiment of the inventive concept. It will now be described. Figure 1 Semiconductor package 100 and Figure 9 The differences between semiconductor packages 100E. (Refer to...) Figure 9 The semiconductor package 100E may further include a second molding layer MD2 that at least partially surrounds the second semiconductor chip 150. The second molding layer MD2 may be located on the second bonding insulating layer BO2. The side surfaces of the second molding layer MD2 may be coplanar with the side surfaces of the first molding layer MD1. The second molding layer MD2 may withstand temperatures of about 300°C or higher, may have a coefficient of thermal expansion of about 0 ppm / °C to 10 ppm / °C, and may include a material with good adhesion to the second bonding insulating layer BO2. The second molding layer MD2 may include, for example, epoxy resin, silicone resin, or a combination thereof. The second molding layer MD2 may include, for example, EMC. According to some embodiments, the second molding layer MD2 may include the same material as the first molding layer MD1.

[0062] Figure 10 This is a cross-sectional view of a semiconductor package 100F according to an embodiment of the inventive concept. It will now be described. Figure 1 Semiconductor package 100 and Figure 10 Differences between 100F semiconductor packages. (Refer to...) Figure 10 The semiconductor package 100F may include a first molding layer MD1F instead of Figure 1 The first molding layer MD1F may not surround the first semiconductor chip 140, but may surround the second semiconductor chip 150. The second bonding insulating layer BO2 may be located on the second semiconductor chip 150 and the first molding layer MD1F. According to some embodiments, the side surface of the first semiconductor chip 140 may be coplanar with the side surface of the first molding layer MD1F. According to some embodiments, the side surface of the first semiconductor chip 140 may be coplanar with the side surface of the first connection structure 130.

[0063] Figure 11 This is a cross-sectional view of a semiconductor package 100G according to an embodiment of the inventive concept. It will now be described... Figure 1Semiconductor package 100 and Figure 11 The differences between 100G semiconductor packages. (Refer to...) Figure 11 The semiconductor package 100G may further include a third semiconductor chip 170 located between the first connection structure 130 and the first bonding insulating layer BO1. The third semiconductor chip 170 may be at least partially surrounded by the first molding layer MD1. The third semiconductor chip 170 may be disposed on one side of the first semiconductor chip 140. The third semiconductor chip 170 may include a substrate 171, a semiconductor device 172 located on the substrate 171, a first chip pad 174A located on the upper surface of the substrate 171, a second chip pad 174B located on the lower surface of the substrate 171, TSVs 175 extending through the substrate 171 between the first chip pad 174A and the second chip pad 174B, a first chip insulating layer 173A located on the upper surface of the substrate 171 and at least partially surrounding the first chip pad 174A, and a second chip insulating layer 173B located on the lower surface of the substrate 171 and at least partially surrounding the second chip pad 174B.

[0064] The description of the substrate 171, semiconductor device 172, first chip pad 174A, second chip pad 174B, TSV 175, first chip insulating layer 173A, and second chip insulating layer 173B of the third semiconductor chip 170 is consistent with... Figure 1 The descriptions of the substrate 141, semiconductor device 142, first chip pad 144A, second chip pad 144B, TSV 145, first chip insulating layer 143A and second chip insulating layer 143B of the first semiconductor chip 140 are the same and will therefore be omitted here.

[0065] The semiconductor package 100G may further include a fifth bonding pad BP5 and a sixth bonding pad BP6. The fifth bonding pad BP5 may be located on the first chip pad 174A of the third semiconductor chip 170 and may be at least partially surrounded by a first bonding insulating layer BO1. The sixth bonding pad BP6 may be located on the lower surface of the second semiconductor chip 150 and may be at least partially surrounded by a second bonding insulating layer BO2. The sixth bonding pad BP6 may directly contact the fifth bonding pad BP5. The fifth bonding pad BP5 and the sixth bonding pad BP6 may include conductive materials, such as metallic materials including copper (Cu), silver (Ag), gold (Au), tungsten (W), aluminum (Al), titanium (Ti), tantalum (Ta), or combinations thereof.

[0066] Figure 12 This is a cross-sectional view of a semiconductor package 100H according to an embodiment of the inventive concept. It will now be described. Figure 12 Semiconductor package 100H and Figure 11 The differences between 100G semiconductor packages. (Refer to...) Figure 12The semiconductor package 100H may include a third semiconductor chip 170H instead of Figure 11 The third semiconductor chip 170. The third semiconductor chip 170H may not include Figure 11 The TSV 175, first chip pad 174A, second chip pad 174B, first chip insulating layer 173A, and second chip insulating layer 173B are included. The third semiconductor chip 170H may not be directly connected to the first connection structure 130. For example, the third semiconductor chip 170H may not be connected to the first connection structure 130, or it may be connected to the first connection structure 130 via the second semiconductor chip 150.

[0067] Figure 13 This is a cross-sectional view of a semiconductor package 100I according to an embodiment of the inventive concept. It will now be described. Figure 10 100F semiconductor package and Figure 13 The differences between semiconductor packages 100I. (Refer to...) Figure 13 The semiconductor package 100I may further include a third semiconductor chip 170I located on the second bonding insulating layer BO2. The third semiconductor chip 170I may be at least partially surrounded by the first molding layer MD1F. The third semiconductor chip 170I may be disposed on one side of the second semiconductor chip 150. The third semiconductor chip 170I may include a substrate 171 and a semiconductor device 172 located on the lower surface of the substrate 171.

[0068] The semiconductor package 100I further includes a fifth bonding pad BP5 and a sixth bonding pad BP6. The fifth bonding pad BP5 may be located on the first chip pad 144A of the first semiconductor chip 140 and may be at least partially surrounded by a first bonding insulating layer BO1. The sixth bonding pad BP6 may be located on the lower surface of the third semiconductor chip 170I and may be at least partially surrounded by a second bonding insulating layer BO2. The sixth bonding pad BP6 may directly contact the fifth bonding pad BP5. The fifth bonding pad BP5 and the sixth bonding pad BP6 may include conductive materials, such as metallic materials including copper (Cu), silver (Ag), gold (Au), tungsten (W), aluminum (Al), titanium (Ti), tantalum (Ta), or combinations thereof.

[0069] Figure 14 This is a cross-sectional view of a semiconductor package 100J according to an embodiment of the inventive concept. It will now be described. Figure 1 Semiconductor package 100 and Figure 14 The differences between semiconductor packages 100J. (Refer to...) Figure 14The semiconductor package 100J may include a semiconductor chip stack 140S, which includes a first semiconductor chip 140. The semiconductor chip stack 140S may include a plurality of semiconductor chips stacked vertically on the first connection structure 130, namely, the first semiconductor chip 140 and additional semiconductor chips 140-1 to 140-3. In other words, the semiconductor package 100J may also include additional semiconductor chips 140-1 to 140-3 stacked between the first semiconductor chip 140 and the first connection structure 130. Although in Figure 14 The semiconductor chip stack 140S includes four semiconductor chips 140 and 140-1 to 140-3, but the semiconductor chip stack 140S may include more or fewer semiconductor chips than four semiconductor chips. Each of the additional semiconductor chips 140-1 to 140-3 may include a substrate 141, a semiconductor device 142 located on the substrate 141, a first chip pad 144A located on the upper surface of the substrate 141, a second chip pad 144B located on the lower surface of the substrate 141, a TSV 145 extending through the substrate 141 between the first chip pad 144A and the second chip pad 144B, a first chip insulating layer 143A located on the upper surface of the substrate 141 and at least partially surrounding the first chip pad 144A, and a second chip insulating layer 143B located on the lower surface of the substrate 141 and at least partially surrounding the second chip pad 144B.

[0070] The semiconductor chip stack 140S may further include an inter-chip connection member 146, which connects two adjacent semiconductor chips (e.g., semiconductor chips 140 and 140-1) and is located between the two adjacent semiconductor chips. In other words, a first chip pad 144A of the lower semiconductor chip (e.g., 140-1) and a second chip pad 144B of the upper semiconductor chip (e.g., 140) of the two adjacent semiconductor chips (e.g., 140 and 140-1) may be connected to each other via the inter-chip connection member 146. The inter-chip connection member 146 may include a conductive material, including tin (Sn), lead (Pb), copper (Cu), silver (Ag), or combinations thereof. The semiconductor chip stack 140S may further include a chip adhesive layer 147 located between semiconductor chips 140 and 140-1 to 140-3 of the semiconductor chip stack 140S and surrounding the inter-chip connection member 146. The chip adhesive layer 147 may include, for example, epoxy resin, polyurethane resin, acrylic resin, or a combination thereof. The semiconductor chip stack 140S may be at least partially surrounded by the first molding layer MD1.

[0071] Figure 15This is a cross-sectional view of a semiconductor package 100K according to an embodiment of the inventive concept. It will now be described. Figure 14 Semiconductor package 100J and Figure 15 The differences between 100K semiconductor packages. (Refer to...) Figure 15 Two adjacent semiconductor chips (e.g., 140 and 140-1) within the semiconductor chip stack 140S can be connected via chip-to-chip bonding pads (i.e., the first additional bonding pad BP1-1 and the second additional bonding pad BP2-1) instead of Figure 14 The inter-chip connection components 146 are connected to each other. Additional semiconductor chips 140-1 to 140-3 may be surrounded by additional molding layers MD1-1 to MD1-3, respectively. First additional bonding pads BP1-1 to BP1-3 may be located on first chip pads 144A of the additional semiconductor chips 140-1 to 140-3, respectively. First additional bonding insulating layers BO1-1 to BO1-3 may be located on the additional semiconductor chips 140-1 to 140-3 and on the additional molding layers MD1-1 to MD1-3 surrounding the additional semiconductor chips 140-1 to 140-3, and may also surround the first additional bonding pads BP1-1 to BP1-3, respectively. Second additional bonding pads BP2-1 to BP2-3 may be located on second chip pads 144B of the semiconductor chips (e.g., 140, 140-1, and 140-2), respectively. The second additional bonding insulating layers BO2-1 to BO2-3 may be located on semiconductor chips 140, 140-1, and 140-2, respectively, and on the first molding layer MD1 and the additional molding layers MD1-1 and MD1-2 surrounding semiconductor chips 140, 140-1, and 140-2, respectively, and may surround the second additional bonding pads BP2-1 to BP2-3, respectively. The first additional bonding pads BP1-1 to BP1-3 and the second additional bonding pads BP2-1 to BP2-3 may be in direct contact with each other.

[0072] Two adjacent connecting members (e.g., CP and CP-1) can be connected to each other by additional bonding pads (i.e., third additional bonding pad BP3-1 and fourth additional bonding pad BP4-1) extending between them. Third additional bonding pads BP3-1 to BP3-3 can be located on the respective upper surfaces of connecting members CP-1 to CP-3, respectively. First additional bonding insulation layers BO1-1 to BO1-3 can surround the third additional bonding pads BP3-1 to BP3-3, respectively. Fourth additional bonding pads BP4-1 to BP4-3 can be located on the respective lower surfaces of connecting members CP, CP-1, and CP-2, respectively. Second additional bonding insulation layers BO2-1 to BO2-3 can surround the fourth additional bonding pads BP4-1 to BP4-3. Third additional bonding pads BP3-1 to BP3-3 can directly contact the fourth additional bonding pads BP4-1 to BP4-3.

[0073] The first additional bonding pads BP1-1 to BP1-3, the second additional bonding pads BP2-1 to BP2-3, the third additional bonding pads BP3-1 to BP3-3, and the fourth additional bonding pads BP4-1 to BP4-4 may comprise conductive materials, such as metallic materials including copper (Cu), silver (Ag), gold (Au), tungsten (W), aluminum (Al), titanium (Ti), tantalum (Ta), or combinations thereof. The first additional bonding insulating layers BO1-1 to BO1-3 and the second additional bonding insulating layers BO2-1 to BO2-3 may comprise inorganic insulating materials, such as silicon oxide, silicon nitride, silicon carbonitride, or combinations thereof.

[0074] Figure 16 This is a cross-sectional view of a semiconductor package 200 according to an embodiment of the inventive concept. (Refer to...) Figure 16 The semiconductor package 200 may include a package substrate 220, an interposer 240 on the package substrate 220, a first bonding pad BPa on the interposer 240, a second bonding pad BPb on the interposer 240, a first bonding insulating layer BOa on the interposer 240 and surrounding the first bonding pad BPa and the second bonding pad BPb, a third bonding pad BPc in direct contact with the first bonding pad BPa, a fourth bonding pad BPd in ​​direct contact with the second bonding pad BPb, a second bonding insulating layer BOb surrounding the third bonding pad BPc and the fourth bonding pad BPd, a first semiconductor chip 250 on the second bonding insulating layer BOb and the third bonding pad BPc, a second semiconductor chip 260 on the second bonding insulating layer BOb and the fourth bonding pad BPd, and a first molding layer MDa on the second bonding insulating layer BOb and surrounding the first semiconductor chip 250 and the second semiconductor chip 260. According to some embodiments, the semiconductor package 200 may also include external connection terminals 210 located on the lower surface of the package substrate 220. According to some embodiments, the semiconductor package 200 may further include an internal connection member 230 located between the interposer 240 and the package substrate 220. According to some embodiments, the semiconductor package 200 may further include a second molding layer MDb located on the package substrate 220 and surrounding the interposer 240 and the first molding layer MDa.

[0075] The encapsulation substrate 220 may be, for example, a printed circuit board (PCB). The encapsulation substrate 220 may include, for example, a body 221, a lower conductive pattern 222 on a lower surface of the body 221, an upper conductive pattern 223 on an upper surface of the body 221, and a through-hole 224 connecting the lower conductive pattern 222 to the upper conductive pattern 223 by penetrating the body 221. The body 221 may include phenolic resin, epoxy resin, polyimide resin, or combinations thereof. For example, the body 221 may include flame retardant 4 (FR4), tetrafunctional epoxy resin, polyphenylene ether, epoxy / polyphenylene oxide, bismaleimide triazine (BT), polyamide fiber nonwoven fabric (thermount), cyanate ester, polyimide, or liquid crystal polymer. The lower conductive pattern 222, the upper conductive pattern 223, and the through-hole 224 may include conductive materials, such as metallic materials including copper (Cu), silver (Ag), gold (Au), tungsten (W), aluminum (Al), titanium (Ti), tantalum (Ta), or combinations thereof.

[0076] External connection terminals 210 may be located on the lower conductive pattern 222 of the package substrate 220. External connection terminals 210 may include, for example, conductive materials, including tin (Sn), lead (Pb), copper (Cu), silver (Ag), or combinations thereof.

[0077] Intermediate 240 can connect the first semiconductor chip 250 and the second semiconductor chip 260 to the package substrate 220. Intermediate 240 may include, for example, a substrate 242, a through-hole 243 penetrating the substrate 242, a lower pad 241 located on the lower surface of the substrate 242 and connected to the through-hole 243, and a redistribution structure 244 located on the upper surface of the substrate 242 and connected to the through-hole 243. According to some embodiments, the redistribution structure 244 may be located on the lower surface of the substrate 242 or may be located on both the upper and lower surfaces of the substrate 242. The substrate 242 may include semiconductor materials, ceramic materials, or organic materials. The lower pad 241 and the through-hole 243 may include conductive materials, such as metallic materials including copper (Cu), silver (Ag), gold (Au), tungsten (W), aluminum (Al), titanium (Ti), tantalum (Ta), or combinations thereof. A detailed description of the redistribution structure 244 is provided below. Figure 1 The detailed description of the first connection structure 130 is the same and will therefore be omitted here. According to some embodiments, the side surface of the intermediary 240 may be coplanar with the side surface of the first molding layer MDa.

[0078] Internal connection member 230 can connect intermediate 240 to package substrate 220. Internal connection member 230 can be located between the lower pad 241 of intermediate 240 and the upper conductive pattern 223 of package substrate 220. Internal connection member 230 can include, for example, a conductive material, including tin (Sn), lead (Pb), copper (Cu), silver (Ag), or combinations thereof.

[0079] The first semiconductor chip 250 may include a substrate 251 and a semiconductor device 252 located on the lower surface of the substrate 251. The second semiconductor chip 260 may include a substrate 261 and a semiconductor device 262 located on the lower surface of the substrate 261. The descriptions of the substrates 251 and 261 of the first semiconductor chip 250 and the second semiconductor chip 260 are consistent with... Figure 1 The descriptions of the substrates 141 and 151 of the first semiconductor chip 140 and the second semiconductor chip 150 are the same and will therefore be omitted here. The descriptions of the semiconductor devices 252 and 262 of the first semiconductor chip 250 and the second semiconductor chip 260 are the same as those of the substrates 141 and 151 of the second semiconductor chip 150. Figure 1 The semiconductor devices 142 and 152 of the first semiconductor chip 140 and the second semiconductor chip 150 are described the same, and therefore will be omitted here.

[0080] According to the inventive concept, since there are no bumps between the first semiconductor chip 250 and the interposer 240, and between the second semiconductor chip 260 and the interposer 240, due to the direct contact between the first bonding pad BPa and the third bonding pad BPc, and between the second bonding pad BPb and the fourth bonding pad BPd, the first semiconductor chip 250 and the second semiconductor chip 260 can be directly connected to the interposer 240. Therefore, because a polymer layer with low thermal conductivity, located between the first semiconductor chip 250 and the interposer 240 and between the second semiconductor chip 260 and the interposer 240, is not required around the bumps, the semiconductor package 200 can have improved thermal conductivity. Because relatively large bumps are not required, bonding pads BPa to BPd with small size and small pitch can be used, and therefore the semiconductor package 200 can have improved integration and increased speed.

[0081] Figures 17A to 17H This is a cross-sectional view illustrating a method for manufacturing a semiconductor package according to an embodiment of the inventive concept. Figure 17F yes Figure 17E A magnified view of region C. (Refer to...) Figure 17A Multiple first semiconductor chips 140 can be arranged on the carrier CR. According to some embodiments, multiple connecting members CP can be further arranged on the carrier CR.

[0082] Reference Figure 17BA first molding layer MD1 can be formed on a carrier CR surrounding a plurality of first semiconductor chips 140 and a plurality of connecting members CP. For example, the first molding layer MD1 can be formed on the carrier CR, the plurality of first semiconductor chips 140, and the plurality of connecting members CP. Next, the first molding layer MD1 can be planarized, exposing the respective upper surfaces of the plurality of first semiconductor chips 140 and the respective upper surfaces of the plurality of connecting members CP. According to some embodiments, after the first molding layer MD1 surrounding the plurality of first semiconductor chips 140 is formed on the carrier CR, a plurality of connecting members CP penetrating the first molding layer MD1 can be arranged on the carrier CR.

[0083] Reference Figure 17C Multiple first bonding pads BP1 can be formed on multiple first semiconductor chips 140. Multiple third bonding pads BP3 can be formed on multiple connecting members CP. A first bonding insulating layer BO1 can be formed around the multiple first bonding pads BP1 on the multiple first semiconductor chips 140 and the first molding layer MD1. The first bonding pads BP1 and the third bonding pads BP3 can be formed, for example, by sputtering and / or electroplating. The first bonding insulating layer BO1 can be formed, for example, by chemical vapor deposition (CVD). The material of the first molding layer MD1 can withstand temperatures of about 300°C or higher while forming the first bonding insulating layer BO1, can have a coefficient of thermal expansion of about 10 ppm / °C or less, and can be selected as a material with good adhesion to the first bonding insulating layer BO1. Through the above operations, a first wafer structure WS1 can be formed. The first wafer structure WS1 includes a plurality of first semiconductor chips 140, a plurality of connecting members CP, a first molding layer MD1 surrounding the plurality of first semiconductor chips 140 and the plurality of connecting members CP, a plurality of first bonding pads BP1 located on the plurality of first semiconductor chips 140, a plurality of third bonding pads BP3 located on the plurality of connecting members CP, and a first bonding insulating layer BO1 located on the plurality of first semiconductor chips 140 and the first molding layer MD1.

[0084] Reference Figure 17DA second wafer structure WS2 can be formed, comprising a plurality of second semiconductor chips 150, a plurality of second bonding pads BP2 located on the plurality of second semiconductor chips 150, a plurality of fourth bonding pads BP4 located on the plurality of second semiconductor chips 150, and a second bonding insulating layer BO2 located on and surrounding the plurality of second bonding pads BP2 and the plurality of fourth bonding pads BP4. Specifically, the plurality of second semiconductor chips 150 can be formed by forming a plurality of semiconductor devices 152 on the wafer W. The plurality of second semiconductor chips 150 can share a single wafer W. In other words, the substrate 151 of each second semiconductor chip 150 can be part of the same wafer W. The plurality of second bonding pads BP2 and the plurality of fourth bonding pads BP4 can be formed on the plurality of second semiconductor chips 150. The plurality of second bonding pads BP2 and the plurality of fourth bonding pads BP4 can be formed, for example, by sputtering and / or electroplating. The second bonding insulating layer BO2 can be formed on the plurality of second semiconductor chips 150 surrounding the plurality of second bonding pads BP2 and the plurality of fourth bonding pads BP4. The second bonding insulating layer BO2 can be formed, for example, by CVD.

[0085] Reference Figure 17E and Figure 17F This allows the first wafer structure WS1 to be bonded to the second wafer structure WS2. According to some embodiments, the first bonding insulating layer BO1 can be first combined with the second bonding insulating layer BO2. For example, the first bonding insulating layer BO1 and the second bonding insulating layer BO2 can be combined by applying a relatively low pressure (about 1 kN or less) at room temperature (about 25°C). According to some embodiments, when the first bonding insulating layer BO1 has been bonded to the second bonding insulating layer BO2, the first bonding pad BP1 and the third bonding pad BP3 may be recessed upwards from the lower surface of the first bonding insulating layer BO1. The second bonding pad BP2 and the fourth bonding pad BP4 may be recessed downwards from the upper surface of the second bonding insulating layer BO2. Therefore, the first bonding pad BP1 may not be bonded to the second bonding pad BP2, and the third bonding pad BP3 may not be bonded to the fourth bonding pad BP4. Next, for example, by raising the temperature to about 300°C, the first bonding pad BP1 can be bonded to the second bonding pad BP2, and the third bonding pad BP3 can be bonded to the fourth bonding pad BP4. In other words, the operation of bonding the first bonding insulating layer BO1 to the second bonding insulating layer BO2 can be performed at a first temperature, and the operation of bonding a plurality of first bonding pads BP1 and a plurality of third bonding pads BP3 to a plurality of second bonding pads BP2 and a plurality of fourth bonding pads BP4 can be performed at a second temperature, and the second temperature (e.g., about 300°C) can be higher than the first temperature (e.g., about 25°C).

[0086] According to another embodiment, such as Figure 5As shown, the first bonding pad BP1 can protrude upward from the upper surface of the first bonding insulating layer BO1, and the second bonding pad BP2 can protrude downward from the lower surface of the second bonding insulating layer BO2. Therefore, even when the first bonding pad BP1 contacts the second bonding pad BP2, the first bonding insulating layer BO1 can be spaced apart from the second bonding insulating layer BO2. Thus, the first bonding pad BP1 can bond to the second bonding pad BP2, but the first bonding insulating layer BO1 can not bond to the second bonding insulating layer BO2.

[0087] When the first wafer structure WS1 is bonded to the second wafer structure WS2, misalignment may occur between the first wafer structure WS1 and the second wafer structure WS2. The misalignment between the first wafer structure WS1 and the second wafer structure WS2 can be approximately 100 nm or smaller. For example... Figure 3B As shown, misalignment between the first wafer structure WS1 and the second wafer structure WS2 may lead to misalignment between the first bonding pad BP1 and the second bonding pad BP2.

[0088] Reference Figure 17E and Figure 17G The carrier CR can be separated from the first wafer structure WS1. Next, a first connection structure 130 can be formed on the first wafer structure WS1. To reduce the thickness of the wafer W, a portion of the wafer W can be removed (e.g., ground).

[0089] Reference Figure 17H Multiple terminal pads 120 can be formed on the first connection structure 130. Next, multiple external connection terminals 110 can be formed on the multiple terminal pads 120 respectively. The multiple external connection terminals 110 can be formed, for example, by reflowing solder balls. By cutting / dicing the first connection structure 130, the first wafer structure WS1, and the second wafer structure WS2 together along the dicing line CL, multiple first semiconductor chips 140 and multiple second semiconductor chips 150 can be divided into... Figure 1 Multiple semiconductor packages 100. According to reference... Figures 17A to 17H The described semiconductor package manufacturing method can form Figure 1 Semiconductor package 100. When the first semiconductor chip 140 can be Figure 14 When the semiconductor chip stack 140S is replaced, it can form Figure 14 100J of semiconductor packaging components.

[0090] According to reference Figures 17A to 17HThe described semiconductor package manufacturing method allows multiple first semiconductor chips 140 to be processed into a single first wafer structure WS1, and multiple second semiconductor chips 150 to be processed into a single second wafer structure WS2, with the first wafer structure WS1 directly bonded to the second wafer structure WS2. By processing the multiple first semiconductor chips 140 and the multiple second semiconductor chips 150 into the first wafer structure WS1 and the second wafer structure WS2, problems caused by particles generated during the operation of dicing wafers W to obtain the first semiconductor chips 140 and the second semiconductor chips 150, as well as during the operation of processing the first semiconductor chips 140 and the second semiconductor chips 150 separately, can be prevented or reduced. Because wafer-to-wafer direct bonding can significantly reduce the number of bonding processes performed and can increase the yield of the bonding process, wafer-to-wafer direct bonding is more advantageous than chip-to-wafer direct bonding. Because wafer-to-wafer direct bonding can be easier or more precise than chip-to-wafer direct bonding, wafer-to-wafer direct bonding is more advantageous than chip-to-wafer direct bonding.

[0091] Figures 18A to 18D This is a cross-sectional view illustrating a method for manufacturing a semiconductor package according to an embodiment of the inventive concept. A description will now be given with reference to... Figures 17A to 17H The semiconductor package manufacturing method and reference described Figures 18A to 18D The differences between the described semiconductor package manufacturing methods. (Refer to...) Figure 18A A first connection structure 130C can be formed on the carrier CR. (Refer to...) Figure 18B A first wafer structure WS1 can be formed on the first interconnect structure 130C. (Refer to...) Figure 18C The first wafer structure WS1 can be bonded to the second wafer structure WS2.

[0092] Reference Figure 18C and Figure 18D This allows the carrier CR to be separated from the first connection structure 130C. The lower portion of the second wafer structure WS2 can be removed to reduce the thickness of the wafer W. Multiple terminal pads 120 can be formed on the first connection structure 130C. Next, multiple external connection terminals 110 can be formed on the multiple terminal pads 120. Next, multiple semiconductor packages 100C can be obtained by cutting the first connection structure 130C, the first wafer structure WS1, and the second wafer structure WS2 along the dicing line CL. (Refer to reference...) Figures 18A to 18D The described semiconductor package manufacturing method first forms a first interconnect structure 130C, and then a first wafer structure WS1 can be formed on the first interconnect structure 130C. Therefore, the first interconnect structure 130C can have an RDL first structure and can be formed... Figure 7 Semiconductor package 100C.

[0093] Figure 19 This is a cross-sectional view illustrating a method for manufacturing a semiconductor package according to an embodiment of the inventive concept. The description will now refer to... Figures 17A to 17H The semiconductor package manufacturing method and reference described Figure 19 The differences between the described semiconductor package manufacturing methods. (Refer to...) Figure 19 The first wafer structure WS1a can be used instead. Figures 17A to 17H The first wafer structure WS1 is formed to form Figure 8 The semiconductor package 100D. The first wafer structure WS1a may further include a second connection structure 160 located between the first molding layer MD1 and the first bonding insulating layer BO1. Specifically, the first connection structure 130C may be formed on the carrier CR, a plurality of first semiconductor chips 140 and a plurality of connection members CP may be arranged on the first connection structure 130C, and a first molding layer MD1 may be formed on the first connection structure 130C surrounding the plurality of first semiconductor chips 140 and the plurality of connection members CP. Next, the second connection structure 160 may be formed on the plurality of first semiconductor chips 140, the plurality of connection members CP and the first molding layer MD1. Next, a plurality of first bonding pads BP1, a plurality of third bonding pads BP3 and the first bonding insulating layer BO1 may be formed on the second connection structure 160.

[0094] Figure 20A and Figure 20B This is a cross-sectional view illustrating a method for manufacturing a semiconductor package according to an embodiment of the inventive concept. The description will now refer to... Figures 17A to 17H The semiconductor package manufacturing method and reference described Figure 20A and Figure 20B The differences between the semiconductor package manufacturing methods described.

[0095] Reference Figure 20AThe first wafer structure WS1b may include a plurality of first semiconductor chips 140, a plurality of first bonding pads BP1 located on the plurality of first semiconductor chips 140, and a first bonding insulating layer BO1 located on the plurality of first semiconductor chips 140 and surrounding the plurality of first bonding pads BP1. Specifically, the plurality of first semiconductor chips 140 can be formed by forming a plurality of semiconductor devices 142 on the wafer W, forming TSVs 145 penetrating the wafer W, forming first chip pads 144A and second chip pads 144B on both sides of the wafer W, and forming first chip insulating layers 143A and second chip insulating layers 143B on both sides of the wafer W. The plurality of semiconductor devices 142 may share the wafer W. In other words, the substrate 141 of each first semiconductor chip 140 may be part of the wafer W. A plurality of first bonding pads BP1 may be formed on the plurality of first chip pads 144A. A first bonding insulating layer BO1 surrounding the plurality of first bonding pads BP1 may be formed on the plurality of first semiconductor chips 140.

[0096] The second wafer structure WS2b may include a plurality of second semiconductor chips 150, a first molding layer MD1F surrounding the plurality of second semiconductor chips 150, a plurality of second bonding pads BP2 located on the plurality of second semiconductor chips 150, and a second bonding insulating layer BO2 located on the plurality of second semiconductor chips 150 and the first molding layer MD1F and surrounding the plurality of second bonding pads BP2. Specifically, the plurality of second semiconductor chips 150 may be arranged on a carrier CR. Next, the first molding layer MD1F surrounding the plurality of second semiconductor chips 150 may be formed on the carrier CR. Next, the plurality of second bonding pads BP2 may be formed on the plurality of second semiconductor chips 150. The second bonding insulating layer BO2 surrounding the plurality of second bonding pads BP2 may be formed on the plurality of second semiconductor chips 150 and the first molding layer MD1F.

[0097] Reference Figure 20B The first wafer structure WS1b can be bonded to the second wafer structure WS2b, such that multiple first bonding pads BP1 directly contact multiple second bonding pads BP2. A first connection structure 130 can be formed on the first wafer structure WS1b. Next, multiple terminal pads 120 can be formed on the first connection structure 130. Multiple external connection terminals 110 can be formed on the multiple terminal pads 120 respectively. The carrier CR can be separated from the second wafer structure WS2b. Multiple semiconductor packages 100F can be obtained by cutting the first connection structure 130, the first wafer structure WS1b, and the second wafer structure WS2b along the dicing line CL. (Refer to reference) Figure 20A and 20B The described semiconductor package manufacturing method can form Figure 10 100F semiconductor package.

[0098] Figure 21 This is a cross-sectional view illustrating a method for manufacturing a semiconductor package according to an embodiment of the inventive concept. The description will now refer to... Figures 17A to 17H The semiconductor package manufacturing method and reference described Figure 21 The differences between the described semiconductor package manufacturing methods. (Refer to...) Figure 21 The second wafer structure WS2c can be used instead. Figure 17D The second wafer structure WS2 is formed to form Figure 9 The semiconductor package 100E. The second wafer structure WS2c may include a plurality of second semiconductor chips 150, a second molding layer MD2 surrounding the plurality of second semiconductor chips 150, a plurality of second bonding pads BP2 located on the plurality of second semiconductor chips 150, and a second bonding insulating layer BO2 located on the plurality of second semiconductor chips 150 and the second molding layer MD2 and surrounding the plurality of second bonding pads BP2. Specifically, a plurality of first semiconductor chips 150 may be arranged on a carrier CR. Next, a second molding layer MD2 surrounding the plurality of second semiconductor chips 150 may be formed on the carrier CR. Next, a plurality of second bonding pads BP2 may be formed on the plurality of second semiconductor chips 150. Next, a second bonding insulating layer BO2 surrounding the plurality of second bonding pads BP2 may be formed on the plurality of second semiconductor chips 150 and the second molding layer MD2.

[0099] Figure 22 This is a cross-sectional view illustrating a method for manufacturing a semiconductor package according to an embodiment of the inventive concept. The description will now refer to... Figures 17A to 17H The semiconductor package manufacturing method and reference described Figure 22 The differences between the described semiconductor package manufacturing methods. (Refer to...) Figure 22 The first wafer structure WS1d and the second wafer structure WS2d can be used instead. Figures 17A to 17H The first wafer structure WS1 and the second wafer structure WS2 are used to form Figure 11 100G of semiconductor packaging components.

[0100] The first wafer structure WS1d may further include a plurality of third semiconductor chips 170 and a plurality of fifth bonding pads BP5 located on the plurality of third semiconductor chips 170. Specifically, a plurality of third semiconductor chips 170, a plurality of first semiconductor chips 140, and a plurality of connecting members CP may be arranged on a carrier CR. Next, a first molding layer MD1 may be formed on the carrier CR surrounding the plurality of third semiconductor chips 170, the plurality of first semiconductor chips 140, and the plurality of connecting members CP. Next, a plurality of first bonding pads BP1 may be formed on the plurality of first semiconductor chips 140, a plurality of third bonding pads BP3 may be formed on the plurality of connecting members CP, and a plurality of fifth bonding pads BP5 may be formed on the plurality of third semiconductor chips 170. A first bonding insulating layer BO1 may be formed on the first molding layer MD1, the plurality of first semiconductor chips 140, and the plurality of third semiconductor chips 170.

[0101] The second wafer structure WS2d may further include a plurality of sixth bonding pads BP6 located on a plurality of second semiconductor chips 150. The sixth bonding pads BP6 may be formed simultaneously with the second bonding pads BP2 and the fourth bonding pads BP4. When the first wafer structure WS1d is bonded to the second wafer structure WS2d, the plurality of sixth bonding pads BP6 may respectively contact the plurality of fifth bonding pads BP5.

[0102] Figure 23 This is a cross-sectional view illustrating a method for manufacturing a semiconductor package according to an embodiment of the inventive concept. The description will now refer to... Figure 20A and Figure 20B The semiconductor package manufacturing method and reference described Figure 23 The differences between the described semiconductor package manufacturing methods. (Refer to...) Figure 23 The first wafer structure WS1e and the second wafer structure WS2e can be used instead. Figure 20A and Figure 20B The first wafer structure WS1b and the second wafer structure WS2b are used to form Figure 13 100I semiconductor package.

[0103] The first wafer structure WS1e may further include a plurality of fifth bonding pads BP5 located on a plurality of first semiconductor chips 140. The second wafer structure WS2e may further include a plurality of third semiconductor chips 170 surrounded by a first molding layer MD1F and a plurality of sixth bonding pads BP6 located on the plurality of third semiconductor chips 170. Specifically, a plurality of second semiconductor chips 150 and a plurality of third semiconductor chips 170 may be arranged on a carrier CR. Next, a first molding layer MD1F may be formed on the carrier CR surrounding the plurality of second semiconductor chips 150 and the plurality of third semiconductor chips 170. Next, a plurality of second bonding pads BP2 may be formed on the plurality of second semiconductor chips 150, and a plurality of sixth bonding pads BP6 may be formed on the plurality of third semiconductor chips 170. A second bonding insulating layer BO2 may be formed on the plurality of second semiconductor chips 150, the plurality of third semiconductor chips 170, and the first molding layer MD1F surrounding the plurality of second bonding pads BP2 and the plurality of sixth bonding pads BP6. When the first wafer structure WS1e is bonded to the second wafer structure WS2e, the plurality of fifth bonding pads BP5 may respectively contact the plurality of sixth bonding pads BP6.

[0104] Figure 24 This is a cross-sectional view illustrating a method for manufacturing a semiconductor package according to an embodiment of the inventive concept. The description will now refer to... Figures 17A to 17H The semiconductor package manufacturing method and reference described Figure 24 The differences between the described semiconductor package manufacturing methods. (Refer to...) Figure 24 ,like Figures 17A to 17E As shown, a first wafer structure WS1 and a second wafer structure WS2 can be formed. The first wafer structure WS1 can be bonded to the second wafer structure WS2, and the carrier CR can be separated from the first wafer structure WS1. Additional bonding pads BP2-1 and BP4-1, as well as a second additional bonding insulating layer BO2-1, can be formed on the first wafer structure WS1. According to the reference... Figures 17A to 17HThe described semiconductor package manufacturing method can fabricate an additional wafer structure WS3. The additional wafer structure WS3 may include a plurality of additional semiconductor chips 140-1, a plurality of additional connecting members CP-1, an additional molding layer MD1-1 surrounding the plurality of additional semiconductor chips 140-1 and the plurality of additional connecting members CP-1, a plurality of first additional bonding pads BP1-1 located on the plurality of additional semiconductor chips 140-1, a plurality of third additional bonding pads BP3-1 located on the plurality of additional connecting members CP-1, and a first additional bonding insulating layer BO1-1 located on the plurality of additional semiconductor chips 140-1 and the additional molding layer MD1-1 and surrounding the plurality of first additional bonding pads BP1-1 and the plurality of third additional bonding pads BP3-1. The third wafer structure WS3 can be bonded to the first wafer structure WS1 such that the plurality of first additional bonding pads BP1-1 respectively contact a plurality of second additional bonding pads BP2-1, and the plurality of third additional bonding pads BP3-1 respectively contact a plurality of fourth additional bonding pads BP4-1. The first additional bonding insulating layer BO1-1 can be bonded to the second additional bonding insulating layer BO-2, or it can be separated from the second additional bonding insulating layer BO-2. By sequentially bonding multiple wafer structures in this manner, it is possible to manufacture... Figure 15 100K semiconductor packages.

[0105] Figure 25A and Figure 25B This is a cross-sectional view illustrating a method for manufacturing a semiconductor package according to an embodiment of the inventive concept. (Refer to...) Figure 25A A first wafer structure WSa is formed, comprising a mediator wafer 240W having a plurality of interposers 240, a plurality of first bonding pads BPa located on the mediator wafer 240W, a plurality of second bonding pads BPb located on the mediator wafer 240W, and a first bonding insulating layer BOa surrounding the plurality of first bonding pads BPa and the plurality of second bonding pads BPb on the mediator wafer 240W. Specifically, the mediator wafer 240W comprising the plurality of interposers 240 can be fabricated. Next, the plurality of first bonding pads BPa and the plurality of second bonding pads BPb can be formed on the mediator wafer 240W. The first bonding insulating layer BOa surrounding the plurality of first bonding pads BPa and the plurality of second bonding pads BPb can be formed on the mediator wafer 240W.

[0106] A second wafer structure WSb is fabricated, comprising a plurality of first semiconductor chips 250, a plurality of second semiconductor chips 260, a first molding layer MDa surrounding the plurality of first semiconductor chips 250 and the plurality of second semiconductor chips 260, a plurality of third bonding pads BPc located on the plurality of first semiconductor chips 250, a plurality of fourth bonding pads BPd located on the plurality of second semiconductor chips 260, and a second bonding insulating layer BOb surrounding the plurality of third bonding pads BPc and the plurality of fourth bonding pads BPd on the plurality of first semiconductor chips 250, the plurality of second semiconductor chips 260 and the first molding layer MDa. For example, the plurality of first semiconductor chips 250 and the plurality of second semiconductor chips 260 can be arranged on a carrier CR. Next, the first molding layer MDa surrounding the plurality of first semiconductor chips 250 and the plurality of second semiconductor chips 260 can be formed on the carrier CR. Next, the plurality of third bonding pads BPc can be formed on the plurality of first semiconductor chips 250 and the plurality of fourth bonding pads BPd can be formed on the plurality of second semiconductor chips 260. A second bonding insulation layer BOb can be formed on the first molding layer MDa, surrounding a plurality of third bonding pads BPc and a plurality of fourth bonding pads BPd.

[0107] Reference Figure 25B The first wafer structure WSa can be bonded to the second wafer structure WSb, such that multiple first bonding pads BPa respectively contact multiple third bonding pads BPc, and multiple second bonding pads BPb respectively contact multiple fourth bonding pads BPd. The carrier CR can be separated from the second wafer structure WS2b. Multiple semiconductor packages 200 can be obtained by cutting the first wafer structure WSa and the second wafer structure WSb along the dicing line CL.

[0108] Reference Figure 16 The intermediate body 240 can be attached to the package substrate 220 using multiple internal connection members 230. A second molding layer MDb can be formed on the package substrate 220 surrounding the intermediate body 240 and the first molding layer MDa. External connection terminals 210 can be attached to the lower surface of the package substrate 220. Therefore, a... Figure 16 200 semiconductor packages.

[0109] According to reference Figure 25A and Figure 25BThe described semiconductor package manufacturing method allows multiple first semiconductor chips 250 and multiple second semiconductor chips 260 to be processed into a single second wafer structure WSb, and multiple interposers 240 to be processed into a single first wafer structure WSa, with the first wafer structure WSa directly bonded to the second wafer structure WSb. By processing the multiple first semiconductor chips 250, the second semiconductor chips 260, and the multiple interposers 240 into the second wafer structure WSb and the first wafer structure WSa, problems caused by particles generated during the operation of dicing wafers to obtain the first semiconductor chips 250, the second semiconductor chips 260, and the interposers 240, as well as during the operation of separately processing the first semiconductor chips 250, the second semiconductor chips 260, and the interposers 240, can be prevented or reduced. Because wafer-to-wafer direct bonding can significantly reduce the number of bonding processes performed and can increase the yield of the bonding process, wafer-to-wafer direct bonding can be more advantageous than chip-to-wafer direct bonding. Because wafer-to-wafer direct bonding can be easier or more precise than chip-to-wafer direct bonding, wafer-to-wafer direct bonding can be more advantageous than chip-to-wafer direct bonding.

[0110] Although the inventive concept has been specifically shown and described with reference to embodiments thereof, it will be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the claims.

Claims

1. A packaged semiconductor device, the semiconductor device comprising: First connection structure; A first semiconductor chip is located on the upper surface of a first connection structure. The first semiconductor chip includes a semiconductor substrate, a through-substrate via, and a first chip pad. A first molding layer is positioned on the upper surface of the first connection structure and at least partially surrounds the first semiconductor chip; The first bonding pad is located on the first semiconductor chip; A first bonding insulating layer at least partially surrounds the first bonding pad; The second bonding pad directly contacts the first bonding pad; A second bonding insulation layer at least partially surrounds the second bonding pad; as well as The second semiconductor chip is located on the second bonding pad and the second bonding insulating layer. The first chip pad is located between the through-substrate via and the first bonding pad and is in direct contact with the first bonding pad. The through-substrate via extends through the semiconductor substrate to be electrically connected to the first bonding pad via the first chip pad.

2. The semiconductor device according to claim 1, wherein, The second bonding insulation layer is in direct contact with the first bonding insulation layer.

3. The semiconductor device according to claim 1, further comprising: The connecting component penetrates the first molding layer; The third bonding pad is positioned on the connecting member and is at least partially surrounded by the first bonding insulation layer; as well as The fourth bonding pad is in direct contact with the third bonding pad and is at least partially surrounded by the second bonding insulation layer.

4. The semiconductor device according to claim 1, wherein, The first semiconductor chip also includes semiconductor devices located on a semiconductor substrate.

5. The semiconductor device according to claim 4, wherein, The first semiconductor chip also includes: The second chip pad is located between the through-substrate via and the first connection structure.

6. The semiconductor device according to claim 1, wherein, The first semiconductor chip also includes semiconductor devices adjacent to the surface of the semiconductor substrate.

7. The semiconductor device according to claim 1, further comprising: External connection terminals are located on the lower surface of the first connection structure.

8. The semiconductor device according to claim 1, wherein, The side surface of the first connecting structure is coplanar with the side surface of the first molding layer.

9. The semiconductor device according to claim 1, wherein, The side surface of the second semiconductor chip is coplanar with the side surface of the first molding layer.

10. The semiconductor device of claim 1, further comprising a second molding layer positioned on the second bonding insulating layer and at least partially surrounding the second semiconductor chip.

11. A packaged semiconductor device, the semiconductor device comprising: Redistributed structure; Solder bumps are located on the first surface of the redistribution structure; A first semiconductor chip is located on a second surface of a redistribution structure. The first semiconductor chip includes: a semiconductor substrate; a lower chip pad located on the lower surface of the semiconductor substrate; an upper chip pad located on the upper surface of the semiconductor substrate; and a through-substrate via located in the semiconductor substrate, the through-substrate via extending between the lower chip pad and the upper chip pad. A first molding layer is located on the second surface of the redistribution structure and at least partially surrounds the first semiconductor chip; The first bonding pad is located on the upper chip pad of the first semiconductor chip; A first bonding insulating layer is located on the upper surface of the first semiconductor chip and the upper surface of the first molding layer, and at least partially surrounds the first bonding pad; The second bonding pad contacts the first bonding pad; A second bonding insulation layer contacts the first bonding insulation layer and at least partially surrounds the second bonding pad; and The second semiconductor chip is located on the second bonding pad and the second bonding insulating layer. In this configuration, the upper chip pad is in direct contact with the first bonding pad, and The through-substrate via extends through the semiconductor substrate to be electrically connected to the first bonding pad via the upper chip pad.

12. The semiconductor device of claim 11, further comprising: A third semiconductor chip is located on the second surface of the redistribution structure and is at least partially surrounded by the first molding layer; The third bonding pad is positioned on the upper surface of the third semiconductor chip and is at least partially surrounded by the first bonding insulating layer. as well as The fourth bonding pad is in direct contact with the third bonding pad and is at least partially surrounded by the second bonding insulation layer.

13. The semiconductor device according to claim 11, wherein, The first bonding insulating layer and the second bonding insulating layer each comprise a material selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, and combinations thereof.

14. The semiconductor device according to claim 11, wherein, The coefficient of thermal expansion of the first molding layer is in the range of 0 ppm / ℃ to 10 ppm / ℃.

15. A packaged semiconductor device, the semiconductor device comprising: Connection structure; A first semiconductor chip is located on the upper surface of the connection structure. The first semiconductor chip includes a semiconductor substrate, a through-substrate via, and a first chip pad. The first bonding pad is located on the first semiconductor chip; A first bonding insulating layer extends on the first semiconductor chip and at least partially surrounds the first bonding pad; The second bonding pad directly contacts the first bonding pad; The second bonding insulation layer at least partially surrounds the second bonding pad; The second semiconductor chip is located on the second bonding pad and the second bonding insulating layer; as well as A first molding layer is positioned on the second bonding insulating layer and at least partially surrounds the second semiconductor chip. The first chip pad is located between the through-substrate via and the first bonding pad and is in direct contact with the first bonding pad. The through-substrate via extends through the semiconductor substrate to be electrically connected to the first bonding pad via the first chip pad.

16. The semiconductor device according to claim 15, wherein, The side surface of the first semiconductor chip is coplanar with the side surface of the first molding layer.

17. The semiconductor device of claim 15, further comprising a second molding layer extending between the interconnect structure and the first bonding insulating layer, and at least partially surrounding the first semiconductor chip.

18. The semiconductor device of claim 15, further comprising: The third bonding pad is located on the first semiconductor chip and is at least partially surrounded by the first bonding insulating layer; The fourth bonding pad directly contacts the third bonding pad and is at least partially surrounded by the second bonding insulation layer; as well as The third semiconductor chip is positioned on the fourth bonding pad and the second bonding insulating layer, and is at least partially surrounded by the first molding layer.

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