Write and query operations in a content addressable memory system having a content addressable memory buffer

Abstract

A device (e.g., a content addressable memory system) may have a controller, a first content addressable memory coupled to the controller, and a second content addressable memory coupled to the controller. The controller may be configured to cause the first content addressable memory to write data to the first content addressable memory, cause the second content addressable memory to write the data to the second content addressable memory, and cause the second content addressable memory to query the data written to the second content addressable memory while the first content addressable memory continues to write the data to the first content addressable memory.

Description

Technical Field

[0001] The present disclosure relates generally to content addressable memory, and more particularly to write and query operations in a content addressable memory system having a content addressable memory buffer. Background Art

[0002] Memory systems can be implemented in electronic systems such as computers, cellular phones, handheld electronic devices, and the like. Some memory systems, such as solid-state drives (SSDs), embedded multimedia controller (eMMC) devices, universal flash storage (UFS) devices, and the like, may include non-volatile storage memory for storing host (e.g., user) data from a host. Non-volatile storage memory provides persistent data by retaining stored data when not powered, and may include NAND flash memory, NOR flash memory, read-only memory (ROM), electrically erasable programmable ROM (EEPROM), erasable programmable ROM (EPROM), and resistance variable memory, such as phase-change random access memory (PCRAM), three-dimensional cross-point memory (e.g., 3D XPoint), resistive random access memory (RRAM), ferroelectric random access memory (FeRAM), magnetoresistive random access memory (MRAM), and programmable conductive memory, among other types of memory.

[0003] Some memory cells, such as individual resistance variable memory cells, can be arranged in a cross-point architecture, such that the memory cell is located at the intersection of signal lines used to access the cell (e.g., the intersection of a word line and a bit line). For example, the state (e.g., the stored data value) of a resistance variable memory cell can depend on the programmed resistance of the memory cell.

[0004] The memory typically returns user data to the host (e.g., during a read operation) in response to an address supplied by the host. Another form of memory is a content-addressable memory (CAM), also known as an associative pattern memory (APM). In some examples, the CAM can be queried to determine whether input data (e.g., an input data vector) is stored in the CAM. For example, the CAM can receive input data and can perform a search to determine whether data stored in the CAM (e.g., a stored data vector) matches the input data.

[0005] CAMs can be used as hardware-based search devices in applications where fast searching or pattern matching is required, such as in computer systems, databases, image or speech recognition, biometrics, data compression, cache memory controllers, or computer and communication networks (e.g., in network switches, media access controllers, network routers, etc.). Summary of the Invention

[0006] One aspect of the present disclosure provides a device for performing write and query operations in a content addressable memory system having a content addressable memory buffer, wherein the device includes: a controller; a first content addressable memory coupled to the controller; and a second content addressable memory coupled to the controller; wherein the controller is configured to: cause the first content addressable memory to write data in the first content addressable memory; cause the second content addressable memory to write the data in the second content addressable memory; and when the first content addressable memory continues to write the data in the first content addressable memory, cause the second content addressable memory to query the data written in the second content addressable memory.

[0007] Another aspect of the present disclosure provides a device for performing write and query operations in a content addressable memory system having a content addressable memory buffer, wherein the device includes: a controller; a main content addressable memory coupled to the controller; and a buffer content addressable memory coupled to the controller; wherein the controller is configured to cause the buffer content addressable memory to query the buffer content addressable memory rather than causing the main content addressable memory to query partially filled memory tiles in the main content addressable memory.

[0008] Another aspect of the present disclosure provides a method for performing write and query operations in a content addressable memory system having a content addressable memory buffer, wherein the method includes: writing a data vector in a memory tile of a first content addressable memory; writing the data vector in a region of a second content addressable memory corresponding to the memory tile; and querying the region instead of the memory tile. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1A is a simplified block diagram of a device according to several embodiments of the present disclosure.

[0010] Figure 1B Shown are examples of data structures according to several embodiments of the present disclosure.

[0011] Figure 2A is a block diagram of a portion of a nonvolatile CAM corresponding to a specific write phase according to several embodiments of the present disclosure.

[0012] Figure 2B According to several embodiments of the present disclosure, Figure 2A A block diagram of a portion of a nonvolatile CAM during a specific write phase following the specific write phase.

[0013] Figure 3A is a block diagram of a portion of a buffer CAM corresponding to a specific write phase according to several embodiments of the present disclosure.

[0014] Figure 3B According to several embodiments of the present disclosure, Figure 3A Block diagram of a portion of a buffer CAM of a specific write phase after the specific write phase.

[0015] Figure 4 is a simplified block diagram of a CAM according to several embodiments of the present disclosure.

[0016] Figure 5 A portion of a non-volatile CAM according to several embodiments of the present disclosure is shown.

[0017] Figure 6 Querying data stored in a non-volatile CAM according to several embodiments of the present disclosure is shown. DETAILED DESCRIPTION

[0018] In various situations, non-volatile memory can be used as a CAM. Providing a non-volatile memory CAM can have various advantages over a volatile CAM (e.g., an SRAM CAM). For example, a non-volatile CAM does not require power to maintain its data, and non-volatile memory cells typically have a smaller footprint than volatile memory cells, thus providing greater storage density. Volatile CAMs can also typically provide faster data write times than non-volatile CAMs, so that data written to a volatile CAM can be queried sooner than data written to a non-volatile CAM.

[0019] In some instances, the non-volatile CAM is not accessible for querying while data is being written to the CAM. For example, while additional data is being written to the non-volatile CAM, previously stored data in the non-volatile CAM is not accessible for querying. This problem can be exacerbated by the relatively long write times associated with the non-volatile CAM, as previously written data is not accessible for querying during the write time.

[0020] As further described herein, various embodiments of the present disclosure provide CAM implementations that can take into account the write times associated with nonvolatile memory cells. Thus, embodiments can provide nonvolatile CAMs with improved query times and other benefits over previous approaches.

[0021] As an example, several embodiments may employ a non-volatile first CAM as a primary CAM and a second CAM, such as a volatile CAM (e.g., an SRAM buffer CAM), as a buffer CAM. Data can be written to both the primary CAM and the buffer CAM, and data written to the buffer CAM can be queried while data continues to be written to the primary CAM. This can eliminate delays associated with waiting for data to be written to the primary CAM before querying the data in the primary CAM, for example.

[0022] In some examples, previously written data in the primary CAM can be copied to the buffer CAM so that when additional data is written to the primary CAM, the previously written data can be queried in the buffer CAM. For example, this can eliminate the problem of previously written data in the primary CAM being inaccessible for querying when additional data is written to the primary CAM.

[0023] Using a buffer CAM in conjunction with a primary non-volatile CAM can reduce energy requirements, cost, and time required to obtain reliable comparison results compared to using a DRAM buffer or a table as a buffer in conjunction with a primary CAM. For example, using a DRAM or table can involve a time-consuming process of scanning the entire contents of the DRAM or table to identify data corresponding to data in the primary CAM to be compared with the input data.

[0024] Figure 1A is a simplified block diagram of a device in the form of a computing system 100 according to several embodiments of the present disclosure. The computing system 100 includes a device in the form of a CAM system 102, which may be, for example, a Peripheral Component Interconnect Express (PCIe) CAM system, among other types of CAM systems.

[0025] CAM system 102 may include a controller 104, CAMs 106-1 through 106-8 coupled to controller 104 via a bus 108, and CAMs 110-1 and 110-2 coupled to controller 104. Although eight CAMs 106 and two CAMs 110 are shown, any number of CAMs 106 and 110 may be present. In some examples, CAM 106 may be referred to as a primary (e.g., master) CAM, and CAM 110 may be referred to as a buffer CAM (e.g., because CAM 110 may act as a buffer for CAM 106). In some examples, there may be a single primary CAM 106 that may include CAMs 106-1 through 106-8, and there may be a single buffer CAM 110 that may include CAMs 110-1 and 110-2. Herein, "CAM 106" and / or "primary CAM" will be used to refer to one or more of CAMs 106-1 through 106-8, and "CAM 110" and / or "buffer CAM" will be used to refer to one or more of CAMs 110-1 and 110-2.

[0026] The controller 104 may cause the primary CAM to write data (e.g., one or more data vectors) to the primary CAM, cause the buffer CAM to write data to the buffer CAM, and cause the buffer CAM to query the data written in the buffer CAM while the primary CAM continues to write data to the primary CAM. In some examples, querying the data in the primary CAM and / or the buffer CAM may include comparing input data (e.g., input data vectors) with data in the primary CAM and / or the buffer CAM. In some examples, the controller 104 may cause the buffer CAM to remove the data written in the buffer CAM in response to determining that the primary CAM has finished writing data to the primary CAM, and may then cause the primary CAM to query the data in the primary CAM.

[0027] In various examples, the controller 104 may include match verification circuitry that can be used to verify a match between an input data vector and a data vector stored in the buffer CAM or the main CAM. For example, in response to receiving an indication that the input data vector matches a stored data vector, the match verification circuitry can cause the buffer CAM or the main CAM to read the stored data vector and return the data vector read from the buffer CAM or the main CAM to the controller 104. The match verification circuitry can then compare the returned data vector with the input data vector to determine whether the previously indicated match is valid.

[0028] In some examples, the primary CAM and the buffer CAM may include match verification circuitry that can be used to verify a match between an input data vector and a stored data vector. For example, in response to the input data vector matching the stored data vector, the match verification circuitry can read the stored data vector and compare the read data vector with the input data vector to determine whether the previously indicated match is valid. If the match is not valid, the match verification circuitry can change the comparison result from a match to a no match and send the result to the controller 104.

[0029] The controller 104 may cause the main CAM and the buffer CAM to write data to the main CAM and the buffer CAM in parallel until the buffer CAM finishes writing data to the buffer CAM, and may cause the buffer CAM to query the data written to the buffer CAM while the main CAM continues writing data to the main CAM. For example, the main CAM may write data to the main CAM during a first time period; the buffer CAM may write data to the buffer CAM during a second time period that overlaps with an initial portion of the first time period; and the buffer CAM may query the data written to the buffer CAM during the remainder of the first time period. In some examples, the buffer CAM may write data to the buffer CAM faster than the main CAM writes data to the main CAM.

[0030] In some examples, the main CAM may be a non-volatile CAM, and the buffer CAM may be a volatile CAM, such as an SRAM CAM. For example, data written and / or stored in the buffer CAM may be written and / or stored in SRAM memory cells, and data written and / or stored in the main CAM may be written and / or stored in non-volatile memory cells. In some examples, the main CAM may be a cross-point device that may include resistance variable memory cells, such as a 3D XPoint device. However, the present disclosure is not limited thereto, and the main CAM may include other types of non-volatile memory cells.

[0031] The controller 104 may create a data structure, such as a lookup (e.g., mapping) table 112 (e.g., in the controller 104), each time a data vector is written to the primary CAM (e.g., in response to the primary CAM writing the data vector to the primary CAM). It should be noted that the buffer CAM may write a corresponding data vector to the buffer CAM each time the primary CAM writes the data vector to the primary CAM. In some examples, the controller 104 may manage the lookup table 112.

[0032] In some examples, controller 104 may include a logical-to-physical (L2P) mapping table 113 that may map logical addresses of data vectors received from host 103 to physical addresses of data vectors in the primary CAM.

[0033] Controller 104 may be a field programmable gate array (FPGA) and / or an application specific integrated circuit (ASIC), among other types of controllers. Host 103 may be, for example, a host system such as a personal laptop computer, a desktop computer, a digital camera, a mobile device (e.g., a cell phone), a network server, an Internet of Things (IoT)-enabled device, or a memory card reader, among other types of hosts. For example, host 103 may include one or more processors capable of accessing CAM system 102 (e.g., via controller 104) via interface 116, which may include a bus. Interface 116 may be a standardized interface, such as Serial Advanced Technology Attachment (SATA), PCIe, or Universal Serial Bus (USB), among other interfaces.

[0034] In some examples, the CAM system 102 can be part of a memory system of the computing system 100. For example, the memory system can be a storage system, such as an SSD, a UFS device, an eMMC device, etc. In various examples in which the CAM system 102 can be part of the memory system, the controller 104 can be part of (e.g., control logic integrated therein) a memory system controller (e.g., an SSD controller, an application-specific integrated circuit ASIC, a processor, etc.) coupled to the memory system and configured to control various memory devices of the memory system.

[0035] Figure 1B An example of a data structure in the form of a lookup table 112 is shown in accordance with several embodiments of the present disclosure. The lookup table 112 may include entries 114-1 through 114-N that may map locations (e.g., addresses of locations) in the primary CAM to locations (e.g., addresses of locations) in the buffer CAM. For example, the lookup table 112 may map primary CAM addresses to buffer CAM addresses.

[0036] In some examples, the primary CAM address may be the physical address of the location of a group of memory cells in the primary CAM where the data vector is written, and the buffer address may be the physical address of the location of a group of memory cells in the buffer CAM that stores a data vector corresponding to the data vector written in the primary CAM. For example, entries 114-1 through 114-N may map the address of the location of the data vector in the primary CAM to the address of the location of the corresponding data vector in the buffer CAM. The controller 104 may manage the lookup table 112, for example, by writing the address of the data vector in the primary CAM and the address of the data vector in the buffer CAM in entry 114. While the primary CAM is writing the corresponding data vector in the location in the primary CAM, the mapping in entry 114 may be valid, and the controller 104 may manage the lookup table 112, for example, by invalidating the mapping in response to determining that the primary CAM has finished writing data in the location in the primary CAM.

[0037] In some examples, the primary CAM address may be a physical address of a memory tile in the primary CAM, and the buffer address may be a physical address of a region in the buffer CAM. For example, entries 114-1 through 114-N may map the address of a location of a memory tile in the primary CAM to the address of a location of a region in the buffer CAM. In some examples, each of the memory tile addresses may be mapped to an address range corresponding to a region in the buffer CAM. In some examples, the mapping in entry 114 may be valid as long as the corresponding memory tile is partially filled (e.g., not completely filled) with data, and the controller 104 may invalidate the mapping in response to determining that the corresponding memory tile is completely filled.

[0038] Figure 2A is a block diagram of a portion of a nonvolatile CAM corresponding to a specific write phase according to several embodiments of the present disclosure. Figure 2B According to several embodiments of the present disclosure, Figure 2A A block diagram of a portion of a nonvolatile CAM in a specific write phase after the specific write phase of the nonvolatile CAM. For example, Figure 2A and 2B A non-volatile CAM array 218 of a primary CAM is shown, such as CAM 206 of CAM 106. CAM array 218 may include several memory tiles 220 (e.g., memory tiles 220-1 through 220-M). In some examples, a memory tile may be the smallest grouping of memory cells that is unavailable for querying during a write operation. For example, when a data vector is being written to a memory tile 220, the memory tile may be unavailable for querying.

[0039] Each of the memory tiles 220-1 through 220-M may include a corresponding group of memory cells at corresponding locations 225-1 through 225-K. The corresponding locations 225-1 through 225-K in each of the memory tiles 220-1 through 220-M may have physical addresses Addr 1 through Addr K, respectively. A corresponding data vector may be written to the corresponding locations 225-1 through 225-K in each of the memory tiles 220-1 through 220-M. In some examples, the L2P table 113 may map a corresponding logical address from the host 103 to a corresponding address Addr in the corresponding memory tile 220 in the corresponding primary CAM.

[0040] Each respective location 225 may be specified by specifying the location of a respective primary CAM in the CAM system (e.g., CAM 106 in CAM system 102), the location of a respective memory tile in the respective primary CAM (e.g., memory tile 220), and the respective location 225 in the respective memory tile. For example, location 225-2 in memory tile 220-1 in CAM 106-3 may be specified by specifying the location of CAM 106-3 in CAM system 102, the location of memory tile 220-1 in CAM 106-3, and location 225-2 in memory tile 220-1.

[0041] The corresponding physical address Addr may specify the location of the corresponding data vector, for example, by specifying the location of the corresponding primary CAM in the CAM system, the location of the corresponding memory tile in the corresponding primary CAM, and the location of the corresponding data vector in the corresponding memory tile. For example, the physical address Addr 2 may specify the location of the data vector Vector 2 by specifying the location of the CAM 106-3, the location of the memory tile 220-1 in the CAM 106-3, and the location 225-1 of Vector 2 in the memory tile 220-1.

[0042] In some examples, the locations 225-1 through 225-K in each memory tile 220 can be an ordered sequence, where the locations 225-1 through 225-K are the first through Kth locations in the ordered sequence, respectively. Furthermore, the addresses Addr 1 through Addr K can be an ordered sequence, where the addresses Addr 1 through Addr K are the lowest to highest addresses in the ordered sequence, respectively. For example, data vectors can be written sequentially (e.g., successively) to the sequence of free locations 225-1 through 225-K in the order in which the data vectors are received from the host 103.

[0043] The corresponding data vectors may be written sequentially in a sequence of corresponding first available free locations. For example, Vector 1 and Vector 2 may be received sequentially from the host 103, and the sequence of locations 225-1 to 225-K may be the available free locations in the memory tile 220-1. Thus, Vector 1 may be written to the first available free location 225-1, and Vector 2 may be subsequently written to the first available free location 225-2 following location 225-1. It should be noted that the next K-2 data vectors Vector 3 to Vector K received consecutively from the host 103 may be written sequentially to locations 225-3 to 225-K, i.e., the subsequent available free locations following location 225-2, respectively. Figure 2B As shown in .

[0044] In some examples, the memory tiles 220-1 through 220-M may be in an ordered sequence, where the memory tiles 220-1 through 220-M are the first through Mth memory tiles in the ordered sequence, respectively. For example, the memory tiles 220-1 through 220-M may be written to sequentially.

[0045] Vector (K+1) may be received after Vector K is written in position 225-K, and thus after tile 220-1 is fully filled. For example, Vector (K+1) may be written in the first available free memory tile 220-2 in the sequence of memory tiles, e.g., in the first available free position 225-1 in the sequence of positions 225-1 to 225-K in memory tile 220-2, as shown in FIG. Figure 2B As shown in .

[0046] In some examples, K+1 data vectors Vector 1 through Vector (K+1) may be written in response to K+1 write commands sequentially received at the controller 104 from the host 103. For example, the write commands may each specify a logical address, and the L2P mapping table 113 may map the first K logical addresses to physical addresses Addr 1 through Addr K in the tile 220-1, and map the K+1th logical address to address Addr 1 in the tile 220-2.

[0047] In some examples, the controller 104 may cause the CAM 206 to write to the first available memory tile 220 in the enabled sequence of memory tiles 220-1 through 220-M in response to receiving a write command, such as the first of the aforementioned K+1 write commands from the host 103. For example, the first available memory tile may be the first memory tile in the sequence that has at least one free location.

[0048] Next, the controller 104 may cause all data vectors previously written in the write-enabled memory tiles to be copied to corresponding regions of the buffer CAM. For example, the controller may cause the CAM 206 to read all data vectors previously written in the write-enabled memory tiles and output the read data vectors to the controller 104. The controller 104 may then send the data vectors read from the CAM 206 to the buffer CAM and cause the buffer CAM to write the data vectors in corresponding regions of the buffer CAM.

[0049] The controller 104 may cause the CAM 206 to subsequently write the data vector specified in the command to the first available free location in the write-enabled memory tile, and may cause the buffer CAM to write the data vector specified in the command to the region in the buffer CAM, such that the CAM 206 and the buffer CAM write the data vector in parallel until the buffer CAM finishes writing the data vector to the region in the buffer CAM. The controller 104 may map the address of the location of the tile to the address of the region, and may query the region instead of the tile as the CAM 206 continues to write the data vector to the write-enabled memory tile. In response to finishing writing the data vector to the write-enabled memory tile, the controller 104 may invalidate the mapping of the address of the location of the tile to the address of the region, and / or remove the data vector from the region.

[0050] In this example, Vector 1 and Vector 2 may have been previously written in tile 220-1, as shown in FIG. Figure 2A . Subsequently, the controller 104 may receive a write command to write Vector 3 to Vector K. The controller 104 may cause Vector 1 and Vector 2 to be copied to the area in the buffer CAM, and cause the CAM 206 and the buffer CAM to write Vector 3 to Vector K in tile 220-1 and in the area in the buffer CAM in parallel until the buffer CAM finishes writing Vector 3 to Vector K to the area in the buffer CAM.

[0051] The controller 104 may map the address of the location of tile 220-1 to the address of the region and query the region instead of tile 220-1 as the CAM 206 continues to write Vector 3 through Vector K in memory tile 220-1. In response to the CAM 206 finishing writing Vector 3 through Vector K in tile 220-1, the controller 104 may invalidate the mapping of the address of the location of tile 220-1 to the address of the region and / or remove the data vector from the region.

[0052] Alternatively, in response to determining that the memory tile 220-1 is completely filled with data vectors, the controller 104 may invalidate the mapping of addresses of locations in the tile 220-1 to addresses of the region and / or remove the data vectors from the region, as shown. Figure 2B . For example, the controller 104 may track the fill level of tile 220-1 (e.g., by tracking the percentage of tile 220-1 used). Instead of causing CAM 206 to query tile 220-1, the controller 104 may cause the buffer CAM to query a region in the buffer CAM as long as the tile 220-1 is partially filled with a data vector, regardless of whether the tile 220-1 is write-enabled and / or actively being written to. For example, the controller 104 may cause the buffer CAM to maintain a copy of the data vector in a region of the buffer CAM until the tile 220-1 is completely filled.

[0053] It should be noted that after the mapping of the address of the location of tile 220-1 to the address of the region in the buffer CAM is invalidated and / or Vectors 1 to K are removed from the region in the buffer CAM, the controller may cause CAM 206 to write Vector (K+1) to location 225-1 in memory tile 220-2 and the region in the buffer CAM in parallel until Vector (K+1) is written to the buffer CAM. Controller 104 may map memory tile 220-2 to the region in the buffer CAM. While CAM 206 continues to write Vector (K+1) to memory tile 220-2 and / or before memory tile 220-2 is completely filled with data vectors, controller 104 may cause the buffer CAM to query the buffer CAM for Vector (K+1). Furthermore, CAM 206 may query the completely filled tile 220-1, and the buffer CAM may query the region in the buffer CAM corresponding to memory tile 220-2 in parallel.

[0054] In some examples, the host 103 may send a write command to write a new data vector in a location in the memory tile storing a previously written data vector, e.g., to update (e.g., overwrite) the previously written data vector. For example, the write command may include a logical address that is mapped by the L2P table 113 to the location 225-1 storing Vector 1. In response to the write command, the controller 104 may write the new data vector in a first available free location. For example, the first available free location may be Figure 2A Location 225-3 in memory tile 220-1 or Figure 2B The controller 104 may then modify the L2P table 113 to remap the logical address to the location 225-2 in the memory tile 220-2. Figure 2A Position 225-3 in tile 220-1 or Figure 2B Position 225-2 in tile 220-2.

[0055] Figure 3A is a block diagram of a portion of the buffer CAM 310 corresponding to a specific write phase according to several embodiments of the present disclosure. Figure 3B According to several embodiments of the present disclosure, Figure 3A 1. A block diagram of a portion of a buffer CAM 310 for a specific write phase after the specific write phase of FIG. 1. For example, the buffer CAM 310 may be CAM 110. In some examples, Figure 3A A specific write phase may correspond to Figure 2A a specific write phase, and Figure 3B A specific write phase may correspond to Figure 2B Specific write phase.

[0056] The buffer CAM 310 may have a CAM array 331 of volatile memory cells, such as SRAM memory cells, which may store vectors from various memory tiles in various primary CAMs, such as CAMs 106-1 to 106-8 and / or CAM 206. Vectors from respective memory tiles may be stored in respective regions 330-1 to 330-4. For example, a region may store data vectors from a memory tile that is currently being written to and / or partially filled. Although in Figure 3A and 3B Four regions are shown in the example of , but there may be any number of regions, eg, depending on the number of memory tiles whose data vectors may need to be stored in the buffer CAM 310 .

[0057] Regions 330-1 to 330-4 may correspond to address ranges 332-1 to 332-4, respectively, in buffer CAM 310. The addresses of the corresponding memory tiles may be mapped to address ranges 332-1 to 332-4, respectively. For example, it should be noted that Figure 2A and 2B The vectors of the memory tile 220 - 1 may be stored in the region 330 - 1 , and the addresses of the memory tile 220 - 1 may be mapped to the address range 332 - 1 .

[0058] Respective data vectors from respective memory tiles may be stored in respective locations in respective regions corresponding to the respective memory tiles. For example, each respective location may include a respective group of volatile memory cells that may store the respective data vectors. The respective locations in each respective region may have addresses in the address range 332 that correspond to the respective region. The locations in each respective region may correspond to locations in the respective memory tiles.

[0059] For example, locations 335-1 through 335-K in region 330-1 may correspond to locations 225-1 through 225-K in memory tile 220-1, respectively, and may have addresses Addr BC1 through Addr BCK, respectively, in address range 332-1. In some examples, addresses Addr 1 through Addr K of memory tile 220-1 may be mapped to addresses Addr BC1 through Addr BCK, respectively, of region 330-1.

[0060] It should be noted that Vector 1 and Vector 2 can be written in parallel in tile 220-1 and region 330-1 until Vector 1 and Vector 2 are written to region 330-1. While writing Vector 1 and Vector 2 to memory tile 220-1 continues and / or whenever memory tile 220-1 is partially filled with data vectors, Vector 1 and Vector 2 in region 330-1 can be queried, as shown in FIG. Figure 2A As shown in .

[0061] In some examples, in response to write-enabling memory tile 220-1 to write Vector 3 to Vector K in memory tile 220-1, Vector 1 and Vector 2 may be copied to region 330-1, as previously described in conjunction with Figure 2B After copying Vector 1 and Vector 2 into region 330-1, Vector 3 through Vector K can be written in parallel in memory tile 220-1 and region 330-1, as shown in FIG. Figure 2B and 3B As shown in , until Vector 3 to Vector K are written into area 330 - 1 .

[0062] For example, Vector 3 to Vector K may be written in locations 225-3 to 225-K and locations 335-3 to 335-K in parallel, respectively, until the writing of Vector 3 to Vector K in locations 335-3 to 335-K is completed. While continuing to write Vector 3 to Vector K in tile 220-1 and / or before completing writing Vector 3 to Vector K in memory tile 220-1 so that memory tile 220-1 is completely filled with data vectors, Vector 3 to Vector K in region 330-1 may be queried, as shown in FIG. Figure 2BIn response to memory tile 220-1 being completely filled with data vectors, controller 104 may invalidate the mapping between the address of tile 220-1 and address range 332-1 and / or may cause buffer CAM 310 to remove Vector 3 through Vector K from region 330-1.

[0063] Figure 4 4 is a simplified block diagram of a CAM 440 according to several embodiments of the present disclosure. CAM 440 can be configured as a primary CAM or a buffer CAM, for example. CAM 440 includes a CAM array 442 that can be coupled to an input data register 444. CAM array 442 can be, for example, CAM array 218, where CAM 440 is a primary CAM, or CAM array 331, where CAM 440 is a buffer CAM. CAM array 442 can store data (e.g., in the form of stored data vectors), and input data register 444 can receive input data vectors from controller 404 (e.g., controller 104) for comparison with stored data vectors. For example, the stored data vectors can be queried using the input data vectors. In the example where CAM 440 is a buffer CAM, CAM array 222 can be an SRAM memory array having SRAM cells. In the example where CAM 440 is a primary CAM, CAM array 442 can be a nonvolatile memory array having nonvolatile memory cells, such as resistance variable memory cells (e.g., arranged in a cross-point manner).

[0064] The CAM 440 may have a control circuit system 445 (e.g., a control state machine) that can direct the internal operation of the CAM 440 and can manage the CAM array 442. The control circuit system 445 can receive control signals from the controller 404 through the control interface 446. For example, the controller 404 can cause the control circuit system 445 to query the data vector stored in the CAM array 442 using the input data vector by causing the control circuit system 445 to compare the input data vector with the data vector stored in the CAM array 442. The controller 404 can also cause the control circuit system 445 to write the data vector to the CAM array 442. In some examples, the controller 445 may include the control circuit system 445 previously described in conjunction with Figure 1A Described matching verification circuit system.

[0065] The detector 449 can be coupled to the CAM array 442 via lines 450-1 through 450-K (e.g., match lines). For example, each of the respective lines 450-1 through 450-K can correspond to a respective data vector stored in the CAM array 442. For example, in an example where the CAM 440 is a primary CAM, the respective lines 450-1 through 450-K can correspond to respective data vectors of a tile, such as Vector 1 through Vector K of tile 220-1, respectively. In an example where the CAM 440 is a buffer CAM, the respective lines 450-1 through 450-K can correspond to respective data vectors in a region in the buffer CAM, such as Vector 1 through Vector K in region 330-1, respectively.

[0066] The detector 449 may detect whether the stored data vectors match the input data vector and may generate, for each respective stored data vector, a respective result (eg, a data bit) indicating whether the respective stored data vector matches the input data vector.

[0067] For example, Figure 4 As shown in , detector 449 may generate a data bit having a value of logic one (1) to indicate that the corresponding stored data vector matches the input data vector, and a data bit having a value of logic zero (0) to indicate that the corresponding stored data vector mismatches (e.g., does not match) the input data vector. However, the present disclosure is not limited in this regard, and the roles of logic one and logic zero may be reversed. In some examples, the vector comparison results may be combined to form a result (e.g., output) vector 452 having a component (e.g., 1 or 0) corresponding to each stored vector.

[0068] Detector 449 may be configured to associate (e.g., relate) the address of each corresponding stored vector with a corresponding result of result vector 452 (e.g., of its corresponding component). In some examples, detector 449 may have a sense amplifier coupled to each of lines 450-1 through 450-K (e.g., at Figure 4 4. For example, each sense amplifier may be configured to generate a logic 1 or 0 depending on whether the sense amplifier detects a match or a mismatch. Result vector 452 and the associated addresses of the components may be sent to input / output (I / O) buffer 454 for output to controller 404 via interface 455.

[0069] In instances where CAM 440 is a buffer CAM, result vector 452 may be output to controller 404 in response to the query being to the buffer CAM rather than the primary CAM. Note that the addresses associated with the components of result vector 452 may be mapped to the addresses of the data vectors in the primary CAM. In some instances, controller 404 may associate the corresponding logical addresses with the addresses of the data vectors in the primary CAM and may output the result vector to a host, such as host 103.

[0070] Figure 5 FIG. 1 shows a portion of a nonvolatile CAM according to several embodiments of the present disclosure. For example, Figure 5 A portion of a non-volatile CAM array of a primary CAM is shown, such as memory tile 520, which may be tile 220. Memory tile 520 may have a number of data planes, such as data vector planes 560-1 through 560-J.

[0071] Each data vector plane 560 may have word lines 562-1 through 562-8. Each of word lines 562-1 through 562-8 may span bit lines 563-1 through 563-8. Thus, each data vector plane 560 may be a cross-point data vector plane. At each intersection of a word line and a bit line, a memory cell 564, such as a resistance variable memory cell, may be present. In some examples, a group of memory cells (e.g., a column of memory cells) commonly coupled to a bit line 563 may store a data vector. For example, a column of memory cells commonly coupled to bit lines 563-1 through 563-8 may store data vectors 565-1 through 565-8, respectively. Although eight bit lines and eight word lines are shown, any number of bit lines and word lines may be present.

[0072] The bit lines 563-1 to 563-8 in each vector plane 560 can be coupled to sense amplifiers 567-1 to 567-8, respectively. Sense amplifiers 567-1 to 567-8 can generate a comparison result of the input data vector 568 with the stored vectors 565-1 to 565-8, respectively. For example, the result can be a component of result vector 569. In some examples, the stored data vectors in the tile can be compared with the input data vector 466 for one plane at a time (e.g., on a plane-by-plane basis).

[0073] Figure 6 1 shows data query stored in the non-volatile main CAM according to several embodiments of the present disclosure. For example, the stored data is queried with the input data by comparing the input data with the stored data. For example, in Figure 6, an input data vector 668 is compared in parallel with data vectors 665-1 through 665-8 in a vector plane 660 of the primary CAM (e.g., which may be a memory tile). For example, the input data vector 668 may have component data (e.g., bit) values 00110011 corresponding to bits Bit1 through Bit8, respectively.

[0074] Vector plane 660 may have word lines 662-1 to 662-8. Each of word lines 662-1 to 662-8 may cross bit lines 663-1 to 663-8. At each intersection of a word line and a bit line, there may be a memory cell 664, such as a resistance variable memory cell. Figure 6 Eight bit lines and eight word lines are shown in the example of FIG, but embodiments are not limited to a particular number of word lines and / or bit lines.

[0075] Data vectors 665-1 through 665-8 can be stored in columns of memory cells commonly coupled to bit lines 663-1 through 663-8, respectively.For example, memory cells 664-1 through 664-8 in each respective column can be coupled to word lines 662-1 through 662-8, respectively. In this example, data vector 665-1 (01111111) is stored in a cell coupled to bit line 663-1, data vector 665-2 (11110111) is stored in a cell coupled to bit line 663-2, data vector 665-3 (11111111) is stored in a cell coupled to bit line 663-3, data vector 665-4 (11111101) is stored in a cell coupled to bit line 663-4, data vector 665-5 (00110011) is stored in a cell coupled to bit line 663-5, data vector 665-6 (00000000) is stored in a cell coupled to bit line 663-6, data vector 665-7 (11111110) is stored in a cell coupled to bit line 663-7, and data vector 665-8 (00000000) is stored in a cell coupled to bit line 665-8. It should be noted that the corresponding data values (eg, components) of each of the corresponding data vectors 665-1 through 665-8 are stored in memory cells 664-1 through 664-8, respectively.

[0076] Bit lines 663-1 through 663-8 may be coupled to sense amplifiers 667-1 through 667-8, respectively. Sense amplifiers 667-1 through 667-8 may generate a comparison result of input data vector 668 with stored vectors 665-1 through 665-8, respectively. For example, the result may be a component of result vector 669 (00001000).

[0077] Bits 1 through 8 of input data vector 668 can be compared with data stored in memory cells 664-1 through 664-8, respectively, coupled to each of data lines 663-1 through 663-8. A bit value of logic 0 can be compared with the data stored in memory cell 664 by applying a voltage difference (e.g., demarcation voltage VDM1) across the memory cells. A bit value of logic 1 can be compared with the data stored in memory cell 664 by applying a demarcation voltage VDM2 across the memory cells.

[0078] For example, VDM1 may correspond to an input bit value of logic 0, and VDM2 may correspond to an input bit value of logic 1. In some examples, the demarcation voltage may be a voltage applied to a bit line coupled to a memory cell minus a voltage applied to a word line coupled to the memory cell. Note that in this example, VDM1 and VDM2 have opposite polarities, with VDM1 having a negative polarity and VDM2 having a positive polarity. However, the present disclosure is not limited thereto.

[0079] In some examples, memory cell 664 can undergo a switching event, such as a threshold event (e.g., a turnaround event), in response to application of VDM1 across memory cell 664, or a switching event in response to application of VDM2 across memory cell 664. For example, memory cell 664 can switch from one conductivity state, such as a low conductivity state (e.g., a high resistance state), to another conductivity state, such as a high conductivity state (e.g., a low resistance state).

[0080] In some examples, a memory cell that experiences a switching event in response to a demarcation voltage can be considered to store a data value that does not match the input data value corresponding to the demarcation voltage. For example, a memory cell storing a logic 1 can experience a switching event in response to application of VDM1 across the memory cell (e.g., corresponding to an input logic 0), and a memory cell storing a logic 0 can experience a switching event in response to application of VDM2 across the memory cell (e.g., corresponding to an input logic 1).

[0081] In this example, memory cells that do not experience a switching event in response to the demarcation voltage can be considered to store data values that match the input data value corresponding to the demarcation voltage. For example, a memory cell storing a logic 0 may not experience a switching event in response to VDM1 being applied across the memory cell, and a memory cell storing a logic 1 may not experience a switching event in response to VDM2 being applied across the memory cell. However, it should be noted that in other examples, a switching event may indicate a match, and the absence of a switching event may indicate a mismatch.

[0082] It should be noted that if the data stored in at least one memory cell of data vector 665 does not match the corresponding bit of input data vector 668, then data vector 665 can be considered to not match input data vector 668. Sense amplifier 667 can sense a switching event experienced by one or more memory cells corresponding to data vector 665 by sensing a change in current, which can be reflected in the output voltage of the sense amplifier. Thus, the sense amplifier can sense a mismatch between a data vector coupled to the sense amplifier and input data vector 668 by sensing the switching event. For example, the sense amplifier can generate (e.g., output) a logic 0 in response to sensing the switching event, indicating a mismatch between the data vector coupled to the sense amplifier and input data vector 668. The sense amplifier can generate a logic 1 in response to not sensing the switching event, indicating a match between the data vector coupled to the sense amplifier and input data vector 668.

[0083] In some examples, during a first time period corresponding to a first comparison phase, a portion of the input data vector 668 can be compared with corresponding portions of the data vectors 665-1 to 665-8, and during a second time period corresponding to a second comparison phase, the remaining portion of the input data vector 668 can be compared with corresponding portions of the data vectors 665-1 to 665-8. During the first phase, Bit 1, Bit 2, Bit 5, and Bit 6 of the input data vector 668 having a logic 0 can be compared with the data values stored in the memory cells 664-1, 664-2, 664-5, and 664-6 of each of the data vectors 665-1 to 665-8, respectively, by applying VDM1 across those memory cells while applying, for example, zero volts across the remaining memory cells 664-3, 664-4, 664-7, and 664-8.

[0084] During the second phase, Bit 3, Bit 4, Bit 7, and Bit 8 of the input data vector 668 having a logic 1 may be compared with the data values stored in the memory cells 664-3, 664-4, 664-7, and 664-8 of each of the data vectors 665-1 to 665-8, respectively, by applying VDM2 across those memory cells while applying, for example, zero volts across the remaining memory cells 664-1, 664-2, 664-5, and 664-6. However, the present disclosure is not limited thereto, and VDM1 and VBM2 may be applied in parallel (e.g., during the same phase).

[0085] In some examples, VDM1 may be replaced with a write voltage that writes (e.g., programs) the memory cell to a resistance state corresponding to a logic 0. For example, the write voltage may be greater than VDM1 in a negative sense. In some examples, VDM2 may be replaced with a write voltage that writes the memory cell to a resistance state corresponding to a logic 1. For example, the write voltage may be greater than VDM2 in a positive sense. In some examples, a write voltage that writes a logic 0 may be applied during the first phase, and a write voltage that writes a logic 1 may be applied during the second phase. However, the present disclosure is not limited thereto, and the corresponding write voltages may be applied in parallel (e.g., during the same phase).

[0086] The CAM array of the primary CAM may include a two-dimensional (2D) and / or three-dimensional (3D) array structure, such as a cross-point array structure. Memory cells (e.g., memory cells 564 and 664) may include, for example, various types of resistance variable storage elements and / or switching elements. For example, the cells may be phase change random access memory (PCRAM) cells or resistive random access memory (RRAM) cells.

[0087] As used herein, a storage element refers to the programmable portion of a memory cell. For example, a primary CAM may be a 3D cross-point device, whose cells may include a "stacked" structure in which a storage element is coupled in series with a switching element, and which may be referred to herein as a 3D phase change material and switch (PCMS) device. A 3D PCMS cell may include, for example, a two-terminal chalcogenide-based storage element coupled in series with a two-terminal chalcogenide-based switching element (e.g., an oscillatory threshold switch (OTS)). In some examples, the memory cell may be a select-by-self memory (SSM) cell, in which a single material may serve as both a switching element and a storage element. The SSM cell may include a chalcogenide alloy; however, embodiments are not limited thereto.

[0088] As non-limiting examples, memory cells of the disclosed nonvolatile CAM may include phase-change materials (e.g., phase-change chalcogenide alloys), such as indium (In)-antimony (Sb)-tellurium (Te) (IST) materials (e.g., In2Sb2Te5, In1Sb2Te4, In1Sb4Te7, etc.) or germanium (Ge)-antimony (Sb)-tellurium (Te) (GST) materials (e.g., Ge2Sb2Te5, Ge1Sb2Te4, Ge1Sb4Te7, etc.). As used herein, hyphenated chemical composition symbols indicate elements included in a particular mixture or compound and are intended to represent all stoichiometric amounts involving the indicated elements. Other memory cell materials may include GeTe, In-Se, Sb2Te3, GaSb, InSb, As-Te, Al-Te, GE-Sb-Te, Te-Ge-As, In-Sb-T e. Te-Sn-Se, Ge-Se-Ga, Bi-Se-Sb, Ga-Se-Te, Sn-Sb-Te, In-Sb-Ge, Te-Ge-Sb-S, Te-Ge-Sn-O , Te-Ge-Sn-Au, Pd-Te-Ge-Sn, In-Se-Ti-Co, Ge-Sb-Te-Pd, Ge-Sb-Te-Co, Sb-Te-Bi-Se, Ag-I n-Sb-Te, Ge-Sb-Se-Te, Ge-Sn-Sb-Te, Ge-Te-Sn-Ni, Ge-Te-Sn-Pd and Ge-Te-Sn-Pt, as well as various other materials.

[0089] In the preceding detailed description of the present disclosure, reference is made to the accompanying drawings which form a part hereof and in which are shown by way of illustration several embodiments of how the present disclosure may be practiced. These embodiments are described in sufficient detail to enable one skilled in the art to practice the embodiments of the present disclosure, and it is to be understood that other embodiments may be utilized and that process, electrical and / or structural changes may be made without departing from the scope of the present disclosure.

[0090] As used herein, "several" or "a certain number" of something may refer to one or more of such things. For example, several or a certain number of memory cells may refer to one or more memory cells. "Multiple" something means two or more. As used herein, the term "coupled" may include electrically coupling, directly coupling, and / or directly connecting (e.g., by direct physical contact) without intervening elements, or indirectly coupling and / or connecting with intervening elements, or wirelessly coupling. The term coupled may further include two or more elements that cooperate or interact with each other (e.g., in a causal relationship). As used herein, multiple actions performed simultaneously refer to actions that overlap at least partially within a specific time period.

[0091] Although specific embodiments have been illustrated and described herein, it will be understood by those skilled in the art that arrangements calculated to achieve the same results may be substituted for the specific embodiments shown. The present disclosure is intended to cover adaptations or variations of several embodiments of the present disclosure. It should be understood that the above description is by way of illustration and not by way of limitation. Upon reviewing the above description, the combination of the above embodiments and other embodiments not specifically described herein will be apparent to those skilled in the art. The scope of several embodiments of the present disclosure includes other applications in which the above structures and methods are used. Therefore, the scope of several embodiments of the present disclosure should be determined with reference to the appended claims together with the full scope of equivalents to which such claims are entitled.

[0092] In the foregoing Detailed Description, some features are grouped together in a single embodiment for the purpose of streamlining the disclosure. This approach to the disclosure should not be interpreted as reflecting an intention that the disclosed embodiments of the disclosure necessarily utilize more features than are expressly recited in each claim. Rather, as the appended claims reflect, the inventive subject matter lies in less than all features of a single disclosed embodiment. Therefore, the appended claims are hereby incorporated into the Detailed Description, with each claim standing on its own as a separate embodiment.

Claims

1. An apparatus for performing write and query operations in a content addressable memory system having a content addressable memory buffer, comprising: Controller (104, 404); a first content addressable memory (106-1, 106-2, 106-3, 106-4, 106-5, 106-6, 106-7, 106-8, 206, 440) coupled to the controller, wherein the first content addressable memory comprises non-volatile memory cells; as well as a second content addressable memory (110-1, 110-2, 310, 440) coupled to the controller, wherein the second content addressable memory includes volatile memory cells; The controller is configured to: causing the first content addressable memory to write data (565-1, 565-2, 565-3, 565-4, 565-5, 565-6, 565-7, 565-8, 568, 665-1, 665-2, 665-3, 665-4, 665-5, 665-6, 665-7, 665-8, 668) into the first content addressable memory; causing the second content addressable memory to write the data into the second content addressable memory, wherein the first and second content addressable memories write the data into the first and second content addressable memories in parallel before the second content addressable memory finishes writing the data into the second content addressable memory; as well as When the first content addressable memory continues to write the data in the first content addressable memory, the second content addressable memory is enabled to query the data written in the second content addressable memory.

2. The apparatus of claim 1 , wherein the controller is configured to: causing the first content addressable memory to write the data into memory tiles (220-1, 220-2, ..., 220-M) of the first content addressable memory; causing the second content addressable memory to write the data into an area (330-1, 330-2, 330-3, 330-4) in the second content addressable memory; and Mapping the locations of the memory tiles (225-1, 225-2, 225-3, ..., 225-K, 335-1, 335-2, 335-3, ..., 335-4) in the first content-addressable memory to the locations of the regions (225-1, 225-2, 225-3, ..., 225-K, 335-1, 335-2, 335-3, ..., 335-4) in the second content-addressable memory. 3 . The apparatus of claim 2 , wherein the controller is configured to invalidate a mapping of the location of the memory tile to the location of the region in response to determining that the memory tile is full of data. 4 . The apparatus of claim 2 , wherein the controller is configured to cause the second content addressable memory to remove the data from the region in response to determining that the memory tile is full of data.

5. The apparatus according to any one of claims 1 to 4, wherein the second content addressable memory is configured to query the data written in the second content addressable memory by comparing input data with the data written in the second content addressable memory.

6. The apparatus according to any one of claims 1 to 4, wherein The first content addressable memory is a nonvolatile content addressable memory configured to write the data into a resistance variable memory cell (564, 664-1, 664-2, 664-3, 664-4, 664-5, 664-6, 664-7, 664-8) in the first content addressable memory; and The second content addressable memory is a volatile content addressable memory configured to write the data into static random access memory cells (564, 664-1, 664-2, 664-3, 664-4, 664-5, 664-6, 664-7, 664-8) in the second content addressable memory.

7. The apparatus according to any one of claims 1 to 4, wherein the controller is configured to: When the data is being written to the first content addressable memory, mapping a location (225-1, 225-2, 225-3, ..., 225-K, 335-1, 335-2, 335-3, ..., 335-4) of the data in the first content addressable memory to a location (225-1, 225-2, 225-3, ..., 225-K, 335-1, 335-2, 335-3, ..., 335-4) of the data in the second content addressable memory; and The mapping is invalidated in response to the first content addressable memory completing writing of the data in the first content addressable memory.

8. The apparatus of any one of claims 1 to 4, wherein the controller is configured to cause the second content addressable memory to remove the data from the second content addressable memory in response to the first content addressable memory completing writing of the data in the first content addressable memory.

9. An apparatus for performing write and query operations in a content addressable memory system having a content addressable memory buffer, comprising: Controller (104, 404); a primary content addressable memory (106-1, 106-2, 106-3, 106-4, 106-5, 106-6, 106-7, 106-8, 206, 440) coupled to the controller, wherein the primary content addressable memory comprises non-volatile memory cells; as well as a buffer content addressable memory (110-1, 110-2, 310, 440) coupled to the controller, wherein the buffer content addressable memory comprises volatile memory cells; The controller is configured to: causing the buffer content addressable memory to query the buffer content addressable memory instead of causing the primary content addressable memory to query partially filled memory tiles (220-1, 220-2, ..., 220-M) in the primary content addressable memory; while causing the buffer content addressable memory to query the buffer content addressable memory, causing the primary content addressable memory to query memory tiles (220-1, 220-2, ..., 220-M) in the primary content addressable memory that are completely populated with data (565-1, 565-2, 565-3, 565-4, 565-5, 565-6, 565-7, 565-8, 568, 665-1, 665-2, 665-3, 665-4, 665-5, 665-6, 665-7, 665-8, 668) rather than causing the primary content addressable memory to query memory tiles (220-1, 220-2, ..., 220-M) that are partially populated; as well as In response to causing the primary content addressable memory to write-enable the partially filled memory tile, causing the primary content addressable memory to write a second data vector (565-1, 565-2, 565-3, 565-4, 565-5, 565-6, 565-7, 565-8, 568, 665-1, 665-2, 665-K) in an empty location (225-1, 225-2, 225-3, . . . , 225-K, 335-1, 335-2, 335-3, . . . , 335-4) in the partially filled memory tile. -3, 665-4, 665-5, 665-6, 665-7, 665-8, 668), while simultaneously causing the first data vector (565-1, 565-2, 565-3, 565-4, 565-5, 565-6, 565-7, 565-8, 568, 665-1, 665-2, 665-3, 665-4, 665-5, 665-6, 665-7, 665-8, 668) in the partially filled memory tile to be copied from the partially filled memory tile to the buffer content addressable memory.

10. The apparatus according to claim 9, wherein: The controller is configured to: causing the buffer content addressable memory to write the second data vector in the buffer content addressable memory while the primary content addressable memory is writing the second data vector in the partially filled memory tile; as well as The buffer content addressable memory is caused to query the buffer content addressable memory for the first and second data vectors while the primary content addressable memory continues to write the second data vector in the partially filled memory tile.

11. The apparatus of claim 10 , wherein the controller is configured to manage a data structure comprising entries ( 114 ) that map addresses of locations of the partially filled memory tiles ( 225 - 1 , 225 - 2, 225 - 3, ..., 225 -K, 335 - 1 , 335 - 2, 335 - 3, ..., 335 - 4) in the primary content addressable memory to address ranges ( 332 - 1 , 332 - 2, 332 - 3, 332 - 4) in the buffer content addressable memory corresponding to the first and second data vectors.

12. The apparatus of claim 10 , wherein the primary content addressable memory is configured to store the first data vector (565-1, 565-2, 565-3, 565-4, 565-5, 565-6, 565-7, 565-8, 568, 665-1, 665-2, 665-3, 665-4, 665-5, 665-6, 665-7, 565-8, 568, 665-1, 665-2, 665-3, 665-4, 665-5, 665-6, 665-7 -7, 665-8, 668) replaces the first data vector (565-1, 565-2, 565-3, 565-4, 565-5, 565-6, 565-7, 565-8, 568, 665-1, 665-2, 665-3, 665-4, 665-5, 665-6, 665-7, 665-8, 668) in the primary content addressable memory: writing the second data vector into an empty location (225-1, 225-2, 225-3, ..., 225-K, 335-1, 335-2, 335-3, ..., 335-4) of the primary content addressable memory; and The locations (225-1, 225-2, 225-3, ..., 225-K, 335-1, 335-2, 335-3, ..., 335-4) of the first data vector in the primary content addressable memory are mapped to the free locations.

13. A method for performing write and query operations in a content addressable memory system having a content addressable memory buffer, comprising: writing data vectors (225-1, 225-2, 225-3, ..., 225-K, 335-1, 335-2, 335-3, ..., 335-4) in memory tiles (220-1, 220-2, ..., 220-M) of a first content addressable memory (106-1, 106-2, 106-3, 106-4, 106-5, 106-6, 106-7, 106-8, 206, 440), wherein the first content addressable memory comprises non-volatile memory cells; writing the data vector in a region (330-1, 330-2, 330-3, 330-4) of a second content addressable memory (110-1, 110-2, 310, 440) corresponding to the memory tile, wherein the second content addressable memory includes volatile memory cells; as well as In response to determining that the memory tile is not full with previously written data vectors, querying the region instead of the memory tile; Wherein writing the data vector in the memory tile and in the region comprises writing the data vector in the memory tile and in the region in parallel before completing writing the data vector in the region.

14. The method according to claim 13, wherein: Querying the region instead of the memory tile includes querying the data vector in the region when writing the data vector in the memory tile after completing writing the data vector in the region.

15. The method of claim 13, wherein querying the region instead of the memory tile comprises: In response to determining that additional memory tiles (220-1, 220-2, ..., 220-M) in the first content addressable memory are full of previously written data vectors, the additional memory tiles are queried concurrently with the region instead of the memory tiles.

16. The method of any one of claims 13 to 15, further comprising copying previously written data vectors (565-1, 565-2, 565-3, 565-4, 565-5, 565-6, 565-7, 565-8, 568, 665-1, 665-2, 665-3, 665-4, 665-5, 665-6, 665-7, 665-8, 668) in the memory tile to the region before writing the data vector in the memory tile and in the region.

17. The method according to any one of claims 13 to 15, further comprising: comparing an input data vector (568, 668) with additional data vectors (565-1, 565-2, 565-3, 565-4, 565-5, 565-6, 565-7, 565-8, 665-1, 665-2, 665-3, 665-4, 665-5, 665-6, 665-7, 665-8) stored in the first content addressable memory or the second content addressable memory; and Whether a match between the input data vector and the additional data vector is valid is determined by match verification circuitry.

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