Method for manufacturing ohmic contact and electronic component having ohmic contact

Abstract

The invention relates to a method for manufacturing an ohmic contact for an electronic component, wherein a layer (3) composed of a semiconductor is applied indirectly or directly to a substrate (1), characterized in that the surface to be contacted of the applied semiconductor layer (3) is wet-chemically etched, the wet-chemically etched surface is rinsed with radicals, and a conductor (8) or a semiconductor (7) is applied to the surface rinsed with radicals. The invention also relates to an electronic component having a plurality of semiconductor layers (2, 3, 4) on a substrate (1), having a top layer (5) on one or more of the semiconductor layers (2, 3, 4) applied to the substrate (1), wherein the top layer (5) is composed of a non-conductive dielectric and has a channel (6) leading to the semiconductor layer (3) through the top layer; adjacent semiconductor layers (2, 3, 4) are composed of different II-VI semiconductors; the channel (6) is at least partially filled with a II-VI semiconductor (7), and a metal contact (8) is applied to the II-VI semiconductor (7), and the contact extends to the outside of the top layer (5) or protrudes outward relative to the top layer (5).

Description

Technical Field

[0001] The present invention relates to a method for manufacturing an ohmic contact on an electronic component. The present invention relates to an electronic component with an ohmic contact for a buried semiconductor. Background Art

[0002] An ohmic contact is a connection with a very small resistance between a metal and a semiconductor.

[0003] A buried semiconductor is a semiconductor located inside an electronic component. It is usually a layer composed of a semiconductor and is sandwiched between two other layers.

[0004] A local ohmic contact for a buried semiconductor is an electrical conductor composed of a metal or a semiconductor with an ohmic contact, which passes through a hole in the electronic component and contacts the buried semiconductor.

[0005] To manufacture an electronic component, one or more layers can be applied (deposited) on a substrate. One or more layers can be composed of a semiconductor. One or more of these applied semiconductor layers can be composed of a doped semiconductor, especially an n-doped semiconductor. For example, the semiconductor can be doped with chlorine or iodine. Fluorine doping is also possible, but in principle it is less suitable compared to chlorine and iodine. Phosphorus doping is also possible, but it is less suitable in many cases. An electrically insulating top layer can be applied on one or more semiconductor layers applied on the substrate. In the sense of the present invention, one or more semiconductor layers are then buried semiconductor layers. To manufacture an ohmic contact for the buried semiconductor layer, a hole can be created, which passes through the top layer to the buried semiconductor layer. The hole can be manufactured by etching. After the hole is created, the hole can be filled with a metal to create a local ohmic contact, which can be electrically contacted above the top layer. Thus, for example, an additional gate electrode required for a unipolar element (such as a field effect transistor or an electron spin qubit) can be subsequently provided for the electronic component.

[0006] In an electronic component comprising a substrate and / or layers of GaAs and AlGaAs or layers of Si and SiGe, the metal can be thermally alloyed into the created hole in the top layer to contact the buried semiconductor and manufacture a local ohmic contact. Before alloying in the metal by ion implantation, additional dopants can be locally introduced to create a suitably good ohmic contact.

[0007] Known methods for manufacturing local ohmic contacts are not applicable to all compound semiconductors. For example, the II-VI compound semiconductor ZnSe is not resistant to high temperatures, while high temperatures are necessary for effective alloying of the metal. Ion implantation severely damages the crystal structure of such compound semiconductors, greatly reducing the conductivity. Thus, it is impossible to produce a connection with a very small resistance between the metal and the semiconductor. The problem mainly occurs with II-VI compound semiconductors. However, III-V compound semiconductors are also affected by this problem.

[0008] The ability to operate electronic components at low temperatures may be of interest. This may be necessary, for example, for the electron spin qubits of a quantum computer. Summary of the Invention

[0009] The object of the present invention is to be able to fabricate ohmic contacts on electronic components, in particular local ohmic contacts on buried III-V compound semiconductors or II-VI compound semiconductors of electronic components. Preferably, this is also possible for II-VI compound semiconductors that can be doped with chlorine. The ohmic contact should preferably also enable the operation of the associated electronic components at low temperatures.

[0010] To solve this problem, a method for fabricating an ohmic contact of an electronic component is provided. To fabricate an electronic component, a layer composed of a semiconductor, i.e., a semiconductor layer, is applied to a substrate (substrate) either indirectly or directly. If the semiconductor layer is applied directly to the substrate, there are no other layers between the semiconductor layer and the substrate. If the semiconductor layer is applied indirectly to the substrate, one or more layers are present between the substrate and the semiconductor layer.

[0011] The surface of the semiconductor to be contacted is wet-chemically etched. The wet-chemically etched surface is rinsed with radicals. A conductor or semiconductor is applied to the surface rinsed with radicals. In this way, a connection to the semiconductor can be produced that can be easily damaged by production processes that normally cannot produce connections with small resistances. Surprisingly, it has been found that these problems can be solved by chemical etching and subsequent radical rinsing, even if the surface has previously been treated in a destructive manner (such as ion etching).

[0012] A radical is an atom or molecule with at least one unpaired valence electron. Rinsing with hydrogen radicals has proven to be effective. These have proven to be appropriate reactions.

[0013] Wet-chemical etching and subsequent radical rinsing have proven to be decisive steps for contacting sensitive II-VI and III-V compound semiconductors, enabling almost perfect linear current-voltage characteristics and extremely low contact resistances at room temperature and very low temperatures.

[0014] Preferably, the rinsing is carried out in the absence of oxygen. Preferably, the rinsing is carried out in ultra-high vacuum and thus also in the absence of oxygen to obtain a further improved effect. This embodiment is particularly advantageous for compound semiconductors that can be rapidly oxidized in air. ZnSe is an example of a compound semiconductor that can be rapidly oxidized in air. By oxidation, a non-conductive surface oxide layer that forms a barrier to current transport can be formed. Thus, connections with small resistances can be prevented.

[0015] The effect can be further improved by rinsing at an elevated temperature, for example, from 100 °C to 200 °C.

[0016] The rinsing is preferably carried out for several minutes, for example, 2 - 10 minutes, to achieve the desired effect.

[0017] In wet chemical etching, the chemical bonds of the material to be processed are broken by the etching medium and converted into soluble components. The commonly used etching media are K2Cr2O7 + HBr + H2O or NH3 + H2O2 + H2O or K2Cr2O7 + H2SO4 + H2O.

[0018] Preferably, the wet chemical etching is carried out for several seconds, for example, 2 - 10 seconds, so as to be able to contact the compound semiconductor in a suitable manner.

[0019] Semiconductors prepared for making ohmic contacts by wet chemical etching and subsequent radical rinsing can be II - VI compound semiconductors or III - V compound semiconductors. II - VI compound semiconductors that can be doped with chlorine benefit most from the advantages of this method. Examples of such II - VI compound semiconductors are (Zn, Mg)Se, (Zn, Cd)Se, (Zn, Mg)SSe, (ZnCd)SSe, ZnSe, CdSe or ZnSSe.

[0020] The metal of the compound semiconductor is preferably selected from zinc (Zn), cadmium (Cd), magnesium (Mg) and / or beryllium (Be). The non - metal of the compound semiconductor is preferably selected from selenium (Se) and / or sulfur (S).

[0021] To fabricate an ohmic contact for a buried semiconductor, a manufacturing method may include the following steps:

[0022] • Applying one or more semiconductor layers onto a substrate;

[0023] • Applying a non - conductive top layer to the one or more applied semiconductor layers, wherein the top layer may consist of a non - conductive dielectric;

[0024] • Creating holes through the top layer to the semiconductor layer;

[0025] • As described above, wet chemical etching the surface of the semiconductor layer accessible through the holes;

[0026] • As described above, rinsing the surface of the wet chemically etched with radicals;

[0027] • Applying a doped semiconductor to the surface and rinsing with radicals; and

[0028] • Applying a metal (such as aluminum) to the applied doped semiconductor.

[0029] For example, an electronic component manufactured in this way can subsequently be equipped with a gate electrode.

[0030] Holes created in the top layer of the top layer may have been partially or completely filled with a doped semiconductor. The holes created in the top layer may have passed through one or more further layers below the top layer to reach the desired semiconductor layer. One or more further layers can be semiconductor layers, i.e., composed of semiconductors.

[0031] Multiple holes can be created in the top layer to fabricate multiple local ohmic contacts.

[0032] Filling the holes with a doped semiconductor is preferably carried out by molecular beam epitaxy. This enables selective growth. Thus, the growth can be restricted to the hole region. This application of molecular beam epitaxy is called a regrowth process. This process simplifies production. Additional steps, i.e., etching the doped semiconductor between multiple holes, are omitted. However, this does not exclude that in one embodiment of the invention, a subsequently applied metal layer is etched away between the holes or between the fabricated ohmic contacts. Advantageously, the subsequently applied metal layer between the holes or between the fabricated ohmic contacts is etched away, so that in this step, then one or more additional gate electrodes are also fabricated independently of the ohmic contacts.

[0033] To manufacture an electronic component (which can be a unipolar component in a finished state and can also be used at low temperatures), one or more semiconductor layers can be applied to a substrate in an ultra-high vacuum. Subsequently, a top layer can be applied to the one or more semiconductor layers deposited in the ultra-high vacuum. During the application process, the surface of the layer is not exposed to the atmosphere in this configuration, and thus, the surface to which the top layer is to be applied is also not exposed to the atmosphere.

[0034] Adjacent semiconductor layers are composed of different semiconductor materials and / or are doped at least in different ways.

[0035] Thus, for example, a first semiconductor layer can be applied to the substrate. Subsequently, a second semiconductor layer can be applied to the first semiconductor layer. Subsequently, a third semiconductor layer can be applied to the second semiconductor layer. Subsequently, a top layer can be applied to the third semiconductor layer. However, more than three semiconductor layers can be applied before applying the top layer.

[0036] The first and / or the third applied semiconductor layer can be composed of (Zn, Mg)Se, (Zn, Cd)Se, Zn(S, Se), or (Zn, Mg)(S, Se). The second layer can be composed of ZnSe or CdSe. These materials are particularly suitable for producing unipolar components, which can also be used as qubits in a quantum computer at low temperatures. The second layer can be produced as a doped layer. However, this is not necessary.

[0037] The top layer can be composed of oxide ceramics. For example, the top layer is composed of alumina, silica, or hafnium oxide. However, the top layer can also be composed of another material, such as silicon nitride. These materials can serve as the best gate dielectrics for the production of unipolar elements, such as 2D or 3D field-effect transistors or electrostatically defined electron spin qubits. Therefore, the present invention also relates to unipolar elements of this type.

[0038] Generally speaking, non-conductive dielectrics are suitable as the top layer material for the production of unipolar elements.

[0039] The substrate can be composed of semiconductors. The substrate can be composed of III-V semiconductors or II-VI compound semiconductors so that a II-VI semiconductor layer can be appropriately produced on the substrate. Therefore, the substrate can be composed of GaAs, ZnSe, (In, Ga)As, InAs, (In, Ga)P, (In, Ga, Al)P, InAs, or InP.

[0040] Through wet chemical etching, especially using HF, holes can be created through the top layer. Alternatively, holes can be created through reactive ion etching, especially using CHF3 + O2.

[0041] If the holes are to continue into the underlying layer, it can be accomplished through reactive ion etching. This can generally be achieved through Cl2 + Ar, Cl2 + BCl3, or CH4 + H2 + Ar, for example, in the case of compound semiconductors composed of (Zn, Mg)Se, Zn(S, Se), CdSe, or ZnSe.

[0042] The dry etching process can severely damage the crystal structure of the compound semiconductor near the surface. However, the resulting problems can be eliminated through subsequent chemical wet etching and radical rinsing, so connections with small resistance can still be produced. The rinsing is carried out without oxygen, especially in cases where the corresponding semiconductor can be easily oxidized.

[0043] In order to create holes through the top layer by etching, an etching mask can be applied on the top layer. The top layer can be composed of photoresist, where the resist has holes. The resist with holes may be produced through optical lithography techniques.

[0044] After creating holes through the top layer by etching to the desired depth, the surface of the applied semiconductor to be contacted can be wet chemically etched as described above.

[0045] After the final etching, the etching mask can be removed. For technical reasons, it is now recommended to perform cleaning, such as using solvents like isopropyl alcohol. In particular, the surface of the applied semiconductor to be contacted, that is, the semiconductor layer provided for ohmic contact, should be cleaned subsequently.

[0046] To further improve the expected technical effects, it is advantageous to subject the components to a heat treatment after etching and preferably after cleaning. This can be carried out at a temperature between 100 °C and 200 °C. The heat treatment can last for several minutes, for example at least 15 minutes. The heat treatment can be terminated after at most 60 minutes, after which more favorable effects are generally not achievable. For example, a treatment time of about 30 minutes is sufficient.

[0047] To obtain a further improved technical effect, the heat treatment is preferably carried out in an ultra-high vacuum. In this way, adverse environmental effects can be appropriately avoided.

[0048] After the heat treatment, the component can be flushed with free radicals, especially hydrogen radicals, preferably for several minutes. This is preferably done in an ultra-high vacuum, particularly preferably in the ultra-high vacuum provided for the heat treatment. In particular, this can prevent the component to be produced from coming into contact with the atmosphere after the heat treatment and before flushing with free radicals.

[0049] Advantageously, after flushing with free radicals, the surface to be contacted of the semiconductor layer is treated with metal vapor. The metal vapor includes metals that are also present in the semiconductor. Thus, for example, if the semiconductor consists of ZnSe, the metal vapor includes zinc as the metal. Thus, in the case of ZnSe, the metal vapor is generated from a zinc source. The metal is thermally evaporated by this metal source. Thus, possible metal defects can be filled, thereby further improving the expected technical effects. The treatment with metal vapor is preferably carried out in an ultra-high vacuum, preferably in the ultra-high vacuum that has already been provided for the previous step. As mentioned before, contact with the atmosphere is prevented.

[0050] Finally, the holes can be filled completely or partially with a semiconductor. In principle, the holes are filled with a semiconductor that matches the semiconductor to be contacted. For example, if the layer to be contacted consists of ZnSe, the holes are preferably filled completely or partially with ZnSe. However, the doping of the two semiconductors may be different. Thus, the holes can be filled completely or partially with n-doped ZnSe to contact a layer made of undoped ZnSe.

[0051] The holes are preferably filled with a semiconductor at a temperature particularly suitable for growth, for example 200 - 400 °C. For example, a temperature of 300 °C is suitable for ZnSe. The filling of the holes is carried out in an ultra-high vacuum, preferably still in the ultra-high vacuum that has already been provided in the previous step, to further prevent contact with the atmosphere.

[0052] Once the holes are completely or partially filled with the semiconductor, the metal is finally applied to this semiconductor. For example, this is achieved by a metal chemical vapor deposition system. Preferably, this is again consistently carried out in the above-mentioned ultra-high vacuum in order to consistently prevent contact with the atmosphere. For example, the semiconductor produced by regrowth cannot be oxidized before the metal deposition.

[0053] Aluminum is particularly suitable as a metal. Titanium or magnesium is also very suitable.

[0054] In order for the subsequent steps to be carried out in situ in an ultra-high vacuum, the required equipment is coupled to each other through an ultra-high vacuum. Therefore, there is a chamber that can generate an ultra-high vacuum. The chamber includes a molecular beam epitaxy system for compound semiconductors, an evaporation system for metals (such as aluminum), an atomic layer deposition system, and a radical source (such as hydrogen radicals).

[0055] Comparative tests show that in the case of sensitive compound semiconductors, compared with the state of the art, ohmic contacts with quite good performance can be provided in this way.

[0056] The present invention also relates to an electronic component that can be manufactured according to this method. The electronic component has a plurality of semiconductor layers on a substrate, and has a top layer on one or more semiconductor layers applied to the substrate, where the top layer is composed of a non-conductive dielectric. The adjacent semiconductor layers are composed of different II-VI semiconductors, so there is a heterojunction. Since holes are created, there are channels leading to the semiconductor layers through the top layer. The channels are at least partially filled with II-VI semiconductors. A metal contact is applied to the II-VI semiconductor. This at least completely fills the channels and extends at least to the outside of the top layer. Generally, the metal contact protrudes outward relative to the top layer. The metal contact is particularly composed of aluminum.

[0057] The applied first and / or third semiconductor layers are preferably composed of (Zn, Mg)Se, Zn(S, Se), (Zn, Cd)Se, or (Zn, Mg)(S, Se). In particular, the second semiconductor layer is composed of ZnSe or CdSe. The top layer is preferably composed of alumina, silica, hafnium oxide, or silicon nitride. The substrate can be composed of GaAs, ZnSe, AlAs, InAs, GaP, AlP, or InP, or in a mixed form such as (In, Ga)As or (In, Al)GaP.

[0058] The present invention also relates to a unipolar component, which can be constructed as described above. The unipolar component can be a field effect transistor or a high mobility transistor. It can be an electron spin qubit component. Description of the Drawings

[0059] The present invention will be explained in more detail below by way of examples.

[0060] The drawings show:

[0061] Figure 1 : A layer structure with a ZnSe layer;

[0062] Figure 2 : A layer structure with holes;

[0063] Figure 3 : A layer structure with a semiconductor partially filling the holes;

[0064] Figure 4 : A layer structure with aluminum applied;

[0065] Figure 5 : A layer structure for completing local ohmic contacts;

[0066] Figure 6 : Measured current - voltage characteristics;

[0067] Figure 7 : Further structure of an electronic component with a buried semiconductor layer and local ohmic contacts. Detailed implementation

[0068] Figure 1 Figure 1 shows a gallium arsenide substrate 1 on which a buried first semiconductor layer 2 of (Zn, Mg)Se is deposited in ultra - high vacuum. On the first semiconductor layer 2, a buried second semiconductor layer 3 of ZnSe is deposited in situ in ultra - high vacuum. On the second semiconductor layer 3, a buried third semiconductor layer 4 of (Zn, Mg)Se is deposited in situ in ultra - high vacuum. On the third semiconductor layer 4, a top layer 5 of Al2O3 is deposited in situ in ultra - high vacuum. The deposition is completed, for example, by atomic layer deposition. These layers can be several tens of nanometers thick, for example, 20 nm thick.

[0069] In situ means Figure 1 the structure generated in Figure 1 is not removed from the ultra - high vacuum during its generation, so no harmful oxidation occurs.

[0070] After depositing the Al2O3 layer, the structure is removed from the ultra - high vacuum. By conventional optical lithography, a mesh mask with holes is defined in a previously applied photoresist, where ohmic contacts will be created later by regrowth. At the positions of the holes, the Al2O3 layer 5 is first opened using HF wet chemistry or CHF3 + O2 reactive ion etching. Then, the underlying (Zn, Mg)Se layer 4 and ZnSe layer 3 are opened using Cl2 + Ar reactive ion etching. Thus, as shown in Figure 2, downward etching is performed to create holes 6. The semiconductor layer 3 can be contacted through the holes 6. Figure 2 Figure 2 shows that downward etching is performed to create holes 6. The semiconductor layer 3 can be contacted through the holes 6.

[0071] After reactive ion etching, the resulting radiation damage is removed by wet chemical re-etching for about 5 seconds using a solution of K2Cr2O7 + HBr + H2O. The photoresist is then removed, the etched ZnSe semiconductor layer 3 is cleaned with isopropyl alcohol, and it is re-introduced into ultra-high vacuum for the regrowth process. The structure is then heated to 150 °C in ultra-high vacuum for 30 minutes and then rinsed with hydrogen radicals for 5 minutes. In this way, chemical residues from the etching and cleaning processes as well as possible oxide residues on the surface are removed. The etched layer is then slowly heated under zinc flux to a growth temperature suitable for the regrowth process at 300 °C. This helps to fill possible zinc vacancies remaining near the etched surface. Subsequently, a chlorine-doped ZnSe layer 7 is grown by molecular beam epitaxy (MBE) under standard growth parameters. This is as Figure 3 shown. Layer 7 should be at least thick enough to fill the holes up to the Al2O3 layer 5. Otherwise, the metal 8 on layer 7 will make lateral contact with layer 4 and thus contact the semiconductor (Zn,Mg)Se. This can be disadvantageous and should therefore be avoided.

[0072] Subsequently, the newly grown doped ZnSe layer 7 is coated in-situ with aluminum 8 as the ohmic contact material, as Figure 4 shown. The in-situ deposited aluminum layer 8 prevents the formation of an oxide between the chlorine-doped ZnSe layer 7 and the aluminum layer 8, thus enabling unhindered current transport through the aluminum-ZnSe interface.

[0073] In the last step, excess aluminum and ZnSe between the actual local contacts are removed using optical lithography and subsequent wet chemical etching until the structure shown in Figure 5 is obtained.

[0074] Figure 5 The layer thicknesses in

[0075] are only schematic. The two semiconductor layers 2 and 4 can be thicker than the semiconductor layer 3. The top layer 5 can be thinner than the semiconductor layer 3. Advantageously, the semiconductor layer 7 is at least thick enough to extend into the dielectric layer 5. Figure 6 shows a plot of the corresponding linear current-voltage characteristics measured for the structure shown in Figure 7 at room temperature RT (solid line) and 4K (dashed line). The distance between the two ohmic contacts of the element used for the measurement is 30 µm. The measured current in milliamperes is plotted against the applied voltage in volts. In addition to the excellent linearity of the current-voltage characteristics, Figure 7 the contact resistance and sheet resistance of the element shown in can also be determined by measurement. At room temperature, the contact resistance is and the sheet resistance is , the sheet resistance is .

[0076] Figure 7 The element shown includes a gallium arsenide substrate 1. There is an undoped ZnSe semiconductor layer 2 about 20 nm thick on the substrate. There is a chlorine-doped ZnSe semiconductor layer 3 about 800 nm thick on the ZnSe semiconductor layer 2. There is an Al2O3 dielectric layer 5 about 20 nm thick on the semiconductor layer 3. The channel formed through the hole to the semiconductor layer 2 has been completely filled with chlorine-doped ZnSe (i.e., ZnSe:Cl). Aluminum 8 about 120 nm thick is applied on the ZnSe:Cl filling 7.

Claims

1. A method for manufacturing an ohmic contact of an electronic component, wherein, A semiconductor layer (3) is applied indirectly or directly to a substrate (1), characterized in that a non-conductive top layer (5) is applied to the semiconductor layer (3), a channel (6) is created leading through the top layer (5) to the semiconductor layer (3), the surface of the applied semiconductor layer (3) to be contacted through the channel (6) is wet-chemically etched, the wet-chemically etched surface is rinsed with radicals, the surface rinsed with radicals is treated with a metal vapor, the metal vapor including a metal also present in the semiconductor layer (3), after the metal vapor treatment, the channel (6) is at least partially filled with a doped semiconductor (7), and a conductor (8) is applied on the doped semiconductor (7).

2. The method according to claim 1, wherein Rinsing is carried out using hydrogen radicals.

3. The method according to claim 1, wherein Rinsing is carried out in an ultra-high vacuum.

4. The method according to any one of claims 1 to 3, characterized in that Rinsing is carried out at a temperature between 100 °C and 200 °C.

5. The method according to any one of claims 1 to 3, characterized in that, Wet-chemical etching is carried out using K2Cr2O7 + HBr + H2O or NH3 + H2O2 + H2O or K2Cr2O7 + H2SO4 + H2O.

6. The method according to any one of claims 1-3, characterized in that Wet-chemical etching is carried out for 1 to 20 seconds.

7. The method according to any one of claims 1 to 3, characterized in that, The semiconductor layer (3) is a II-VI semiconductor or a III-V semiconductor.

8. The method according to claim 7, wherein The semiconductor layer (3) consists of (Zn, Mg)Se, Zn(S, Se), ZnSe, CdSe or (Zn, Mg)(S, Se).

9. The method according to any one of claims 1-3, characterized in that The metal of the semiconductor layer (3) is selected from zinc (Zn), cadmium (Cd), magnesium (Mg) or beryllium (Be).

10. The method according to any one of claims 1 to 3, characterized in that The non-metal of the semiconductor layer (3) is selected from selenium (Se) and / or sulfur (S).

11. The method according to any one of claims 1 to 3, characterized in that The semiconductor layer (3) is doped with chlorine (Cl).

12. An electronic component is prepared by using the method for manufacturing an ohmic contact for an electronic component according to any one of claims 1-11, the electronic component having a semiconductor layer (3) on a substrate (1) and a top layer (5) on the semiconductor layer (3) applied to the substrate (1), characterized in that, The top layer (5) consists of a non-conductive dielectric and has a channel (6) leading through the top layer to the semiconductor layer (3) and extending into the semiconductor layer (3); the channel (6) is at least partially filled with a doped II-VI semiconductor (7), and a metal contact (8) is applied to the doped II-VI semiconductor (7), the metal contact (8) extending outside the top layer (5) or protruding outward relative to the top layer (5); Among them, at room temperature, the contact resistance of the electronic component is , and the sheet resistance is .

13. The electronic component according to claim 12, characterized in that, The semiconductor layer (3) consists of ZnSe.

14. The electronic component according to claim 12, characterized in that, The top layer (5) consists of aluminum oxide, silicon oxide, hafnium oxide or silicon nitride.

15. The electronic component according to any one of claims 12-14, characterized in that, The substrate (1) consists of GaAs, ZnSe, (In, Ga)As, InAs, (In, Ga)P, (In, Ga, Al)P or InP.

16. The electronic component according to any one of claims 12-14, characterized in that It is a unipolar element.

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