Charging Pile Error Verification Device and Method

Abstract

A charging pile error verification device and method. Among them, the charging pile error verification device includes a controllable load and a detection circuit. When the detection circuit conducts error testing on the charging pile, it divides the current period of the target verification current into N sub-periods according to a preset discreteness N, and controls the target load provided by the controllable load to be connected to the charging pile during the first sub-period. Thus, on the premise of not reducing the target verification current for full-load detection of the charging pile, by only outputting 1 / N of the current period of the target verification current value of the charging pile, the target verification current flowing through the controllable load evenly for only 1 / N of the current period is equivalent to reducing the power of the controllable load by N times, thereby reducing the volume of each resistor in the controllable load and reducing the weight of each resistor, solving the problem of large load volume and heavy weight in the traditional charging pile error verification device.

Description

Technical Field

[0001] This application belongs to the technical field of charging pile detection, and particularly relates to a charging pile error verification device and method. Background Art

[0002] Currently, AC / DC charging piles for electric vehicles / non-vehicle-mounted DC chargers have been included in the mandatory catalog of the "Catalog of Measuring Instruments Subject to Compulsory Management". The active electric energy of charging piles will be a mandatory item that must be verified by the quality inspection system every year. Currently, most AC charging piles adopt the scheme of an AC charging pile calibrator + an AC charging pile load. For three-phase AC charging piles, a load of 42 kW generally needs to be configured, which is large in volume, heavy in weight, and inconvenient to carry and use.

[0003] Therefore, there is a problem of large load volume and heavy weight in traditional charging pile error verification devices. Summary of the Invention

[0004] The purpose of this application is to provide a charging pile error verification device and method, aiming to solve the problem of large load volume and heavy weight in traditional error verification devices.

[0005] The first aspect of the embodiment of this application provides a charging pile error verification device, including:

[0006] A controllable load, which is connected to the bus of the charging pile. The controllable load is used to provide a target load for the charging pile so that the bus current is the target verification current; and

[0007] A detection circuit, which is connected to the controllable load. The detection circuit is used to divide the current cycle of the target verification current into N sub-cycles according to a preset discreteness N during the error test of the charging pile, and control the target load to be connected to the bus of the charging pile during the first sub-cycle.

[0008] The second aspect of the embodiment of this application provides a charging pile error verification method, including:

[0009] Obtain the bus voltage of the charging pile;

[0010] According to the bus voltage, the preset target verification current, and the maximum resistance value of the controllable load connected to the charging pile, determine the resistance that needs to be connected to the bus of the charging pile in the controllable load when the bus current of the charging pile is the target verification current and mark it;

[0011] Based on the preset discreteness N of the target verification current, divide the current cycle of the target verification current into N sub-cycles, and control the marked resistance to be connected to the bus during the first sub-cycle;

[0012] Read the measured power parameters of the charging pile, calculate the calculated power parameters of the charging pile, and calculate the power error of the charging pile based on the measured power parameters and the calculated power parameters.

[0013] The above-mentioned charging pile error verification device includes a controllable load and a detection circuit. When the detection circuit performs error testing on the charging pile, it divides the current cycle of the target verification current into N sub-cycles according to a preset discreteness N, and controls the target load provided by the controllable load to be connected to the charging pile during the first sub-cycle. Thus, without reducing the target verification current for full-load detection of the charging pile, by only outputting 1 / N of the current cycle of the target verification current of the charging pile, the controllable load evenly passes through only 1 / N of the current cycle of the target verification current, which is equivalent to reducing the power of the controllable load by N times. Thereby, the volume of each resistor in the controllable load is reduced, the weight of each resistor is alleviated, and the problem of large load volume and heavy weight in the traditional charging pile error verification device is solved. Description of the Drawings

[0014] Figure 1 Schematic circuit diagram of the charging pile error verification device provided by an embodiment of the present application;

[0015] Figure 2 For Figure 1 Example circuit schematic diagram of the charging pile error verification device shown;

[0016] Figure 3 For Figure 1 Example circuit schematic diagram of the controllable load of the charging pile error verification device shown;

[0017] Figure 4 For Figure 1 Example circuit schematic diagram of the thyristor drive circuit of the charging pile error verification device shown;

[0018] Figure 5 Specific flowchart of the charging pile error verification method provided by an embodiment of the present application;

[0019] Figure 6 For Figure 1 Specific flowchart of step S400 of the charging pile error verification method shown;

[0020] Figure 7 For Figure 1 Specific flowchart of step S400 of the charging pile error verification method shown. Detailed Description of the Invention

[0021] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present application more clearly understood, the present application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0022] It should be noted that when an element is referred to as being "fixed to" or "disposed on" another element, it can be directly on the other element or indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or indirectly connected to the other element.

[0023] It should be understood that the orientation or positional relationship indicated by the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation to the present application.

[0024] In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance or implicitly indicating the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the present application, "a plurality of" means two or more unless otherwise specifically defined.

[0025] Figure 1 The circuit schematic diagram of the charging pile error verification device provided by the first aspect of the embodiment of the present application is shown. For the convenience of description, only the parts related to this embodiment are shown and are described in detail as follows:

[0026] The charging pile error verification device in this embodiment includes: a controllable load 200 and a detection circuit 300. The controllable load 200 is connected to the bus of the charging pile 100, and the detection circuit 300 is connected to the controllable load 200 and the charging pile 100. The controllable load 200 is used to provide a target load for the charging pile 100 so that the bus current is the target verification current. The detection circuit 300 is used to divide the current period of the target verification current into N sub-periods according to a preset dispersion N during the error test of the charging pile 100, and control the target load to be connected to the bus of the charging pile 100 during the first sub-period.

[0027] It should be understood that after the detection circuit is used to make the bus output the target verification current, it is also used to obtain the measured power parameters of the charging pile under the target verification current, calculate the calculated power parameters of the charging pile under the target verification current, and determine the power error of the charging pile according to the measured power parameters and the calculated power parameters, so as to complete the error test of the charging pile.

[0028] It should be understood that the detection circuit 300 in this embodiment controls the target load to be connected to the bus of the charging pile 100 during the first sub-cycle, which means that the detection circuit 300 closes the connection between the target load and the charging pile 100 during the first sub-cycle, and disconnects the target load from the charging pile 100 when it is turned on in the second sub-cycle until the end of the last sub-cycle.

[0029] It should be understood that the charging pile 100 can output three-phase alternating current or single-phase alternating current. When the charging pile 100 is a three-phase AC charging pile, the target verification current of the charging pile 100 is three-phase current, and the controllable load 200 is three identical loads to be respectively connected to the three phases of the AC charging pile 100. The charging pile 100 can be an AC charging pile or a DC charging pile. Please refer to Figure 2 , the bus of the charging pile 100 can be connected to the controllable load 200 through the AC power supply socket 900. When the charging pile 100 is a DC charging pile, the AC power supply socket 900 is used to be connected in series to the AC circuit of the DC charging pile.

[0030] Optionally, the detection circuit 300 can be composed of a processor and its peripheral devices, such as the BF609 chip and its peripherals.

[0031] Optionally, in one embodiment, the determination method of the preset dispersion N can be:

[0032] 1. According to the target verification current Iset, determine the minimum current value I1N corresponding to the maximum power in the controllable load 200. I1N can be a fixed value or can be adjusted according to the actual target verification current Iset. For example, I1N can be 3A;

[0033] 2. Divide the target verification current Iset by the minimum current value I1N and round down to obtain the preset dispersion N, that is, N = INT(Iset / I1N), where INT is the rounding-down function.

[0034] It can be understood that the volume of the resistor is related to its power. The larger the volume of the resistor, the greater its power, and vice versa. Therefore, in the traditional charging pile error verification device, a load with a power of 42kW is generally used to complete the power detection of the charging pile 100 under the verification current.

[0035] It can be understood that due to the thermal inertia effect of the resistor, passing the current applied to the resistor through only 1 / N current cycles in a short period of time is equivalent to reducing the power of the resistor by N times. That is, on the premise of the same target verification current, the power of the resistor is reduced, thereby reducing the volume of the resistor. That is, compared with the technical solution of the resistor with the original full-load power, the power of the resistor in this embodiment is reduced by 1 / N. Therefore, a resistor with a volume reduced by N times compared with the original resistor can be used, and the weight of the resistor is related to its volume. That is, the weight of the resistor is also reduced at the same time. That is, the volume and weight of the controllable load 200 as the load in this embodiment are both reduced, which is convenient for carrying. This solves the problem of large volume and heavy weight of the load in the traditional charging pile error verification device.

[0036] It can be understood that the charging pile error verification device in this embodiment includes a controllable load 200 and a detection circuit 300, that is, the calibration circuit and the load are combined together, so that two devices do not need to be used when inspecting the charging pile 100, solving the problem of complex on-site wiring caused by the traditional charging pile error verification device using the scheme of an AC charging pile calibrator + an AC charging pile load.

[0037] Please refer to Figure 3 , in one embodiment, the controllable load 200 includes a plurality of parallel-connected resistors and a plurality of thyristors respectively connected in series with the resistors, and the resistance values of the resistors increase in a geometric progression.

[0038] It should be understood that the resistance values of the resistors increasing in a geometric progression means that the resistance values of the resistors form a geometric sequence. For example, the geometric relationship can be a geometric sequence with a common ratio of 2 and a constant of 4, that is, the resistance value of the first resistor R1 is 4*2 0 Ω, the resistance value of the second resistor R2 is 4*2 1 Ω, the resistance value of the third resistor R3 is 4*2 2 Ω,..., the resistance value of the Mth resistor is 4*2 M-1 Ω (M is the total number of resistors of the controllable load 200 and is an integer).

[0039] Optionally, the thyristors in this embodiment are bidirectional thyristors, and the control terminals of the thyristors are respectively connected to the detection circuit 300 in one-to-one correspondence.

[0040] In one embodiment, the detection circuit 300 determines and marks the resistors that make up the target load according to the bus voltage of the charging pile 100, the target verification current, and the resistor with the largest resistance value in the controllable load 200. It should be understood that the total resistance value of the marked resistors is equal to the target load.

[0041] Optionally, in one embodiment, determining the marked resistors can be specifically:

[0042] 1. Assume that the target verification current at the verification point of the charging pile 100 is Iset, the bus voltage of the charging pile 100 is Vset = 220V, the controllable load 200 includes 16 resistors, and the resistance values of each resistor form a geometric sequence with a constant of 4 ohms and a common ratio of 2. The first resistor has the smallest resistance value, and the sixteenth resistor has the largest resistance value;

[0043] 2. The resistor with the largest resistance value is the sixteenth resistor, and its resistance value is: Rmax = 4Ω * 32768 = 131072Ω;

[0044] 3. Then the lowest bit current value ILSB of the current parallel switching in the controllable load 200 is: ILSB = Vset / Rmax = 220V / 131072Ω = 0.0016785A;

[0045] 4. Calculate the input ratio with R1 as the highest bit and R16 as the lowest bit. The input ratio is a 16 - BIT binary value:

[0046] Di = Iset / ILSB;

[0047] Assume Iset = 6A, then Di = Iset / ILSB = 6 / 0.0016785 = 3575 = 0xDF7 = b110111110111. That is, Di = 0000110111110111, where the highest bit corresponds to the first resistor R1, the lowest bit corresponds to the last resistor, that is, the sixteenth resistor R6. The resistors corresponding to the binary 1 form the target load, that is, the marked resistors at this time are: resistor R5, resistor R6, resistor R8, resistor R9, resistor R10, resistor R11, resistor R12, resistor R14, resistor R15, and resistor R16.

[0048] It should be understood that at this time, the connection between the target load and the charging pile 100 can be controlled by controlling the thyristors connected in series with the marked resistors.

[0049] Please refer to Figure 2 , in one embodiment, it further includes a plurality of thyristor drive circuits 400. Each thyristor drive circuit 400 is correspondingly connected to the output end of the detection circuit 300 and the thyristor. The thyristor drive circuit 400 is used to drive the on - off of the thyristor connected in series with the marked resistor under the control of the detection circuit 300.

[0050] Optionally, please refer to Figure 4, in one embodiment, the thyristor drive circuit 400 includes an isolated power supply U1, a first resistor Rin, an optocoupler U2, a second resistor Rout, and a tracking drive amplifier U3. The input terminal of the isolated power supply U1 is connected to a power supply, the output terminal of the isolated power supply U1 is connected to the power supply terminal of the optocoupler U2, the input terminal of the optocoupler U2 is connected to the second terminal of the first resistor Rin, the first terminal of the first resistor Rin is connected to the detection circuit 300, the output terminal of the optocoupler U2, the second terminal of the second resistor Rout, and the input terminal of the tracking drive amplifier U3 are connected, the first terminal of the second resistor Rout is connected to the output terminal of the coupled and isolated power supply U1, and the output terminal of the tracking drive amplifier U3 is connected to the control terminal of the thyristor corresponding to the thyristor drive circuit 400.

[0051] In the thyristor drive circuit 400 of this embodiment, by adding the isolated power supply U1, the first resistor Rin, the optocoupler U2, the second resistor Rout, and the tracking drive amplifier U3, the amplification and filtering of the control signal for controlling the thyristor output by the detection circuit 300 are realized, thereby avoiding the inability to control the thyristor due to too small a control signal or the influence of clutter.

[0052] Optionally, the power supply in this embodiment can be a battery; it can also be Figure 2 the power supply module 10 as shown. The power supply module 10 is connected to the charging pile 100. By accessing the single-phase electric energy of the charging pile 100 and converting it into multiple target electric energies, and supplying each target electric energy to each circuit of the charging pile error verification device for use, the target electric energy is the working electric energy of each circuit of the charging pile error verification device.

[0053] Please refer to Figure 2 , in one embodiment, the charging pile error verification device further includes: a current conversion circuit 500, a voltage conversion circuit 600, and an analog-to-digital conversion circuit 700. The current conversion circuit 500 is connected to the charging pile 100 and the controllable load 200, the voltage conversion circuit 600 is connected to the charging pile 100 and the controllable load 200, and the analog-to-digital conversion circuit 700 is connected to the current conversion circuit 500, the voltage conversion circuit 600, and the detection circuit 300; the current conversion circuit 500 is used to collect the output current of the charging pile 100, convert the output current into a current signal according to a first preset transformation ratio and output it; the voltage conversion circuit 600 is used to collect the bus voltage of the charging pile 100, convert the bus voltage into a voltage signal according to a second preset transformation ratio and output it; the analog-to-digital conversion circuit 700 is used to convert the current signal and the voltage signal into digital signals and output them to the detection circuit 300.

[0054] It should be understood that the current conversion circuit 500 can be composed of a three-phase precision current converter. Among them, the three-phase precision current converter can be composed of a zero-flux current transformer of 0.01 level, an operational amplifier OPA2277, and an RF resistor with an accuracy of 0.01% (temperature drift of 1ppm). The conversion ratio of the first preset current-to-voltage conversion ratio in this embodiment can be, for example, 80A:1V. The first preset conversion ratio can be adjusted. The conversion of the current conversion circuit 500 can be exemplified as follows:

[0055] Assume that the AC current inputs of the charging pile 100 are Ia, Ib, and Ic, and the voltage values output by the current conversion circuit 500 are VI2a, VI2b, and VI2c. The first preset conversion ratio is a, that is:

[0056] VI2a = Ia / a;

[0057] VI2b = Ib / a;

[0058] VI2c = Ic / a.

[0059] For example, when a = 80:1, the secondary voltage value corresponding to a current value of 63A is 0.7875VAC.

[0060] It should be understood that the voltage conversion circuit 600 can be composed of a three-phase precision voltage conversion circuit 600. Among them, the three-phase precision voltage converter can be composed of a high-stability resistor with a temperature drift of 1ppm and an accuracy of 0.01% and a voltage follower circuit composed of an A2277 operational amplifier U3. The second preset conversion ratio in this embodiment can be adjusted. The second preset conversion ratio in this embodiment is a reduction ratio. The voltage conversion of the voltage conversion circuit 600 is specifically exemplified as follows:

[0061] Assume that the AC voltage inputs of the charging pile 100 are Ua, Ub, and Uc, and the output values of the voltage conversion circuit 600 are U2a, U2b, and U2c. The second preset conversion ratio is b, that is: U2a = Ua / b, U2b = Ub / b, U2c = Uc / b, (b > 1). For example, when b is 200, that is, U2a = Ua / 200, U2b = Ub / 200, U2c = Uc / 200.

[0062] It should be understood that the analog-to-digital conversion circuit 700 can be composed of an analog-to-digital conversion chip, such as a chip with the model number ADS1278.

[0063] Please refer to Figure 2, in one embodiment, it further includes a pulse collector 800. The pulse collector 800 is connected to the charging pile 100 and the detection circuit 300. The pulse collector 800 is used to collect the electrical energy pulses of the charging pile 100 and convert them into electrical signals for output to the detection circuit 300. The detection circuit 300 records the number of electrical signals within a preset time period as the measured pulse number of the charging pile 100, and calculates the electrical energy error of the charging pile 100 based on the measured pulse number of the charging pile 100.

[0064] Optionally, the pulse collector 800 can be composed of a non-frequency-dividing verification optoelectronic head. The input end of the non-frequency-dividing verification optoelectronic head is connected to the charging pile 100, and the output end of the non-frequency-dividing verification optoelectronic head is connected to the detection circuit 300.

[0065] It should be understood that the charging pile 100 in this embodiment corresponds to a charging pile 100 with electrical energy pulse output. The error test in this embodiment is carried out when both the charging pile error verification device and the charging pile 100 are working continuously. The calculation method of the electrical energy error γ of the charging pile 100 is as follows:

[0066]

[0067]

[0068] where m 0 is the calculated pulse constant; m is the measured pulse number of the standard meter, that is, the cumulative pulse number calculated inside the charging pile error verification device in this embodiment; N x is the measured pulse number of the charging pile 100; C 0 is the pulse constant of the charging pile error verification device in this embodiment, which can be set by the detection circuit 300; C L is the pulse constant of the charging pile 100, and this pulse constant can be input according to the parameter display of the charging pile 100.

[0069] Optionally, in order to ensure that the value of N x is related to the frequency of the pulse output of the electric energy meter of the charging pile 100. For example, if the frequency is fast, the value of N x is large, and vice versa, it is small; in order to improve the accuracy of detection, it should be ensured that the preset time period is not less than 5 seconds and not less than one pulse.

[0070] In one embodiment, the detection circuit 300 is further used to calculate the verified electrical energy value of the charging pile 100 according to the voltage signal, current signal, and preset time period, read the electrical energy indication value displayed by the electric energy meter of the charging pile 100 within the preset time period, and calculate the electrical energy error of the charging pile 100 based on the verified electrical energy value and the electrical energy indication value. It can be understood that the verified electrical energy value of the charging pile 100 is the calculated electrical energy parameter of the charging pile 100, and the electrical energy indication value displayed by the electric energy meter of the charging pile 100 is the measured electrical energy parameter of the charging pile 100.

[0071] It should be understood that the charging pile 100 in this embodiment corresponds to a charging pile 100 with pulse output, and the verification method in this embodiment is carried out when both the charging pile error verification device and the charging pile 100 are working continuously. The calculation method of the power error γ of the charging pile 100 is as follows:

[0072] γ = [(W’ - W) / W] * 100% + γ 0 ;

[0073] Among them, γ 0 is the determined systematic error of the charging pile error verification device, which can be zero;

[0074] W’ is the indicated value (kWh) shown at the beginning and end of the charging pile 100 within a preset time period;

[0075] W is the power value (kWh) of the charging pile 100 within the preset time period without the verification device. Specifically, the detection circuit 300 can calculate it according to the voltage signal, current signal, and preset time period.

[0076] In one embodiment, an input circuit 20 is further included. The input circuit 20 is connected to the detection circuit 300, and the input circuit 20 can be a keyboard, an input panel, etc. That is, the charging pile error verification device in this embodiment can input the measured power parameters of the charging pile 100 (such as the power indicated value shown on the electric energy meter of the charging pile 100) and operation instructions into the detection circuit 300 in a manual input manner. It should be understood that in other embodiments, the detection circuit 300 can also obtain the measured power parameters of the charging pile 100 by communicating with a pan-tilt camera, and the pan-tilt camera is used to detect the charging pile 100.

[0077] In one embodiment, a display circuit 30 is further included. The display circuit 30 is connected to the detection circuit 300, and the display circuit 30 can be composed of a liquid crystal display screen. The display circuit 30 can be used to display the test results of the detection circuit 300 for error testing of the charging pile, etc.

[0078] Please refer to Figure 5 , the second aspect of the embodiment of the present application provides a charging pile error verification method, which is applied to the above-mentioned charging pile error verification device. The charging pile error verification method includes:

[0079] Step S100: Collect the bus voltage of the charging pile 100;

[0080] It should be understood that the bus voltage of the charging pile 100 can be obtained through a voltage sensor connected to the bus of the charging pile 100, etc.

[0081] Step S200: Determine the resistance of the controllable load 200 required to be connected to the bus of the charging pile 100 when the bus current of the charging pile 100 is the target verification current according to the bus voltage, the preset target verification current, and the maximum resistance value of the controllable load 200 connected to the charging pile, and mark it; it can be understood that the total resistance value of the marked resistors is the above-mentioned target load.

[0082] Please refer to Figure 6 , in one embodiment, step S200 specifically includes:

[0083] Step S210: Calculate the lowest-bit current value ILSB of the controllable load 200 under the bus voltage according to the bus voltage and the maximum resistance value;

[0084] It should be understood that assuming the bus voltage is Vset = 220V, the target verification current is Iset, the controllable load 200 includes 16 resistors, and the resistance values of each resistor form a geometric sequence with a constant of 4 ohms and a common ratio of 2. The first resistor R1 has the smallest resistance value, and the sixteenth resistor R16 has the largest resistance value. Then: the maximum resistance value is the resistance value of the sixteenth resistor R16, Rmax = 4Ω * 32768 = 131072Ω; then ILSB = Vset / Rmax = 220V / 131072Ω = 0.0016785A;

[0085] Step S220: Calculate the input ratio according to the target verification current and the lowest-bit current value ILSB;

[0086] It should be understood that the input ratio is the resistor in the controllable load 200 that needs to be connected to the charging pile 100 so that the output current of the charging pile 100 is the target verification current;

[0087] Assume the input ratio is Di, then Di = Iset / ILSB.

[0088] Step S230: Convert the input ratio into a binary value with the target number of bits, and the target number of bits is equal to the number of resistors of the controllable load 200;

[0089] For example, when the controllable load 200 includes 16 resistors, the input ratio is converted into a 16-bit binary value.

[0090] Assume Iset = 6A, then Di = Iset / ILSB = 6 / 0.0016785 = 3575 = 0xDF7 = b110111110111. That is, Di = 0000110111110111, where the highest bit corresponds to the first resistor R1, and the lowest bit corresponds to the last resistor, that is, the sixteenth resistor R6.

[0091] Step S240: Mark the corresponding resistors with a binary value of 1 according to the binary value.

[0092] For example, when Di = 0000110111110111, the target load at this time is: resistor R5, resistor R6, resistor R8, resistor R9, resistor R10, resistor R11, resistor R12, resistor R14, resistor R15, and resistor R16.

[0093] Step S300: Based on the preset dispersion N of the target verification current, divide the current period of the target verification current into N sub-periods, and control the marked resistor to be connected to the bus during the first sub-period;

[0094] Optionally, in one embodiment, please refer to Figure 7 , step S300 specifically includes:

[0095] Step S310: Determine the minimum current value corresponding to the maximum power of the controllable load 200 according to the target verification current;

[0096] Step S320: Divide the target verification current by the minimum current value and round up to the preset dispersion N;

[0097] Step S330: Divide the current period of the target verification current into N sub-periods according to the preset dispersion N;

[0098] After step S330, it further includes: controlling the marked resistor to be connected to the bus during the first sub-period, that is, closing the connection between the marked resistor and the charging pile 100 during the first sub-period, and disconnecting the marked resistor from the charging pile 100 when the second sub-period starts to the end of the last sub-period.

[0099] Step S400: Read the measured electrical energy parameters of the charging pile, calculate the calculated electrical energy parameters of the charging pile, and calculate the electrical energy error of the charging pile according to the measured electrical energy parameters and the calculated electrical energy parameters.

[0100] It should be understood that the electrical energy parameters can be electrical energy values or electrical energy pulses.

[0101] It should be understood that the magnitudes of the sequence numbers of the steps in the above embodiments do not mean the order of execution. The order of execution of each process should be determined by its function and internal logic, and should not constitute any limitation to the implementation process of the embodiments of the present application.

[0102] Those skilled in the art can clearly understand that, for the convenience and brevity of description, only the above-mentioned division of each functional unit and module is used as an example. In actual applications, the above functions can be allocated to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. Each functional unit and module in the embodiments can be integrated into a processing unit, or each unit can exist physically alone, or two or more units can be integrated into one unit. The above integrated unit can be implemented in the form of hardware or in the form of a software functional unit. In addition, the specific names of each functional unit and module are only for the convenience of mutual distinction and do not limit the protection scope of this application. The specific working processes of the units and modules in the above system can refer to the corresponding processes in the foregoing method embodiments and will not be elaborated herein.

[0103] In the above embodiments, the descriptions of the respective embodiments have their own emphases. For the parts not detailed or recorded in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0104] Those of ordinary skill in the art can realize that the units and algorithm steps of the examples described in conjunction with the embodiments disclosed herein can be implemented by electronic hardware, or by a combination of computer software and electronic hardware. Whether these functions are executed in hardware or software depends on the specific application and design constraints of the technical solution. A professional technician can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of this application.

[0105] In the embodiments provided in this application, it should be understood that the disclosed device / terminal device and method can be implemented in other ways. For example, the device / terminal device embodiments described above are merely illustrative. For example, the division of the modules or units is only a logical function division, and there can be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the displayed or discussed couplings or direct couplings or communication connections to each other can be through some interfaces. The indirect couplings or communication connections of the devices or units can be in electrical, mechanical or other forms.

[0106] The units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they can be located in one place or distributed to multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0107] In addition, each functional unit in various embodiments of the present application may be integrated into one processing unit, may exist physically as individual units, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of a software functional unit.

[0108] If the integrated module / unit is implemented in the form of a software functional unit and sold or used as an independent product, it may be stored in a computer-readable storage medium. Based on such an understanding, all or part of the processes in the above-mentioned embodiment methods of the present application can also be completed by instructing relevant hardware through a computer program. The computer program can be stored in a computer-readable storage medium. When the computer program is executed by a processor, the steps of the above-mentioned various method embodiments can be implemented. Among them, the computer program includes computer program code, and the computer program code can be in the form of source code, object code, executable file or some intermediate form, etc. The computer-readable medium may include: any entity or device capable of carrying the computer program code, recording medium, USB flash drive, mobile hard disk, magnetic disk, optical disc, computer memory, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), electrical carrier signal, telecommunication signal, and software distribution medium, etc. It should be noted that the content included in the computer-readable medium may be appropriately increased or decreased according to the requirements of legislation and patent practice in the jurisdiction. For example, in some jurisdictions, according to legislation and patent practice, the computer-readable medium does not include electrical carrier signals and telecommunication signals.

[0109] The above-mentioned embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the various embodiments of the present application, and should all be included in the protection scope of the present application.

Claims

1. A charging pile error verification device, characterized in that, it includes: A controllable load, the load is connected to the bus of the charging pile, and the controllable load is used to provide a target load for the charging pile so that the bus current is the target verification current; and A detection circuit, the detection circuit is connected to the controllable load, and the detection circuit is used to divide the current cycle of the target verification current into N sub-cycles according to a preset dispersion degree N when performing error testing on the charging pile, and control the target load to be connected to the bus of the charging pile during the first sub-cycle; The controllable load includes a plurality of parallel-connected resistors and a plurality of thyristors respectively connected in series with the resistors, and the resistance values of the respective resistors increase in a geometric progression; The detection circuit determines and marks the resistors that make up the target load according to the bus voltage of the charging pile, the target verification current, and the resistor with the largest resistance value in the controllable load; The determination method of the preset dispersion degree N is: According to the target verification current Iset, determine the minimum current value I1N corresponding to the maximum power in the controllable load, divide the target verification current Iset by the minimum current value I1N and take the integer as the preset dispersion degree N, that is, N = INT(Iset / I1N), where INT is the integer function.

2. The charging pile error verification device according to claim 1, characterized in that, It further includes a plurality of thyristor drive circuits, and each thyristor drive circuit is correspondingly connected to the output end of the detection circuit and the thyristor, and the thyristor drive circuit is used to drive the on and off of the thyristor connected in series with the marked resistor under the control of the detection circuit.

3. The charging pile error verification device according to claim 1 or 2, characterized in that, It further includes: A current conversion circuit, the current conversion circuit is connected to the charging pile and the controllable load, and the current conversion circuit is used to collect the output current of the charging pile, convert the output current into a current signal according to a first preset ratio and output it; A voltage conversion circuit, the voltage conversion circuit is connected to the charging pile and the controllable load, and the voltage conversion circuit is used to collect the bus voltage of the charging pile, convert the bus voltage into a voltage signal according to a second preset ratio and output it; and An analog-to-digital conversion circuit, the analog-to-digital conversion circuit is connected to the current conversion circuit, the voltage conversion circuit, and the detection circuit, and the analog-to-digital conversion circuit is used to convert the current signal and the voltage signal into digital signals and output them to the detection circuit; The detection circuit is further used to calculate the verified electric energy value of the charging pile according to the voltage signal, the current signal, and a preset duration, read the electric energy indication value displayed by the electric energy meter of the charging pile within the preset duration, and calculate the electric energy error of the charging pile according to the verified electric energy value and the electric energy indication value.

4. The charging pile error verification device according to claim 3, characterized in that, It further includes a pulse collector, which is connected to the charging pile and the detection circuit. The pulse collector is used to collect the power pulses of the charging pile and convert them into electrical signals for output to the detection circuit. The detection circuit records the number of the electrical signals within a preset time period as the measured pulse number of the charging pile, and calculates the power error of the charging pile based on the measured pulse number of the charging pile.

5. A method for calibrating the error of a charging pile, characterized in that, it includes: obtaining the bus voltage of the charging pile; determining and marking the resistance that needs to be connected to the bus of the charging pile in the controllable load when the bus current of the charging pile is the target calibration current according to the bus voltage, a preset target calibration current, and the maximum resistance value of the controllable load connected to the charging pile; dividing the current cycle of the target calibration current into N sub-cycles based on a preset dispersion degree N of the target calibration current, and controlling the marked resistance to be connected to the bus during the first sub-cycle; reading the measured power parameters of the charging pile, calculating the calculated power parameters of the charging pile, and calculating the power error of the charging pile according to the measured power parameters and the calculated power parameters; the determination method of the preset dispersion degree N is: determining the minimum current value I1N corresponding to the maximum power in the controllable load according to the target calibration current Iset, dividing the target calibration current Iset by the minimum current value I1N and taking the integer as the preset dispersion degree N, that is, N = INT(Iset / I1N), where INT is the integer function.

6. The method for calibrating the error of a charging pile according to claim 5, characterized in that, the step of determining and marking the resistance that needs to be connected to the bus of the charging pile in the controllable load when the bus current of the charging pile is the target calibration current according to the bus voltage, a preset target calibration current, and the maximum resistance value of the controllable load connected to the charging pile includes: calculating the lowest bit current value of the controllable load under the bus voltage according to the bus voltage and the maximum resistance value; calculating the input ratio according to the target calibration current and the lowest bit current value; converting the input ratio into a binary value corresponding to the target number of bits, where the target number of bits is equal to the number of resistances of the controllable load; marking the corresponding resistances with a binary value of 1 according to the binary value.

7. The method for calibrating the error of a charging pile according to claim 5, characterized in that, dividing the current cycle of the target calibration current into N sub-cycles based on a preset dispersion degree N of the target calibration current includes: determining the minimum current value corresponding to the maximum power of the controllable load according to the target calibration current; dividing the target calibration current by the minimum current value and taking the integer as the preset dispersion degree N; dividing the current cycle of the target calibration current into N sub-cycles according to the preset dispersion degree N.

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