Display device and method of driving the same

Abstract

A display device and a method for driving the display device are provided. The display device includes the following elements: a light-emitting diode; a first transistor including a drain electrode, a source electrode, and a gate electrode, the drain electrode being connected to the light-emitting diode; a second transistor connected between a data line and the source electrode; a third transistor connected between the drain electrode and the gate electrode; and a fourth transistor connected between a first initialization voltage source and the gate electrode. The third transistor is turned off during a first time period, turned on during a second time period immediately following the first time period, and turned off during a third time period immediately following the second time period. The fourth transistor is turned off during a fourth time period, turned on during a fifth time period immediately following the fourth time period, and turned off during a sixth time period immediately following the fifth time period. The second time period overlaps with the fifth time period.

Description

[0001] This application claims priority to and the benefit of Korean Patent Application No. 10-2020-0055184 filed on May 8, 2020, in the Korean Intellectual Property Office, which is incorporated herein by reference. Technical Field

[0002] The technical field relates to a light-emitting display device and a driving method of a light-emitting display device. Background Art

[0003] The display device may be, for example, a liquid crystal display (LCD) or an organic light emitting diode (OLED) display. The display device may be used in various electronic devices such as portable phones, navigation systems, digital cameras, electronic books, portable game consoles, and various terminals.

[0004] A display device may include pixels arranged in rows and columns. The pixels may include transistors and capacitors. The display device may include wiring that can transmit signals to these transistors and capacitors. The display device may display an image based on the signals.

[0005] The background section is used to enhance understanding of the background technology of the described technology. The background section may contain information that does not constitute prior art. Summary of the Invention

[0006] Embodiments may relate to a light emitting display device that allows a predetermined voltage to be maintained substantially constant. Embodiments may relate to a driving method of a light emitting display device.

[0007] According to an embodiment, the light-emitting display device includes: a light-emitting diode; a driving transistor that transmits an output current to the light-emitting diode; a second transistor that transmits a data voltage to a source electrode of the driving transistor; a third transistor that connects a drain electrode and a gate electrode of the driving transistor; a fourth transistor that initializes the gate electrode of the driving transistor with a first initialization voltage; and an eighth transistor that applies a bias voltage to the source electrode of the driving transistor, wherein a section during which the third transistor is turned on and the drain electrode and the gate electrode of the driving transistor are connected and a section during which the fourth transistor is turned on and the voltage of the gate electrode of the driving transistor is changed to the first initialization voltage at least partially overlap with each other.

[0008] The third transistor may be turned on after a section during which the light emitting diode emits light is terminated and an odd number of 1Hs has passed.

[0009] The fourth transistor may be turned on after a section during which the light emitting diode emits light is terminated and an odd number of 1Hs has passed.

[0010] The second transistor can be turned on when the fourth transistor is in the off state and the third transistor is in the on state, where the state in which the fourth transistor is in the off state and the third transistor is in the on state is called a write-available section, and the write-available section includes multiple unit application sections, each of the multiple unit application sections includes a first application section and a second application section, the second transistor is turned on during the first application section, and the second transistor is not turned on during the second application section.

[0011] The second application section may be a section during which the initialization control signal controlling the fourth transistor floats.

[0012] When a frequency at which the eighth transistor is turned on is referred to as a first frequency and a frequency at which the third and fourth transistors are turned on is referred to as a second frequency, the first frequency may be higher than the second frequency.

[0013] The light-emitting display device may further include: a first scan line connected to the gate electrode of the second transistor; a second scan line connected to the gate electrode of the third transistor; an initialization control line connected to the gate electrode of the fourth transistor; and a bias control line connected to the gate electrode of the eighth transistor, wherein the second scan line, the initialization control line and the bias control line are simultaneously connected to two rows of pixels, and the first scan line is formed in each single row of pixels.

[0014] The light-emitting display device may further include: a fifth transistor, which transmits a driving voltage to a source electrode of the driving transistor; a sixth transistor, which connects a drain electrode of the driving transistor and an anode of the light-emitting diode to each other; a seventh transistor, which initializes the voltage of the anode of the light-emitting diode to a second initialization voltage; and a light-emitting control line, which is connected to the gate electrode of the fifth transistor and the gate electrode of the sixth transistor, wherein the gate electrode of the seventh transistor may be connected to a bias control line.

[0015] According to the embodiment, the driving method of the light-emitting display device includes: a light-emitting section, during which the driving transistor transmits an output current to the light-emitting diode, so that the light-emitting diode emits light; a pre-bias section, during which the bias voltage is applied to the source electrode of the driving transistor; an anode reset section, during which the anode of the light-emitting diode is initialized; a gate initialization section, during which the gate electrode of the driving transistor is initialized; a drain initialization section, during which the drain electrode of the driving transistor is initialized; and a threshold voltage compensation and data writing section, during which the threshold voltage of the driving transistor is compensated and the data voltage is written, wherein the drain initialization section starts after the light-emitting section ends and an odd number of 1Hs have passed.

[0016] The gate initialization section may start after the light emitting section ends and an odd number of 1Hs elapse.

[0017] The drain initialization section and the gate initialization section may at least partially overlap each other.

[0018] The drain initialization section and the gate initialization section may start at the same timing.

[0019] When a segment in which the drain initialization segment is in progress after the gate initialization segment is terminated is called a write-available segment, the write-available segment includes multiple unit application segments, and each of the multiple unit application segments includes a first application segment in which the threshold voltage compensation and data writing segment are set and a second application segment in which the threshold voltage compensation and data writing segment are not set, so the threshold voltage compensation and data writing segment are set in one 1H of the first application segment.

[0020] The second application section may be a section during which the initialization control signal of the control gate initialization section floats.

[0021] When the frequency at which the light emitting section, pre-bias section and anode reset section are repeatedly positioned is referred to as a first frequency, and the frequency at which the gate initialization section, drain initialization section and threshold voltage compensation and data writing section are repeatedly positioned is referred to as a second frequency, the first frequency may be higher than the second frequency.

[0022] According to the embodiment, the driving method of the light-emitting display device includes: a light-emitting section, during which the driving transistor transmits the output current to the light-emitting diode, so that the light-emitting diode emits light; a pre-bias section, during which the bias voltage is applied to the source electrode of the driving transistor; an anode reset section, during which the anode of the light-emitting diode is initialized; a gate initialization section, during which the gate electrode of the driving transistor is initialized; a drain initialization section, during which the drain electrode of the driving transistor is initialized; and a write-available section, including a threshold voltage compensation and data writing section, during which the threshold voltage of the driving transistor is compensated and the data voltage is written, wherein the write-available section includes a plurality of unit application sections, each of the plurality of unit application sections is divided into a first application section and a second application section, and the threshold voltage compensation and data writing section is positioned in the first application section.

[0023] The second application section may be a section during which the initialization control signal of the control gate initialization section floats.

[0024] The drain initialization section or the gate initialization section may start after the light emitting section ends and an odd number of 1Hs elapse.

[0025] The drain initialization section and the gate initialization section may at least partially overlap each other.

[0026] When the frequency at which the light emitting segment, pre-bias segment and anode reset segment are repeatedly positioned is referred to as a first frequency, and the frequency at which the gate initialization segment, drain initialization segment and threshold voltage compensation and data writing segment are repeatedly positioned is referred to as a second frequency, the first frequency may be higher than the second frequency.

[0027] Embodiments may relate to a display device. The display device may include the following elements: a light-emitting diode; a first transistor, wherein a drain electrode of the first transistor may be electrically connected to the light-emitting diode and may be connected between the light-emitting diode and a source electrode of the first transistor; a data line for transmitting a data voltage; a second transistor electrically connected between the data line and the source electrode of the first transistor; a third transistor electrically connected between the drain electrode of the first transistor and the gate electrode of the first transistor; and a fourth transistor electrically connected between a first initialization voltage source and the gate electrode of the first transistor for initializing the gate electrode of the first transistor with the first initialization voltage. The third transistor may be turned off during a first time period, may be turned on during a second time period immediately following the first time period, and may be turned off during a third time period immediately following the second time period. The fourth transistor may be turned off during a fourth time period, may be turned on during a fifth time period immediately following the fourth time period, and may be turned off during a sixth time period immediately following the fifth time period. The second time period may overlap with the fifth time period.

[0028] The light emitting diode may emit light in the seventh time period. The odd-numbered scan signal length may be immediately after the seventh time period and immediately before the second time period.

[0029] An odd-numbered scan signal length may be immediately after the seventh period and may be immediately before the fifth period.

[0030] The write-enabled period may overlap with each of the second period and the sixth period, may include the first application period, and may include the second application period immediately following the first application period. The second transistor may be turned on during the first application period and may be turned off during the second application period.

[0031] The gate electrode of the fourth transistor may receive an initialization control signal. The initialization control signal may float during the second application period.

[0032] The display device may further include a bias voltage transistor. The drain electrode of the bias voltage transistor may be electrically connected to the source electrode of the first transistor. The source electrode of the bias voltage transistor may be electrically connected to a bias voltage source. The bias voltage transistor may be turned on according to a first frequency. Each of the third transistor and the fourth transistor may be turned on according to a second frequency. The first frequency may be higher than the second frequency.

[0033] The display device may further include the following elements: a first scan line electrically connected to the gate electrode of the second transistor; a second scan line electrically connected to the gate electrode of the third transistor; an initialization control line electrically connected to the gate electrode of the fourth transistor; a bias voltage transistor, wherein the drain electrode of the bias voltage transistor can be electrically connected to the source electrode of the first transistor, and wherein the source electrode of the bias voltage transistor can be electrically connected to a bias voltage source; and a bias control line electrically connected to the gate electrode of the bias voltage transistor. Each of the second scan line, the initialization control line, and the bias control line can be electrically connected to pixels of the two pixel rows. The first scan line can be electrically connected to pixels of each single row in the two pixel rows.

[0034] The display device may further include the following elements: a fifth transistor, wherein a source electrode of the fifth transistor may be electrically connected to a driving voltage source, and wherein a drain electrode of the fifth transistor may be electrically connected to a source electrode of the first transistor; a sixth transistor, wherein a source electrode of the sixth transistor may be electrically connected to a drain electrode of the first transistor, and wherein a drain electrode of the sixth transistor may be electrically connected to an anode of a light-emitting diode; a seventh transistor for initializing a voltage of the anode of the light-emitting diode to a second initialization voltage, wherein a source electrode of the seventh transistor may be electrically connected to the second initialization voltage source, and wherein a drain electrode of the seventh transistor may be electrically connected to the anode of the light-emitting diode; and a light emission control line electrically connected to each of a gate electrode of the fifth transistor and a gate electrode of the sixth transistor. The gate electrode of the seventh transistor may be electrically connected to a bias control line.

[0035] Embodiments may relate to a method for driving a display device, the display device including a driving transistor, a light-emitting diode, and a storage capacitor. The method may include the following steps: transmitting an output current to the light-emitting diode through the driving transistor during a light-emitting period to cause the light-emitting diode to emit light; applying a bias voltage to the source electrode of the driving transistor during a pre-bias period; initializing the anode of the light-emitting diode during an anode reset period; initializing the gate electrode of the driving transistor during a gate initialization period; initializing the drain electrode of the driving transistor during a drain initialization period; and compensating the threshold voltage of the driving transistor and writing a data voltage to the storage capacitor during a threshold voltage compensation and data writing period. An odd-numbered scan signal length may be immediately after the light-emitting period and immediately before the drain initialization period.

[0036] An odd-numbered scan signal length may be immediately after the light emitting period and may be immediately before the gate initialization period.

[0037] The drain initialization period and the gate initialization period at least partially overlap with each other.

[0038] The drain initialization period and the gate initialization period may start at the same time.

[0039] The write-available period may begin after the gate initialization period has ended, may overlap with the drain initialization period, may include the first application period, and may include the second application period. Compensation and writing may be performed during the first application period but not during the second application period. The threshold voltage compensation and data writing period may be equal to the length of one scan signal within the first application period.

[0040] The method may further include providing an initialization control signal in the gate initialization period for controlling initialization of the gate electrode of the driving transistor. The initialization control signal may be floated in the second application period.

[0041] The light emission period, the pre-bias period, and the anode reset period may be repeated at a first frequency. The gate initialization period, the drain initialization period, and the threshold voltage compensation and data writing period may be repeated at a second frequency. The first frequency may be higher than the second frequency.

[0042] Embodiments may relate to a method for driving a display device, the display device including a driving transistor, a light-emitting diode, and a storage capacitor. The method may include the following steps: transmitting an output current to the light-emitting diode through the driving transistor during the entire light-emitting period to cause the light-emitting diode to emit light; applying a bias voltage to the source electrode of the driving transistor during the entire pre-bias period; initializing the anode of the light-emitting diode during the entire anode reset period; initializing the gate electrode of the driving transistor during the entire gate initialization period; initializing the drain electrode of the driving transistor during the entire drain initialization period; and compensating the threshold voltage of the driving transistor during the entire threshold voltage compensation and data writing period, and writing the data voltage to the storage capacitor. The write-available period may include a first application period and a second application period. The threshold voltage compensation and data writing period may be within the first application period.

[0043] The method may further include providing an initialization control signal in the gate initialization period for controlling initialization of the gate electrode of the driving transistor. The initialization control signal may be floated in the second application period.

[0044] The odd-numbered scan signal length may be immediately before the drain initialization period or the gate initialization period, and may be immediately after the light emitting period.

[0045] The drain initialization period and the gate initialization period may at least partially overlap with each other.

[0046] The light emission period, the pre-bias period, and the anode reset period may be repeated at a first frequency. The gate initialization period, the drain initialization period, and the threshold voltage compensation and data writing period may be repeated at a second frequency. The first frequency may be higher than the second frequency.

[0047] According to an embodiment, the voltage of an element in a pixel (e.g., a first initialization voltage applied to a gate electrode of a driving transistor) is maintained substantially constant, and / or the voltage level of a signal applied to the pixel (e.g., a scanning signal or an initialization control signal) is maintained substantially constant, so that the desired brightness of the pixel can be stably displayed. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] Figure 1 is a schematic diagram of a light emitting display device according to an embodiment.

[0049] Figure 2 is a circuit diagram of a pixel of a light emitting display device according to an embodiment.

[0050] Figure 3 is applied to the Figure 2 The waveform diagram of the pixel signal.

[0051] Figure 4is a waveform diagram showing a signal applied in a comparative example.

[0052] Figure 5 3 is a waveform diagram comparing the signal in the comparative example with the signal in the embodiment.

[0053] Figure 6 is a waveform diagram of a signal applied in a comparative example.

[0054] Figure 7 is a waveform diagram showing the waveform of a signal measured in the comparative example.

[0055] Figure 8 : is a waveform diagram showing the waveform of a signal measured in the embodiment.

[0056] Figure 9 is applied to the Figure 2 The waveform diagram of the pixel signal.

[0057] Figure 10 、 Figure 11 and Figure 12 is a waveform diagram according to one or more embodiments.

[0058] Figure 13 is a timing diagram of signals applied to a light emitting display device according to an embodiment.

[0059] Figure 14 is a schematic diagram of a light emitting display device according to an embodiment.

[0060] Figure 15 and Figure 16 is a waveform diagram of a signal according to one or more embodiments. DETAILED DESCRIPTION

[0061] The exemplary embodiments have been described with reference to the accompanying drawings. The described embodiments can be modified in various ways.

[0062] The same reference numbers may identify the same or similar elements.

[0063] In the drawings, the sizes of elements may be exaggerated for clarity.

[0064] Although the terms "first", "second" etc. can be used to describe various elements, these elements should not be limited by these terms. These terms can be used to distinguish an element from another element. Without departing from the teaching of one or more embodiments, the first element can be named as the second element. Describing an element as a "first" element may not require or imply the presence of a second element or other elements. The terms "first", "second" etc. can be used to distinguish elements of different categories or sets. For the sake of simplicity, the terms "first", "second" etc. can represent "first type (or first set)", "second type (or second set)" etc. respectively.

[0065] The term "segment" may mean "period". The term "floating" may mean "floating". The term "connected" may mean "electrically connected" or "not electrically connected through an intermediate transistor". The term "driven" may mean "operating" or "controlling". The term "connected with..." may mean "connected to...". The expression "formed by..." may mean "composed of...". The term "compensate" may mean "compensate for...". The term "within..." or "during..." may mean "in the entire...". The expression "passed through" may mean "passed through" or "passed". The expression "overlapping with..." may mean "overlapping". The expression "terminate" may mean "end". The expression "odd number of 1Hs" may mean "odd number of scan signal lengths (1H)".

[0066] Figure 1 is a schematic diagram of a light emitting display device according to an embodiment.

[0067] The light-emitting display device includes a plurality of pixels PX.

[0068] Each pixel PX included in a light-emitting display device includes a driving circuit portion and a light-emitting element portion. In some embodiments, the light-emitting element portion includes a light-emitting diode and may include a capacitor, while the driving circuit portion may include multiple transistors and a capacitor. The driving circuit portion is formed on a substrate, and the light-emitting element portion may be disposed on the driving circuit portion.

[0069] exist Figure 1 In the pixel PX shown in FIG, the driving circuit portion has a rectangular shape and may be arranged in a matrix format along rows and columns.

[0070] The light emitting element portion of the pixel PX is formed on the driving circuit portion and includes a rectangular structure, and can be formed in various structures such as a circle or a diamond. The light emitting element portion may not be arranged in a matrix format, but may be provided in various arrangements.

[0071] exist Figure 1 In the embodiment, an example is shown in which two rows of pixels PX receive at least one signal.

[0072] exist Figure 1 In the example, the emission control line EM, bias control line GB, second scan line GC, and initialization control line GI are shared by two pixel rows; a first scan line GW is provided for each pixel row. The wiring (emission control line EM, bias control line GB, second scan line GC, and initialization control line GI) connected to two rows of pixels PX is called a common connection wiring.

[0073] When common connection wiring is formed, the number of wirings in the region where the pixels PX are located (ie, the display region) is reduced, thereby forming pixels with high resolution. The area of ​​the non-display region outside the display region can also be reduced.

[0074] On the other hand, when common wiring is used, a constant voltage is not directly applied to the wiring receiving each signal for one frame, but a constant level of voltage can be applied by repeating the timing of directly applying a signal and the timing of maintaining the existing voltage by floating.

[0075] The pixel PX additionally receives a data voltage, a driving voltage, an initialization voltage, and a bias voltage.

[0076] Figure 2 is a circuit diagram of a pixel of a light emitting display device according to an embodiment.

[0077] A pixel PX formed in a light-emitting display device includes transistors T1, T2, T3, T4, T5, T6, T7, and T8, capacitors Cst and Cled, and a light-emitting diode LED connected to a signal line. The driving circuit portion includes a plurality of transistors T1, T2, T3, T4, T5, T6, T7, and T8 and a storage capacitor Cst, and the light-emitting element portion includes a light-emitting diode LED and a capacitor Cled for the light-emitting diode.

[0078] The signal lines connected to one pixel PX include a first scan line GW, a second scan line GC, an initialization control line GI, a bias control line GB, an emission control line EM, a data line, a first initialization voltage line, a second initialization voltage line, a bias voltage line, a driving voltage line, and a driving low voltage line.

[0079] The first scan line GW transmits the first scan signal GW[n] to the gate electrode of the second transistor T2 of the pixel PX, and one first scan line GW is formed in each pixel row.

[0080] The second scan line GC transmits the second scan signal GC[n] to the gate electrode of the third transistor T3 of the pixel PX, and is one of the common connection wirings because the second scan line GC is formed for every two pixel rows.

[0081] The initialization control line GI transmits the initialization control signal GI[n] to the gate electrode of the fourth transistor T4 of the pixel PX, and is one of the common connection wirings because the initialization control line GI is formed for every two pixel rows.

[0082] The bias control line GB transmits the bias control signal GB[n] to the gate electrodes of the seventh and eighth transistors T7 and T8 of the pixel PX, and is one of the common connection wirings because it is formed for every two pixel rows.

[0083] The emission control line EM transmits the emission control signal EM[n] to the gate electrodes of the fifth and sixth transistors T5 and T6 of the pixel PX, and is one of the common connection wirings because it is formed for every two pixel rows.

[0084] The data line transmits the data voltage Data to the first electrode of the second transistor T2 of the pixel PX and is formed for a corresponding pixel column.

[0085] The first initialization voltage line transmits the first initialization voltage Vint1 to the first electrode of the fourth transistor T4 of the pixel PX and applies the first initialization voltage Vint1 of a constant level to all pixels PX. According to an embodiment, the first initialization voltage line may have a mesh structure connected in row and column directions.

[0086] The second initialization voltage line transmits the second initialization voltage Vint2 to the first electrode of the seventh transistor T7 of the pixel PX, and applies the second initialization voltage Vint2 of a constant level to all pixels PX. The second initialization voltage Vint2 has a lower level than the first initialization voltage Vint1. In addition, according to an embodiment, the second initialization voltage line may have a grid structure connected in the row direction and the column direction.

[0087] The bias voltage line transmits the bias voltage VEH to the first electrode of the eighth transistor T8 of the pixel PX. Depending on the embodiment, the bias voltage VEH may have a constant level or a level that varies according to the bias control signal GB[n]. When the bias voltage VEH is constant, the bias voltage line may be connected to all pixels PX. However, when the bias voltage VEH varies, a separate bias voltage line may be formed for each pixel column or pixel row, or one bias voltage line may be formed for multiple pixel columns or multiple pixel rows.

[0088] The driving voltage line transmits the driving voltage ELVDD to the first electrode of the fifth transistor T5 of the pixel PX and one end of the storage capacitor Cst, and applies the driving voltage ELVDD of a constant high voltage level to all pixels PX. According to an embodiment, the driving voltage line may have a grid structure connected in row and column directions.

[0089] The driving low voltage line transmits the driving low voltage ELVSS to the cathode of the light emitting diode LED of the pixel PX and one end of the capacitor Cled for the light emitting diode LED, and applies the driving low voltage ELVSS of a constant low voltage level to all pixels PX. According to an embodiment, the driving low voltage line may have a grid structure connected in the row direction and the column direction.

[0090] The driving transistor T1 (also referred to as the first transistor) may have P-type transistor characteristics and may include a polycrystalline semiconductor. The driving transistor T1 receives the data voltage Data from the second transistor T2 and outputs an output current during the light-emitting section according to the magnitude of the data voltage Data. The output current is transmitted to the anode of the light-emitting diode LED, causing the light-emitting diode LED to emit light. The source electrode (or first electrode) of the driving transistor T1 is connected to the second electrode of the second transistor T2 to receive the data voltage Data, the drain electrode of the driving transistor T1 outputs the output current, and the gate electrode of the driving transistor T1 is connected to one electrode of the storage capacitor Cst.

[0091] The storage capacitor Cst is used to maintain the voltage of the gate electrode of the driving transistor T1 for one frame or longer. One electrode of the storage capacitor Cst is connected to the gate electrode of the driving transistor T1 and the other electrode is connected to the driving voltage line, thereby receiving a constant driving voltage ELVDD.

[0092] The second transistor T2 may have P-type transistor characteristics and may include a polycrystalline semiconductor. The second transistor T2 is configured to receive a data voltage Data in the pixel PX. The gate electrode of the second transistor T2 is connected to the first scan line GW, the first electrode of the second transistor T2 is connected to the data line, and the second electrode of the second transistor T2 is connected to the source electrode of the driving transistor T1. When the first scan signal GW[n] transmitted via the first scan line GW is at a low level, the second transistor T2 is turned on, and the data voltage Data transmitted via the data line is transmitted to the source electrode of the driving transistor T1.

[0093] The third transistor T3 may have N-type transistor characteristics and may include an oxide semiconductor. The third transistor T3 electrically connects the drain electrode of the driving transistor T1 and the gate electrode of the driving transistor T1, so that the driving transistor T1 has a diode connection structure, and the data voltage Data transmitted to the source electrode of the driving transistor T1 is transmitted to the gate electrode of the driving transistor T1 (i.e., one electrode of the storage capacitor Cst). The gate electrode of the third transistor T3 is connected to the second scan line GC, the first electrode of the third transistor T3 is connected to the drain electrode of the driving transistor T1, and the second electrode of the third transistor T3 is connected to one electrode of the storage capacitor Cst and the gate electrode of the driving transistor T1. When the second scan signal GC[n] transmitted through the second scan line GC is high, the third transistor T3 is turned on, thereby connecting the gate electrode and drain electrode of the driving transistor T1, and transmitting the data voltage Data applied to the source electrode of the driving transistor T1 to one electrode of the storage capacitor Cst and storing the data voltage Data in the storage capacitor Cst.

[0094] The fourth transistor T4 may have N-type transistor characteristics and may include an oxide semiconductor. The fourth transistor T4 is used to initialize the gate electrode of the driving transistor T1 and one electrode of the storage capacitor Cst with a first initialization voltage Vint1. The gate electrode of the fourth transistor T4 is connected to the initialization control line GI, the first electrode of the fourth transistor T4 is connected to the first initialization voltage line, and the second electrode of the fourth transistor T4 is connected to the second electrode of the third transistor T3, one electrode of the storage capacitor Cst, and the gate electrode of the driving transistor T1. When the initialization control signal GI[n] transmitted through the initialization control line GI is high, the fourth transistor T4 is turned on, so that the first initialization voltage Vint1 is transmitted to the gate electrode of the driving transistor T1 and the storage capacitor Cst. Therefore, the voltage of the gate electrode of the driving transistor T1 and the voltage of one electrode of the storage capacitor Cst are initialized to the first initialization voltage Vint1.

[0095] The fifth transistor T5 may have P-type transistor characteristics and may include a polycrystalline semiconductor. The fifth transistor T5 is used to transmit the driving voltage ELVDD to the source electrode of the driving transistor T1. The gate electrode of the fifth transistor T5 is connected to the emission control line EM, the first electrode of the fifth transistor T5 is connected to the driving voltage line, and the second electrode of the fifth transistor T5 is connected to the first electrode of the driving transistor T1. When the emission control signal EM[n] transmitted via the emission control line EM is at a low level, the fifth transistor T5 is turned on and transmits the driving voltage ELVDD to the source electrode of the driving transistor T1.

[0096] The sixth transistor T6 may have P-type transistor characteristics and may include a polycrystalline semiconductor. The sixth transistor T6 is configured to transmit the output current from the driving transistor T1 to the anode of the light-emitting diode LED. The gate electrode of the sixth transistor T6 is connected to the emission control line EM. A first electrode of the sixth transistor T6 is connected to the drain electrode of the driving transistor T1, and a second electrode is connected to the anode of the light-emitting diode LED. When the emission control signal EM[n] transmitted via the emission control line EM is low, the sixth transistor T6 turns on and transmits the output current from the driving transistor T1 to the anode of the light-emitting diode LED.

[0097] The seventh transistor T7 may have P-type transistor characteristics and may include a polycrystalline semiconductor. The seventh transistor T7 is used to initialize the anode of the light-emitting diode LED with a second initialization voltage Vint2. The gate electrode of the seventh transistor T7 is connected to the bias control line GB, the second electrode of the seventh transistor T7 is connected to the anode of the light-emitting diode LED, and the first electrode of the seventh transistor T7 is connected to the second initialization voltage line. When the bias signal GB[n] is at a low level, the seventh transistor T7 is turned on, so that the second initialization voltage Vint2 is applied to the anode of the light-emitting diode LED, thereby initializing the anode of the light-emitting diode LED.

[0098] The eighth transistor T8 may have P-type transistor characteristics and may include a polycrystalline semiconductor. The eighth transistor T8 is used to apply a bias voltage VEH to the first electrode of the driving transistor T1. The gate electrode of the eighth transistor T8 is connected to the bias control line GB, the first electrode of the eighth transistor T8 is connected to the bias voltage line, and the second electrode of the eighth transistor T8 is connected to the source electrode of the driving transistor T1. When the bias signal GB[n] is at a low level, the eighth transistor T8 is turned on, and the bias voltage VEH is applied to the source electrode of the driving transistor T1.

[0099] The light emitting diode LED includes an anode, a cathode and an intermediate emission layer. The anode is connected to the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7, and the cathode receives the driving low voltage ELVSS. When the output current of the driving transistor T1 is transmitted to the anode, the output current passes through the emission layer and is then transmitted to the cathode, causing the emission layer to emit light. In this case, when the intensity of the output current increases, the brightness of the light emitted from the light emitting diode LED increases. According to an embodiment, the emission layer can display one of the primary colors and can include a quantum dot (QD) material. According to an embodiment, the light emitting display device may further include a color reproduction layer including a color filter or a quantum dot (QD) material to display improved color sensing.

[0100] A capacitor Cled for light emitting diodes including an anode and a cathode may be additionally formed near the light emitting diode LED. The capacitor Cled for light emitting diodes includes an anode, a cathode, and an insulating layer disposed between the anode and the cathode, and is used to help the voltage of the anode remain constant within one frame.

[0101] One pixel PX of the light-emitting display panel may include a light-emitting diode LED, a driving transistor T1 transmitting an output current to the light-emitting diode LED, a second transistor T2 transmitting a data voltage to a source electrode of the driving transistor T1, a third transistor T3 connecting a drain electrode and a gate electrode of the driving transistor T1, a fourth transistor T4 initializing a voltage of the gate electrode of the driving transistor T1 to a first initialization voltage, and an eighth transistor T8 applying a bias voltage VEH to the source electrode of the driving transistor T1.

[0102] A first scan line GW connected to the gate electrode of the second transistor T2, a second scan line GC connected to the gate electrode of the third transistor T3, an initialization control line GI connected to the gate electrode of the fourth transistor T4, and a bias control line GB connected to the gate electrode of the eighth transistor T8 are formed, and the second scan line GC, the initialization control line GI, and the bias control line GB are common connection wirings connected to every two rows of pixels at the same time, while the first scan line GW can be formed in every single row of pixels.

[0103] The pixel PX may further include a fifth transistor T5 that transmits the driving voltage ELVDD to the source electrode of the driving transistor T1, a sixth transistor T6 that connects the drain electrode of the driving transistor T1 and the anode of the light-emitting diode LED, a seventh transistor T7 that initializes the anode of the light-emitting diode LED by applying a second initialization voltage Vint2 to the anode of the light-emitting diode LED, and an emission control line EM connected to the gate electrodes of the fifth transistor T5 and the sixth transistor T6. The gate electrode of the seventh transistor T7 may be connected to a bias control line GB.

[0104] The number of transistors, the number of capacitors, and the connection relationship in the pixel PX may be configured according to embodiments. The gate electrode of the driving transistor T1 and the first scan line GW may partially overlap each other, and the pixel PX may further include an additional capacitor (also referred to as a boosting capacitor).

[0105] exist Figure 2In the embodiment shown in , the driving transistor T1 may include a polycrystalline semiconductor. The third transistor T3 and the fourth transistor T4 may include an oxide semiconductor. The second transistor T2, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 may include a polycrystalline semiconductor. At least one of the second transistor T2, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 may include an oxide semiconductor. The third transistor T3 and the fourth transistor T4 include a semiconductor material different from the semiconductor material of the driving transistor T1, so that more stable and reliable driving can be achieved.

[0106] Can be sent to Figure 1 and Figure 2 The structure of the light emitting display device pixel PX is applied Figure 3 The signal shown in .

[0107] Figure 3 is applied to the Figure 2 The waveform diagram of the pixel signal.

[0108] When the light emitting control signal EM[n] changes to a high level, the light emitting section ends.

[0109] After the light emitting section ends, the bias control signal GB[n] changes to a low level after passing through section B, so that the pre-bias and anode reset section (Pre-bias & anode reset) begins. Section B includes a plurality of odd-numbered sections 1H. Figure 3 In the embodiment of FIG, segment B includes three 1Hs. 1H (i.e., 1 scan signal length) is a time period / length during which the first scan signal GW[n] transmitted through the first scan line GW maintains a low level, and is a time period / length for writing the data voltage Data into one row of pixels (corresponding to Figure 3 The threshold voltage compensation and data writing segment Vth&DW in the pre-bias and anode reset segments are performed during segment C and Figure 3 In the embodiment of the present invention, it is executed within four 1H.

[0110] The pre-bias and anode reset section includes a pre-bias section and an anode reset section.

[0111] When the bias control signal GB[n] changes to a low level, the eighth transistor T8, which receives the low-level bias control signal GB[n], turns on. As a result, the bias voltage VEH is transmitted to the source electrode of the driving transistor T1, and the voltage of the source electrode of the driving transistor T1 changes to a bias voltage VEH suitable for subsequent operation. This is referred to as pre-biasing, and the timing section during which pre-biasing is performed is referred to as a pre-bias section.

[0112] During the anode reset section, the bias control signal GB[n] changes to a low level, and the seventh transistor T7 having received the low-level bias control signal GB[n] is turned on, so that the second initialization voltage Vint2 is transmitted to the node of the light-emitting diode LED, so that the voltage of the anode of the light-emitting diode LED is initialized to the second initialization voltage Vint2. The timing section during which this anode reset operation is performed is called the anode reset section.

[0113] The pre-bias section and the anode reset section are executed simultaneously due to the same signal (ie, the bias control signal GB[n]). In an embodiment, the pre-bias section and the anode reset section may be located in different sections, or may only partially overlap each other.

[0114] When the bias control signal GB[n] returns to a high level, the pre-bias section and the anode reset section are terminated. Figure 3 The gate and drain initialization section (Gate & Drain Initial) starts to initialize the gate electrode and drain electrode of the driving transistor T1. The gate and drain initialization section (Gate & Drain Initial) is also positioned after an odd number of 1Hs have passed since the end of the light emitting section (when the light emitting control signal EM[n] changes to a high level) (this is in the embodiment of ... Figure 3 After the section marked as A). Figure 3 In the embodiment of FIG, segment A includes segment B, segment C, and segment D, and is formed of a total of nine 1Hs.

[0115] The gate and drain initialization section (Gate & Drain Initial) includes a section during which the gate electrode of the driving transistor T1 is initialized and a section during which the drain electrode (or second electrode) of the driving transistor T1 is initialized, and signals for controlling the two sections are different from each other.

[0116] When the initialization control signal GI[n] changes to a high level, the fourth transistor T4 that has received the high-level initialization control signal GI[n] is turned on, so that the first initialization voltage Vint1 is transmitted to the gate electrode of the driving transistor T1, so that the voltage of the gate electrode of the driving transistor T1 is initialized to the first initialization voltage Vint1. The first initialization voltage Vint1 is also transmitted to one electrode of the storage capacitor Cst connected to the gate electrode of the driving transistor T1, and the storage capacitor Cst stores the received first initialization voltage Vint1 and is initialized. The initialization control signal GI[n] has a high level during the segment E. Figure 3 In the embodiment, segment E includes four 1Hs.

[0117] In the drain initialization section (Drain Initial), the drain electrode of the driving transistor T1 is initialized.

[0118] When the second scanning signal GC[n] changes to a high level, the third transistor T3 that has received the high-level second scanning signal GC[n] is turned on, so that the gate electrode and the drain electrode of the driving transistor T1 are connected, so that the driving transistor T1 is diode-connected. In this case, the first initialization voltage Vint1 transmitted to the gate electrode of the driving transistor T1 through the fourth transistor T4 is also transmitted to the drain electrode of the driving transistor T1, so that the drain electrode of the driving transistor T1 is initialized with the first initialization voltage Vint1.

[0119] In the section during which the second scanning signal GC[n] has a high level, the section during which the drain electrode of the driving transistor T1 is initialized (Drain Initial) corresponds only to the section during which the initialization control signal GI[n] has a high level. Figure 3 , the gate and drain initialization section (Gate&Drain Initial) is section E, and section E is a section during which the initialization control signal GI[n] and the second scan signal GC[n] have a high level.

[0120] The second scan signal GC[n] has a high level in section F, which includes section E (eg, gate and drain initialization section). Section F starts at the same timing as section E, but continues for a constant time period even after section E ends. Figure 3 , segment F includes twenty 1Hs. In segment F, the segment after segment E (i.e., gate and drain initialization segment, Gate & Drain Initial) is a segment during which at least one first scan signal GW[n] is applied, and this segment will be referred to as a write-enabled segment hereinafter. Therefore, the segment during which the second scan signal GC[n] has a high level (i.e., segment F) includes the gate and drain initialization segment (Gate & Drain Initial) (segment E) and the write-enabled segment.

[0121] At least one first scan signal GW[n] is applied in a section (i.e., a write-enabled section) during which the initialization control signal GI[n] has a low level and the second scan signal GC[n] has a high level. The write-enabled section includes at least one threshold voltage compensation and data writing section (Vth&DW), and the first scan signal GW[n] has a low level during the at least one threshold voltage compensation and data writing section (Vth&DW).

[0122] exist Figure 3 In the embodiment, segment E ends when the initialization control signal GI[n] changes to a low level, and then, after 4 1Hs, when the first scan signal GW[n] changes to a low level, the threshold voltage compensation and data writing segment (Vth&DW) starts.

[0123] When the first scan signal GW[n] changes to a low level, the data voltage Data is transmitted to the pixel PX through the second transistor T2, and the transmitted data voltage Data passes through the driving transistor T1 and the third transistor T3, and is then stored in one electrode of the storage capacitor Cst (i.e., the gate electrode of the driving transistor T1). The data voltage Data stored in the storage capacitor Cst may be the data voltage Data compensated from the threshold voltage of the driving transistor T1.

[0124] More specifically, operations for compensating for a threshold voltage and writing data will now be described.

[0125] The source electrode of the driving transistor T1 has a bias voltage VEH through a pre-bias section (Pre-bias), and the gate electrode and the drain electrode have a first initialization voltage Vint1 through a gate and drain initialization section (Gate & Drain Initial). The bias voltage VEH has a high voltage value, and the first initialization voltage Vint1 has a low voltage value. Therefore, the driving transistor T1 is in a conductive state due to the voltage difference between the bias voltage VEH and the first initialization voltage Vint1.

[0126] In this state, when the second transistor T2 is turned on by the first scan signal GW[n], the data voltage Data is transmitted to the source electrode of the driving transistor T1. Since the driving transistor T1 is in the on state, the data voltage Data transmitted to the source electrode of the driving transistor T1 is output to the drain electrode of the driving transistor T1, and then transmitted to one electrode of the storage capacitor Cst (the gate electrode of the driving transistor T1) through the turned-on third transistor T3. As a result, the voltage of the gate electrode of the driving transistor T1 gradually increases. Then, the voltage of the gate electrode of the driving transistor T1 increases to a voltage that turns off the driving transistor T1 (a voltage obtained by subtracting the threshold voltage of the driving transistor T1 from the data voltage Data), turning off the driving transistor T1. Therefore, the voltage stored in one electrode of the storage capacitor Cst has a value obtained by subtracting the threshold voltage of the driving transistor T1 from the data voltage Data. Then, not only is the data voltage Data written to the storage capacitor Cst, but the threshold voltage of the driving transistor T1 is also written to the storage capacitor Cst while being compensated.

[0127] When the driving voltage ELVDD is applied to the source electrode of the driving transistor T1 in the light-emitting section, the threshold voltage stored in the storage capacitor Cst is used to turn on the driving transistor T1, and the data voltage Data is used to determine the output level of the output current of the driving transistor T1. Therefore, the intensity of the output current of the driving transistor T1 varies according to the magnitude of the data voltage Data. The output current of the driving transistor T1 is transmitted to the light-emitting diode LED, and the brightness of the light emitted by the light-emitting diode LED is determined by the intensity of the output current transmitted to the light-emitting diode LED.

[0128] Reference Figure 1 , forming a common connection wiring (i.e., the emission control line EM, the bias control line GB, the second scan line GC, and the initialization control line GI) connected to two rows through a single wiring, and only the first scan line GW is formed for each row. Therefore, a low-level first scan signal GW[n] is applied to the n-th row, and then a low-level first scan signal GW[n+1] is applied to the n+1-th row in the next 1H. The operation of the n+1-th pixel row according to the first scan signal GW[n+1] is the same as the case where the first scan signal GW[n] is applied to the n-th row.

[0129] Reference Figure 3 The write-enabled section includes at least one unit application section G, which is a single unit section during which the first scan signal GW[n] and the first scan signal GW[n+1] can be applied. The unit application section (section G) includes a first application section shown as hatched and a second application section that is not hatched.

[0130] The first application section is a section during which the voltage of another signal (e.g., initialization control signal GI[n]) does not change or hardly changes even when the first scan signal GW[n] and the first scan signal GW[n+1] are applied; the second application section is a section during which, when the first scan signal GW[n] and the first scan signal GW[n+1] are applied, the voltage of another signal (e.g., initialization control signal GI[n]) changes greatly compared to the first application section, so that unnecessary voltage fluctuations may occur. Therefore, in the following embodiments, the first scan signal GW[n] and the first scan signal GW[n+1] may be applied only in the first application section and not in the second application section. In an embodiment, when the first scan signal GW[n] and the first scan signal GW[n+1] are applied in the second application section, although a small voltage fluctuation also occurs, no error occurs in the display operation, or no display brightness difference is visible, or the required specifications are met, and the first scan signal GW[n] and the first scan signal GW[n+1] may be applied in the second application section.

[0131] exist Figure 3 , the initialization control signal GI[n] has a low level in the write-available segment, but the difference is that the initialization control signal GI[n] is floating, thereby having a low level in part of the write-available segment, and having a low level in other parts by receiving a low-level voltage. Therefore, when the first scan signal GW[n] and the first scan signal GW[n+1] are applied while the initialization control signal GI[n] is floating, the voltage level of the initialization control signal GI[n] is easily affected. The segment during which the initialization control signal GI[n] floats corresponds to the second application segment, and the segment during which the initialization control signal GI[n] receives a low-level voltage corresponds to the first application segment. Therefore, the first scan signal GW[n] and the first scan signal GW[n+1] are applied in the first application segment, thereby reducing the fluctuation of the initialization control signal GI[n]. During the first application segment, a low-level voltage is applied to the initialization control signal GI[n], and the initialization control signal GI[n] has a low level.

[0132] exist Figure 3 In the embodiment of , four unit application sections (sections G) are included. Figure 3 , the first scan signal GW[n] is applied to the first 1H of the first application section of the second unit application section among the four unit application sections, and the first scan signal GW[n+1] is applied to the second 1H. However, it is possible for the first scan signal GW[n] and the first scan signal GW[n+1] to be applied to the first application section of the first unit application section or the first application section of another unit application section.

[0133] The write-enabled section ends when the second scan signal GC[n] changes from a high level to a low level. That is, when the third transistor T3 is turned off and the driving transistor T1 no longer has a diode-coupled structure, even if the data voltage Data is applied, the data voltage Data cannot be transmitted to the gate electrode of the driving transistor T1, making it impossible to perform a write operation.

[0134] After the write-available section ends and section B' is passed, the light-emitting section starts when the light-emitting control signal EM[n] changes to a low level. Section B' includes an odd number of 1Hs. Figure 3 In FIG, segment B′ includes three 1Hs, and segment B′ has the same length as segment B.

[0135] During the light-emitting section, the low-level light-emitting control signal EM[n] is transmitted to the gate electrode of the fifth transistor T5 and the gate electrode of the sixth transistor T6, so the fifth transistor T5 and the sixth transistor T6 are turned on, and the driving transistor T1 outputs the output current according to the written data voltage Data, and transmits the output current to the anode of the light-emitting diode LED.

[0136] The fifth transistor T5 transmits the high-level driving voltage ELVDD to the source electrode of the driving transistor T1, so that the driving transistor T1 outputs an output current due to the voltage of the source electrode and the gate electrode. The voltage of the gate electrode of the driving transistor T1 is equal to the voltage stored in one electrode of the storage capacitor Cst, and the voltage stored in one electrode of the storage capacitor Cst has a value obtained by compensating the data voltage Data applied to the pixel PX with the threshold voltage value of the driving transistor T1 via the threshold voltage compensation and data writing section (Vth&DW). The threshold voltage value of the driving transistor T1 is used together with the driving voltage ELVDD to turn on the driving transistor T1, and the data voltage Data is used to determine the intensity of the current output by the turned-on driving transistor T1. Therefore, although the driving transistor T1 set in each pixel PX has a different threshold voltage value, the driving transistor T1 outputs an output current based on the written data voltage Data, regardless of the threshold voltage value.

[0137] The sixth transistor T6 is also turned on, connecting the drain electrode of the driving transistor T1 to the anode electrode of the light-emitting diode LED. Therefore, the current output from the driving transistor T1 is transmitted to the anode electrode of the light-emitting diode LED, causing the light-emitting diode LED to emit light. The light-emitting diode LED emits light with a brightness that varies according to the intensity of the output current of the driving transistor T1.

[0138] After that, as the light emitting control signal EM[n] returns to a high level, the light emitting section ends and one frame ends. The next frame starts from section B.

[0139] The section during which the light-emission control signal EM[n] has a high level (i.e., a non-light-emission section) is relatively shorter than the light-emission section during which the light-emission control signal EM[n] has a low level. During this long light-emission section, the anode and cathode voltages of the light-emitting diode capacitor Cled are maintained, allowing the light-emitting diode LED to emit light at a constant brightness. In this case, the storage capacitor Cst also maintains a constant voltage at the gate electrode of the driving transistor T1.

[0140] exist Figure 3In the embodiment, the first application section and the second application section in the unit application section (section G) are respectively formed by two 1Hs. The length of the first application section and the length of the second application section may correspond to the number of pixels PX to which the emission control line EM, the bias control line GB, the second scan line GC, or the initialization control line GI is simultaneously connected. That is, since the emission control line EM, the bias control line GB, the second scan line GC, and the initialization control line GI are connected at the same time, the length of the first application section and the second application section may correspond to the number of pixels PX to which the emission control line EM, the bias control line GB, the second scan line GC, and the initialization control line GI are simultaneously connected. Figure 1 is connected to two rows of pixels PX at the same time, so Figure 3 , the first application section and the second application section each have a width of 2 1Hs, and the unit application section (section G) of the first scan signal GW[n] has twice the width of 2 1Hs, that is, a width of 4 1Hs.

[0141] The width of the cell application section may be equal to the width of the pre-bias and anode reset section (ie, section C) or the width of the gate and drain initialization section (Gate & Drain Initial) (ie, section E).

[0142] exist Figure 3 This waveform diagram includes the following features.

[0143] First, after the light emitting section is terminated, an odd number of 1Hs are positioned until the pre-bias and anode reset section (Pre-bias & anode reset) and the gate and drain initialization section (Gate & Drain Initial).

[0144] That is, after the light emitting control signal EM[n] changes to a high level and an odd number of 1H segments (ie, Figure 3 After section B in FIG, the pre-bias and anode reset section begins when the bias control signal GB[n] changes to a low level.

[0145] After the light emitting control signal EM[n] changes to a high level and an odd number of 1Hs (ie, Figure 3 After the section A in FIG, the gate and drain initialization section (Gate&Drain Initial) starts when the second scan signal GC[n] and the initialization control signal GI[n] change to a high level.

[0146] The drain initialization section (Drain Initial) starts after an odd number of 1Hs have passed from the end of the light emitting section, so it starts when the third transistor T3 is turned on after the section during which the light emitting diode LED emits light has ended and an odd number of 1Hs have passed.

[0147] The gate initialization section (Gate Initial) starts after the light emitting section ends and an odd number of 1Hs elapse, so it starts when the fourth transistor T4 is turned on after the section during which the light emitting diode LED emits light ends and an odd number of 1Hs elapse.

[0148] As described above, when the end time of a light-emitting segment differs from the start time of each segment by an odd number of 1H, the light-emitting control signal EM[n] applied to the subsequent pixel rows is applied every two 1Hs, so that the light-emitting control signal EM[n] and the application timing do not overlap. Therefore, high-level voltages can be generated and output at different timings, thereby eliminating defects such as a decrease in the high-level voltage value generated when executing at the same timing or relatively significant changes caused by the influence of peripheral signals due to the same timing.

[0149] exist Figure 3 In FIG, segment B is formed of three 1Hs, and segment A is formed of nine 1Hs, but this is not restrictive, and both segment B and segment A may include various odd numbers of 1Hs (such as 1, 3, 5, 7, 9, etc.). Figure 3 In the waveform diagram of , segment B′ which is a period from the end of the write-available segment until the start of the light-emitting segment is formed by an odd number of 1Hs.

[0150] Next, a section for initializing the gate electrode of the driving transistor T1 and a section for initializing the drain electrode of the driving transistor T1 overlap.

[0151] Reference Figure 3 , a section (Gate Initial) during which the gate electrode of the driving transistor T1 is initialized by using the initialization control signal GI[n] and a section (Drain Initial) during which the drain electrode of the driving transistor T1 is initialized by using the second scan signal GC[n] are shown as section E, and the two sections overlap for more than 1 H. More specifically, the section (Gate Initial) during which the initialization control signal GI[n] is applied at a high level and the gate electrode of the driving transistor T1 is initialized is included in the section (Drain Initial) during which the second scan signal GC[n] is applied at a high level and the drain electrode of the driving transistor T1 is initialized, and the two sections start at the same timing.

[0152] According to an embodiment, a section for initializing the gate electrode of the driving transistor T1 and a section for initializing the drain electrode of the driving transistor T1 may at least partially overlap with each other. That is, a section during which the third transistor T3 is turned on to connect the drain electrode and the gate electrode of the driving transistor T1 and a section during which the fourth transistor T4 is turned on to change the voltage of the gate electrode of the driving transistor T1 to the first initialization voltage Vint1 may at least partially overlap.

[0153] The section during which the gate electrode of the driving transistor T1 is initialized is shorter than the section during which the drain electrode of the driving transistor T1 is initialized, so all or at least a portion of the section during which the gate electrode of the driving transistor T1 is initialized may be included in the section during which the drain electrode of the driving transistor T1 is initialized.

[0154] The section for initializing the drain electrode of the driving transistor T1 may begin before the initialization of the gate electrode of the driving transistor T1 is terminated. That is, the level of the second scanning signal GC[n] is set to change to a high level at the same time as the gate electrode of the driving transistor T1 is initialized. Therefore, even if the voltage level of the second scanning signal GC[n] changes due to the coupling between the gate electrode of the driving transistor T1 and the second scanning line GC to which the second scanning signal GC[n] is applied, the voltage of the gate electrode of the driving transistor T1 is ultimately initialized to the first initialization voltage Vint1. Therefore, there is no change in the gate electrode initialization voltage of the driving transistor T1 (i.e., the first initialization voltage).

[0155] Secondly, the write-available segment during which the first scan signal GW[n] and the first scan signal GW[n+1] can be applied may have a plurality of unit application segments (segments G), and a single unit application segment (segment G) includes a first application segment and a second application segment. The first application segment may be a segment in which it is suitable to apply the first scan signal GW[n] and the first scan signal GW[n+1] because almost no voltage change at the periphery occurs even if the first scan signal GW[n] and the first scan signal GW[n+1] are applied. On the contrary, the second application segment is a segment in which a relatively significant voltage change occurs when the first scan signal GW[n] and the first scan signal GW[n+1] are applied during the segment and it is necessary to check whether unnecessary side effects occur, so according to an embodiment, it would be inappropriate to apply the first scan signal GW[n] and the first scan signal GW[n+1]. Figure 3 In the embodiment, the segment to which the first scan signal GW[n] and the first scan signal GW[n+1] can be applied can be the 1+4nth 1H or the 2+4nth 1H in the write-available segment.

[0156] The initialization control signal GI[n] is directly applied as a low level voltage in the first application section, so even if the first scan signal GW[n] and the first scan signal GW[n+1] are applied in the first application section, the voltage level of the initialization control signal GI[n] remains at a low level voltage without voltage level changes due to coupling.

[0157] However, the initialization control signal GI[n] floats in the second application section, so when the first scan signal GW[n] and the first scan signal GW[n+1] are applied in the second application section, the voltage of the wiring receiving the initialization control signal GI[n] (i.e., the initialization control line GI) may change significantly due to coupling. The voltage of the electrode connected to the initialization control line GI (i.e., the gate electrode of the fourth transistor T4) may be unstable.

[0158] In an embodiment, the first scan signal GW[n] and the first scan signal GW[n+1] are applied only during the first application section among the unit application section (section G).

[0159] The state in which the fourth transistor T4 is in the off state and the third transistor T3 is in the on state is referred to as a write-available section. After the section (Gate Initial) during which the gate electrode of the driving transistor T1 is initialized is terminated, the section (Gate Initial) during which the drain electrode of the driving transistor T1 is initialized may also be referred to as a write-available section. The write-available section may be a section in which the drain electrode and the gate electrode of the driving transistor T1 are connected to each other through the third transistor T3.

[0160] The write-available segment includes a plurality of unit application segments, and each of the plurality of unit application segments includes a first application segment and a second application segment, during which the second transistor T2 can be turned on and during which the second transistor T2 is not turned on. The threshold voltage compensation and data writing segment (Vth&DW) is set in one 1H among the write-available segments so that the second transistor T2 can be turned on. The second application segment can be a segment during which the initialization control signal GI[n] for controlling the fourth transistor T4 floats. In addition to the above features, Figure 3 The waveform diagram may also include various features, and depending on the embodiment, may include only some of the following three features.

[0161] Hereinafter, each feature will be described in more detail with reference to the accompanying drawings.

[0162] Regarding the first feature (odd number of 1H gaps), we will use Figure 4 and Figure 5 The comparison examples in are used to illustrate the differences.

[0163] Figure 4 is a waveform diagram showing a signal applied in a comparative example, Figure 5 It is a waveform diagram comparing the signal in the comparative example and the signal in the embodiment.

[0164] Figure 4 A comparative example is shown in which the light emitting control signal EM[n] differs from the second scanning signal GC[n] or the initialization control signal GI[n] by an even number of 1H, and light emitting control signals EM[n] applied to different pixel rows in this case are also shown. Figure 4 In the comparative example of , the light emitting control signal EM[n] applied to the pixels in the current row has a timing of changing to a high level 8 1Hs before the second scanning signal GC[n] or the initialization control signal GI[n].

[0165] As described, when there is an even number of 1H differences, such as Figure 4 As shown in the box, the timing at which the second scanning signal GC[n] or the initialization control signal GI[n] transitions to a high level overlaps with the timing at which the light-emission control signal EM[n] transitions to a high level. In this case, when the driver simultaneously generates and outputs the high-level light-emission control signal EM[n] and the high-level second scanning signal GC[n] or the initialization control signal GI[n], there is a disadvantage that the high-level voltage value is reduced by a certain level.

[0166] Reference Figure 4 , the light emitting control signal EM[n+10] and the light emitting control signal EM[n+11] are the same, and they also change to a high level at the same timing as the second scanning signal GC[n+2] and the second scanning signal GC[n+3]. Figure 4 FIG. 1 shows that the light-emission control signals EM[n+12] and EM[n+13] are identical and also change to a high level at the same timing as the second scanning signals GC[n+4] and GC[n+5]. The light-emission control signals EM[n+14] and EM[n+15] are identical and also change to a high level at the same timing as the second scanning signals GC[n+6] and GC[n+7]. Because this relationship occurs throughout the entire light-emitting display device, the problem of a reduced high-level voltage value affects the entire light-emitting display device, which can cause display quality problems and be recognized as crosstalk.

[0167] Reference Figure 5 , the solid line corresponds to Figure 4 The dotted line portion (which is the light emitting control signal delayed by 1H) is a comparative example.<EM_1> and<EM_2> ) corresponds to Figure 3 Example of .

[0168] Reference Figure 5 ,exist Figure 4 In the comparative example, the light emission control signal<EM_2> The GC signal is changed to a high level at the same timing as the second scanning signal and the GI signal is changed to a high level at the same timing as the initialization control signal. Figure 5 Shown in Figure 3 In the embodiment, the light emitting control signal<EM_1> and<EM_2> The timing of each of the first and second scan signals GC and the initialization control signal GI is postponed by 1 hour, thereby causing an odd number of 1 hour differences to occur. Therefore, the light emission control signal changes to a high level at a timing different from that of the second scan signal GC and the initialization control signal GI (a timing with a 1 hour difference). Therefore, a high-level voltage can be generated and output at different timings, thereby eliminating defects such as a decrease in the high-level voltage value generated when the same timing is used or a relatively significant change caused by affecting peripheral signals due to the same timing.

[0169] Hereinafter, with respect to the second feature (overlap of the section for initializing the gate electrode of the driving transistor T1 and the section for initializing the drain electrode of the driving transistor T1), reference will be made to Figure 6 A comparative example is provided to illustrate the differences.

[0170] Figure 6 is a waveform diagram of a signal applied in a comparative example.

[0171] exist Figure 6 In the comparison example, Figure 3 Unlike the embodiment of FIG. 1 , the timing at which the initialization control signal GI[n] initializes the gate electrode of the driving transistor T1 and the timing at which the second scanning signal GC[n] initializes the drain electrode of the driving transistor T1 do not overlap, and the gate initialization section and the drain initialization section do not overlap. That is, the timing at which the second scanning signal GC[n] is applied and simultaneously changed to a high level after the initialization control signal GI[n] changes to a high level and then to a low level is shown.

[0172] Now it will be based on Figure 6 This comparative example is used to describe Figure 2 Pixel operations.

[0173] First, the fourth transistor T4 is turned on when the initialization control signal GI[n] changes to a high level, so that the first initialization voltage Vint1 is transmitted to the gate electrode of the driving transistor T1, so that the voltage of the gate electrode of the driving transistor T1 is initialized to the first initialization voltage Vint1. In this case, the first initialization voltage Vint1 is stored in one electrode of the storage capacitor Cst. Thereafter, the fourth transistor T4 is turned off when the initialization control signal GI[n] changes to a low level, so that the first initialization voltage Vint1 is no longer applied to the gate electrode of the driving transistor T1 and one electrode of the storage capacitor Cst.

[0174] Afterwards, the third transistor T3 is turned on when the second scan signal GC[n] changes to a high level, and the voltage stored in one electrode of the storage capacitor Cst changes due to coupling. That is, since the first initialization voltage Vint1 is no longer applied to the gate electrode of the drive transistor T1 and one electrode of the storage capacitor Cst, the voltage of one electrode of the storage capacitor Cst changes due to coupling caused by the change in the peripheral voltage level. Since the second scan signal GC[n] changes to a high level, the voltage of the gate electrode of the drive transistor T1 and the voltage of one electrode of the storage capacitor Cst also increase due to coupling. Because the drive transistor T1 may not be turned on during the threshold voltage compensation and data writing section, or even if the drive transistor T1 is turned on, the duration of the on-time period of the drive transistor T1 may not be fully ensured, the increase in the voltage of the gate electrode of the drive transistor T1 may cause problems with display peak brightness.

[0175] Therefore, with Figure 6 Unlike the comparative example of , in the embodiment, the section in which the drain electrode of the driving transistor T1 is initialized can be set to start before the initialization of the gate electrode of the driving transistor T1 is terminated. That is, the level of the second scanning signal GC[n] is set to change to a high level at the same time as the gate electrode of the driving transistor T1 is initialized. Therefore, even if the voltage of the gate electrode of the driving transistor T1 changes due to the coupling between the gate electrode of the driving transistor T1 and the second scanning line GC to which the second scanning signal GC[n] is applied in the second scanning signal GC[n], the voltage of the gate electrode of the driving transistor T1 is ultimately initialized to the first initialization voltage Vint1. Therefore, the gate electrode initialization voltage (first initialization voltage Vint1) of the driving transistor T1 does not change, and therefore, in the subsequent threshold voltage compensation and data writing section, the conduction characteristics of the driving transistor T1 do not change.

[0176] Hereinafter, regarding the third feature (applying the first scanning signal GW[n] in the first application section of the unit application section), the following will be described by using Figure 7 Comparison example and Figure 8The waveforms of the examples are used to describe the differences.

[0177] Figure 7 is a waveform diagram of the waveform of the signal measured in the comparative example, Figure 8 : is a waveform diagram showing the waveform of a signal measured in the embodiment.

[0178] exist Figure 7 In the comparative example of FIG. 1 , the first scan signal GW[n] is applied in the second application section among the unit application sections. Figure 8 In the embodiment, as in Figure 3 In the embodiment, the first scan signal GW[n] is applied in the first application section among the unit application sections.

[0179] exist Figure 7 In the comparative example of , the second application section during which the first scan signal GW[n] is applied is a section during which the initialization control signal GI[n] is floated, and Figure 8 In the embodiment of the present invention, the first application section during which the first scan signal GW[n] is applied is a section during which a low-level voltage is directly applied to the initialization control signal GI[n].

[0180] exist Figure 7 and Figure 8 In the waveform diagram, the first scanning signal GW[n], the initialization control signal GI[n] and the gate electrode of the driving transistor T1 (in Figure 7 and Figure 8 Specifically, in Figure 7 and Figure 8 , waveforms of pixels in two rows (odd rows / even rows) are included, and a voltage waveform pattern in a case where each pixel displays black and a voltage waveform pattern in a case where each pixel displays white are shown.

[0181] Comparing the data voltage Data when displaying white with the data voltage Data when displaying black, the data voltage Data when displaying white has a lower voltage, so the output current of the driving transistor T1 increases, thereby increasing the display brightness of the light-emitting diode LED. The data voltage Data when displaying black is high enough, so the driving transistor T1 is not turned on. In this case, the driving transistor T1 does not generate an output current, so that the light-emitting diode LED does not generate brightness.

[0182] As in Figure 7In the comparative example of , when the first scanning signal GW[n] changes to a low level while the initialization control signal GI[n] is in a floating state, the data voltage Data is input to the pixel and is coupled with the initialization control signal GI[n], so that the voltage of the initialization control signal GI[n] changes. In addition, when the first scanning signal GW[n] changes back to a high level, the first scanning signal GW[n] is coupled with the initialization control signal GI[n] accordingly, so that the voltage of the initialization control signal GI[n] increases. In particular, the voltage change of the initialization control signal GI[n] of the data voltage Data requiring a relatively high voltage value in the case of displaying black is significant. This voltage change of the initialization control signal GI[n] is caused by Figure 7 The circle mark in .

[0183] Reference Figure 7 In the circled portion, the voltage of the initialization control signal GI[n] changes a total of four times. That is, when the first scan signal GW[n] of the previous level changes to a low level, the initialization control signal GI[n] changes, then when the first scan signal GW[n] of the previous level changes to a high level, the initialization control signal GI[n] changes, then when the first scan signal GW[n] of the next row changes to a low level, the initialization control signal GI[n] changes, and then when the first scan signal GW[n+1] of the next row changes back to a high level, the initialization control signal GI[n] changes, so a total of four voltage changes occur. Due to the voltage changes of adjacent rows, a display brightness difference occurs due to crosstalk across the panel, and a brightness difference of pixels in two rows (odd rows / even rows) is observed.

[0184] On the contrary, Figure 8 In the embodiment of the present invention, the first scanning signal GW[n] changes to a low level and the low level voltage is directly applied to the initialization control signal GI[n]. Therefore, even if the data voltage Data is coupled with the initialization control signal GI[n] while being input to the pixel, no voltage change occurs in the initialization control signal GI[n]. Figure 8 Therefore, no difference in brightness between pixels in two rows (odd row / even row) is observed.

[0185] like Figure 7 As shown in FIG, since when the voltage of the floating initialization control signal GI[n] is as Figure 7 The crosstalk that occurs when the voltage of the initialization control signal GI[n] changes as shown in FIG. 1 cannot set the first scan signal GW[n] to be applied in the second application section among the unit application sections. However, when the voltage of the initialization control signal GI[n] changes as shown in FIG. 1 , the first scan signal GW[n] cannot be set to be applied in the second application section among the unit application sections. Figure 7When no display brightness difference is observed even when the display brightness difference occurs, or when the display brightness difference is within the allowable range, the first scan signal GW[n] may be exceptionally applied in the second application section.

[0186] Hereinafter, the Figure 9 In the embodiment of Figure 9 In the embodiment of FIG. 1 , the voltage level of each signal is changed once more instead of being kept constant. Figure 3 Like in.

[0187] Figure 9 is applied to the Figure 2 The waveform diagram of the pixel signal.

[0188] and Figure 3 The embodiments are different. Figure 9 In an embodiment, the high-level voltage or the low-level voltage applied to each segment is slightly decreased before being changed.

[0189] Such a voltage level change may not include intentional voltage reduction, but may be a voltage change that occurs when voltage is directly applied to a specific section and floated in other parts in the generation of each signal or incidentally due to a change in voltage applied to the periphery.

[0190] The voltage variation is a fluctuation of a voltage level with respect to a level at which there is no problem when the operation of each section of the pixel PX is performed.

[0191] like Figure 3 Like in Figure 9 The embodiment includes three features, which will be referred to as Figures 10 to 12 Describe in more detail.

[0192] Figure 10 、 Figure 11 and Figure 12 is a waveform diagram according to one or more embodiments.

[0193] First, refer to Figure 10 Describe the first feature.

[0194] The first feature, that is, there are an odd number of 1Hs positioned between the end of the light emitting segment and the pre-bias and anode reset segment and between the end of the light emitting segment and the gate and drain initialization segment, in Figure 10 , the gate and drain initialization section (Gate&Drain Initial) is shown.

[0195] That is, after an odd number of 1Hs have passed since the light emitting control signal EM[n] changes to a high level, the gate and drain initialization section starts when the second scanning signal GC[n] and the initialization control signal GI[n] change to a high level. Figure 10It can be confirmed that 9 1H gaps are set.

[0196] Despite Figure 10 Not shown, but refer to Figure 9 , an odd number of 1Hs are positioned between the end of the light emitting section and the pre-bias and anode reset section. That is, after an odd number of 1Hs have passed since the light emitting control signal EM[n] changes to a high level, the pre-bias and anode reset section begins when the bias control signal GB[n] changes to a low level. Figure 9 In the example, it is confirmed that three 1H gaps are provided.

[0197] Such a first feature causes the timing of the change of the light-emitting control signal EM[n] to be different from the timing of the change of the second scanning signal GC[n], the initialization control signal GI[n] or the bias control signal GB[n], thereby eliminating defects such as a reduction in the high-level voltage value generated when executed with the same timing or a relatively significant change caused by affecting peripheral signals due to the same timing.

[0198] Reference Figure 11 , the second feature, that is, a section during which the gate electrode of the driving transistor T1 is initialized and a section during which the drain electrode of the driving transistor is initialized are set to overlap with each other, will be described.

[0199] exist Figure 11 , the initialization control signal GI[n] and the second scanning signal GC[n] change to a high level at the same timing, and the initialization control signal GI[n] changes to a low level earlier, so the segment (Gate Initial) during which the gate electrode of the driving transistor T1 is initialized is included in the segment (Drain Initial) during which the drain electrode of the driving transistor T1 is initialized, and thus the two segments overlap.

[0200] Therefore, the second scanning signal GC[n] changes to a high level when the gate electrode of the driving transistor T1 is initialized, so the change in the initialization voltage (first initialization voltage Vint1) of the gate electrode of the driving transistor T1 caused by the voltage level change of the second scanning signal GC[n] does not occur.

[0201] Reference Figure 12 , the third feature will be described, that is, the first scan signal GW[n] is set to the first application section ( Figure 12 applied in the section indicated by slashes in the figure).

[0202] That is, the initialization control signal GI[n] is applied with a low-level voltage in the first application section, and thus, even if there is a voltage change due to the application of the first scan signal GW[n] and the first scan signal GW[n+1] in the first application section, the low-level voltage can be maintained in the first application section, but the initialization control signal GI[n] is floating in the second application section, and thus when the first scan signal GW[n] is applied in the second application section, the voltage change of the wiring (i.e., the initialization control line GI) receiving the initialization control signal GI[n] may be significant. Therefore, the voltage change can be reduced by applying the first scan signal GW[n] in the first application section during which the initialization control signal GI[n] directly receives the low-level voltage.

[0203] exist Figure 12 , the first scan signal GW[n] is applied in the first 1H of the first application section of the second unit application section among the four unit application sections. However, it can also be modified to apply the first scan signal GW[n] to the second 1H of the first application section of the second unit application section, or to apply the first scan signal GW[n] to other first application sections marked with oblique lines.

[0204] In the following, reference will be made to Figure 13 A method of driving at a low frequency according to an embodiment will be described.

[0205] Figure 13 is a timing diagram of signals applied to a light emitting display device according to an embodiment.

[0206] Figure 13 The low frequency driving method can be applied to Figures 3 to 9 , and can also be applied to the later described Figure 15 .

[0207] Now refer to Figure 2 The low-frequency driving method is described by using pixels of

[0208] Signals to be applied to the pixel PX can be classified into two types, namely, control signals including a light emitting control signal EM[n] and a bias control signal GB[n], and write signals including a first scan signal GW[n], a second scan signal GC[n], and an initialization control signal GI[n].

[0209] Although Figure 13Although not shown in the figure, the control signals (EM[n] and GB[n]) and the write signals (GW[n], GC[n], and GI[n]) can generally be applied in each frame at the same driving frequency. In this case, the threshold voltage compensation and data write section (Vth & DW) are performed for each frame, thereby writing a new data voltage Data for each frame. Hereinafter, this driving method is referred to as normal frequency driving, compared to the low frequency driving method.

[0210] However, in low-frequency driving, no additional write signals (GW[n], GC[n], and GI[n]) are applied, and thus no new data voltage (Data) is written. Instead, only the control signals (EM[n] and GB[n]) are operated to display the same brightness using the pre-stored data voltage (Data). This low-frequency driving has advantages in terms of power consumption because it can eliminate unnecessary power consumption when displaying a static image. That is, although the control signals (EM[n] and GB[n]) are applied every frame, the frame in which the threshold voltage compensation and data writing section (Vth&DW) are performed can be performed once every several frames.

[0211] exist Figure 13 , the portion marked by the quadrilateral box shows the position where the control signal (EM[n], GB[n]) or the write signal (GW[n], GC[n], and GI[n]) is applied.

[0212] Reference Figure 13 While the control signals (EM[n] and GB[n]) are driven at 240 Hz, the write signals (GW[n], GC[n], and GI[n]) can be driven at various drive frequencies, with 120 Hz, 80 Hz, 60 Hz, and 48 Hz being shown as examples. That is, each frame is displayed at 240 Hz, but the actual frame at which data is written can be any of 120 Hz, 80 Hz, 60 Hz, and 48 Hz. This makes it suitable for still images and reduces power consumption.

[0213] But, unlike in Figure 13 As shown in FIG, the control signals (EM[n] and GB[n]) can be applied at a driving frequency of 120 Hz or other driving frequencies. In this case, the write signals (GW[n], GC[n] and GI[n]) can also be applied at a frequency lower than the driving frequency of the control signals (EM[n] and GB[n]).

[0214] In low-frequency driving, based on the existing data voltage Data stored in the storage capacitor Cst, the bias control signal GB[n] is applied, thereby applying the bias voltage VEH to the source electrode of the driving transistor T1, so that the driving transistor T1 is set to be turned on, and then the light-emitting control signal EM[n] is applied for light emission.

[0215] In this case, the voltage value of the bias voltage VEH may be different from the voltage value of the bias voltage VEH that has been applied in normal frequency driving, and under low frequency driving, the voltage value of the bias voltage VEH may be changed according to the timing or pre-applied data voltage Data.

[0216] When Figure 13 When low-frequency driving is performed as in the embodiment of FIG, it is not necessary to write the data voltage Data for each frame, thereby reducing power consumption. Furthermore, while applying a variable bias voltage VEH, the drive transistor T1 is biased for each frame, thereby preventing degradation of display brightness. Therefore, low-frequency driving with low power consumption can be performed without causing degradation of display quality.

[0217] In the above, Figure 1 As shown in FIG, an embodiment has been described in which some of the signals are simultaneously applied to two rows of pixels PX by using the common connection wiring (i.e., the emission control line EM, the bias control line GB, the second scan line GC, and the initialization control line GI). According to an embodiment, the common connection wiring may be formed in three or more rows of pixels PX.

[0218] In the following, reference will be made to Figures 14 to 16 An embodiment that does not include common connection wiring will be described.

[0219] First, refer to Figure 14 A light emitting display device according to another embodiment is described.

[0220] Figure 14 is a schematic diagram of a light emitting display device according to an embodiment.

[0221] exist Figure 14 In, unlike in Figure 1 As in FIG, a light emitting control line EM, a bias control line GB, a second scanning line GC, an initialization control line GI, and a first scanning line GW are formed for each single row of pixels PX.

[0222] Figure 14 The structure of the pixel PX in Figure 2 The structure of the pixels PX is the same.

[0223] and Figure 3 Different, such as Figure 15 and Figure 16 The signal is applied to the Figure 14 A light-emitting display device with a connection structure.

[0224] Figure 15 and Figure 16 is Figure 14FIG. 1 is a waveform diagram of a signal applied in an embodiment of the present invention.

[0225] Figure 15 The waveform diagram corresponds to Figure 3 The waveform diagram, and Figure 15 Shown in Figure 14 All waveforms applied in the examples.

[0226] and Figure 3 Compared with the waveform diagram, Figure 15 In the waveform diagram, the width of some segments is reduced to half.

[0227] That is to say, in Figure 15 In the waveform diagram of , the pre-bias and anode reset sections as well as the gate and drain initialization sections are reduced to 2 1H widths respectively. Figure 15 In the example, the waveform needs to be applied only to the first scanning signal GW[n], so there is no need to use Figure 3 Each segment is formed by a width of 4 1H.

[0228] Reference Figure 3 All three characteristics described are included in Figure 15 In the embodiment of .

[0229] exist Figure 15 The first feature is shown in FIG, namely, an odd number of 1Hs are positioned between the termination of the light emitting section and the pre-bias and anode reset section, and between the termination of the light emitting section and the gate and drain initialization section, and Figure 15 There are three 1Hs and seven 1Hs located in the chart.

[0230] Such a first feature causes the timing of the change of the light-emitting control signal EM[n] and the timing of the change of the second scanning signal GC[n], the initialization control signal GI[n] or the bias control signal GB[n] to be different from each other, thereby eliminating defects such as a reduction in the high-level voltage value generated when executed with the same timing or a relatively significant change caused by affecting peripheral signals due to the same timing.

[0231] Reference Figure 15 , shows the second feature, that is, the section for initializing the gate electrode of the driving transistor T1 and the section for initializing the drain electrode of the driving transistor T1 overlap with each other. Figure 15 In the gate and drain initialization section (Gate&Drain Initial), the second scan signal GC[n] and the initialization control signal GI[n] are simultaneously changed to a high level at the same timing.

[0232] As described, the section during which the gate electrode of the driving transistor T1 is initialized and the section during which the drain electrode of the driving transistor T1 is initialized are set to overlap with each other, and the second scan signal GC[n] changes to a high level at the same time as the gate electrode of the driving transistor T1 is initialized. Therefore, a change in the initialization voltage (first initialization voltage Vint1) of the gate electrode of the driving transistor T1 due to a change in the voltage level of the second scan signal GC[n] does not occur, so that the voltage of the gate electrode of the driving transistor T1 becomes equal to the first initialization voltage Vint1.

[0233] Reference Figure 15 ,exist Figure 15 The third feature is shown in FIG. 1 , that is, the section in which the first scanning signal GW[n] is applied is set to the first application section (in Figure 15 (marked by slashes).

[0234] Such a feature involves the initialization of the section where the control signal GI[n] is floating, which will be referred to as Figure 16 Describe in more detail.

[0235] Reference Figure 16 , including only Figure 15 The initialization control signal GI[n] and the first scan signal GW[n] are respectively configured.

[0236] Figure 16 The initialization control signal GI[n] shown in includes a section where a voltage is applied and a section where a signal floats, and a low-level voltage is directly applied in a first application section (a section marked by slashes), but the signal floats in a second application section.

[0237] Therefore, even though the first scan signal GW[n] is applied to the first application section and its voltage changes, the initialization control signal GI[n] can maintain a low-level voltage. When the first scan signal GW[n] is applied in the second application section, the initialization control signal GI[n] is in a floating state, so its voltage changes according to the change of the first scan signal GW[n]. Therefore, by applying the first scan signal GW[n] in the first application section, where the initialization control signal GI[n] directly receives a low-level voltage, the voltage change can be reduced.

[0238] exist Figure 15 and Figure 16 , the first scan signal GW[n] is applied in the first application section of the second unit application section among the four unit application sections. In an embodiment, the first scan signal GW[n] may be applied to other first application sections marked with oblique lines.

[0239] exist Figure 15 and Figure 16In the embodiment, the segment to which the first scan signal GW[n] can be applied can be the 1+2nth 1H (here, n is a natural number) among the write-available segments.

[0240] In the description of the third feature above, the effect has been described focusing on the floating of the initialization control signal GI[n]. Similar features can be applied to other signals. It is possible to apply the first scan signal GW[n] to a section where the voltage level variation of the signal can be reduced.

[0241] While example embodiments have been described, actual embodiments are not limited to the described embodiments and are intended to cover various modifications and equivalent arrangements within the scope of the appended claims.

Claims

1. A display device, comprising: light-emitting diodes; a first transistor, wherein a drain electrode of the first transistor is electrically connected to the light emitting diode and is connected between the light emitting diode and a source electrode of the first transistor; Data line, used for transmitting data voltage; a second transistor electrically connected between the data line and the source electrode of the first transistor; a third transistor electrically connected between the drain electrode of the first transistor and the gate electrode of the first transistor; and a fourth transistor electrically connected between a first initialization voltage source and the gate electrode of the first transistor, for initializing the gate electrode of the first transistor with a first initialization voltage; The third transistor is turned off in a first time period, turned on in a second time period immediately following the first time period, and turned off in a third time period immediately following the second time period. The fourth transistor is turned off in a fourth time period, turned on in a fifth time period immediately after the fourth time period, and turned off in a sixth time period immediately after the fifth time period, and The second time period overlaps with the fifth time period.

2. The display device according to claim 1, wherein The light emitting diode emits light in a seventh period, and an odd-numbered scanning signal length is immediately after the seventh period and immediately before the second period.

3. The display device according to claim 2, wherein: The odd-numbered scan signal lengths are immediately after the seventh period and immediately before the fifth period.

4. The display device according to claim 1, wherein The write-available period overlaps with each of the second period and the sixth period, includes a first application period, and includes a second application period immediately after the first application period, and wherein the second transistor is turned on during the first application period and is turned off during the second application period.

5. The display device according to claim 4, wherein A gate electrode of the fourth transistor receives an initialization control signal, and wherein the initialization control signal floats during the second application period.

6. The display device according to claim 1, further comprising: a bias voltage transistor, wherein a drain electrode of the bias voltage transistor is electrically connected to the source electrode of the first transistor, wherein a source electrode of the bias voltage transistor is electrically connected to a bias voltage source, wherein the bias voltage transistor is turned on according to a first frequency, wherein each of the third transistor and the fourth transistor is turned on according to a second frequency, and wherein the first frequency is higher than the second frequency.

7. The display device according to claim 1, further comprising: a first scan line electrically connected to the gate electrode of the second transistor; a second scan line electrically connected to the gate electrode of the third transistor; an initialization control line electrically connected to the gate electrode of the fourth transistor; a bias voltage transistor, wherein a drain electrode of the bias voltage transistor is electrically connected to the source electrode of the first transistor, and wherein a source electrode of the bias voltage transistor is electrically connected to a bias voltage source; and a bias control line electrically connected to the gate electrode of the bias voltage transistor, wherein each of the second scan line, the initialization control line, and the bias control line is electrically connected to pixels of two pixel rows, The first scan line is electrically connected to pixels in each single row of the two pixel rows.

8. The display device according to claim 7, further comprising: a fifth transistor, wherein a source electrode of the fifth transistor is electrically connected to a driving voltage source, and wherein a drain electrode of the fifth transistor is electrically connected to the source electrode of the first transistor; a sixth transistor, wherein a source electrode of the sixth transistor is electrically connected to the drain electrode of the first transistor, and wherein a drain electrode of the sixth transistor is electrically connected to an anode of the light emitting diode; a seventh transistor for initializing the voltage of the anode of the light-emitting diode to a second initialization voltage, wherein a source electrode of the seventh transistor is electrically connected to a second initialization voltage source, and wherein a drain electrode of the seventh transistor is electrically connected to the anode of the light-emitting diode; and a light emitting control line electrically connected to each of the gate electrode of the fifth transistor and the gate electrode of the sixth transistor, Wherein, the gate electrode of the seventh transistor is electrically connected to the bias control line.

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