Writing method of memory device and memory system

Abstract

The present invention provides a memory device write method and a memory system, wherein the memory device write method comprises the following steps: first, issuing a write command; then, determining the width of a pulse to be provided to a memory cell string included in the memory device based on temperature data of the memory device; and finally, providing a pulse to the memory cell string to perform a write operation. The pulse width decreases as the temperature of the memory device increases.

Description

Technical Field

[0001] The present invention relates to a semiconductor device and an operating method thereof, and more particularly to a writing method of a memory device and a memory system. Background Art

[0002] During a write operation on a memory device, a write pulse is applied to the selected word line of the memory device to supply the selected memory cell. Unselected memory cells on the same word line typically have a suppression voltage applied to their respective memory strings to maintain a higher channel potential, thereby preventing the unselected memory cells from experiencing Fowler-Nordheim tunneling (FN tunneling). However, when a memory device is written at high temperatures, the memory cells generate a large leakage current, causing the channel potential of the unselected memory cells to gradually decrease during the write operation, ultimately causing them to experience severe write disturb.

[0003] Figure 1 FIG. 2 shows a voltage waveform diagram of a memory device in the prior art when performing a write operation. Figure 1 As shown, the width BW_C of the pulses applied to the word line (including the write pulse VPGM_C and the pass pulse VPASS_C) does not change with temperature. Therefore, when a conventional memory device performs a write operation at high temperature, the channel potential Vch_C of unselected memory cells on the selected word line will gradually decrease from Vch_C1 to Vch_C2 due to the generation of large leakage current, with a large decrease of ΔVch_C. This will affect the unselected memory cells on the same word line and reduce the ability to prevent write disturb. Summary of the Invention

[0004] The present invention provides a writing method for a memory device and a memory system, which can prevent unselected memory cells from being disturbed by writing.

[0005] The memory device write method of the present invention includes the following steps. First, a write command is issued. Next, the width of a pulse to be provided to a memory cell string included in the memory device is determined based on temperature data of the memory device. Finally, a pulse is provided to the memory cell string to perform a write operation. The pulse width decreases as the temperature of the memory device increases.

[0006] The memory system of the present invention includes a memory device, a controller, and a temperature sensor. The memory device includes a memory cell array, an address decoder, a voltage generator, a page buffer, and control logic. The memory cell array includes a plurality of memory cell strings. The address decoder is coupled to the memory cell array. The voltage generator is coupled to the address decoder for generating pulses provided to the memory cell strings. The page buffer is coupled to the memory cell array. The control logic is coupled to the address decoder, the voltage generator, and the page buffer. The controller is coupled to the memory device for issuing a write command to the memory device. The temperature sensor is used to obtain temperature data of the memory device, wherein the temperature sensor is located in the memory device or in the controller. The above-mentioned control logic determines the width of the pulse to be provided to the memory cell strings included in the memory device based on the temperature data of the memory device. The width of the above-mentioned pulse decreases as the temperature of the memory device increases.

[0007] Based on the above, the write method of the memory device of the present invention reduces the width of the pulse applied to the memory cell string as the temperature of the memory device increases. Therefore, when the memory device of the present invention performs a write operation at a high temperature, the decrease in the channel potential of the unselected memory cell is small, so that the memory device of the present invention still has the ability to prevent write interference. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 This is a voltage waveform diagram of a conventional memory device during a write operation.

[0009] Figure 2 A memory system according to an embodiment of the present invention is shown.

[0010] Figure 3 Drawing basis Figure 2 elements in the memory cell array.

[0011] Figure 4 A memory system according to another embodiment of the present invention is shown.

[0012] Figure 5 A flowchart of a writing method for a memory device according to an embodiment of the present invention is shown.

[0013] Figure 6 FIG2 shows voltage waveforms of a memory device according to an embodiment of the present invention when performing a write operation at different temperatures.

[0014] Figure 7 A flowchart of a writing method for a memory device according to another embodiment of the present invention is shown.

[0015]

Explanation of symbols

[0016] 10a, 10b: Memory system

[0017] 100a, 100b: memory devices

[0018] 110: Memory cell array

[0019] 120: Address decoder

[0020] 130: Voltage generator

[0021] 140: Page buffer

[0022] 150: Control Logic

[0023] 200a, 200b: Controller

[0024] 300: Temperature sensor

[0025] BL1~BL m : Bit line

[0026] BW_C, BW_HT, BW_LT, BW_RT: Width

[0027] CS1~CS m :Storage cell string

[0028] CSRC: Shared Source Line

[0029] DSL k DSL k+1 : Drain select line

[0030] MC n 、MCI n : Storage unit

[0031] SGD k , SGD k+1 : Drain select gate transistor

[0032] SGS k 、SGS k+1 : Source select gate transistor

[0033] SSL k , SSL k+1 : Source select line

[0034] TD: Temperature data

[0035] Vch_C, Vch_HT: channel potential

[0036] Vch_C1, Vch_C2, Vch_HT1, Vch_HT2: channel potential values

[0037] ΔVch_C, AVch_HT: Decrease amplitude

[0038] VPASS_C, VPASS_HT, VPASS_LT, VPASS_RT: By pulse

[0039] VPGM_C, VPGM_HT, VPGM_LT, VPGM_RT: Write pulses

[0040] WL n-2 ~WL n+2 :Word line DETAILED DESCRIPTION

[0041] Figure 2 A memory system according to an embodiment of the present invention is shown, and Figure 3 Drawing basis Figure 2 Please also refer to Figure 2 and Figure 3 The memory system 10 a of this embodiment includes a memory device 100 a , a controller 200 a , and a temperature sensor 300 .

[0042] In some embodiments, the memory device 100 a includes a memory cell array 110 , an address decoder 120 , a voltage generator 130 , a page buffer 140 , and control logic 150 .

[0043] The memory cell array 110 includes a plurality of memory cell strings CS1 to CS m , where the storage cell strings CS1~CS m Each of them is connected to bit lines BL1-BL m In some embodiments, a plurality of memory cell strings CS1-CS m Each of the transistors may include a source select gate transistor SGS. k 、SGS k+1 , a plurality of memory cells connected in series with each other and a drain selection gate transistor SGD k SGD k+1 . Source select gate transistor SGS k 、SGS k+1 Each is connected to the source select line SSL k , SSL k+1 , multiple memory cells are each connected to a word line WL n-2 ~WL n+2 , and the drain select gate transistor SGD k SGD k+1 Each is connected to the drain select line DSL k DSL k+1 In addition, the source side of the source selection gate transistor SGSk is connected to the shared source line CSRC, and the drain selection gate transistor SGD kThe drain side of the shared source line CSRC is connected to the corresponding bit line. In some embodiments, the shared source line CSRC is commonly connected to multiple memory cell strings CS1-CS m .

[0044] In some embodiments, the drain select line DSL k DSL k+1 , word line WL n-2 ~WL n+2 and the source select line SSL k , SSL k+1 Controlled by the address decoder 120, the bit lines BL1 to BL m is controlled by the page buffer 140 , and the shared source line CSRC is controlled by the control logic 150 .

[0045] The address decoder 120 is coupled to the memory cell array 110. Specifically, the address decoder 120 receives the drain select line DSL. k DSL k+1 , word line WL n-2 ~WL n+2 and the source select line SSL k , SSL k+1 coupled to the memory cell array 110. In some embodiments, the address decoder 120 is configured to operate under the control of the control logic 150. For example, the address decoder 120 may receive address data from an external source through the control logic 150, where the address data may include a word line address and a bit line address. In some embodiments, the address decoder 120 includes a word line decoder (not shown) and a bit line decoder (not shown).

[0046] The word line decoder may be used to decode the word line address to apply a pulse provided from the voltage generator 130 to the drain select line DSL according to the decoded word line address. k DSL k+1 , word line WL n-2 ~WL n+2 and the source select line SSL k , SSL k+1 For example, during a write operation, the word line decoder may apply a write pulse to the selected word line WL. n , to the word line WL n The selected memory cell MC on n The write operation is performed, and the unselected memory cells (eg memory cell MCI n ) needs to be suppressed, and a pass pulse smaller than the write pulse is applied to the unselected word line WL n-2 、WL n-1 、WL n+1 、WLn+2 The bit line decoder may be used to decode the bit line address to select one of the memory cell columns in the memory cell array 110 according to the decoded bit line address.

[0047] The voltage generator 130 is coupled to the address decoder 120 and is used to generate voltages for the memory cell strings CS1-CS m In some embodiments, the voltage generator 130 includes a plurality of internal power supplies, and activates the plurality of internal power supplies under the control of the control logic 150 to generate a plurality of pulses, wherein the generated plurality of pulses are applied to the word line WL through the address decoder 120. n-2 ~WL n+2 .

[0048] The page buffer 140 is coupled to the memory cell array 110. In some embodiments, the page buffer 140 may include a plurality of bit lines BL1 to BL2. m The plurality of page buffer units (not shown) are connected to each other and operate under the control of the control logic 150. For example, during a write operation, the page buffer 140 receives write data from the control logic 150 and writes data to the selected word line WL when a write pulse is applied to the selected word line WL. n When the page buffer 140 passes the bit lines BL1 to BL m The write data is sent to the selected memory cell.

[0049] The control logic 150 is coupled to the address decoder 120, the voltage generator 130, and the page buffer 140. In some embodiments, the control logic 150 receives a write command and address data from the controller 200a and controls the address decoder 120, the voltage generator 130, and the page buffer 140 in response to the write command. Furthermore, the control logic 150 sends the address data to the address decoder 120.

[0050] The controller 200a is coupled to the memory device 100a and is used to issue a write command to the memory device 100a. In some embodiments, the controller 200a receives a write command from a host device (not shown) to control the memory device 100a.

[0051] The temperature sensor 300 is located in the memory device 100a and is coupled to the control logic 150. The temperature sensor 300 is used to obtain temperature data TD of the memory device 100a. In this embodiment, the temperature sensor 300 senses the temperature of the memory device 100a at specific time intervals and generates temperature data TD. Subsequently, in response to instructions from the control logic 150, the temperature data TD generated by the temperature sensor 300 is supplied to the voltage generator 130 through the control logic 150, so that the voltage generator 130 can generate various pulses based on the temperature data TD.

[0052] In this embodiment, the temperature sensor 300 converts the temperature of the memory device 100a into temperature data TD, where the temperature data TD is an n-bit temperature code, where n is a natural number greater than or equal to 1. The following exemplary embodiments illustrate a case where the temperature data TD is a 3-bit temperature code, but it should be noted that the present invention is not limited thereto.

[0053] [Table 1]

[0054] Temperature code Temperature range of the memory device 100a 000 Less than -45℃ (first temperature value) 001 Greater than -45°C (first temperature value) and less than -15°C (second temperature value) 010 Greater than -15°C (second temperature value) and less than 15°C (third temperature value) 011 Greater than 15°C (third temperature value) and less than 45°C (fourth temperature value) 100 Greater than 45°C (the fourth temperature value) and less than 75°C (the fifth temperature value) 101 Greater than 75°C (fifth temperature value) and less than 105°C (sixth temperature value) 110 Greater than 105°C (sixth temperature value) and less than 135°C (seventh temperature value) 111 Greater than 135℃ (the seventh temperature value)

[0055] As shown in Table 1, when the temperature data TD is a 3-bit temperature code, seven temperature values are selected to divide the temperature range into eighths (2 to the power of 3) for conversion of the temperature data TD. In this embodiment, the seven temperature values are -45°C (first temperature value), -15°C (second temperature value), 15°C (third temperature value), 45°C (fourth temperature value), 75°C (fifth temperature value), 105°C (sixth temperature value), and 135°C (seventh temperature value). Bit 1 of the temperature code is used to determine the relationship between the temperature of the memory device 100a and the fourth temperature value (i.e., 45°C; similar cases are not further described below). For example, when the temperature of the memory device 100a is higher than the fourth temperature value, bit 1 of the temperature code is "1." Conversely, when the temperature of the memory device 100a is lower than the fourth temperature value, bit 1 of the temperature code is "0." Bit 2 of the temperature code is used to determine the relationship between the temperature of the memory device 100a and the second and sixth temperature values. Specifically, when the first bit of the temperature code is "0," the temperature of the memory device 100a is compared to the second temperature value, and when the first bit of the temperature code is "1," the temperature of the memory device 100a is compared to the sixth temperature value. For example, when the temperature of the memory device 100a is higher than the second temperature value or the sixth temperature value, the second bit of the temperature code is "1." Conversely, when the temperature of the memory device 100a is lower than the second temperature value or the sixth temperature value, the first bit of the temperature code is "0." The third bit of the temperature code is used to determine the relationship between the temperature of the memory device 100a and the first, third, fifth, and seventh temperature values. Specifically, when both the first and second bits of the temperature code are "0," the temperature of the memory device 100a is compared with the first temperature value. When the first bit of the temperature code is "0" and the second bit is "1," the temperature of the memory device 100a is compared with the third temperature value. When the first bit of the temperature code is "1" and the second bit is "0," the temperature of the memory device 100a is compared with the fifth temperature value. Furthermore, when both the first and second bits of the temperature code are "1," the temperature of the memory device 100a is compared with the seventh temperature value. For example, when the temperature of the memory device 100a is higher than the first, third, fifth, or seventh temperature value, the third bit of the temperature code is "1." Conversely, when the temperature of the memory device 100a is lower than the first, third, fifth, or seventh temperature value, the third bit of the temperature code is "0."

[0056] For example, when the temperature of memory device 100a is 80°C, its temperature determination is greater than the fourth temperature value, so the first bit of the temperature code is "1." Subsequently, when the first bit of the temperature code is "1," the temperature of memory device 100a is compared with the sixth temperature value, and the determination is less than the sixth temperature value, so the second bit of the temperature code is "0." Next, when the first bit of the temperature code is "1" and the second bit of the temperature code is "0," the temperature of memory device 100a is compared with the fifth temperature value, and the determination is less than the fifth temperature value, so the third bit of the temperature code is "0." Based on this, temperature sensor 300 converts the temperature of memory device 100a to temperature code "100" and supplies it to voltage generator 130 via control logic 150, so that voltage generator 130 generates the desired pulses accordingly. In this embodiment, the widths of the write pulses and pass pulses generated by voltage generator 130 decrease as the temperature of memory device 100a increases. Additionally, in some embodiments, the amplitudes of the write pulses and pass pulses generated by the voltage generator 130 increase as the temperature of the memory device 100a increases. In general, the width or amplitude of the pulses generated by the voltage generator 130 changes with the temperature of the memory device 100a, as will be described in detail in the following embodiments.

[0057] Figure 4 A memory system according to another embodiment of the present invention is shown. It should be noted that Figure 4 The implementation examples follow Figure 2 The component numbers and partial contents of the embodiments are the same or similar numbers are used to represent the same or similar components, and the description of the same technical contents is omitted. For the description of the omitted parts, please refer to the description and effects of the above embodiments, and the following embodiments will not be repeated. Figure 4 For at least a portion of the description of the embodiments that is not omitted, please refer to the subsequent content.

[0058] Please refer to Figure 4 ,exist Figure 4 In the illustrated embodiment, the memory system 10b differs from the memory system 10a in that the temperature sensor 300 of this embodiment is not disposed in the memory device 100b but rather in the controller 200b. In this case, the controller 200b can directly instruct the temperature sensor 300 to obtain the temperature data TD of the memory device 100b. After obtaining the temperature data TD of the memory device 100b, the controller 200b issues a write command to the memory device 100b. In response to the write command, the control logic 150 controls the voltage generator 130 to generate various desired pulses based on the temperature data TD.

[0059] Please refer to Figure 5 , Figure 5A flowchart of a writing method for a memory device according to an embodiment of the present invention is shown. Figure 5 The memory device described herein is taken as an example of the memory device 100 a described above, but it should be noted that the present invention is not limited thereto.

[0060] The memory device write method 500 of this embodiment includes the following steps. First, in step S510, a write command is issued. Then, in step S520, temperature data of the memory device is obtained. Next, in step S530, the width of the pulse to be provided to the memory cell string included in the memory device is determined based on the temperature data of the memory device. Finally, in step S540, a pulse is provided to the memory cell string to perform the write operation. It should be noted that the execution methods of steps S510 and S520 can refer to the above-mentioned embodiments and will not be detailed below.

[0061] Please refer to this synchronously Figure 5 、 Figure 6 and Table 1, where Figure 6 FIG2 shows voltage waveforms of a memory device according to an embodiment of the present invention when performing a write operation at different temperatures.

[0062] When executing step S530, the width of the pulse to be generated by the voltage generator 130 will decrease as the temperature of the memory device 100a increases. For example, if the temperature of the memory device 100a is at a relatively high temperature (e.g., higher than the seventh temperature value), the pulse to be applied to the selected word line WL n The write pulse VPGM_HT is determined to have a width BW_HT and is applied to the unselected word lines WL n-2 、WL n-1 、WL n+1 、WL n+2 The pass pulse VPASS_HT is also determined to have a width BW_HT. If the temperature of the memory device 100a is at room temperature (eg, about the fourth temperature value), the pulse to be applied to the selected word line WL n The write pulse VPGM_RT is determined to have a width BW_RT and is applied to the unselected word lines WL n-2 、WL n-1 、WL n+1 、WL n+2 The pass pulse VPASS_RT is also determined to have a width BW_RT. If the temperature of the memory device 100a is at a relatively low temperature (eg, lower than a first temperature value), the pass pulse VPASS_RT to be applied to the selected word line WL n The write pulse VPGM_LT is determined to have a width BW_LT and is applied to the unselected word line WL n-2 、WL n-1 、WLn+1 、WL n+2 The pass pulse VPASS_LT is also determined to have a width BW_LT. In this embodiment, BW_HT<BW_RT<BW_LT. In addition, in some embodiments, the amplitude of the pulse to be generated by the voltage generator 130 may increase as the temperature of the memory device 100a increases, such as Figure 6 shown.

[0063] The following exemplary embodiments are listed to illustrate the relationship between the temperature of a memory device and the width of a write pulse, but it should be noted that the present invention is not limited thereto.

[0064] [Table 2]

[0065]

[0066]

[0067] The predetermined time in Table 2 is, for example, 10 microseconds, and the compensation value is, for example, 1 microsecond. However, it should be noted that the data in Table 2 are merely illustrative and are not intended to limit the present invention. In general, the width of the write pulse to be generated by the voltage generator 130 of this embodiment decreases as the temperature of the memory device 100a increases.

[0068] When executing step S540, a desired pulse is provided according to the temperature of the memory device 100a. n MC on the storage unit n Perform write operation, so the same word line WL n Storage unit MCI n Need to be suppressed.

[0069] When the temperature of the memory device 100a is at a relatively high temperature during a write operation, the selected word line WL n Receives the write pulse VPGM_HT from the voltage generator 130. During the write operation, the memory cell MCI n The channel potential Vch_HT value of the memory cell MCI decreases from Vch_HT1 to Vch_HT2 due to the generation of leakage current. However, since the width BW_HT of the write pulse VPGM_HT is short (ie, the write time is short), the memory cell MCI n The channel potential Vch_HT of the memory cell MCI is prevented from decreasing due to the influence of the leakage current. n Since the leakage current is greatly affected, the ability to prevent write disturbance is reduced.

[0070] When the memory device 100a is at room temperature and a write operation is performed, the selected word line WL n Receiving the write pulse VPGM_RT from the voltage generator 130, since the memory cell MCI n The channel potential of the memory cell MCI decreases slightly at this temperature and the width BW_RT of the write pulse VPGM_RT does not need to be shortened intentionally. n The ability to prevent write disturb at this temperature is not affected.

[0071] When the temperature of the memory device 100a is relatively low to perform a write operation, the selected word line WL n Receiving the write pulse VPGM_LT from the voltage generator 130, since the memory cell MCI n The channel potential of the memory cell MCI decreases less at this temperature and the width BW_LT of the write pulse VPGM_LT can be increased so that the amplitude of the write pulse VPGM_LT provided by the voltage generator 130 can be reduced. n The ability to prevent write disturbance at this temperature is also not affected. Based on this, when the memory device 100a performs a write operation at a low temperature, the memory cell MCI n The channel potential of the word line WL is less affected by the leakage current, so by increasing the n The width BW_LT of the write pulse VPGM_LT can compensate for the large bias voltage of the memory device 100 a used at a high temperature.

[0072] In addition, the pass pulses VPASS_HT, VPASS_RT, and VPASS_LT also have different widths as the temperature changes. The relationship between them is the same as described in the above embodiment and will not be repeated here.

[0073] Please refer to Figure 7 , Figure 7 A flowchart of a writing method for a memory device according to another embodiment of the present invention is shown. Figure 7 The memory device described herein is based on the memory device 100b described above as an example, but it should be noted that the present invention is not limited thereto. Figure 7 The implementation examples follow Figure 5 The component numbers and partial contents of the embodiments are the same or similar numbers are used to represent the same or similar components, and the description of the same technical contents is omitted. For the description of the omitted parts, please refer to the description and effects of the above embodiments, and the following embodiments will not be repeated. Figure 7 For at least a portion of the description of the embodiments that is not omitted, please refer to the subsequent content.

[0074] Please refer to Figure 7In step S710, the temperature data of the memory device is obtained. Then, in step S720, a write command is issued containing the temperature data of the memory device. Next, in step S730, the width of a pulse to be provided to a memory cell string included in the memory device is determined based on the temperature data of the memory device. Finally, in step S740, a pulse is provided to the memory cell string to perform a write operation.

[0075] The main difference between the writing method 700 of this embodiment and the writing method 500 is that the writing method 700 of this embodiment first obtains the temperature data TD of the memory device 100 b and then issues a write command to the memory device 100 b according to the temperature data TD.

[0076] It is worth noting that the above embodiments of this case can be applied to two-dimensional NAND flash memory or three-dimensional NAND flash memory. In addition, the above embodiments of this case can be applied to single-level cell (SLC), double-level cell (MLC), triple-level cell (TLC), or quad-level cell (QLC).

[0077] In summary, the write method of the memory device of the present invention reduces the width of the pulse applied to the memory cell string as the temperature of the memory device increases. When the memory device of the present invention performs a write operation at a high temperature, the width of the write pulse applied to the selected word line is reduced, thereby increasing the write speed of the selected memory cell. Consequently, the impact of leakage current on unselected memory cells on the same word line is reduced. Specifically, the magnitude of the drop in the channel potential of the unselected memory cells is reduced, thereby maintaining the ability to prevent write disturb. Furthermore, when the memory device of the present invention performs a write operation at a low temperature, the magnitude of the drop in the channel potential of the memory cells is less affected by leakage current. Therefore, the width of the write pulse applied to the selected word line can be increased to compensate for the large bias voltage used in the memory device of the present invention at high temperatures.

Claims

1. A method for writing to a memory device, comprising: Issue a write command; determining a width of a pulse to be provided to a memory cell string included in the memory device according to temperature data of the memory device; as well as providing the pulse to the memory cell string to perform a write operation, The width of the pulse decreases as the temperature of the memory device increases, and the pulse includes a write pulse and a pass pulse, the write pulse is provided to the memory cell string through a selected word line, and the pass pulse is provided to the memory cell string through an unselected word line. 2 . The memory device writing method according to claim 1 , wherein the temperature data of the memory device is obtained after the write command is issued. 3 . The method for writing to a memory device as claimed in claim 1 , wherein the temperature data of the memory device is obtained before the write command is issued. 4 . The writing method of the memory device as claimed in claim 1 , wherein the temperature data of the memory device is an n-bit temperature code, and n is a natural number greater than or equal to 1. 5 . The method for writing to a memory device according to claim 1 , wherein the amplitude of the write pulse increases as the temperature of the memory device increases. 6 . The method for writing to a memory device according to claim 1 , wherein the amplitude of the pass pulse increases as the temperature of the memory device increases.

7. A memory system comprising: A memory device comprising: a memory cell array comprising a plurality of memory cell strings; an address decoder coupled to the memory cell array; a voltage generator, coupled to the address decoder, for generating a pulse provided to the memory cell string; A page buffer coupled to the memory cell array; and a control logic coupled to the address decoder, the voltage generator, and the page buffer; a controller coupled to the memory device and configured to issue a write command to the memory device; and a temperature sensor for obtaining temperature data of the memory device, wherein the temperature sensor is located in the memory device or in the controller; wherein the control logic determines the width of the pulse to be provided to the plurality of memory cell strings included in the memory device according to the temperature data of the memory device, wherein the width of the pulse decreases as the temperature of the memory device increases, The pulses include a write pulse and a pass pulse, wherein the write pulse is provided to the selected memory cell in the memory cell string through a selected word line, and the pass pulse is provided to the unselected memory cells in the memory cell string through an unselected word line. 8 . The memory system of claim 7 , wherein the temperature data of the memory device is an n-bit temperature code, and n is a natural number greater than or equal to 1.

9. The memory system of claim 7, wherein the amplitude of the write pulse increases as the temperature of the memory device increases.

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