Semiconductor Device and Method of Forming the Same

Abstract

A semiconductor device and a method of forming the same are provided. The method includes providing a workpiece having a semiconductor structure; depositing a two-dimensional (2D) material layer over the semiconductor structure; forming source and drain components electrically connected to the semiconductor structure and the 2D material layer, wherein the source and drain components include semiconductor material; and forming a gate structure over the 2D material layer, and the gate structure is between the source and drain components. The gate structure, the source component, the drain component, the semiconductor structure, and the 2D material layer are configured to form a field effect transistor. The semiconductor structure and the 2D material layer serve as a first channel and a second channel, respectively, between the source and drain components.

Description

Technical Field

[0001] Embodiments of the present invention relate to semiconductor devices and methods of forming the same. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced multiple generations of ICs, with each generation having smaller and more complex circuits than the previous one. During the development of ICs, the functional density (i.e., the number of interconnected devices per chip area) generally increases, while the geometric size (i.e., the smallest components (or lines) that can be created using the manufacturing process) decreases.

[0003] This scaling process generally provides benefits by increasing production efficiency and reducing related costs.

[0004] This scaling also increases the complexity of processing and manufacturing ICs.

[0005] For example, as integrated circuit (IC) technology advances to smaller technology nodes, multi-gate devices have been introduced to improve gate control by increasing gate-channel coupling, reducing off-state current, and minimizing short-channel effects (SCEs). A multi-gate device generally refers to a device or a portion thereof having a gate structure disposed above more than one side of a channel region. Fin field-effect transistors (FinFETs) and multi-bridge-channel (MBC) transistors are examples of multi-gate devices, which have become popular and promising candidates for high-performance and low-leakage applications. A FinFET has a raised channel (e.g., a gate wraps around the top and sidewalls of a "fin" of semiconductor material extending from a substrate) that is wrapped by gates on more than one side. An MBC transistor has a gate structure that can partially or fully extend around a channel region to provide access to the channel region on two or more sides. Since its gate structure surrounds the channel region, an MBC transistor can also be referred to as a surround-gate transistor (SGT) or a gate-all-around (GAA) transistor. The channel region of an MBC transistor can be formed of nanowires, nanosheets, other nanostructures, and / or other suitable structures. The shape of the channel region also gives the MBC transistor alternative names, such as a nanosheet transistor or a nanowire transistor. As scaling continues, MBC transistors may not provide satisfactory drive current. Thus, while traditional multi-gate structures are generally adequate for their intended purposes, they are not entirely satisfactory in all respects. Summary of the Invention

[0006] Embodiments of the present invention provide a method of forming a semiconductor device, including: providing a workpiece having a semiconductor structure; depositing a two-dimensional (2D) material layer over the semiconductor structure; forming source and drain components electrically connected to the semiconductor structure and the 2D material layer, wherein the source and drain components include semiconductor material; and forming a gate structure over the 2D material layer, and the gate structure is between the source and drain components, wherein the gate structure, the source component, the drain component, the semiconductor structure, and the 2D material layer are configured to form a field effect transistor, and wherein the semiconductor structure and the 2D material layer serve as a first channel and a second channel, respectively, between the source and drain components.

[0007] Another embodiment of the present invention provides a method of forming a semiconductor device, including: forming a semiconductor stack including first and second semiconductor layers alternately arranged, wherein the first and second semiconductor layers have different compositions; depositing a two-dimensional (2D) material layer on the second semiconductor layer; forming source and drain components electrically connected to the second semiconductor layer and the 2D material layer, wherein the source and drain components include semiconductor material; selectively removing the first semiconductor layer; and forming a gate structure over the 2D material layer, and the gate structure extends to wrap each of the second semiconductor layers.

[0008] Yet another embodiment of the present invention provides a semiconductor device, including: a channel member including a first channel layer and a second channel layer over the first channel layer; a gate structure over the channel member; and source and drain components of semiconductor material, wherein the first channel layer includes silicon, germanium, a III-V semiconductor, or a II-VI semiconductor, wherein the second channel layer includes a 2D material, wherein the 2D material includes graphene, tungsten disulfide (WS2), tungsten telluride (WTe2), tungsten selenide (WSe2), molybdenum disulfide (MoS2), molybdenum telluride (MoTe2), black phosphorus, or molybdenum selenide (MoSe2), and the semiconductor material of the source and drain components is electrically connected to the first and second channel layers. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The present invention is best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale and are for illustrative purposes only. In fact, for clarity of discussion, the dimensions of the various components may be arbitrarily increased or decreased.

[0010] Figure 1A perspective view of a semiconductor device according to one or more aspects of the present invention is shown.

[0011] Figure 2 A flowchart of a first method of manufacturing a semiconductor device according to one or more aspects of the present invention is shown.

[0012] 3A to 3H Shows at various manufacturing stages of the first method according to one or more aspects of the present invention in Figure 2 Partial cross-sectional views of the workpiece are shown.

[0013] Figure 4 A flowchart of a second method of manufacturing a semiconductor device according to one or more aspects of the present invention is shown.

[0014] FIG. 5A to FIG. 5H Shows at various manufacturing stages of the second method according to one or more aspects of the present invention in Figure 4 Partial cross-sectional views of the workpiece are shown.

[0015] Figure 6 A flowchart of a third method of manufacturing a semiconductor device according to one or more aspects of the present invention is shown.

[0016] 7A to 7O Shows at various manufacturing stages of the third method according to one or more aspects of the present invention in Figure 6 Partial cross-sectional views of the workpiece are shown.

[0017] Figure 8 A flowchart of a fourth method of manufacturing a semiconductor device according to one or more aspects of the present invention is shown.

[0018] FIG. 9A to FIG. 9N Shows at various manufacturing stages of the fourth method according to one or more aspects of the present invention in Figure 8 Partial cross-sectional views of the workpiece are shown.

[0019] Fig.10 A flowchart of a fifth method of manufacturing a semiconductor device according to one or more aspects of the present invention is shown.

[0020] FIG. 11A to FIG. 11P Shows at various manufacturing stages of the fifth method according to one or more aspects of the present invention in Fig.10 Partial cross-sectional views of the workpiece are shown.

[0021] Fig.12 A flowchart of a sixth method of manufacturing a semiconductor device according to one or more aspects of the present invention is shown.

[0022] FIG. 13A to FIG. 13O Shows at various manufacturing stages of the sixth method according to one or more aspects of the present invention in Fig.12 Partial cross-sectional views of the workpiece at various manufacturing stages of the sixth method in

[0023] Fig.14 A flowchart showing a seventh method of manufacturing a semiconductor device according to one or more aspects of the present invention.

[0024] FIG. 15A to FIG. 15N Shows, according to one or more aspects of the present invention, in Fig.14 Partial cross-sectional views of the workpiece at various manufacturing stages of the seventh method in

[0025] Fig.16 A flowchart showing an eighth method of manufacturing a semiconductor device according to one or more aspects of the present invention.

[0026] FIG. 17A to FIG. 17P Shows, according to one or more aspects of the present invention, in Fig.16 Partial cross-sectional views of the workpiece at various manufacturing stages of the eighth method in

[0027] Fig.18 A flowchart showing a ninth method of manufacturing a semiconductor device according to one or more aspects of the present invention.

[0028] FIG. 19A to FIG. 19L Shows, according to one or more aspects of the present invention, in Fig.18 Partial cross-sectional views of the workpiece at various manufacturing stages of the ninth method in

[0029] Fig. 20 A cross-sectional view of a semiconductor device according to one or more aspects of the present invention. Detailed Description

[0030] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include embodiments where the first and second components are in direct contact, and may also include embodiments where additional components may be formed between the first and second components such that the first and second components may not be in direct contact. Additionally, the present invention may repeat reference numerals and / or letters in various examples. This repetition is for simplicity and clarity purposes and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0031] In addition, for ease of description, spatial relative terms such as "below", "beneath", "lower", "above", "upper", etc. may be used herein to describe the relationship of one element or component to another as shown in the figures. In addition to the orientation shown in the figures, the spatial relative terms are intended to include different orientations of the device during use or operation. The device may be positioned otherwise (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein may be interpreted accordingly. Further, unless otherwise stated, when a numerical value or numerical range is described with terms such as "about", "approximate", etc., the term is intended to cover values within + / - 10% of the described numerical value. For example, the term "about 5 nm" covers a size range from 4.5 nm to 5.5 nm.

[0032] The present invention generally relates to multi-gate transistors and manufacturing methods, and more particularly to multi-gate transistors having a channel member that includes a second channel layer formed of a two-dimensional material in addition to a first channel layer.

[0033] Multi-gate devices include transistors in which a gate structure is formed on at least two sides of a channel region. Examples of multi-gate devices include fin field-effect transistors (FinFETs) having a fin structure and MBC transistors having multiple channel members. As described above, MBC transistors may also be referred to as SGT, GAA transistors, nanosheet transistors, or nanowire transistors. These multi-gate devices may be n-type or p-type. An MBC transistor includes any device in which its gate structure or a portion thereof is formed on four sides of a channel region (e.g., surrounding a portion of the channel region). The MBC device according to the present invention may have a channel region disposed in a nanowire channel member, a strip channel member, a nanosheet channel member, a nanostructure channel member, a bridge channel member, and / or other suitable channel configurations. As scaling continues, the dimensions of the channel members in MBC transistors may not support a satisfactory drive current level.

[0034] The present invention provides embodiments of a semiconductor device. The channel member of the semiconductor device includes a first channel layer formed of silicon, germanium, a III-V semiconductor, or a II-VI semiconductor, and a second channel layer formed of a two-dimensional (2D) material. The second channel layer is configured to have a bandgap similar to that of the first channel layer. In this way, the first channel layer and the second channel layer can be turned on simultaneously. The second channel layer serves as a drive current booster to increase the overall drive current of the semiconductor device. Due to the implementation of the first channel layer and the second channel layer, the semiconductor device of the present invention can be referred to as a dual-channel transistor (DCT), a dual-channel field-effect transistor (DCFET), or a dual-mode field-effect transistor (DMFET). The DCFET can be a planar device, a FinFET, or an MBC transistor. Embodiments in the FinFET and MBC transistors are shown and described herein.

[0035] Various aspects of the present invention will now be described in more detail with reference to the various figures. Figure 1 A perspective view of a semiconductor device 100 is shown. The semiconductor device 100 can be a FinFET or an MBC transistor. Since the semiconductor device 100 is formed from a workpiece, the semiconductor device 100 can be referred to as the workpiece 100 as needed according to the context. As Figure 1 shown, the semiconductor device 100 includes a substrate 102. In one embodiment, the substrate 102 can be a silicon substrate. In some other embodiments, the substrate 102 can include other semiconductors, such as germanium (Ge), silicon germanium (SiGe), III-V semiconductor materials, or II-VI semiconductor materials. Example III-V semiconductor materials can include gallium arsenide (GaAs), indium phosphide (InP), gallium phosphide (GaP), gallium nitride (GaN), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium phosphide (GaInP), and indium gallium arsenide (InGaAs). Example II-VI semiconductor materials can include cadmium selenide (CdSe), cadmium sulfide (CdS), cadmium telluride (CdTe), zinc selenide (ZnSe), zinc sulfide (ZnS), and zinc telluride (ZnTe).

[0036] Figure 1 The semiconductor device 100 in [reference] includes one or more channel members (104, not shown in [reference], but in Figure 1 [reference], but in Figure 3G [reference], Figure 3H [reference], Figure 5G [reference], Figure 5H [reference], Figure 7M [reference], Figure 9M [reference], Fig.11N [reference], Figure 13M [reference], Figure 15L [reference], Fig.17N [reference], Figure 19L and Fig. 20As shown in [figure reference], the channel member is disposed above the substrate portion 104B extending from the substrate 102. Note that Figure 1 only the substrate portion 104B is shown. Due to the presence of other structures, the channel member is not visible in Figure 1 [figure reference]. One or more channel members and the substrate portion 104B extend longitudinally along the X direction. The semiconductor device 100 further includes an isolation member 106 that isolates adjacent substrate portions 104B. Each substrate portion 104B includes a channel region 104C spanning between two source and drain (or source / drain) regions 104SD. The channel member is disposed above the channel region 104C, and the source and drain (or source / drain) members 108 are disposed above the source / drain regions 104SD. A gate structure extending along the Y direction (perpendicular to the X direction) is disposed above the channel member above the channel region 104C. The gate structure includes a gate stack 110 and a gate spacer layer 118. The gate stack 110 may include an interface layer 112, a high-k dielectric layer 114 disposed above the interface layer 112, and a gate electrode 116 disposed above the high-k dielectric layer 114. In some embodiments, the gate stack 110 may be spaced apart from the source / drain members 108 by the gate spacer layer 118.

[0037] The isolation member 106 may also be referred to as a shallow trench isolation (STI) member 106. The isolation member 106 may include silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), low-k dielectrics, combinations thereof, and / or other suitable materials. The source / drain members 108 may include semiconductor materials doped with an n-type dopant such as phosphorus (P) or arsenide (As) or a p-type dopant such as boron (B). The semiconductor material for the source / drain members 108 may include silicon or silicon germanium. In one embodiment, when the semiconductor device 100 is n-type, the source / drain members 108 may include silicon and may be doped with phosphorus (P). In another embodiment, when the semiconductor device 100 is p-type, the source / drain members 108 may include silicon germanium doped with boron (B).

[0038] The interface layer 112 of the gate stack 110 may include a dielectric material, such as silicon oxide, hafnium silicate, or silicon oxynitride. In some embodiments, in order to better connect the two-dimensional material, the interface layer 112 may include hexagonal boron nitride. The high-k dielectric layer 114 of the gate stack 110 may include a high-k dielectric material, and the dielectric constant of the dielectric material of the high-k dielectric material is greater than the dielectric constant of silicon dioxide (about 3.9). In some cases, the high-k dielectric layer 114 may include a metal oxide or a metal nitride, such as hafnium oxide, zirconium oxide, zirconium oxide aluminum, hafnium aluminum oxide, hafnium silicon oxide, aluminum oxide, titanium oxide, tantalum oxide, lanthanum oxide, yttrium oxide, tantalum carbonitride, zirconium nitride, combinations thereof, or other suitable materials. In some cases, the high-k dielectric layer 114 may have a thickness between about 5nm and about 30nm. The gate electrode 116 of the gate stack 110 may include a single layer or optionally a multilayer structure, such as a metal layer, a liner layer, a wetting layer, an adhesion layer, a metal alloy, or various combinations of metal silicides having a selected work function to enhance device performance (such as reducing the threshold voltage). For example, the gate electrode 116 may include Ti, Ag, Al, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, TiN, TaN, Ru, Mo, Al, WN, Cu, W, Re, Ir, Co, Ni, other suitable metal materials, or combinations thereof. The gate spacer layer 118 is a dielectric layer and may be a single layer or a multilayer. In some cases, the gate spacer layer 118 may include silicon oxide, silicon oxycarbide, silicon carbonitride, silicon nitride, zirconium oxide, aluminum oxide, a suitable low-k dielectric material, or a suitable dielectric material.

[0039] Depending on whether the semiconductor device 100 is a FinFET or an MBC transistor, the channel member 104 may be formed by the substrate 102 alone or by a stack of epitaxial layers on the substrate 102. When the semiconductor device 100 is a FinFET, the channel member 104 may be similar to a fin, such as Figure 3G , Figure 3H , Figure 5G , Figure 5H , Figure 7M , Figure 9M , Figure 19L and Fig. 20 When the semiconductor device 100 is an MBC transistor, the channel member 104 may be similar to a sheet or a line, such as Fig.11N , Figure 13M , Figure 15L and Fig.17N Representatively shown in . Return to reference Figure 1 Regardless of the shape of the channel member 104, the channel member 104 ( Figure 3G , Figure 3H , Figure 5G , Figure 5H , Figure 7M , Figure 9M , Fig.11N , Figure 13M , Figure 15L , Fig.17N , Figure 19L and Fig. 20 extends between two source / drain components 108 on opposite sides of the gate stack 110, as shown in

[0040] According to the present invention, the channel member 104 of the semiconductor device 100 includes one or more layers formed of a two-dimensional (2D) material. Here, the two-dimensional material refers to a thin (i.e., having a thickness between about 1 angstrom and about 30 angstroms) semiconductor material that conducts electricity only along a two-dimensional plane. The two-dimensional material conducts electricity only along a two-dimensional plane because charge carriers (such as electrons) can move freely only along the two-dimensional plane. In some cases, the two-dimensional material may also be referred to as a monolayer material. The present invention provides several embodiments, including Figure 3G , Figure 3H , Figure 5G , Figure 5H , Figure 7M , Figure 9M , Figure 19L and Fig. 20 the FinFET embodiments shown in Fig.11N , Figure 13M , Figure 15L and Fig.17N the MBC transistor embodiments shown in Figure 2 the first method 200 shown in Figure 4 the second method 300 shown in Figure 6 the third method 400 shown in Figure 8 the fourth method 500 shown in Fig.10 the fifth method 600 shown in Fig.12 the sixth method 700 shown in Fig.14 the seventh method 800 shown in Fig.16 the eighth method 900 shown in Fig.18 the ninth method 930 shown in These methods are merely examples and are not intended to limit the present invention to what is expressly set forth therein. Additional steps may be provided before, during, and after these methods, and for additional embodiments of the methods, some of the described steps may be replaced, eliminated, or rearranged. For simplicity, not all steps are described in detail herein. Each of these methods is described below in connection with a local cross-sectional view along the cross-section I-I', J-J', or K-K' shown in Figure 1 3A to 3H In this regard, the first method 200 is described below in connection with FIG. 5A to FIG. 5HDescribe the second method 300. The following will be combined with 7A to 7O Describe the third method 400. The following will be combined with FIG. 9A to FIG. 9N Describe the fourth method 500. The following will be combined with FIG. 11A to FIG. 11P Describe the fifth method 600. The following will be combined with FIG. 13A to FIG. 13O Describe the sixth method 700. The following will be combined with FIG. 15A to FIG. 15N Describe the seventh method 800. The following will be combined with FIG. 17A to FIG. 17P Describe the eighth method 900. The following will be combined with FIG. 19A to FIG. 19L Describe the ninth method 930.

[0041] Figure 2 The flowchart of the first method 200 for manufacturing a FinFET is illustrated. Refer to Figure 2 and Figure 3A , the first method 200 includes a block 202 of providing a workpiece 100. As Figure 3A shown, the workpiece 100 includes a fin structure 103. Figure 3A The fin structure 103 in can be formed from a substrate 102 and continuously extends from the substrate 102. As described above with respect to Figure 1 , the fin structure 103 extends longitudinally along the X direction. In some embodiments, the fin structure 103 may include silicon (Si), germanium (Ge), silicon germanium (SiGe), III-V semiconductor materials, or II-VI semiconductor materials. In some embodiments, the fin structure 103 may be doped with dopants such as phosphorus (P), arsenide (As), or boron (B). The fin structure 103 may have different thicknesses along the Y direction.

[0042] Refer to Figure 2 and Figure 3B , the first method 200 includes a block 204 in which a two-dimensional material layer 1000 is deposited on the workpiece 100. As Figure 3BAs shown, at block 204, a two-dimensional material layer 1000 is deposited over the fin structure 103. In the depicted embodiment, the two-dimensional material layer is a single-layer material, such as a crystalline material composed of a single layer of atoms. In some embodiments, the two-dimensional material layer 1000 may include graphene, tungsten disulfide (WS2), tungsten telluride (WTe2), tungsten selenide (WSe2), molybdenum disulfide (MoS2), molybdenum telluride (MoTe2), molybdenum selenide (MoSe2), black phosphorus, or a suitable two-dimensional material having a substantially band alignment with the semiconductor material of the fin structure 103. Here, the substantially band alignment means that the bandgap of the fin structure 103 and the bandgap of the two-dimensional material overlap. The bandgap of a material refers to the difference between the valence band (Ev) and the conduction band (Ec) of the material. For example, silicon has a valence band of -5.17 eV, a conduction band of -4.05 eV, and a bandgap of 1.12 eV between -5.17 eV and -4.05 eV. Tungsten telluride (WTe2) has a valence band of approximately -4.5 eV, a conduction band of approximately -3.7 eV, and a bandgap of 0.8 eV between -4.5 eV and -3.7 eV. In this example, since the bandgap of tungsten telluride overlaps with the bandgap of silicon, tungsten telluride and silicon have a substantially band alignment. Like the fin structure 103, the two-dimensional material layer may be doped with dopants such as sulfur (S), selenium (Se), tellurium (Te), zirconium (Zr), hafnium (Hf), tungsten (W), molybdenum (Mo), boron (B), oxygen (O), nitrogen (N), carbon (C), silicon (Si), or tin (Sn). Regarding the fin structure 103 and the two-dimensional material layer 1000, the electron confinement due to film thickness and doping may affect the bandgap and thus the band alignment. The present invention contemplates using electron confinement and doping to adjust the bandgap to achieve a band alignment between the fin structure 103 and the two-dimensional material layer 1000. The bandgap alignment between the fin structure 103 and the two-dimensional material can be achieved by doping the two-dimensional material with the aforementioned dopants and / or by doping the fin structure 103 with an n-type dopant (such as phosphorus (P)) or a p-type dopant (such as boron (B)).

[0043] In some embodiments, the two-dimensional material layer 1000 can be deposited over the workpiece 100 by epitaxial growth, chemical vapor deposition (CVD), atomic layer deposition (ALD), or a combination thereof. As Figure 3B shown, since the fin structure 103 and the substrate 102 are formed of the same material, the two-dimensional material layer 1000 is deposited not only on the top surface and sidewalls of the fin structure 103, but also on the top surface of the substrate 102. In some cases, the thickness of the two-dimensional material layer 1000 can be between about 1 angstrom and about 30 angstroms, such as between about 2 angstroms and about 10 angstroms. Compared with silicon, germanium, silicon germanium, III-V semiconductors, or II-VI semiconductors, the two-dimensional material of the two-dimensional material layer 1000 has a higher density of states (DoS) due to its higher inversion charge density (Qinv).

[0044] Refer to Figure 2 and Figure 3C , the first method 200 includes forming a frame 206 of the isolation member 106. In some embodiments, the isolation member 106 may include a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), a low-k dielectric, combinations thereof, and / or other suitable materials. In an exemplary process, the dielectric material of the isolation member 106 is first deposited as a blanket over the workpiece 100 by spin coating or CVD. Thereafter, the blanket-deposited dielectric material is planarized in a planarization process, such as a chemical mechanical polishing (CMP) process. Then, as Figure 3C shown, the planarized dielectric material is selectively recessed or etch-back such that the fin structures 103 rise above the isolation member 106. At the frame 206, since the isolation member 106 is formed after the deposition of the two-dimensional material layer 1000, the isolation member 106 does not directly contact the sidewalls of the base portion 104B and the top surface of the substrate 102. In other words, the isolation member 106 is spaced apart from the base portion 104B and the substrate 102 by the two-dimensional material layer 1000. In Figure 3C , the two-dimensional material layer 1000 and the fin structures 103 not covered by the isolation member 106 may be collectively referred to as the channel member 104.

[0045] Referring to Figure 2 and Figure 3D , the first method 200 includes a frame 208 for forming a dummy gate structure. Although not explicitly shown, the formation of the dummy gate structure (to be described below) may be performed between the formation of the isolation member 106 at the frame 206 and the formation of the source and drain members 108 at the frame 210. In some embodiments, the dummy gate structure includes a dummy gate stack 1002 and a gate spacer layer 118. The formation of the dummy gate structure includes forming a dummy gate stack 1002 over the channel member 104, which further includes depositing a dummy gate material and patterning the dummy gate material to form one or more dummy gate stacks. The frame 208 may also include forming a gate spacer layer 118 on the sidewalls of the dummy gate stack 1002 by depositing the gate spacer layer 118, and etch-back the gate spacer layer 118 by anisotropic etching, such as plasma etching. As Figure 3D shown, in some embodiments employing a back-gate process, the dummy gate stack 1002 may include an interface layer 112, a high-k dielectric layer 114, and a dummy gate electrode 1004, such as a polysilicon layer. In some embodiments employing a back high-k process, the dummy gate stack 1002 may include a dielectric layer such as silicon oxide and a dummy gate electrode 1004 such as a polysilicon layer.

[0046] Referring to Figure 2 and Figure 3E, the first method 200 includes forming a frame 210 of the source / drain component 108. The formation of the source / drain component 108 may include recessing the source / drain region 104SD and epitaxial growth of the source / drain component 108. In particular, the source / drain component 108 includes one or more semiconductor materials to provide better integration with the channel member 104 (specifically, the two-dimensional material layer 1000), while reducing the contact resistance with the channel member 104. This is because the two-dimensional material layer 1000 has a limited thickness and a reduced contact area with the source / drain component. In some embodiments, the source / drain component 108 includes silicon doped with phosphorus or arsenic for an n-type FET or silicon germanium doped with boron for a p-type FET. The formation of the source / drain component 108 will be further described according to various embodiments later. In some embodiments, a portion of the two-dimensional material layer 1000 located below the gate spacer layer 118 may be doped to form a lightly doped source / drain (LDD) component 1010, and the LDD component 1010 may be formed by an ion implantation process implemented between the formation of the dummy gate electrode 1004 and the formation of the gate spacer layer 118. The LDD component 1010 is doped with the same type of dopant as the source / drain component 108, but the dopant concentration is lower than that of the source / drain component 108.

[0047] Reference Figure 2 and Figure 3F, the first method 200 includes block 212, where a gate stack 110 is formed over the channel member 104. As described above, the gate stack 110 may include an interface layer 112, a high-k dielectric layer 114 over the interface layer 112, and a gate electrode 116 over the high-k dielectric layer 114. The interface layer 112 of the gate stack 110 may include a dielectric material, such as silicon oxide, hafnium silicate, or silicon oxynitride. In some embodiments, to better interface with two-dimensional materials, the interface layer 112 may include hexagonal boron nitride. The high-k dielectric layer 114 of the gate stack 110 may include a high-k dielectric material, and the dielectric constant of the dielectric material of the high-k dielectric material is greater than the dielectric constant of silicon dioxide (which is about 3.9). In some cases, the high-k dielectric layer 114 may include hafnium oxide, zirconium oxide, zirconium aluminum oxide, hafnium aluminum oxide, hafnium silicon oxide, aluminum oxide, titanium oxide, tantalum oxide, lanthanum oxide, yttrium oxide, tantalum carbonitride, zirconium nitride, a combination thereof, or other suitable materials. In some cases, the high-k dielectric layer 114 may have a thickness between about 5 nm and about 30 nm. The gate electrode 116 of the gate stack 110 may include a single-layer or an optional multi-layer structure, such as various combinations of a metal layer (work function metal layer) with a selected work function to enhance device performance, a liner layer, a wetting layer, an adhesion layer, a metal alloy, or a metal silicide. For example, the gate electrode 116 may include Ti, Ag, Al, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, TiN, TaN, Ru, Mo, Al, WN, Cu, W, Re, Ir, Co, Ni, other suitable metal materials, or a combination thereof. In some embodiments, the interface layer 112 may be formed by thermal oxidation or deposited using CVD or ALD. The high-k dielectric layer 114 may be deposited using CVD or ALD. The gate electrode 116 may be deposited using physical vapor deposition (PVD), CVD, ALD, or electroless plating. It should be noted that the interface layer 112 and the high-k dielectric layer 114 together serve as the gate dielectric to control the channel member through the gate electrode 116.

[0048] As Figure 3FAs shown, a gate stack 110 is disposed over a channel member 104 that includes a fin structure 103 and a two-dimensional material layer 1000. Due to the substantially aligned energy bands between the two-dimensional material layer 1000 and the fin structure 103, a single threshold voltage at the gate stack 110 can activate the channel in the fin structure 103 as well as the channel in the two-dimensional material layer 1000. In this sense, the fin structure 103 above the isolation member 106 serves as a first channel layer, and the two-dimensional material layer 1000 serves as a second channel layer. The channel formed in the fin structure 103 does not interact with the channel formed in the two-dimensional material layer 1000. This is due to the two-dimensional nature of the two-dimensional material layer 1000. Since the two-dimensional crystal layers of the two-dimensional material layer 1000 are held together by van der Waals forces rather than valence bonds, the bandgap in the direction perpendicular to the two-dimensional crystal plane may be several orders of magnitude larger than the bandgap in the direction of the two-dimensional crystal plane. Since the fin structure 103 is not in the two-dimensional crystal plane, the large bandgap shields the two-dimensional material layer 1000 from the fin structure 103 and vice versa. Thus, although the two-dimensional material layer 1000 is directly formed on the fin structure 103, the fin structure 103 and the two-dimensional material layer 1000 provide two independent channels that can be simultaneously activated by the same gate stack 110. Accordingly, the semiconductor device 100 may be referred to as a dual-channel transistor (DCT), a dual-channel field-effect transistor (DCFET), or a dual-mode field-effect transistor (DMFET). Since current flow is allowed in the channel formed in the fin structure 103 and the channel formed in the two-dimensional material layer 1000, and the two-dimensional material layer 1000 extends along the sidewalls of the fin structure 103, the effective channel width can be increased by about 1.8 to 2 times and the on-current can also be increased by about 1.8 to 2 times compared to a similar semiconductor device that does not have the two-dimensional material layer 1000 in the channel region.

[0049] The formation of the gate stack 110 may include gate replacement, where a dummy gate stack is removed and replaced by the gate stack 110. In some embodiments, the formation of the gate stack 110 may further include other intermediate processes such as depositing a contact etch stop layer (CESL) over the workpiece 100, depositing an interlayer dielectric (ILD) layer over the workpiece 100, planarizing the ILD layer, and removing the dummy gate stack. Removal of the dummy gate stack leaves a gate trench defined by a gate spacer layer 118. The gate stack 110 formed at block 210 is disposed in the gate trench. The formation of the gate stack 110 may further include a CMP process after deposition to fill the gate trench with gate material. The CMP process removes the excess gate material deposited on the ILD layer and planarizes the top surface of the workpiece.

[0050] Now refer to Figure 2 and Figure 3G, the first method 200 includes a block 214 for performing a further process. In some embodiments, such a further process may include forming a source / drain contact (or source / drain metal component) 1006 as shown in Figure 3G , the formation of a gate contact, the formation of another ILD layer, the formation of source / drain contact vias, and the formation of another interconnect structure. The source / drain metal component 1006 may be formed by metal deposition and patterning, and the patterning includes a lithography process and etching. Optionally, the source / drain metal component 1006 may be formed by forming an interlayer dielectric (ILD) layer; patterning the ILD layer to form an opening; depositing one or more metals into the opening of the ILD layer; and performing a CMP process.

[0051] Optionally, as shown in Figure 3H , the semiconductor device 100 may further include a dielectric layer 1008 disposed under the two-dimensional material layer 1000. In particular, the dielectric layer 1008 is interposed between the first channel layer (the fin structure 103 above the isolation component 106) and the second channel layer (the two-dimensional material layer 1000). The dielectric layer 1008 may include silicon oxide, other suitable dielectric materials, or a combination thereof. Figure 3H The semiconductor device 100 with the inserted dielectric layer 1008 in Figure 3H may be formed by any suitable method. In some embodiments, as described below, the first method 200 is modified to form the semiconductor device 100 in Fig.18The frame 934. In this embodiment, the dielectric layer 1008 provides an operating mode in which only the two-dimensional material layer 1000 serves as a single channel for the corresponding transistor. In a further embodiment, only a single 2D channel on an insulator provides device behavior similar to that of a silicon-on-insulator (SOI) device. The dielectric layer 1008 is a buried dielectric layer, such as silicon oxide or other suitable dielectric material, which has an appropriate thickness to suppress the conduction of the bottom silicon plane device (or the second channel) due to its strong short-channel effect (SCE) and is not suitable for scaled MOSFET devices (such as FETs with a gate length less than 15 nm). Accordingly, the corresponding device reduces or eliminates the short-channel problem, especially for scaled field-effect transistors with a gate length less than 15 nm. In some embodiments, the dielectric layer 1008 includes a thickness ranging between 10 nm and 20 nm. In some embodiments where the transistor has only the two-dimensional material layer 1000 as a single-channel layer, the fin structure below the two-dimensional material layer 1000 is a dielectric fin to serve as an isolation component to eliminate the second channel and thus the short-channel problem.

[0052] In some embodiments, the dielectric layer 1008 provides multiple operating modes in which only the two-dimensional material layer 1000 serves as a single channel during low operating voltages and as a dual channel during high operating voltages, depending on the thickness of the dielectric layer 1008 and the magnitude of the high voltage.

[0053] A method similar to the second method 300 shown in Figure 4 can also be used to form the semiconductor device 100. Referring to Figure 4 and Figure 5A , the second method 300 includes a block 302 of providing the workpiece 100. Since the workpiece 100 has been described above with respect to the first method 200, the details of the workpiece 100 are omitted here for brevity.

[0054] Referring to Figure 4 and Figure 5B , the second method 300 includes a block 304 of forming the isolation component 106. Except for forming the isolation component 106 before depositing the two-dimensional material layer 1000, the operations at block 304 are similar to the operations at block 206 in the first method 200. For brevity, the detailed description of the components and formation of the isolation component 106 is omitted here. As shown in Figure 5B , the isolation component 106 is in direct contact with the sidewalls of the substrate portion 104B and the top surface of the substrate 102. No two-dimensional material layer 1000 is provided between the substrate 102 and the isolation component 106.

[0055] Referring to Figure 4 and Figure 5C, the second method 300 includes block 306, where a two-dimensional material layer 1000 is selectively deposited on the fin structure 103. Different from the operation at block 204 of the first method 200, the deposition of the two-dimensional material layer 1000 at block 306 is selective to the fin structure 103, and the two-dimensional material layer 1000 is substantially not formed above the isolation component 106. In some embodiments, the selective deposition can occur at a process temperature at which the two-dimensional material layer 1000 is not deposited on the isolation component 106, and the isolation component 106 has a greater lattice mismatch with the two-dimensional material layer 1000. Instead, the two-dimensional material layer 1000 is selectively deposited on the fin structure 103 that has a smaller lattice mismatch with the two-dimensional material layer 1000. In some embodiments, the two-dimensional material layer 1000 can include graphene, tungsten disulfide (WS2), tungsten telluride (WTe2), tungsten selenide (WSe2), molybdenum disulfide (MoS2), molybdenum telluride (MoTe2), molybdenum selenide (MoSe2), black phosphorus, or a suitable two-dimensional material having a substantially band alignment with the semiconductor material of the fin structure 103. The two-dimensional material layer 1000 can be doped with dopants such as sulfur (S), selenium (Se), tellurium (Te), zirconium (Zr), hafnium (Hf), tungsten (W), molybdenum (Mo), boron (B), oxygen (O), nitrogen (N), carbon (C), silicon (Si)), or tin (Sn). At block 306, epitaxial growth or ALD can be used to deposit the two-dimensional material layer 1000. In Figure 3C , the two-dimensional material layer 1000 and the fin structure 103 not covered by the isolation component 106 can be collectively referred to as the channel member 104. In this case, the two-dimensional material layer 1000 is patterned to align with the pseudo-gate stack during the formation of the pseudo-gate structure in a subsequent stage.

[0056] In some embodiments, the two-dimensional material layer 1000 is formed in the channel region 104C by other suitable processes. A patterned mask is formed on the workpiece 100 through a lithography process and etching. The patterned mask includes an opening aligned with the channel region 104C. Then, the patterned mask is used as an etching mask, and an etching process is applied to the fin structure 103 through the opening of the patterned mask, so as to form a groove on the fin structure within the channel region 104C. Thereafter, the two-dimensional material layer 1000 is deposited in the groove such that the top surface of the two-dimensional material layer 1000 is substantially coplanar with the top surface of the fin structure 103.

[0057] Refer to Figure 4 and Figure 5D, the second method 300 includes forming a frame 308 of a dummy gate structure. Although not explicitly shown, the formation of the dummy gate structure can be performed between the two-dimensional material layer 1000 formed at block 306 and the source and drain components 108 formed at block 310 (which will be described below). In some embodiments, the dummy gate structure includes a dummy gate stack 1002 and a gate spacer layer 118. The formation of the dummy gate structure includes forming a dummy gate stack 1002 over the channel member 104, which further includes depositing a dummy gate material, patterning the dummy gate material through processes including photolithography and etching to form the dummy gate stack 1002, and may also include using a hard mask as an etch mask. Specifically, the patterning of the dummy gate material includes continuing the corresponding etching process to pattern the two-dimensional material layer 1000 such that the two-dimensional material layer 1000 is aligned with the dummy gate stack 1002. In this case, the etching process can include multiple etching steps using different etchants to etch the corresponding material layers including the dummy gate material and the two-dimensional material layer 1000. In some embodiments, after the patterning process to form the dummy gate stack 1002 and the patterned two-dimensional material layer 1000 aligned with the dummy gate stack 1002, epitaxial growth is applied to selectively deposit a semiconductor material layer 1012 such that the semiconductor material layer 1012 selectively grows on the surface of the fin structure 103. As Figure 5E shown, the selective epitaxial growth is controlled such that the semiconductor material layer 1012 grows to a level substantially matching the top surface of the two-dimensional material layer 1000. In this embodiment, the semiconductor material layer 1012 includes the same semiconductor material as the substrate 102, such as silicon.

[0058] As Figure 5D shown, in some embodiments employing a back-gate process (wherein a gate electrode is formed to replace the dummy gate electrode of the dummy gate stack), the dummy gate stack 1002 can include an interface layer 112, a high-k dielectric layer 114, and a dummy gate electrode 1004, such as a polysilicon layer. In some embodiments employing a back high-k process (wherein a gate electrode and a gate dielectric layer are formed to replace the dummy gate stack), the dummy gate stack 1002 can include a dielectric layer (such as silicon oxide) and a dummy gate electrode 1004 (such as a polysilicon layer).

[0059] Block 308 can also include forming LDD components 1010 in the semiconductor material layer 1012 by a suitable method, such as ion implantation. In the depicted embodiment, the formation of the LDD components 1010 is performed after the formation of the dummy gate electrode 1004 and before the formation of the gate spacer layer 118 (which will be described below).

[0060] As Figure 5EAs shown, the box 308 may also include forming a gate spacer layer 118 on the sidewalls of the dummy gate stack 1002 by depositing a gate spacer layer 118, and etch-back etching the gate spacer layer 118 by anisotropic etching such as plasma etching.

[0061] Reference Figure 4 and Figure 5E , the second method 300 includes a box 310 for forming source / drain components 108. The formation of the source / drain components 108 may include recessing the source / drain regions 104SD and epitaxial growth of the source / drain components 108. Specifically, the source / drain components 108 include one or more semiconductor materials to provide better integration with the LDD components 1010 and the channel member 104 (especially the two-dimensional material layer 1000), while reducing the contact resistance with the channel member 104. This is because the two-dimensional material layer 1000 has a limited thickness and the contact area with the source / drain components is reduced. In some embodiments, the source / drain components 108 include silicon doped with phosphorus or arsenic for n-type FETs or silicon germanium doped with boron for p-type FETs.

[0062] Reference Figure 4 and Fig. 5F , the second method 300 includes a box 312, wherein a gate stack 110 is formed above the channel member 104. Since the composition and formation of the gate stack 110 have been described above with respect to the box 212 of the first method 200, for the sake of brevity, the detailed description of the gate stack 110 is omitted here. Similar to Figure 3F the semiconductor device 100 shown, Fig. 5F the gate stack 110 in Fig. 5F is disposed above the channel member 104 including the two-dimensional material layer 1000 and the fin structure 103. The fin structure 103 and the two-dimensional material layer 1000 provide two independent channels, and these two independent channels can be simultaneously activated by the same gate stack 110. For similar reasons,

[0063] Now referring to Figure 4 and Figure 5G , the second method 300 includes a box 314, wherein a further process is performed. In some embodiments, such a further process may include the formation of source / drain contacts 1006, the formation of gate contacts, the formation of another ILD layer, the formation of source / drain contact vias, and the formation of another interconnect structure.

[0064] In other embodiments, a two-dimensional material layer 1000 is formed at block 312. Block 312 includes removing the dummy gate stack 1002 to create a gate trench; recessing the fin structures 103 in the gate trench by etching; selectively depositing a two-dimensional material layer in the gate trench; depositing a gate material to form a gate stack 110; and performing a CMP process.

[0065] Optionally, as Figure 5H shown, the semiconductor device 100 may further include a dielectric layer 1008 disposed under the two-dimensional material layer 1000. In particular, the dielectric layer 1008 is interposed between a first channel layer (the fin structures 103 over the isolation member 106) and a second channel layer (the two-dimensional material layer 1000). The dielectric layer 1008 may include silicon oxide, other suitable dielectric materials, or a combination thereof. Figure 5H The semiconductor device 100 with the inserted dielectric layer 1008 in Figure 5H can be formed by any suitable method. In some embodiments, the second method 300 is modified to form Figure 5H the semiconductor device 100 as described below. Block 306 is modified to include epitaxially growing a silicon germanium layer on a substrate; then depositing the two-dimensional material layer 1000 on the silicon germanium layer. Block 310 includes patterning the fin structures 103 to form trenches in the source / drain regions 104SD; performing a selective etching process to remove the silicon germanium layer through the trenches; depositing a dielectric layer (such as silicon oxide) in the trenches; and then performing epitaxial growth to form the source and drain components 108. The selective etching process may also include selectively oxidizing the silicon germanium layer and selectively etching the oxidized silicon germanium layer. In an alternative embodiment, block 310 includes patterning the fin structures 103 to form trenches in the source / drain regions 104SD; performing a selective oxidation process to oxidize the silicon germanium layer through the trenches, thereby forming silicon germanium oxide as the dielectric layer 1008; and then performing epitaxial growth to form the source and drain components 108. In some embodiments, the dielectric layer 1008 may be formed by another method, such as the method described in method 930, particularly Fig.18 block 934. As described above Figure 3H when the dielectric layer 1008 is present and thick enough, the channel member 104 includes only the two-dimensional material layer 1000 as a single channel, while the bulk semiconductor under the dielectric layer 1008 is suppressed and non-conductive.

[0066] The method of a third method 400 as Figure 6 shown can also be used to form the semiconductor device 100. Referring to Figure 6 , Fig. 7A and Fig. 7E, the third method 400 includes providing a frame 402 for the workpiece 100. Since the workpiece 100 has been described above with respect to the first method 200, for the sake of brevity, the details of the workpiece 100 are omitted here.

[0067] Reference Figure 6 and Figure 7B , the third method 400 includes forming a frame 404 for the isolation member 106. The operation at frame 404 is similar to the operation at frame 304 in the second method 300. For the sake of brevity, the detailed description of the composition and formation of the isolation member 106 is omitted here. As Figure 7B shown, the isolation member 106 is in direct contact with the sidewalls of the base portion 104B and the top surface of the substrate 102. No two-dimensional material layer 1000 is provided between the substrate 102 and the isolation member 106.

[0068] Reference Figure 6 , Figure 7C , Fig.7D and Figure 7F , the third method 400 includes a frame 406, wherein a two-dimensional material layer 1000 is deposited on the fin structure 103 and the isolation member 106. In some embodiments, the deposition at frame 406 is not selective to the fin structure 103, and the two-dimensional material layer 1000 is deposited in a blanket manner on the fin structure 103 and the top surface of the isolation member 106. In some embodiments, the two-dimensional material layer 1000 may include graphene, tungsten disulfide (WS2), tungsten telluride (WTe2), tungsten selenide (WSe2), molybdenum disulfide (MoS2), molybdenum telluride (MoTe2), molybdenum selenide (MoSe2), black phosphorus, or a suitable two-dimensional material having a substantially band alignment with the semiconductor material of the fin structure 103. The two-dimensional material layer 1000 may be doped with dopants such as sulfur (S), selenium (Se), tellurium (Te), zirconium (Zr), hafnium (Hf), tungsten (W), molybdenum (Mo), boron (B), oxygen (O), nitrogen (N), carbon (C), silicon (Si), or tin (Sn). At frame 406, the two-dimensional material layer 1000 may be deposited using epitaxial growth, CVD, or ALD. In a further embodiment, as Fig.7D shown, the two-dimensional material layer 1000 may be further patterned such that a portion of the two-dimensional material layer 1000 provided on the isolation member 106 is removed. The patterning process includes a lithography process and an etching process.

[0069] In some embodiments, as Fig.7D shown, the deposition at frame 406 is selective deposition, which selectively deposits the two-dimensional material layer 1000 on the fin structure 103. In this case, the operation at step 406 is similar to the operation at step 306. For the sake of brevity, the detailed description of the composition and formation of the two-dimensional material layer 1000 is omitted here.

[0070] Reference Figure 6 and Figure 7G The third method 400 includes a block 408 to form a dummy gate structure. In some embodiments, the dummy gate structure includes a dummy gate stack 1002 and a gate spacer layer 118. The formation of the dummy gate structure includes forming the dummy gate stack 1002 over the channel member 104, which further includes depositing a dummy gate material and patterning the dummy gate material through a process including a lithography process and an etching to form the dummy gate stack 1002, and may further include using a hard mask as an etching mask. In some embodiments employing a back-gate process, the dummy gate stack 1002 may include an interface layer 112, a high-k dielectric layer 114, and a dummy gate electrode 1004, such as a polysilicon layer. In some embodiments employing a back high-k process, the dummy gate stack 1102 may include a dielectric layer such as silicon oxide and a dummy gate electrode 1004 such as a polysilicon layer.

[0071] Block 408 may further include forming an LDD component 1010 in the two-dimensional material layer 1000 by a suitable method such as ion implantation. In the depicted embodiment, the formation of the LDD component 1010 is implemented between the formation of the dummy gate stack 1002 and the formation of the gate spacer layer 118 (to be described below). As with the fin structure 103, the two-dimensional material layer may be doped with dopants such as sulfur (S), selenium (Se), tellurium (Te), zirconium (Zr), hafnium (Hf), tungsten (W), molybdenum (Mo), boron (B), oxygen (O), nitrogen (N), carbon (C), silicon (Si), or tin (Sn).

[0072] As Figure 7G shown, block 408 may further include forming the gate spacer layer 118 on the sidewalls of the dummy gate stack 1002 by depositing the gate spacer layer 118, and back-etching the gate spacer layer 118 by anisotropic etching such as plasma etching. The formation of the gate spacer layer 118 is performed after the formation of the LDD component 1010.

[0073] Referring Figure 6 and Figure 7H The third method 400 includes a block 410 to pattern the fin structure 103 to form trenches 1020 within the source / drain regions 104SD. The patterning process applied to the fin structure at block 410 includes a lithography process and an etching and may use a patterned mask as an etching mask. The dummy gate structure also serves as an etching mask during the patterning process such that the trenches 1020 are aligned with the edges of the gate spacer layer 118.

[0074] Referring Figure 6 and Fig.7I, the third method 400 includes a block 412 to form source / drain components 108, such as by epitaxial growth. Specifically, the source / drain components 108 include one or more semiconductor materials to provide better integration with the LDD components 1010 and the channel member 104 (especially the two-dimensional material layer 1000), and to reduce the contact resistance with the channel member 104. This is because the two-dimensional material layer 1000 has a limited thickness and the contact area with the source / drain components is reduced. In some embodiments, the source / drain components 108 include silicon doped with phosphorus or arsenic for n-type FETs or silicon germanium doped with boron for p-type FETs. As Fig.7I shown, in the depicted embodiment, the epitaxial growth is controlled such that the source and drain components 108 are formed to have a top surface that substantially matches the top surface of the dummy gate stack 1002.

[0075] Reference Figure 6 , Figure 7J and Figure 7K , the third method 400 includes a block 414, where a gate stack 110 is formed over the channel member 104. Since the composition and formation of the gate stack 110 have been described above with respect to block 212 of the first method 200, for the sake of brevity, the detailed description of the gate stack 110 is omitted here. Similar to the semiconductor device 100 shown in Figure 3F , the gate stack 110 in Figure 7K is disposed over the channel member 104 including the two-dimensional material layer 1000 and the fin structure 103. The fin structure 103 and the two-dimensional material layer 1000 provide two independent channels, which can be simultaneously activated by the same gate stack 110. For similar reasons, Figure 7K the semiconductor device 100 in

[0076] is a DCFET. Because current flow is allowed in the channels formed in the fin structure 103 and in the two-dimensional material layer 1000, compared to a similar semiconductor device that does not have the two-dimensional material layer 1000 in the channel region, the effective channel width can be increased by approximately between 1.8 times and 2 times, and the on-current can also be increased by approximately between 1.8 and 2 times. Figure 7J shown; and forming as shown in Figure 7KThe gate structure 116 shown. In particular, when the source and drain components 108 extend upward to the top surface of the pseudo-gate stack 1002, the gate trench 1022 is defined by the gate spacer layer 118 and the sidewalls of the source and drain components 108. The formation of the gate stack 110 includes depositing a gate dielectric 1024 and a gate electrode 116; and performing a CMP process that removes the excess gate material disposed on the gate spacer layer 118 and the source and drain components 108 and planarizes the top surface. In some embodiments, the gate dielectric 1024 includes an interface layer 112 and a high-k dielectric layer 114, and the gate electrode 116 includes a plurality of conductive materials, such as a work function metal layer and a fill metal layer. Thus, the source and drain components 108 have a top surface coplanar with the top surface of the gate stack 110.

[0077] Reference Figure 6 and Figure 7L , the third method 400 includes block 416 of performing a further process. In some embodiments, such a further process may include the formation of source / drain contacts 1006, the formation of gate contacts, the formation of another ILD layer, the formation of source / drain contact vias, and the formation of another interconnect structure.

[0078] Figure 7L the semiconductor device 100 in Figure 7M , Figure 7N and Fig.7O is further shown. Figure 7M is a cross-sectional view of the semiconductor device 100, Figure 7N is along the dashed line NN', Figure 7M a cross-sectional view of the semiconductor device 100 in Fig.7O and Figure 7M is a cross-sectional view of the semiconductor device 100 in

[0079] Figure 1 The semiconductor device 100 in Figure 8 can also be formed using the method of a fourth method 500 as shown in Figure 8 , Fig. 9A and Fig. 9C , the fourth method 500 includes block 502 of providing a workpiece 100. Since the workpiece 100 has been described above with respect to the first method 200, the details of the workpiece 100 are omitted here for the sake of brevity.

[0080] Reference Figure 8 and Fig. 9B, the fourth method 500 includes forming a frame 504 of the isolation member 106. The operations at the frame 504 are similar to those at the frame 304 in the second method 300. For the sake of brevity, the detailed description of the components and formation of the isolation member 106 is omitted here. As Fig. 9B shown, the isolation member 106 is in direct contact with the sidewalls of the base portion 104B and the top surface of the substrate 102. No two-dimensional material layer 1000 is provided between the substrate 102 and the isolation member 106.

[0081] Reference Figure 8 and Fig.9D , the fourth method 500 includes a frame 506 for forming a dummy gate structure. In some embodiments, the dummy gate structure includes a dummy gate stack 1002 and a gate spacer layer 118. The formation of the dummy gate structure includes forming a dummy gate stack 1002 over the fin structure 103, which further includes depositing a dummy gate material and patterning the dummy gate material through processes including a lithography process and an etching to form the dummy gate stack 1002, and may also include using a hard mask as an etching mask. In some embodiments employing a back-gate process, the dummy gate stack 1002 may include an interface layer 112, a high-k dielectric layer 114, and a dummy gate electrode 1004, such as a polysilicon layer. In some embodiments employing a back high-k process, the dummy gate stack 1102 may include a dielectric layer such as silicon oxide and a dummy gate electrode 1004 such as a polysilicon layer.

[0082] As Fig.9D shown, the frame 506 further includes forming a gate spacer layer 118 on the sidewalls of the dummy gate stack 1002 by depositing the gate spacer layer 118, and back-etching the gate spacer layer 118 through anisotropic etching (such as plasma etching). The dummy gate stack 1002 and the gate spacer layer 118 are disposed on the fin structure 103 and in direct contact with the fin structure 103.

[0083] Reference Figure 8 and Fig.9E , the fourth method 500 includes a frame 508 for patterning the fin structure 103 to form trenches (recesses) 1020 in the source / drain regions 104SD. The patterning process applied to the fin structure at the frame 410 includes a lithography process and an etching and may use a patterned mask as an etching mask. The dummy gate structure also serves as an etching mask during the patterning process such that the trenches 1020 are aligned with the edges of the gate spacer layer 118.

[0084] Reference Figure 8 and Fig.9F, the fourth method 500 includes a block 510 to form source / drain components 108, such as by epitaxial growth. Specifically, the source / drain components 108 include one or more semiconductor materials. In some embodiments, the source / drain components 108 include silicon doped with phosphorus or arsenic for n-type FETs or silicon germanium doped with boron for p-type FETs. As Fig.9F shown, in the depicted embodiment, the epitaxial growth is controlled such that the source and drain components 108 are formed to have a top surface that substantially matches the top surface of the dummy gate stack 1002.

[0085] Reference Figure 8 and Figure 9G , the fourth method 500 includes a block 512, where the dummy gate stack 1002 is removed by an etching process, creating a gate trench 1022. The gate trench 1022 is defined by the gate spacer layer 118 and the source and drain components 108.

[0086] Reference Figure 8 , Figure 9H and Fig.9I , the fourth method 500 includes a block 514, where a two-dimensional material layer 1000 is deposited on the fin structure 103 having the gate trench 1022. In some embodiments, the operation at block 514 includes further recessing the fin structure 103 within the gate trench 1022 by a suitable etching process. As Figure 9H shown, for example, a KOH solution can be used to recess the fin structure 103, where the top of the fin structure 103 is silicon, thereby forming a recess 1026 of the fin structure in the gate trench 1022.

[0087] The operation at block 514 also includes depositing the two-dimensional material layer 1000 in the recess 1026 of the fin structure 103 by a suitable method, such as selective deposition. Selective deposition selectively deposits the two-dimensional material layer 1000 on the surface of the fin structure 103 and not on other materials, including the gate spacer layer 118. In some embodiments, where the two-dimensional material layer 1000 can additionally be deposited on the top surface of the source and drain components 108, since the source and drain components 108 and the fin structure 103 can include similar or the same materials, such as silicon. Those portions of the two-dimensional material layer 1000 on the source and drain components 108 can be removed anisotropically, but at a subsequent stage, such as during the operation of forming the gate stack 110 (described later) by a CMP process. As Figure 9JAs shown, epitaxial growth can be controlled such that the two-dimensional material layer 1000 substantially fills the recess 1026 and reaches substantially the same height as the fin structure 103 before the recessing process. In some embodiments, the two-dimensional material layer 1000 can include graphene, tungsten disulfide (WS2), tungsten telluride (WTe2), tungsten selenide (WSe2), molybdenum disulfide (MoS2), molybdenum telluride (MoTe2), molybdenum selenide (MoSe2), black phosphorus, or a suitable two-dimensional material having a substantially band alignment with the semiconductor material of the fin structure 103. The two-dimensional material layer 1000 can be doped with dopants such as sulfur (S), selenium (Se), tellurium (Te), zirconium (Zr), hafnium (Hf), tungsten (W), molybdenum (Mo), boron (B), oxygen (O), nitrogen (N), carbon (C), silicon (Si), or tin (Sn). At block 508, the two-dimensional material layer 1000 can be deposited using epitaxial growth, CVD, or ALD.

[0088] Reference Figure 8 and Figure 9J , a fourth method 500 includes block 516, where a gate stack 110 is formed over the channel member 104. In particular, the gate stack including the gate dielectric 1024 and the gate electrode 116 is formed in the gate trench 1022 by deposition. In the depicted embodiment, the gate electrode 116 and the gate dielectric 1024 are aligned with the two-dimensional material layer 1000. Each of the gate electrode 116, the gate dielectric 1024, and the two-dimensional material layer 1000 spans between the inner edges of the gate spacer layer 118 along the X direction. Additionally, according to the depicted embodiment, the top surface of the two-dimensional material layer 1000 is coplanar with the bottom surface of the gate spacer layer 118. Since the gate dielectric 1024 is deposited in the gate trench 1022 and disposed on the bottom surface and sidewalls of the gate trench 1022, the gate dielectric 1024 can be a U-shaped conformal to the profile of the gate trench 1022.

[0089] When the source and drain components 108 extend upward to the top surface of the gate spacer layer 118, the gate trench 1022 is defined by the gate spacer layer 118 and the sidewalls of the source and drain components 108. The formation of the gate stack 110 includes depositing a gate dielectric 1024 and a gate electrode 116; and performing a CMP process that removes the excess gate material disposed on the source and drain components 108 and planarizes the top surface. If the two-dimensional material layer 1000 is disposed on the source and drain components 108, the CMP process may also remove the two-dimensional material layer 1000. In some embodiments, the gate dielectric 1024 includes an interface layer 112 and a high-k dielectric layer 114, and the gate electrode 116 includes a plurality of conductive materials, such as a work function metal layer and a fill metal layer. Thus, the source and drain components 108 have a top surface coplanar with the top surface of the gate stack 110. Since the components and formation of the gate stack 110 have been described above with respect to block 212 of the first method 200, for the sake of brevity, a detailed description of the gate stack 110 is omitted here. Similar to Figure 3F the semiconductor device 100 shown in Figure 9K the gate stack 110 in Figure 9K is disposed above a channel member 104 including a two-dimensional material layer 1000 and a fin structure 103. The fin structure 103 and the two-dimensional material layer 1000 provide two independent channels that can be simultaneously activated by the same gate stack 110. For similar reasons,

[0090] Now referring to Figure 8 and Figure 9K , the fourth method 500 includes block 518 of performing a further process. In some embodiments, such a further process may include the formation of source / drain contacts 1006, the formation of gate contacts, the formation of another ILD layer, the formation of source / drain contact vias, and the formation of another interconnect structure.

[0091] Figure 9L The semiconductor device 100 of Figure 9M and Figure 9N is further shown in Figure 9L is a cross-sectional view of the semiconductor device 100; Figure 9M is a cross-sectional view of the semiconductor device 100 in Figure 9L along the dashed line MM'; and Figure 9N is a cross-sectional view of the semiconductor device 100 in Figure 9LCross-sectional view of the semiconductor device 100 in []. In particular, the gate dielectric 1024 includes an interfacial layer 112 and a high-k dielectric layer 114. The high-k dielectric layer 114 is U-shaped to wrap the gate electrode 116.

[0092] When Figure 1 the semiconductor device 100 in [] is an MBC transistor, the method of the fifth method 600 as shown in [] can also be used to form the semiconductor device 100. Refer to Fig.10 and Fig.10 、 Fig.11A and Fig.11D , the fifth method 600 includes a block 602, where a first stack 1100 is deposited on the substrate 102. As Fig.11A shown, the first stack 1100 includes a plurality of repeating units, and each repeating unit includes a first semiconductor layer 124 and a second semiconductor layer 126. In the Fig.11A shown embodiment, the first stack 1100 includes three repeating units, and each repeating unit has a first semiconductor layer 124 and a second semiconductor layer 126. In some embodiments, the first semiconductor layer 124 can be referred to as a sacrificial layer 124 and can include silicon germanium (SiGe). In some embodiments, the second semiconductor layer 126 can be referred to as a channel layer 126 and can include silicon (Si). At block 602, epitaxial growth can be used to deposit the first semiconductor layer 124 and the second semiconductor layer 126.

[0093] Refer to Fig.10 and Fig. 11B , the fifth method 600 includes a block 604, where the substrate 102 and the first stack 1100 are patterned into a first fin structure 1040. As Fig. 11B shown, the first fin structure 1040 includes a base portion 104B and a top formed by the first stack 1100. The first fin structure 1040 extends longitudinally along the X direction. Thus, the top includes a sacrificial layer 124 and a channel layer 126. In some embodiments, the patterning at block 604 can include an anisotropic etching process, such as a reactive ion etching (RIE) process. An example RIE process can use a fluorocarbon, such as carbon tetrafluoride (CF4), trifluoromethane (CHF3), octafluoropropane (C3H8), or sulfur hexafluoride (SF6).

[0094] Refer to Fig.10 and Fig. 11C , the fifth method 600 includes a block 606 for forming the isolation component 106.

[0095] In some embodiments, the isolation component 106 may include a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), a low-k dielectric, combinations thereof, and / or other suitable materials. In an exemplary process, the dielectric material of the isolation component 106 is first deposited blanket over the workpiece 100 including the first fin structure 1040 by spin coating, CVD, or other suitable deposition methods. Thereafter, the blanket deposited dielectric material is planarized in a planarization process, such as a chemical mechanical polishing (CMP) process. As Fig. 11C shown, the planarized dielectric material is then selectively recessed or back-etched such that only the substrate portion 104B is disposed within the isolation component 106. The isolation component 106 is in direct contact with the sidewalls of the substrate portion 104B and the top surface of the substrate 102.

[0096] Referring Fig.10 and Fig.11E , a fifth method 600 includes forming a frame 608 of a dummy gate structure. In some embodiments, the dummy gate structure includes a dummy gate stack 1002 and a gate spacer layer 118. Forming the dummy gate structure includes forming the dummy gate stack 1002 over the fin structure 103, which further includes depositing the dummy gate material and patterning the dummy gate material through processes including a lithography process and an etching process to form the dummy gate stack 1002, and may also include using a hard mask as an etching mask. In some embodiments employing a back-gate process, the dummy gate stack 1002 may include an interface layer 112, a high-k dielectric layer 114, and a dummy gate electrode 1004, such as a polysilicon layer. In some embodiments employing a back high-k process, the dummy gate stack 1102 may include a dielectric layer such as silicon oxide and a dummy gate electrode 1004 such as a polysilicon layer.

[0097] As Fig.11E shown, the frame 608 further includes forming the gate spacer layer 118 on the sidewalls of the dummy gate stack 1002 by depositing the gate spacer layer 118, and back-etching the gate spacer layer 118 by anisotropic etching, such as plasma etching. The dummy gate stack 1002 and the gate spacer layer 118 are disposed on the first stack 1100 and in direct contact with the first stack 1100.

[0098] Referring Fig.10 and Fig.11F , the fifth method 600 includes a frame 610 to pattern the first stack 1100 to form trenches 1020 within the source / drain regions 104SD. The patterning process applied to the first stack 1100 at the frame 610 includes a lithography process and an etching process, and additionally may use a patterned mask as an etching mask. The dummy gate structure also serves as an etching mask during the patterning process such that the trenches 1020 are aligned with the edges of the gate spacer layer 118.

[0099] Reference Fig.10 and Fig.11G ,The fifth method 600 includes a block 612 to form source / drain components 108, such as by epitaxial growth. Specifically, the source / drain components 108 include one or more semiconductor materials. In some embodiments, the source / drain components 108 include silicon doped with phosphorus or arsenic for n-type FETs or silicon germanium doped with boron for p-type FETs. As Fig.11G shown, in the depicted embodiment, the epitaxial growth is controlled such that the source and drain components 108 are formed to have a top surface higher than the top surface of the first stack 1100, such that the source and drain components 108 are connected to all the second semiconductor layers 126.

[0100] Reference Fig.10 and Fig.11H ,The fifth method 600 includes a block 614 where the dummy gate structure is removed by an etching process to create a gate trench 1022. In particular, at block 614, the dummy gate stack 1002 and the gate spacer layer 118 are removed by one or more etching steps. The gate trench 1022 is defined by the source and drain components 108 and spans between the source and drain components 108.

[0101] At block 614, the first semiconductor layer 124 is selectively removed from the gate trench 1022 to release a plurality of second semiconductor layers 126. In embodiments where the first semiconductor layer 124 is formed of silicon germanium and the second semiconductor layers 126 are formed of silicon, the selective removal of the first semiconductor layer 124 may include a SiGe oxidation process followed by a SiGe oxide removal. In those embodiments, the SiGe oxidation process may include using ozone. In some implementations, the selective removal of the first semiconductor layer 124 may include using a selective isotropic etching process (e.g., a selective dry etching process or a selective wet etching process). In some embodiments, the selective dry etching process may include using one or more fluorine-based etchants, such as fluorine gas or hydrofluorocarbons. In some embodiments, the selective wet etching process may include a hydrofluoride (HF) or NH4OH etchant. As Fig.11D shown, due to the arrangement of the repeating units in the first stack 1100, the removal of the first semiconductor layer 124 (i.e., the sacrificial layer 124) releases a plurality of channel members 104. Each channel member 104 includes a second semiconductor layer 126 (i.e., the channel layer 126).

[0102] Reference Fig.10 and Fig.11I, the fifth method 600 includes block 616, wherein a two-dimensional material layer 1000 is formed on the surface of the second semiconductor layer 126 through a suitable method such as selective deposition through the gate trench 1022. Since the composition and formation of the two-dimensional material layer 1000 have been described above with respect to block 514 of the fourth method 500, for the sake of brevity, the detailed description of the two-dimensional material layer 1000 is omitted here. In particular, the two-dimensional material layer 1000 is formed on the top and bottom surfaces of each second semiconductor layer 126. Thus, each channel member 104 includes a second semiconductor layer 126 (i.e., the channel layer 126) and the two-dimensional material layer 1000 disposed on the top and bottom surfaces of the corresponding second semiconductor layer 126.

[0103] Reference Fig.10 , Fig.11J and Figure 11K , the fifth method 600 includes block 618, wherein a spacer layer 128 is formed on the sidewalls of the source and drain components 108 through the gate trench 1022. The spacer layer 128 includes one or more dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, other suitable dielectric materials, or combinations thereof. The formation of the spacer layer 128 includes the deposition of the spacer layer 128 to fill the gate trench 1022, as Fig.11J shown; and patterning the spacer layer 128 to form various spacers, as Figure 11K shown. In some embodiments, after the deposition of the spacer layer 128, a CMP process may additionally be applied to the spacer layer 128 to planarize the top surface. The patterning process includes a lithography process and etching, and additionally a patterned mask layer may be used. Thus, the width of the spacers can be appropriately controlled. In some embodiments, the patterning of the spacer layer 128 may include an anisotropic etching process applied to the spacer layer 128. Thus, the spacer layer 128 is substantially removed from the two-dimensional material layer 1000, except for the portions located on the sidewalls of the source and drain components 108. Thus, the patterned spacer layer 128 serves as an internal spacer (the portion between the second semiconductor layers 126) and a gate spacer (the portion above one of the top second semiconductor layers 126).

[0104] Reference Fig.10 and Fig.11L, the fifth method 600 includes a block 620 in which a gate stack 110 is formed over and around each of the plurality of channel members 104. As described above, the gate stack 110 includes a gate dielectric 1024 and a gate electrode 116 located over the gate dielectric 1024. In the depicted embodiment, the gate dielectric 1024 may include an interface layer 112 and a high-k dielectric layer 114 located over the interface layer 112. Since the components of the interface layer 112, the high-k dielectric layer 114, and the gate electrode 116 have been described above with respect to block 210 of the first method 200, for the sake of brevity, a detailed description of the interface layer 112, the high-k dielectric layer 114, and the gate electrode 116 is omitted herein. As Fig.11L shown, the gate dielectric 1024 including the interface layer 112 and the high-k dielectric layer 114 may be sequentially deposited around the channel member 104 using CVD or ALD. Then, as Fig.11L shown, the gate electrode 116 may be deposited using PVD, CVD, ALD, or electroless plating. Due to the two-dimensional nature of the two-dimensional material layer 1000 described above, the channel layer 126 in each channel member 104 serves as a first channel layer, while the two-dimensional material layer 1000 in each channel member 104 serves as a second channel layer. Due to the basic band alignment, the first channel layer and the second channel layer may conduct simultaneously and independently. For similar reasons, Fig.11L the semiconductor device 100 in

[0105] is a DCFET. Since current flow is allowed in the channels formed in the channel layer 126 and the channels formed in the two-dimensional material layer 1000, the effective channel width of each channel member 104 may be increased by a factor of between about 1.2 and 1.5, and the on-current may also be increased by a factor of between about 1.2 and 1.5, compared to a similar semiconductor device that does not have the two-dimensional material layer 1000 in the channel region.

[0105] Now referring to Fig.10 and Fig.11M , the fifth method 600 includes a block 622 for performing a further process. In some embodiments, such a further process may include the formation of source / drain contacts 1006, the formation of gate contacts, the formation of another ILD layer, the formation of source / drain contact vias, and the formation of another interconnect structure.

[0106] Fig.11M The semiconductor device 100 in Fig.11N , Fig.11O and Figure 11P is further shown. Fig.11N is a cross-sectional view of the semiconductor device 100; Fig.11O is a cross-sectional view of the semiconductor device 100 in Fig.11N along the dashed line OO'; and Figure 11P is a cross-sectional view of the semiconductor device 100 in Fig.11NCross-sectional view of the semiconductor device 100 in []. In particular, the gate dielectric 1024 includes an interfacial layer 112 and a high-k dielectric layer 114. The high-k dielectric layer 114 is U-shaped to wrap the gate electrode 116.

[0107] The semiconductor device 100 can also be formed using the method of the sixth method 700 as shown in Fig.12 . Referring to Fig.12 , Fig.13A and Fig.13D , the sixth method 700 includes block 702, where a first stack 1100 is deposited on the substrate 102. As shown in Fig.13A , the first stack 1100 includes a plurality of repeating units, and each repeating unit includes a first semiconductor layer 124 and a second semiconductor layer 126. In the embodiment shown in Fig.13A , the first stack 1100 includes three repeating units, and each repeating unit has a first semiconductor layer 124 and a second semiconductor layer 126. In some embodiments, the first semiconductor layer 124 can be referred to as the sacrificial layer 124 and can include silicon germanium (SiGe). In some embodiments, the second semiconductor layer 126 can be referred to as the channel layer 126 and can include silicon (Si). At block 702, epitaxial growth can be used to deposit the first semiconductor layer 124 and the second semiconductor layer 126.

[0108] Referring to Fig.12 and Fig. 13B , the sixth method 700 includes block 704, where the substrate 102 and the first stack 1100 are patterned into a first fin structure 1040. As shown in Fig. 13B , the first fin structure 1040 includes a base portion 104B and a top formed by the first stack 1100. The first fin structure 1040 extends longitudinally along the X direction. Thus, the top includes the sacrificial layer 124 and the channel layer 126. In some embodiments, the patterning of block 604 can include an anisotropic etching process, such as a reactive ion etching (RIE) process. An example RIE process can use a fluorocarbon compound, such as carbon tetrafluoride (CF4), trifluoromethane (CHF3), octafluoropropane (C3H8), or sulfur hexafluoride (SF6).

[0109] Referring to Fig.12 and Fig. 13C , the sixth method 700 includes block 706 for forming the isolation member 106.

[0110] In some embodiments, the isolation component 106 may include a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), low-k dielectric, combinations thereof, and / or other suitable materials. In an exemplary process, the dielectric material of the isolation component 106 is first deposited blanket over the workpiece 100 including the first fin structure 1040 by spin coating, CVD, or other suitable deposition methods. Thereafter, the blanket-deposited dielectric material is planarized in a planarization process, such as a chemical mechanical polishing (CMP) process. As Fig. 13C shown, the planarized dielectric material is then selectively recessed or etched back such that only the substrate portion 104B is disposed within the isolation component 106. The isolation component 106 is in direct contact with the sidewalls of the substrate portion 104B and the top surface of the substrate 102.

[0111] Referring Fig.12 to Fig.13E and Fig.13D , a sixth method 700 includes forming a frame 708 of a dummy gate structure. In some embodiments, the dummy gate structure includes a dummy gate stack 1002 and a gate spacer layer 118. Forming the dummy gate structure includes forming the dummy gate stack 1002 over the fin structure 103, which further includes depositing a dummy gate material and patterning the dummy gate material through procedures including a lithography process and an etching to form the dummy gate stack 1002, and may further include using a hard mask as an etching mask. In some embodiments employing a back-gate process, the dummy gate stack 1002 may include an interface layer 112, a high-k dielectric layer 114, and a dummy gate electrode 1004, such as a polysilicon layer. In some embodiments employing a back high-k process, the dummy gate stack 1002 may include a dielectric layer such as silicon oxide and a dummy gate electrode 1004 such as a polysilicon layer. As

[0112] Referring Fig.12 to Figure 13F and

[0113] ReferringFigure 12 and Figure 13G The sixth method 700 includes block 712 to form an internal spacer 130 on the side of the first semiconductor layer 124. The formation of the internal spacer 130 may include performing a selective etching process on the first semiconductor layer 124 such that the first semiconductor layer 124 is laterally recessed to form an undercut below the gate spacer layer 118. Thereafter, one or more suitable dielectric material layers are deposited in the undercut, and then an anisotropic etching process (such as plasma etching) is performed to remove the excess spacer material deposited on the sidewalls of the second semiconductor layer 126. Thus, the outer edge of the internal spacer 130 is substantially aligned with the edge of the second semiconductor layer 126. The internal spacer layer 130 includes one or more dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, other suitable dielectric materials, or combinations thereof.

[0114] Reference Figure 12 and Figure 13H The sixth method 700 includes block 714 to form source / drain components 108, such as by epitaxial growth. Specifically, the source / drain components 108 include one or more semiconductor materials. In some embodiments, the source / drain components 108 include silicon doped with phosphorus or arsenic for an n-type FET or silicon germanium doped with boron for a p-type FET. As Figure 13H shown, in the depicted embodiment, the epitaxial growth is controlled such that the source and drain components 108 are formed to have a top surface higher than the top surface of the first stack 1100, such that the source and drain components 108 are connected to all of the second semiconductor layers 126 and are separated from the first semiconductor layer 124 by the internal spacer 130.

[0115] Reference Figure 12 and Figure 13I The sixth method 700 includes block 716, where the dummy gate stack 1002 is removed by an etching process, creating a gate trench 1022. In particular, only the dummy gate stack 1002 is removed at block 716, and the gate spacer layer 118 remains. The gate trench 1022 is defined by the gate spacer layer 118 and spans between the gate spacer layers 118.

[0116] At block 716, the first semiconductor layer 124 is selectively removed from the gate trench 1022 to release a plurality of second semiconductor layers 126. In embodiments where the first semiconductor layer 124 is formed of silicon germanium and the second semiconductor layers 126 are formed of silicon, the selective removal of the first semiconductor layer 124 may include a SiGe oxidation process followed by a SiGe oxide removal. In those embodiments, the SiGe oxidation process may include using ozone. In some implementations, the selective removal of the first semiconductor layer 124 may include using a selective isotropic etching process (e.g., a selective dry etching process or a selective wet etching process). In some embodiments, the selective dry etching process may include using one or more fluorine-based etchants such as fluorine gas or hydrofluorocarbon. In some embodiments, the selective wet etching process may include a hydrofluoride (HF) or NH4OH etchant. As Figure 13D shown, due to the arrangement of the repeating units in the first stack 1100, the removal of the first semiconductor layer 124 (i.e., the sacrificial layer 124) releases a plurality of channel members 104. Each channel member 104 includes a second semiconductor layer 126 (i.e., the channel layer 126).

[0117] Referring Figure 12 and Figure 13J , the sixth method 700 includes block 718, where a two-dimensional material layer 1000 is formed on the surface of the second semiconductor layer 126 through the gate trench 1022 by a suitable method such as selective deposition. Since the components and formation of the two-dimensional material layer 1000 have been described above with respect to block 514 of the fourth method 500, for the sake of brevity, the detailed description of the two-dimensional material layer 1000 is omitted here. In particular, the two-dimensional material layer 1000 is formed on the top and bottom surfaces of each second semiconductor layer 126. Thus, each channel member 104 includes a second semiconductor layer 126 (i.e., the channel layer 126) and a two-dimensional material layer 1000 disposed on the top and bottom surfaces of the corresponding second semiconductor layer 126. Different from the two-dimensional material layer 1000 in Figure 11I , the two-dimensional material layer 1000 in Figure 13J spans between the inner spacers 130 along the X direction and does not extend to the interface between the inner spacer 130 and the second semiconductor layer 126.

[0118] Referring Figure 12 and Figure 13K, the sixth method 700 includes block 720, where a gate stack 110 is formed above and around each of the plurality of channel members 104. As described above, the gate stack 110 includes a gate dielectric 1024 and a gate electrode 116 located above the gate dielectric 1024. In the depicted embodiment, the gate dielectric 1024 may include an interface layer 112 and a high-k dielectric layer 114 located above the interface layer 112. Since portions of the interface layer 112, the high-k dielectric layer 114, and the gate electrode 116 have been described above with respect to block 210 of the first method 200, for the sake of brevity, the detailed description of the interface layer 112, the high-k dielectric layer 114, and the gate electrode 116 is omitted here. The gate dielectric 1024 including the interface layer 112 and the high-k dielectric layer 114 may be sequentially deposited around the channel member 104 using CVD or ALD. Then, as Figure 13K shown, the gate electrode 116 may be deposited using PVD, CVD, ALD, or electroless plating. Due to the two-dimensional nature of the two-dimensional material layer 1000 described above, the channel layer 126 in each channel member 104 serves as the first channel layer, and the two-dimensional material layer 1000 in each channel member 104 serves as the second channel layer. Due to the basic band alignment, the first channel layer and the second channel layer can conduct simultaneously and independently. For similar reasons, Figure 13K the semiconductor device 100 in

[0119] is a DCFET. Since current flow is allowed in the channels formed in the channel layer 126 and the channels formed in the two-dimensional material layer 1000, the effective channel width of each channel member 104 can be increased by about 1.2 to 1.5 times, and the on-current can also be increased by about 1.2 to 1.5 times, compared to a similar semiconductor device that does not have the two-dimensional material layer 1000 in the channel region.

[0119] Now referring to Figure 12 and Figure 13L , the sixth method 700 includes block 722 for performing a further process. In some embodiments, such a further process may include the formation of source / drain contacts 1006, the formation of gate contacts, the formation of another ILD layer, the formation of source / drain contact vias, and the formation of another interconnect structure. Since the operations at block 722 are similar to the operations at block 622, for the sake of brevity, the detailed description of the operations at block 722 is omitted.

[0120] Figure 13L The semiconductor device 100 in Figure 13M , Figure 13N and Figure 13O is further shown. Figure 13M is a cross-sectional view of the semiconductor device 100; Figure 13N is a cross-sectional view of the semiconductor device 100 in Figure 13M along the dashed line NN'; and Figure 13Oalong the dashed line OO’ Figure 13M is a cross-sectional view of the semiconductor device 100 in

[0121] The semiconductor device 100 can also be formed using the method of the seventh method 800 as shown in Figure 14 In the method 800, a two-dimensional material layer 1000 is deposited and incorporated in a semiconductor stack. Referring to Figure 14 , Figure 15A and Figure 15D , the seventh method 800 includes block 802, where a second stack 1200 is deposited on a substrate 102. As shown in Figure 15A and Figure 15D , the second stack 1200 includes a plurality of repeating units, each repeating unit including a first semiconductor layer 124, a two-dimensional material layer 1000 above the first semiconductor layer, a second semiconductor layer 126 above the two-dimensional material layer 1000, and another two-dimensional material layer 1000 above the second semiconductor layer 126. In other words, each second semiconductor layer 126 is directly sandwiched between two two-dimensional material layers. In the embodiment shown in Figure 15A , the second stack 1200 includes three repeating units, each repeating unit having a second semiconductor layer 126 sandwiched between two two-dimensional material layers 1000, and adjacent two-dimensional material layers 1000 are spaced apart by the first semiconductor layer 124. In some embodiments, the first semiconductor layer 124 can be referred to as a sacrificial layer 124 and can include silicon germanium (SiGe), and the second semiconductor layer 126 can be referred to as a channel layer 126 and can include silicon (Si). In some embodiments, the two-dimensional material layer 1000 can include graphene, tungsten disulfide (WS2), tungsten telluride (WTe2), tungsten selenide (WSe2), molybdenum disulfide (MoS2), molybdenum telluride (MoTe2), molybdenum selenide (MoSe2), black phosphorus, or a suitable two-dimensional material having a substantially band alignment with the semiconductor material of the second semiconductor layer 126. The two-dimensional material layer 1000 can be doped with dopants such as sulfur (S), selenium (Se), tellurium (Te), zirconium (Zr), hafnium (Hf), tungsten (W), molybdenum (Mo), boron (B), oxygen (O), nitrogen (N), carbon (C), silicon (Si), or tin (Sn). At block 802, the first semiconductor layer 124, the second semiconductor layer 126, and the two-dimensional material layer 1000 can be deposited using epitaxial growth.

[0122] Referring to Figure 14 and Figure 15B , the seventh method 800 includes block 804, where the substrate 102 and the second stack 1200 are patterned into a second fin structure 1042. As shown in Figure 15BAs shown, the second fin structure 1042 includes a base portion 104B and a top formed by the second stack 1200. The second fin structure 1042 extends longitudinally along the X direction. The top thus includes a sacrificial layer 124, a channel layer 126, and a two-dimensional material layer 1000 sandwiching the channel layer 126. In some embodiments, the patterning at block 804 may include an anisotropic etching process, such as a reactive ion etching (RIE) process. Example RIE processes may use fluorocarbons, such as carbon tetrafluoride (CF4), trifluoromethane (CHF3), octafluoropropane (C3H8), or sulfur hexafluoride (SF6).

[0123] Reference Figure 14 and Figure 15C , the seventh method 800 includes forming a block 806 of the isolation component 106. Since the operations at block 806 are similar to those at block 706, for the sake of brevity, the detailed description of the operations at block 806 is omitted.

[0124] Reference Figure 14 and Figure 15E , the seventh method 800 includes a block 808 to form a dummy gate structure. In some embodiments, the dummy gate structure includes a dummy gate stack 1002 and a gate spacer layer 118. The formation of the dummy gate structure includes forming a dummy gate stack 1002 over the fin structure 103, which further includes depositing a dummy gate material and patterning the dummy gate material to form the dummy gate stack 1002. In some embodiments employing a back-gate process, the dummy gate stack 1002 may include an interface layer 112, a high-k dielectric layer 114, and a dummy gate electrode 1004, such as a polysilicon layer. In some embodiments employing a back high-k process, the dummy gate stack 1102 may include a dielectric layer such as silicon oxide and a dummy gate electrode 1004 such as a polysilicon layer. As Figure 15E shown, block 808 also includes forming a gate spacer layer 118 on the sidewalls of the dummy gate stack 1002 by depositing the gate spacer layer 118, and back-etching the gate spacer layer 118 by anisotropic etching (such as plasma etching). The dummy gate stack 1002 and the gate spacer layer 118 are disposed on the second stack 1200 and in direct contact with the second stack 1200.

[0125] Reference Figure 14 and Figure 15F , the seventh method 800 includes a block 810 to pattern the second stack 1200 to form trenches 1020 in the source / drain regions 104SD. The dummy gate structure also serves as an etch mask during the patterning process, such that the trenches 1020 are aligned with the edges of the gate spacer layer 118.

[0126] Reference Figure 14 and Figure 15G, the seventh method 800 includes block 812 to form an inner spacer 130 on the side of the first semiconductor layer 124. The formation of the inner spacer 130 may include performing a selective etching process on the first semiconductor layer 124 such that the first semiconductor layer 124 is recessed laterally to form an undercut below the gate spacer layer 118. Thereafter, one or more suitable dielectric material layers are deposited in the undercut, and then an anisotropic etching process (such as plasma etching) is performed to remove the excess spacer material deposited on the sidewalls of the second semiconductor layer 126. Thus, the outer edge of the inner spacer 130 is substantially aligned with the edge of the second semiconductor layer 126. The inner spacer layer 130 includes one or more dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, other suitable dielectric materials, or combinations thereof.

[0127] Reference Figure 14 and Figure 15H , the seventh method 800 includes block 814 to form source / drain components 108, such as by epitaxial growth. Specifically, the source / drain components 108 include one or more semiconductor materials. In some embodiments, the source / drain components 108 include silicon doped with phosphorus or arsenic for n-type FETs or silicon germanium doped with boron for p-type FETs. As Figure 15H shown, in the depicted embodiment, the epitaxial growth is controlled such that the source and drain components 108 are formed to have a top surface higher than the top surface of the second stack 1200, such that the source and drain components 108 are connected to the second semiconductor layer 126 and separated from the first semiconductor layer 124 by the inner spacer 130.

[0128] Reference Figure 14 and Figure 15I , the seventh method 800 includes block 816, where the dummy gate stack 1002 is removed by an etching process, creating a gate trench 1022. In particular, only the dummy gate stack 1002 is removed at block 816, and the gate spacer layer 118 remains. The gate trench 1022 is defined by the gate spacer layer 118 and spans between the gate spacer layers 118.

[0129] At block 816, the first semiconductor layer 124 is selectively removed from the gate trench 1022 to release a plurality of second semiconductor layers 126. In embodiments where the first semiconductor layer 124 is formed of silicon germanium and the second semiconductor layers 126 are formed of silicon, the selective removal of the first semiconductor layer 124 may include a SiGe oxidation process followed by a SiGe oxide removal. In those embodiments, the SiGe oxidation process may include using ozone. In some implementations, the selective removal of the first semiconductor layer 124 may include using a selective isotropic etching process (e.g., a selective dry etching process or a selective wet etching process). In some embodiments, the selective dry etching process may include using one or more fluorine-based etchants such as fluorine gas or hydrofluorocarbon. In some embodiments, the selective wet etching process may include a hydrofluoride (HF) or NH4OH etchant. As Figure 15D shown, due to the arrangement of the repeating units in the second stack 1200, the removal of the first semiconductor layer 124 (i.e., the sacrificial layer 124) releases a plurality of channel members 104. Each channel member 104 includes a second semiconductor layer 126 (i.e., the channel layer 126).

[0130] Referring Figure 14 and Figure 15J , the seventh method 800 includes block 818, where a gate stack 110 is formed above and around each of the plurality of channel members 104. As described above, the gate stack 110 includes a gate dielectric 1024 and a gate electrode 116 located above the gate dielectric 1024. In the depicted embodiment, the gate dielectric 1024 may include an interface layer 112 and a high-k dielectric layer 114 located above the interface layer 112. Since the components of the interface layer 112, the high-k dielectric layer 114, and the gate electrode 116 have been described above with respect to block 210 of the first method 200, for the sake of brevity, the detailed descriptions of the interface layer 112, the high-k dielectric layer 114, and the gate electrode 116 are omitted here. The gate dielectric 1024 including the interface layer 112 and the high-k dielectric layer 114 may be sequentially deposited around the channel members 104 using CVD or ALD. Then, as Figure 15J shown, the gate electrode 116 may be deposited using PVD, CVD, ALD, or electroless plating. Due to the two-dimensional nature of the two-dimensional material layer 1000 described above, the channel layer 126 in each channel member 104 serves as a first channel layer, while the two-dimensional material layer 1000 in each channel member 104 serves as a second channel layer. Due to the basic band alignment, the first channel layer and the second channel layer can conduct simultaneously and independently. For similar reasons, Figure 15KThe semiconductor device 100 therein is a DCFET. Since current flow is allowed in the channels formed in the channel layer 126 and in the channels formed in the two-dimensional material layer 1000, the effective channel width of each channel member 104 can be increased by about 1.2 times to 1.5 times, and the on-current can also be increased by between about 1.2 times and 1.5 times, as compared to a similar semiconductor device that does not have the two-dimensional material layer 1000 in the channel region.

[0131] Now referring to Figure 14 and Figure 15K , the seventh method 800 includes a block 820 of performing a further process. In some embodiments, such a further process may include forming source / drain contacts 1006, forming gate contacts, forming another ILD layer, forming source / drain contact vias, and forming another interconnect structure. Since the operations at block 820 are similar to the operations at block 622, for the sake of brevity, the detailed description of the operations at block 820 is omitted.

[0132] Figure 15K The semiconductor device 100 of Figure 15L , Figure 15M and Figure 15N is further shown in Figure 15L is a cross-sectional view of the semiconductor device 100; Figure 15M is the semiconductor device 100 in Figure 15L along the dashed line MM'; and Figure 15N is the semiconductor device 100 in Figure 15L along the dashed line NN'. In particular, the gate dielectric 1024 includes an interface layer 112 and a high-k dielectric layer 114. The high-k dielectric layer 114 is U-shaped to wrap the gate electrode 116.

[0133] The semiconductor device 100 can also be formed using the method of an eighth method 900 as shown in Figure 16 . In the method 900, the inner spacers are formed by different methods and in a different order. Referring to Figure 16 , Figure 17A and Figure 17D , the eighth method 900 includes a block 902, where a second stack 1200 is deposited on a substrate 102. As shown in Figure 17A and Figure 17D , the second stack 1200 includes a plurality of repeating units, each repeating unit including a first semiconductor layer 124, a two-dimensional material layer 1000 located above the first semiconductor layer, a second semiconductor layer 126 located above the two-dimensional material layer 1000, and another two-dimensional material layer 1000 located above the second semiconductor layer 126. In other words, each second semiconductor layer 126 is directly sandwiched between two two-dimensional material layers. In Figure 17AIn the illustrated embodiment, the second stack 1200 includes three repeating units, each repeating unit having a second semiconductor layer 126 sandwiched between two two-dimensional material layers 1000, and adjacent two-dimensional material layers 1000 are spaced apart by a first semiconductor layer 124. In some embodiments, the first semiconductor layer 124 may be referred to as a sacrificial layer 124 and may include silicon germanium (SiGe), and the second semiconductor layer 126 may be referred to as a channel layer 126 and may include silicon (Si). In some implementations, the two-dimensional material layer 1000 may include graphene, tungsten disulfide (WS2), tungsten telluride (WTe2), tungsten selenide (WSe2), molybdenum disulfide (MoS2), molybdenum telluride (MoTe2), molybdenum selenide (MoSe2), black phosphorus, or a suitable two-dimensional material having a substantially band alignment with the semiconductor material of the second semiconductor layer 126. The two-dimensional material layer 1000 may be doped with dopants such as sulfur (S), selenium (Se), tellurium (Te), zirconium (Zr), hafnium (Hf), tungsten (W), molybdenum (Mo), boron (B), oxygen (O), nitrogen (N), carbon (C), silicon (Si), or tin (Sn). At block 902, epitaxial growth may be used to deposit the first semiconductor layer 124, the second semiconductor layer 126, and the two-dimensional material layer 1000.

[0134] Reference Figure 16 and Figure 17B , the eighth method 900 includes block 904, where the substrate 102 and the second stack 1200 are patterned into a second fin structure 1042. As Figure 17B shown, the second fin structure 1042 includes a base portion 104B and a top formed by the second stack 1200. The second fin structure 1042 extends longitudinally along the X direction. The top thus includes the sacrificial layer 124, the channel layer 126, and the two-dimensional material layer 1000 sandwiching the channel layer 126. In some embodiments, the patterning at block 904 may include an anisotropic etching process such as a reactive ion etching (RIE) process. An example RIE process may use a fluorocarbon such as carbon tetrafluoride (CF4), trifluoromethane (CHF3), octafluoropropane (C3H8), or sulfur hexafluoride (SF6).

[0135] Reference Figure 16 and Figure 17C , the eighth method 900 includes block 906 of forming an isolation component 106. Since the operation of block 906 is similar to the operation of block 706, for the sake of brevity, the detailed description of the operation at block 906 is omitted.

[0136] Reference Figure 16 and Figure 17E, the eighth method 900 includes block 908 to form a dummy gate structure. In some embodiments, the dummy gate structure includes a dummy gate stack 1002 and a gate spacer layer 118. Forming the dummy gate structure includes forming a dummy gate stack 1002 over the fin structure 103, which further includes depositing a dummy gate material and patterning the dummy gate material to form the dummy gate stack 1002. In some embodiments employing a back-gate process, the dummy gate stack 1002 may include an interface layer 112, a high-k dielectric layer 114, and a dummy gate electrode 1004, such as a polysilicon layer. In some embodiments employing a back high-k process, the dummy gate stack 1102 may include a dielectric layer such as silicon oxide and a dummy gate electrode 1004 such as a polysilicon layer. As Figure 17E shown, block 908 also includes forming a gate spacer layer 118 on the sidewalls of the dummy gate stack 1002 by depositing the gate spacer layer 118, and etch-back etching the gate spacer layer 118 by anisotropic etching (such as plasma etching). The dummy gate stack 1002 and the gate spacer layer 118 are disposed on the second stack 1200 and in direct contact with the second stack 1200.

[0137] Reference Figure 16 and Figure 17F , the eighth method 900 includes block 910 to pattern the second stack 1200 to form trenches 1020 within the source / drain regions 104SD. The dummy gate structure also serves as an etch mask during the patterning process such that the trenches 1020 are aligned with the edges of the gate spacer layer 118.

[0138] Reference Figure 16 , Figure 17G and Figure 17H , the eighth method 900 includes block 912 to form the LDD component 1010 through the trenches 1020 in the source / drain regions 104SD. As Figure 17G shown, forming the LDD component 1010 includes performing an etching process to laterally recess the channel member including the second semiconductor layer 126 and the two-dimensional material layer 1000, thereby forming an undercut below the gate spacer layer 118. The etching process uses an etchant to selectively etch the second semiconductor layer 126 and the two-dimensional material layer 1000. Note that the lateral recess is designed to laterally recess the channel member 104 rather than the sacrificial layer (the first semiconductor layer 124). As Figure 17HAs shown, the box 912 further includes depositing a semiconductor material to fill the undercut, thereby forming the LDD component 1010. In the depicted embodiment, the semiconductor material includes silicon. The deposition includes selective epitaxial growth with in-situ doping to form the LDD component 1010 having an appropriate dopant (such as phosphorus for nFET or boron for pFET) and doping dose. For example, the epitaxial growth uses precursors including a silicon-containing gas and a dopant-containing gas having a certain partial pressure to achieve the desired doping concentration of the LDD component 1010, and the desired doping concentration is less than the doping concentration of the source and drain components 108 (formed later). Optionally, the epitaxial growth is not selective to the first semiconductor layer 124, and the semiconductor material can be formed on the first semiconductor layer 124. In this case, an anisotropic etching process, such as plasma etching, can be applied later to remove the excess semiconductor material deposited on the sidewalls of the first semiconductor layer 124.

[0139] Reference Figure 16 and Figure 17I , the eighth method 900 includes a box 914 to form the source / drain components 108, such as by epitaxial growth. Specifically, the source / drain components 108 include one or more semiconductor materials. In some embodiments, the source / drain components 108 include silicon doped with phosphorus or arsenic for n-type FETs or silicon germanium doped with boron for p-type FETs. As Figure 17I shown, in the depicted embodiment, the epitaxial growth is controlled such that the source and drain components 108 are formed to have a top surface higher than the top surface of the second stack 1200, such that the source and drain components 108 are connected to all the second semiconductor layers 126 and are separated from the first semiconductor layer 124 by the internal spacer 130.

[0140] Reference Figure 16 and Figure 17J , the eighth method 900 includes a box 916, where the dummy gate structure is removed by an etching process, generating the gate trench 1022. Specifically, the dummy gate stack 1002 and the gate spacer layer 118 are removed at the box 916. The gate trench 1022 is defined by the source and drain components 108 and spans between the source and drain components 108.

[0141] At block 916, the first semiconductor layer 124 is selectively removed from the gate trench 1022 to release a plurality of second semiconductor layers 126. In an embodiment where the first semiconductor layer 124 is formed of silicon germanium and the second semiconductor layers 126 are formed of silicon, the selective removal of the first semiconductor layer 124 may include a SiGe oxidation process followed by a SiGe oxide removal. In those embodiments, the SiGe oxidation process may include using ozone. In some implementations, the selective removal of the first semiconductor layer 124 may include using a selective isotropic etching process (e.g., a selective dry etching process or a selective wet etching process). In some embodiments, the selective dry etching process may include using one or more fluorine-based etchants such as fluorine gas or hydrofluorocarbon. In some embodiments, the selective wet etching process may include a hydrofluoride (HF) or NH4OH etchant. As Figure 17D shown, due to the arrangement of the repeating units in the second stack 1200, the removal of the first semiconductor layer 124 (i.e., the sacrificial layer 124) releases a plurality of channel members 104. Each channel member 104 includes a second semiconductor layer 126 (i.e., the channel layer 126).

[0142] Reference Figure 16 and Figure 17K , the eighth method 900 includes block 918 to form a spacer layer 132 on the sidewalls of the source and drain members 108. The portion of the spacer layer 132 located between the channel members 104 is referred to as an inner spacer, and the portion located above the second stack 1200 is referred to as a gate spacer. The formation of the spacer layer 132 may include depositing a dielectric layer in the gate trench; and performing an anisotropic etching process on the spacer layer 132 such that only the portions on the sidewalls of the source and drain members 108 are retained. The spacer layer 132 includes one or more dielectric materials such as silicon oxide, silicon nitride, silicon oxynitride, other suitable dielectric materials, or combinations thereof.

[0143] Reference Figure 16 and Figure 17L, the eighth method 900 includes block 920 where a gate stack 110 is formed above and around each of the plurality of channel members 104. As described above, the gate stack 110 includes a gate dielectric 1024 and a gate electrode 116 located above the gate dielectric 1024. In the depicted embodiment, the gate dielectric 1024 may include an interface layer 112 and a high-k dielectric layer 114 located above the interface layer 112. Since the components of the interface layer 112, the high-k dielectric layer 114, and the gate electrode 116 have been described above with respect to block 210 of the first method 200, for the sake of brevity, the detailed description of the interface layer 112, the high-k dielectric layer 114, and the gate electrode 116 is omitted here. The gate dielectric 1024 including the interface layer 112 and the high-k dielectric layer 114 can be sequentially deposited around the channel member 104 using CVD or ALD. Then, as Figure 17L shown, the gate electrode 116 can be deposited using PVD, CVD, ALD, or electroless plating. Due to the two-dimensional nature of the above-described two-dimensional material layer 1000, the channel layer 126 in each channel member 104 serves as the first channel layer, while the two-dimensional material layer 1000 in each channel member 104 serves as the second channel layer. Due to the basic band alignment, the first channel layer and the second channel layer can conduct simultaneously and independently. For similar reasons, Figure 17L the semiconductor device 100 in

[0144] is a DCFET. Since current flow is allowed in the channels formed in the channel layer 126 and in the channels formed in the two-dimensional material layer 1000, the effective channel width of each channel member 104 can be increased by approximately between 1.2 times and 1.5 times, and the on-current can also be increased by approximately between 1.2 times and 1.5 times, compared to a similar semiconductor device that does not have the two-dimensional material layer 1000 in the channel region.

[0144] Now referring to Figure 16 and Figure 17M , the eighth method 900 includes block 922 for performing a further process. In some embodiments, such a further process may include the formation of source / drain contact members 1006, the formation of gate contacts, the formation of another ILD layer, the formation of source / drain contact vias, and the formation of another interconnect structure. Since the operations at block 922 are similar to the operations at block 622, for the sake of brevity, the detailed description of the operations at block 922 is omitted.

[0145] Figure 17M The semiconductor device 100 of Figure 17N , Figure 17O and Figure 17P is further shown in Figure 17N is a cross-sectional view of the semiconductor device 100; Figure 17O is a cross-sectional view of the semiconductor device 100 in Figure 17N along the dashed line OO'; and Figure 17Palong the dashed line PP’ Figure 17N is a cross-sectional view of the semiconductor device 100 in Figure 17N . In particular, the gate dielectric 1024 includes an interfacial layer 112 and a high-k dielectric layer 114. The high-k dielectric layer 114 is U-shaped to wrap the gate electrode 116.

[0146] The semiconductor device 100 can also be formed using the method of the ninth method 930 as shown in Figure 18 . The method 930 is similar to the third method 400 including block 402. Since various operations have been described above with respect to the third method 400, for the sake of brevity, the details of those operations in the third method 400 are omitted here. Only the different operations are described below. In particular, block 402 is modified to block 932, and block 932 includes depositing a sacrificial layer and a two-dimensional material layer 1000 on the sacrificial layer. In the depicted embodiment, the sacrificial layer is a silicon-germanium layer 124 deposited by selective epitaxial growth. The ninth method 930 also includes block 934 implemented between patterning the fin structure at block 410 to form trenches in the source / drain regions 104SD and forming the source and drain features 108 at block 412. At block 934, as shown in Figure 19H , a dielectric layer 1008 is formed. The formation of the dielectric layer 1008 can include selectively etching the silicon-germanium layer 124, depositing the dielectric layer 1008; laterally recessing the dielectric layer by selective etching; and epitaxially growing silicon to fill the grooves.

[0147] In some embodiments, the semiconductor device 100 has the structure shown in Figure 20 , and the structure shown in Figure 20 is similar to the structure of the semiconductor device 100 in Figure 19L . However, the two-dimensional material layer 1000 extends into the source and drain components 108 and can also include a portion 1010 as an LDD component. In this structure, the two-dimensional material layer 1000 increases the contact area with the source / drain components 108 and reduces the contact resistance due to improved current diffusion (less current crowding) from the S / D components to the channel of the two-dimensional material layer 1000. The two-dimensional material layer 1000 can include a single two-dimensional film or multiple two-dimensional films. In addition, the bandgap of the two-dimensional material layer 1000 can be modulated by the number of two-dimensional films, which can be used for better Ec / Ev band alignment with the S / D components. In some embodiments, the structure of the semiconductor device 100 is formed in a similar manner as shown in Figure 8 and Figures 9A to 9K . Specifically, at block 514, the operations include recessing the fin structure 103 within the gate trench 1022 by a suitable etching process to form a groove 1026; performing a suitable lateral etching process to extend the groove into the source / drain region; and depositing the two-dimensional material layer 1000.

[0148] The present invention relates to a semiconductor device. The semiconductor device includes a channel member having a first channel layer and a second channel layer located above the first channel layer, and a gate structure located above the channel member. The first channel layer includes silicon, germanium, a III-V semiconductor, or a II-VI semiconductor, while the second channel layer includes a two-dimensional material. In some embodiments, a dielectric layer is provided below the two-dimensional material layer to provide isolation between the device and the substrate. Additionally, source and drain components are formed of a semiconductor material by epitaxial growth, which provides better integration for the two-dimensional channel layer and reduces the contact resistance.

[0149] In one exemplary aspect, the present invention provides a semiconductor manufacturing method. The method includes providing a workpiece including a semiconductor structure; depositing a two-dimensional (2D) material layer above the semiconductor structure; forming source and drain components electrically connected to the semiconductor structure and the two-dimensional material layer, wherein the source and drain components include a semiconductor material; and forming a gate structure above the two-dimensional material layer, and the gate structure is between the source and drain components. The gate structure, the source component, the drain component, the semiconductor structure, and the two-dimensional material layer are configured to form a field effect transistor. The semiconductor structure and the two-dimensional material layer serve as a first channel and a second channel, respectively, between the source and drain components.

[0150] In the above method, wherein the semiconductor structure includes silicon, germanium, a III-V semiconductor, or a II-VI semiconductor; and the two-dimensional material layer includes one of graphene, tungsten disulfide (WS2), tungsten telluride (WTe2), tungsten selenide (WSe2), molybdenum disulfide (MoS2), molybdenum telluride (WTe2), black phosphorus, and molybdenum selenide (WSe2).

[0151] In the above method, wherein the formation of the source and drain components includes: patterning the semiconductor structure to form trenches in the source / drain regions; and epitaxially growing a semiconductor material to fill the trenches, thereby forming the source and drain components.

[0152] In the above method, wherein the formation of the source and drain components includes: patterning the semiconductor structure to form trenches in the source / drain regions; and epitaxially growing a semiconductor material to fill the trenches, thereby forming the source and drain components, wherein the patterning of the semiconductor structure further includes patterning the two-dimensional material layer; and the epitaxial growth of the semiconductor material includes epitaxially growing the semiconductor material in direct contact with the edge of the two-dimensional material layer.

[0153] In the above method, the formation of the source component and the drain component includes: patterning the semiconductor structure to form trenches in the source / drain regions; and epitaxially growing a semiconductor material to fill the trenches, thereby forming the source component and the drain component, wherein the patterning of the semiconductor structure further includes patterning the two-dimensional material layer; and the epitaxial growth of the semiconductor material includes epitaxially growing the semiconductor material in direct contact with the edge of the two-dimensional material layer, wherein the gate structure includes a gate stack and a gate spacer layer, the gate spacer layer having a first spacer and a second spacer disposed on opposite sidewalls of the gate stack; and the patterning of the two-dimensional material layer includes patterning the two-dimensional material layer such that the patterned two-dimensional material layer spans between the first spacer and the second spacer of the gate spacer layer.

[0154] In the above method, the formation of the source component and the drain component includes: patterning the semiconductor structure to form trenches in the source / drain regions; and epitaxially growing a semiconductor material to fill the trenches, thereby forming the source component and the drain component, wherein the patterning of the semiconductor structure further includes patterning the two-dimensional material layer; and the epitaxial growth of the semiconductor material includes epitaxially growing the semiconductor material in direct contact with the edge of the two-dimensional material layer, wherein the gate structure includes a gate stack and a gate spacer layer, the gate spacer layer having a first spacer and a second spacer disposed on opposite sidewalls of the gate stack; and the patterning of the two-dimensional material layer includes patterning the two-dimensional material layer such that the patterned two-dimensional material layer spans between the first spacer and the second spacer of the gate spacer layer, wherein the patterning of the two-dimensional material layer includes patterning the two-dimensional material layer such that opposite edges of the patterned two-dimensional material layer are respectively aligned with the outer sides of the first spacer and the second spacer.

[0155] In the above method, the formation of the source component and the drain component includes: patterning the semiconductor structure to form trenches in the source / drain regions; and epitaxially growing a semiconductor material to fill the trenches, thereby forming the source component and the drain component, wherein the formation of the source component and the drain component includes: forming a sacrificial semiconductor layer on the semiconductor structure before deposition of the two-dimensional material layer; and replacing the sacrificial semiconductor layer with a dielectric layer through the trenches after patterning of the semiconductor structure to form the trenches in the source / drain regions.

[0156] In the above method, the deposition of the two-dimensional material layer includes: forming a dummy gate stack above the semiconductor structure, and forming a gate spacer layer having a first spacer and a second spacer disposed on opposite sidewalls of the dummy gate stack; after the formation of the source component and the drain component, removing the dummy gate stack, generating a gate trench defined by the first spacer and the second spacer, with the semiconductor structure exposed in the gate trench; and selectively depositing the two-dimensional material layer on the semiconductor structure exposed in the gate trench such that the two-dimensional material layer spans between the inner sides of the first spacer and the second spacer respectively.

[0157] In the above method, the deposition of the two-dimensional material layer includes: forming a dummy gate stack above the semiconductor structure, and forming a gate spacer layer having a first spacer and a second spacer disposed on opposite sidewalls of the dummy gate stack; after the formation of the source component and the drain component, removing the dummy gate stack, generating a gate trench defined by the first spacer and the second spacer, with the semiconductor structure exposed in the gate trench; and selectively depositing the two-dimensional material layer on the semiconductor structure exposed in the gate trench such that the two-dimensional material layer spans between the inner sides of the first spacer and the second spacer respectively, and further includes forming a gate structure on the two-dimensional material layer in the gate trench.

[0158] In the above method, the deposition of the two-dimensional material layer includes depositing the two-dimensional material layer with a thickness between 2 angstroms and 10 angstroms.

[0159] The above method further includes forming a dielectric component inserted between the two-dimensional material layer and the semiconductor structure.

[0160] In one exemplary aspect, the present invention provides a semiconductor manufacturing method. The method includes forming a semiconductor stack including an alternately configured first semiconductor layer and a second semiconductor layer. Wherein, the first semiconductor layer and the second semiconductor layer have different compositions; depositing a two-dimensional (2D) material layer on the second semiconductor layer; forming a source component and a drain component electrically connected to the second semiconductor layer and the two-dimensional material layer, wherein the source component and the drain component include semiconductor materials; selectively removing the first semiconductor layer; and forming a gate structure above the two-dimensional material layer, and the gate structure extends to wrap each second semiconductor layer.

[0161] In the above method, the second semiconductor layer includes one of silicon, germanium, group III-V semiconductors, and group II-VI semiconductors; and the two-dimensional material layer includes one of graphene, tungsten disulfide (WS2), tungsten telluride (WTe2), tungsten selenide (WSe2), molybdenum disulfide (MoS2), molybdenum telluride (MoTe2), black phosphorus, and molybdenum selenide (MoSe2).

[0162] In the above method, the formation of the source component and the drain component includes: patterning the semiconductor structure to form trenches in the source / drain regions; and epitaxially growing a semiconductor material to fill the trenches, thereby forming the source component and the drain component, wherein the second semiconductor layer spans between the source component and the drain component.

[0163] In the above method, the formation of the source component and the drain component includes: patterning the semiconductor structure to form trenches in the source / drain regions; and epitaxially growing a semiconductor material to fill the trenches, thereby forming the source component and the drain component, wherein the second semiconductor layer spans between the source component and the drain component, wherein the gate structure is formed above the two-dimensional material layer, and the gate structure extends to wrap each of the second semiconductor layers, including: forming a dummy gate structure above the semiconductor stack before the formation of the source component and the drain component; removing the dummy gate structure after the formation of the source component and the drain component, generating a gate trench; and forming a gate stack in the gate trench, and the gate stack spans between the first gate spacer and the second gate spacer, wherein the selective removal of the first semiconductor layer includes selectively removing the first semiconductor layer through the gate trench after the removal of the dummy gate structure.

[0164] In the above method, the formation of the source component and the drain component includes: patterning the semiconductor structure to form trenches in the source / drain regions; and epitaxially growing a semiconductor material to fill the trenches, thereby forming the source component and the drain component, wherein the second semiconductor layer spans between the source component and the drain component, wherein the gate structure is formed over the two-dimensional material layer, and the gate structure extends to wrap each of the second semiconductor layers, including: forming a dummy gate structure over the semiconductor stack before the formation of the source component and the drain component; removing the dummy gate structure after the formation of the source component and the drain component, creating gate trenches; and forming a gate stack in the gate trenches, and the gate stack spans between the first gate spacer and the second gate spacer, wherein the selective removal of the first semiconductor layer includes selectively removing the first semiconductor layer through the gate trenches after the removal of the dummy gate structure, wherein forming a gate structure over the two-dimensional material layer and the gate structure extending to wrap each of the second semiconductor layers further includes: depositing a dielectric material layer in the gate trenches after the removal of the dummy gate structure; and performing an anisotropic etching process on the dielectric material layer before the formation of the gate stack, thereby forming a first gate spacer on the sidewall of the source component and a second gate spacer on the sidewall of the drain component.

[0165] In the above method, wherein the formation of the source component and the drain component includes: patterning the semiconductor structure to form trenches in the source / drain regions; and epitaxially growing a semiconductor material to fill the trenches, thereby forming the source component and the drain component, wherein the second semiconductor layer spans between the source component and the drain component, wherein the gate structure is formed over the two-dimensional material layer, and the gate structure extends to wrap each of the second semiconductor layers, including: forming a dummy gate structure over the semiconductor stack before the formation of the source component and the drain component; removing the dummy gate structure after the formation of the source component and the drain component, generating a gate trench; and forming a gate stack in the gate trench, and the gate stack spans between the first gate spacer and the second gate spacer, wherein the selective removal of the first semiconductor layer includes selectively removing the first semiconductor layer through the gate trench after the removal of the dummy gate structure, wherein forming the gate structure over the two-dimensional material layer and the gate structure extending to wrap each of the second semiconductor layers further includes: depositing a dielectric material layer in the gate trench after the removal of the dummy gate structure; and performing an anisotropic etching process on the dielectric material layer before the formation of the gate stack, thereby forming a first gate spacer on the sidewall of the source component and a second gate spacer on the sidewall of the drain component, wherein the selective removal of the first semiconductor layer includes selectively removing the first semiconductor layer through the gate trench after the removal of the dummy gate structure; the deposition of the two-dimensional material layer includes depositing the two-dimensional material layer to wrap each of the second semiconductor layers; and the deposition of the dielectric material layer in the gate trench includes depositing the dielectric material layer on the two-dimensional material layer to wrap each of the second semiconductor layers.

[0166] In the above method, wherein the formation of the source component and the drain component includes: patterning the semiconductor structure to form trenches in the source / drain regions; and epitaxially growing semiconductor material to fill the trenches, thereby forming the source component and the drain component, wherein the second semiconductor layer spans between the source component and the drain component, wherein the gate structure is formed over the two-dimensional material layer, and the gate structure extends to wrap each of the second semiconductor layers, including: forming a dummy gate structure over the semiconductor stack before the formation of the source component and the drain component; removing the dummy gate structure after the formation of the source component and the drain component, generating a gate trench; and forming a gate stack in the gate trench, and the gate stack spans between the first gate spacer and the second gate spacer, wherein the selective removal of the first semiconductor layer includes selectively removing the first semiconductor layer through the gate trench after the removal of the dummy gate structure, wherein forming a gate structure over the two-dimensional material layer, and the gate structure extends to wrap each of the second semiconductor layers further includes: depositing a dielectric material layer in the gate trench after the removal of the dummy gate structure; and performing an anisotropic etching process on the dielectric material layer before the formation of the gate stack, thereby forming a first gate spacer on the sidewall of the source component and a second gate spacer on the sidewall of the drain component, wherein the performing of the anisotropic etching process on the dielectric material layer includes performing the anisotropic etching process on the dielectric material layer, thereby forming an internal spacer between two adjacent first semiconductor layers.

[0167] In the above method, wherein the deposition of the two-dimensional material layer on the second semiconductor layer includes depositing the two-dimensional material layer on the top and bottom surfaces of each of the second semiconductor layers.

[0168] In one exemplary aspect, the present invention provides a semiconductor device. The semiconductor device includes a channel member, the channel member including: a first channel layer and a second channel layer located above the first channel layer; a gate structure located above the channel member; and source and drain components of semiconductor material. The first channel layer includes silicon, germanium, a III-V semiconductor, or a II-VI semiconductor. The two-dimensional material includes graphene, tungsten disulfide (WS2), tungsten telluride (WTe2), tungsten selenide (WSe2), molybdenum disulfide (MoS2), molybdenum telluride (MoTe2), black phosphorus, or molybdenum selenide (MoSe2). The second channel layer includes a two-dimensional material. The semiconductor material of the source and drain components is electrically connected to the first channel layer and the second channel layer.

[0169] The features of several embodiments are outlined above so that those skilled in the art can better understand aspects of the present invention. Those skilled in the art should understand that they can readily use the present invention as a basis to design or modify other processes and structures for implementing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also realize that such equivalent configurations do not depart from the spirit and scope of the present invention, and that various changes, substitutions, and alterations can be made herein without departing from the spirit and scope of the present invention.

Claims

1. A method of forming a semiconductor device, comprising: Provide a workpiece having a semiconductor structure; Deposit a two-dimensional material layer over the semiconductor structure; Form source and drain components electrically connected to the semiconductor structure and the two-dimensional material layer, wherein the source and drain components comprise semiconductor material; and Form a gate structure over the two-dimensional material layer, and the gate structure is between the source and drain components, wherein the gate structure, the source component, the drain component, the semiconductor structure, and the two-dimensional material layer are configured to form a field effect transistor, and wherein the semiconductor structure and the two-dimensional material layer are respectively used as a first channel and a second channel between the source and drain components, wherein the deposition of the two-dimensional material layer comprises: Form a dummy gate stack over the semiconductor structure, and form a gate spacer layer having a first spacer and a second spacer disposed on opposite sidewalls of the dummy gate stack; After the formation of the source and drain components, remove the dummy gate stack, generating a gate trench defined by the first spacer and the second spacer, with the semiconductor structure exposed within the gate trench; and Selectively deposit the two-dimensional material layer on the semiconductor structure exposed within the gate trench such that the two-dimensional material layer spans between the inner sides of the first spacer and the second spacer respectively.

2. The method according to claim 1, wherein, The semiconductor structure comprises silicon, germanium, a III-V semiconductor, or a II-VI semiconductor; and The two-dimensional material layer comprises one of graphene, tungsten sulfide, tungsten telluride, tungsten selenide, molybdenum sulfide, molybdenum telluride, black phosphorus, and molybdenum selenide.

3. The method according to claim 1, wherein, The formation of the source and drain components comprises: Pattern the semiconductor structure to form trenches in the source / drain regions; and Epitaxially grow semiconductor material to fill the trenches, thereby forming the source and drain components.

4. The method according to claim 1, wherein, The bottom surface of the two-dimensional material layer is lower than the bottom surfaces of the first spacer and the second spacer.

5. The method according to claim 1, wherein, The gate structure comprises a gate stack and a gate spacer layer having the first spacer and the second spacer disposed on opposite sidewalls of the gate stack.

6. The method according to claim 1, wherein, The two-dimensional material layer is spaced apart from the source and drain components.

7. The method according to claim 1, wherein, The formation of the source and drain components comprises: Pattern the semiconductor structure to form trenches within the source / drain regions; and Form the source and drain components at the trenches by epitaxial growth.

8. The method according to claim 1, wherein, The gate dielectric of the gate structure comprises an interfacial layer and a high-k dielectric layer located above the interfacial layer.

9. The method according to claim 1, further comprising forming the gate structure on the two-dimensional material layer within the gate trench.

10. The method according to claim 1, wherein, The deposition of the two-dimensional material layer comprises depositing the two-dimensional material layer with a thickness between 2 angstroms and 10 angstroms.

11. The method according to claim 5, wherein, The gate electrode of the gate stack comprises Ti, Ag, Al, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, TiN, TaN, Ru, Mo, Al, WN, Cu, W, Re, Ir, Co, Ni, or a combination thereof.

12. A method of forming a semiconductor device, comprising: Form a semiconductor stack including alternately arranged first semiconductor layers and second semiconductor layers, wherein the first semiconductor layers and the second semiconductor layers have different compositions, and wherein a two-dimensional material layer is deposited on the second semiconductor layers; Form a source component and a drain component electrically connected to the second semiconductor layer and the two-dimensional material layer, wherein the source component and the drain component include a semiconductor material; Selectively remove the first semiconductor layer; and Form a gate structure above the two-dimensional material layer, and the gate structure extends to wrap each of the second semiconductor layers and the two-dimensional material layer, wherein the two-dimensional material layer wraps the second semiconductor layer.

13. The method according to claim 12, wherein, The second semiconductor layer includes one of silicon, germanium, III-V semiconductors, and II-VI semiconductors; and The two-dimensional material layer includes one of graphene, tungsten sulfide, tungsten telluride, tungsten selenide, molybdenum sulfide, molybdenum telluride, black phosphorus, and molybdenum selenide.

14. The method according to claim 12, wherein, The formation of the source component and the drain component includes: Patterning the semiconductor stack to form trenches in the source / drain regions; and Epitaxially growing a semiconductor material to fill the trenches, thereby forming the source component and the drain component, wherein the second semiconductor layer spans between the source component and the drain component.

15. The method according to claim 14, wherein, Forming the gate structure above the two-dimensional material layer, and the gate structure extending to wrap each of the second semiconductor layers includes: Before forming the source component and the drain component, form a dummy gate structure above the semiconductor stack and form a first gate spacer and a second gate spacer provided on opposite sidewalls of the dummy gate structure; After forming the source component and the drain component, remove the dummy gate structure to create a gate trench; and Form a gate stack in the gate trench, and the gate stack spans between the first gate spacer and the second gate spacer, wherein the selective removal of the first semiconductor layer includes selectively removing the first semiconductor layer through the gate trench after the removal of the dummy gate structure.

16. The method according to claim 15, wherein, The gate structure includes a gate stack and a gate spacer layer having the first gate spacer and the second gate spacer provided on opposite sidewalls of the gate stack.

17. The method according to claim 12, wherein, The selective removal of the first semiconductor layer includes selectively removing the first semiconductor layer through the gate trench after the removal of the dummy gate structure; and The deposition of the dielectric material layer in the gate trench includes depositing the dielectric material layer on the two-dimensional material layer to wrap each of the second semiconductor layers.

18. The method according to claim 16, wherein, Performing an anisotropic etching process on the dielectric material layer includes performing the anisotropic etching process on the dielectric material layer to form internal spacers between two adjacent first semiconductor layers.

19. The method according to claim 12, wherein, The deposition of the two-dimensional material layer on the second semiconductor layer includes depositing the two-dimensional material layer on the top and bottom surfaces of each of the second semiconductor layers.

20. A semiconductor device, comprising: A channel member, including a first channel layer and a second channel layer located above the first channel layer; A gate structure, located above the channel member; And A source component and a drain component of semiconductor material, Wherein, the first channel layer comprises silicon, germanium, a III-V semiconductor or a II-VI semiconductor, Wherein, the second channel layer comprises a two-dimensional material, Wherein, the two-dimensional material comprises graphene, tungsten sulfide, tungsten telluride, tungsten selenide, molybdenum sulfide, molybdenum telluride, black phosphorus or molybdenum selenide, and The semiconductor material of the source component and the drain component is electrically connected to the first channel layer and the second channel layer, Wherein, the second channel layer is disposed within the first channel layer and extends within a lateral range defined by a gate spacer of the gate structure, and wherein a top surface of the second channel layer is flush with a top surface of the first channel layer.

Images