Display device

Abstract

The display device includes: a base substrate including a first polymer film; an active pattern on the base substrate and including a first channel region; and a first gate electrode overlapping the first channel region, wherein the first polymer film has a first thickness in a first region overlapping the first channel region, and has a second thickness less than the first thickness in a second region different from the first region.

Description

Technical Field

[0001] Aspects of embodiments of the present disclosure relate to a display device. Background Art

[0002] The polymer substrate may be used in a display device to reduce the weight of the display device and change the design of the display device. The polymer substrate may include a polymer such as polyimide or the like.

[0003] When the display device includes a polymer substrate, dipole polarization may be caused by an electrical signal applied to a driving element or the like, and may cause degradation in display quality, for example, afterimages.

[0004] The above information disclosed in this Background section is only for enhancement of understanding of the background technology, and therefore the information discussed in this Background section does not necessarily constitute prior art. Summary of the invention

[0005] Aspects of embodiments of the present disclosure relate to a display device. For example, aspects of the embodiments relate to a display device that can have relatively improved display quality.

[0006] Aspects of the embodiments are directed to a display device having relatively improved display quality.

[0007] According to an embodiment of the present disclosure, a display device includes: a base substrate including a first polymer film, an active pattern on the base substrate and including a first channel region, and a first gate electrode overlapping the first channel region. The first polymer film has a first thickness in a first region overlapping the first channel region and has a second thickness less than the first thickness in a second region different from the first region.

[0008] According to an embodiment, the display device further includes a second gate electrode overlapping the second channel region of the active pattern. The second region overlaps the second channel region.

[0009] According to an embodiment, the display device further includes a light emitting element. A driving transistor defined by the first channel region and the first gate electrode provides a driving current to the light emitting element. A source terminal or a drain terminal of the switching transistor defined by the second channel region and the second gate electrode is electrically connected to a source terminal or a drain terminal of the driving transistor.

[0010] According to an embodiment, the emission control signal is applied to the second gate electrode.

[0011] According to an embodiment, the light emitting element includes an organic light emitting diode.

[0012] According to an embodiment, a ratio of the first thickness to the second thickness is at least about 1.2.

[0013] According to an embodiment, the difference between the first thickness and the second thickness is about to about

[0014] According to an embodiment, the base substrate further includes: a second polymer film under the first polymer film, and an adhesion enhancing layer between the first polymer film and the second polymer film and including amorphous silicon.

[0015] According to an embodiment, the display device further includes a capacitor electrode pattern, wherein an edge of the first region extends along an edge of the capacitor electrode pattern.

[0016] According to an embodiment, the active pattern further includes a second channel region overlapping the second region, wherein a height of the first channel region is greater than a height of the second channel region.

[0017] According to an embodiment of the present disclosure, a display device includes: a base substrate, an active pattern on the base substrate and including a first channel region, and a first gate electrode overlapping the first channel region. The base substrate includes a first polymer film, a second polymer film, and an adhesion enhancement layer between the first polymer film and the second polymer film and including an opening. The first channel region overlaps with the opening of the adhesion enhancement layer.

[0018] According to an embodiment, a display device includes a base substrate, a field barrier pattern, an active pattern on the base substrate, and a first gate electrode. The base substrate includes a first polymer film and an upper barrier layer covering an upper surface of the first polymer film. The field barrier pattern is partially between the first polymer film and the upper barrier layer. The active pattern is on the base substrate, overlaps with the field barrier pattern, and includes an active pattern spaced from the field barrier pattern by an angle equal to or greater than 100 degrees. The first gate electrode overlaps with the first channel region.

[0019] According to an embodiment, a fringe field applied to a transistor may be deformed or blocked, so that a change in transistor characteristics may be prevented or reduced. Therefore, the reliability of a display device including the transistor may be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Aspects of one or more embodiments of the present inventive concept will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0021] Figure 1 is a circuit diagram of a pixel unit of a display device according to an embodiment.

[0022] Figure 2 is a plan view of a driving element of a pixel unit of a display device according to an embodiment.

[0023] Figure 3 To explain along Figure 22 is a cross-sectional view of a driving element and a light emitting element of a display device according to an embodiment, taken along line II′.

[0024] Figure 4 and Figure 5 is a cross-sectional view for explaining the effect of the display device according to the embodiment.

[0025] Figure 6 , Figure 7 and Figure 8 A cross-sectional view for explaining a method for manufacturing a base substrate of a display device according to an embodiment.

[0026] Fig. 9 A plan view of a first region of a base substrate for explaining a display device according to an embodiment.

[0027] Fig.10 and Fig.11 A cross-sectional view for explaining a method for manufacturing a base substrate of a display device according to an embodiment.

[0028] Fig.12 A cross-sectional view illustrating a driving element and a light emitting element of a display device according to an embodiment.

[0029] Fig.13 , Fig.14 and Fig.15 To illustrate the method for manufacturing the Fig.12 A cross-sectional view of a method for forming a base substrate of a display device is illustrated in FIG.

[0030] Fig.16 is a cross-sectional view illustrating a base substrate of a display device according to an embodiment.

[0031] Fig.17 A cross-sectional view illustrating a driving element and a light emitting element of a display device according to an embodiment.

[0032] Fig.18 To illustrate the method for manufacturing the Fig.17 A cross-sectional view of a method for forming a base substrate of a display device is illustrated in FIG.

[0033] Fig.19 A cross-sectional view illustrating a driving element and a light emitting element of a display device according to an embodiment. DETAILED DESCRIPTION

[0034] Hereinafter, a display device according to embodiments of the inventive concept will be described in more detail with reference to the accompanying drawings, in which some embodiments are shown.

[0035] Figure 1 is a circuit diagram of a pixel unit of a display device according to an embodiment. Figure 2is a plan view of a driving element of a pixel unit of a display device according to an embodiment.

[0036] The display device according to the embodiment includes a pixel array for displaying an image in response to a driving signal. Each pixel unit may include a light emitting element and a pixel circuit driving the light emitting element. The pixel circuit may include a plurality of driving elements.

[0037] For example, refer to Figure 1 and Figure 2 The pixel circuit may include first to seventh transistors TR1, TR2, TR3_1, TR3_2, TR4_1, TR4_2, TR5, TR6 and TR7, a storage capacitor CST, a high power supply voltage ELVDD wiring, a low power supply voltage ELVSS wiring, an initialization voltage VINT wiring, a data signal DATA wiring, a scan signal GW wiring, a data initialization signal GI wiring, an emission control signal EM wiring and a diode initialization signal GB wiring, etc.

[0038] The organic light emitting diode OLED may output light based on the driving current ID. The organic light emitting diode OLED may include a first terminal and a second terminal. According to an embodiment, the second terminal of the organic light emitting diode OLED may be supplied with a low power supply voltage ELVSS. For example, the first terminal of the organic light emitting diode OLED may be an anode terminal, and the second terminal of the organic light emitting diode OLED may be a cathode terminal. Alternatively, the first terminal of the organic light emitting diode OLED may be a cathode terminal, and the second terminal of the organic light emitting diode OLED may be an anode terminal.

[0039] The first transistor TR1 may include a gate terminal, a first terminal, and a second terminal. According to an embodiment, the first terminal of the first transistor TR1 may be a source terminal, and the second terminal of the first transistor TR1 may be a drain terminal. Alternatively, the first terminal of the first transistor TR1 may be a drain terminal, and the second terminal of the first transistor TR1 may be a source terminal.

[0040] The first transistor TR1 may generate a driving current ID. According to an embodiment, the first transistor TR1 may operate in a saturation region. In this case, the first transistor TR1 may generate a driving current ID based on a voltage difference between a gate terminal and a source terminal. In addition, a gray scale may be represented based on the magnitude of the driving current ID supplied to the organic light emitting diode OLED. Alternatively, the first transistor TR1 may operate in a linear region. In this case, a gray scale may be represented based on the sum of the times during which the driving current ID is supplied to the organic light emitting diode OLED within one frame.

[0041] The second transistor TR2 may include a gate terminal, a first terminal, and a second terminal. The gate terminal of the second transistor TR2 may be supplied with a scan signal GW. The first terminal of the second transistor TR2 may be supplied with a data signal DATA. The second terminal of the second transistor TR2 may be connected to the first terminal of the first transistor TR1. According to an embodiment, the first terminal of the second transistor TR2 may be a source terminal, and the second terminal of the second transistor TR2 may be a drain terminal. Alternatively, the first terminal of the second transistor TR2 may be a drain terminal, and the second terminal of the second transistor TR2 may be a source terminal.

[0042] The second transistor TR2 may supply the data signal DATA to the first terminal of the first transistor TR1 during the activation of the scan signal GW. In this case, the second transistor TR2 may operate in a linear region.

[0043] Each of the third transistors TR3_1 and TR3_2 may include a gate terminal, a first terminal, and a second terminal. The third transistor TR3_1 and the third transistor TR3_2 may be connected in series and may be operated as a double transistor. For example, when the double transistor is turned off, the leakage current may be reduced. The gate terminal of each of the third transistors TR3_1 and TR3_2 may be supplied with a scan signal GW. The first terminal of each of the third transistors TR3_1 and TR3_2 may be connected to the gate terminal of the first transistor TR1. The second terminal of each of the third transistors TR3_1 and TR3_2 may be connected to the second terminal of the first transistor TR1. According to an embodiment, the first terminal of each of the third transistors TR3_1 and TR3_2 may be a source terminal, and the second terminal of each of the third transistors TR3_1 and TR3_2 may be a drain terminal. Alternatively, the first terminal of each of the third transistors TR3_1 and TR3_2 may be a drain terminal, and the second terminal of each of the third transistors TR3_1 and TR3_2 may be a source terminal.

[0044] Each of the third transistors TR3_1 and TR3_2 may connect the gate terminal of the first transistor TR1 to the second terminal of the first transistor TR1 during the activation of the scan signal GW. In this case, each of the third transistors TR3_1 and TR3_2 may operate in a linear region. In other words, each of the third transistors TR3_1 and TR3_2 may diode-connect the first transistor TR1 during the activation of the scan signal GW. Because the first transistor TR1 is diode-connected, a voltage difference equal to the threshold voltage of the first transistor TR1 may occur between the first terminal of the first transistor TR1 and the gate terminal of the first transistor TR1. As a result, during the activation of the scan signal GW, a voltage obtained by adding the voltage difference (i.e., the threshold voltage) to the voltage of the data signal DATA supplied to the first terminal of the first transistor TR1 may be supplied to the gate terminal of the first transistor TR1. In other words, the data signal DATA as much as the threshold voltage of the first transistor TR1 may be compensated, and the compensated data signal DATA may be supplied to the gate terminal of the first transistor TR1.

[0045] An input terminal of the initialization voltage VINT may be connected to a first terminal of each of the fourth transistors TR4_1 and TR4_2 and a first terminal of the seventh transistor TR7 , and an output terminal of the initialization voltage VINT may be connected to a second terminal of each of the fourth transistors TR4_1 and TR4_2 and a first terminal of the storage capacitor CST.

[0046] Each of the fourth transistors TR4_1 and TR4_2 may include a gate terminal, a first terminal, and a second terminal. The fourth transistor TR4_1 and the fourth transistor TR4_2 may be connected in series and may be operated as a double transistor. For example, when the double transistor is turned off, the leakage current may be reduced. The gate terminal of each of the fourth transistors TR4_1 and TR4_2 may receive a data initialization signal GI. The first terminal of each of the fourth transistors TR4_1 and TR4_2 may be supplied with an initialization voltage VINT. The second terminal of each of the fourth transistors TR4_1 and TR4_2 may be connected to the gate terminal of the first transistor TR1. According to an embodiment, the first terminal of each of the fourth transistors TR4_1 and TR4_2 may be a source terminal, and the second terminal of each of the fourth transistors TR4_1 and TR4_2 may be a drain terminal. Alternatively, the first terminal of each of the fourth transistors TR4_1 and TR4_2 may be a drain terminal, and the second terminal of each of the fourth transistors TR4_1 and TR4_2 may be a source terminal.

[0047] During the activation of the data initialization signal GI, each of the fourth transistors TR4_1 and TR4_2 may supply the initialization voltage VINT to the gate terminal of the first transistor TR1. In this case, each of the fourth transistors TR4_1 and TR4_2 may operate in a linear region. In other words, during the activation of the data initialization signal GI, each of the fourth transistors TR4_1 and TR4_2 may initialize the gate terminal of the first transistor TR1 to the initialization voltage VINT. According to an embodiment, the initialization voltage VINT may have a voltage level sufficiently lower than the voltage level of the data signal DATA maintained by the storage capacitor CST in the previous frame, and the initialization voltage VINT may be supplied to the gate terminal of the first transistor TR1 as a p-channel metal oxide semiconductor (PMOS) transistor. According to an embodiment, the initialization voltage VINT may have a voltage level sufficiently higher than the voltage level of the data signal DATA maintained by the storage capacitor CST in the previous frame, and the initialization voltage VINT may be supplied to the gate terminal of the first transistor TR1 as an n-channel metal oxide semiconductor (NMOS) transistor.

[0048] According to an embodiment, the data initialization signal GI may be a signal that is the same as (or substantially the same as) the scan signal GW one horizontal time ago. For example, the data initialization signal GI supplied to the sub-pixels of the nth row (where n is an integer of 2 or greater) among a plurality of sub-pixels (e.g., a pixel circuit PIXEL CIRCUIT) and the organic light emitting diode OLED included in the organic light emitting display device may be a signal that is the same as (or substantially the same as) the scan signal GW supplied to the sub-pixels of the (n-1)th row among the plurality of sub-pixels. In other words, the activated scan signal GW is supplied to the sub-pixels of the (n-1)th row among the plurality of sub-pixels so that the activated data initialization signal GI may be supplied to the sub-pixels of the nth row among the plurality of sub-pixels. As a result, the data signal DATA may be supplied to the sub-pixels of the (n-1)th row among the plurality of sub-pixels, and the gate terminal of the first transistor TR1 included in the sub-pixels of the nth row among the plurality of sub-pixels may be initialized to the initialization voltage VINT.

[0049] The fifth transistor TR5 may include a gate terminal, a first terminal, and a second terminal. The gate terminal may be supplied with an emission control signal EM. The first terminal may be connected to a high power supply voltage ELVDD wiring. The second terminal may be connected to a first terminal of the first transistor TR1. According to an embodiment, the first terminal of the fifth transistor TR5 may be a source terminal, and the second terminal of the fifth transistor TR5 may be a drain terminal. Alternatively, the first terminal of the fifth transistor TR5 may be a drain terminal, and the second terminal of the fifth transistor TR5 may be a source terminal.

[0050] The fifth transistor TR5 may supply the high power supply voltage ELVDD to the first terminal of the first transistor TR1 during the activation of the emission control signal EM. On the contrary, the fifth transistor TR5 may block the supply of the high power supply voltage ELVDD during the inactivation of the emission control signal EM. In this case, the fifth transistor TR5 may operate in a linear region. The fifth transistor TR5 may supply the high power supply voltage ELVDD to the first terminal of the first transistor TR1 during the activation of the emission control signal EM so that the first transistor TR1 may generate a driving current ID. In addition, the fifth transistor TR5 may block the supply of the high power supply voltage ELVDD during the inactivation of the emission control signal EM so that the data signal DATA supplied to the first terminal of the first transistor TR1 may be supplied to the gate terminal of the first transistor TR1.

[0051] The sixth transistor TR6 may include a gate terminal, a first terminal, and a second terminal. The gate terminal may be supplied with an emission control signal EM. The first terminal may be connected to the second terminal of the first transistor TR1. The second terminal may be connected to the first terminal of the organic light emitting diode OLED. According to an embodiment, the first terminal may be a source terminal, and the second terminal may be a drain terminal. Alternatively, the first terminal may be a drain terminal, and the second terminal may be a source terminal.

[0052] The sixth transistor TR6 may supply the driving current ID generated by the first transistor TR1 to the organic light emitting diode OLED during the activation of the emission control signal EM. In this case, the sixth transistor TR6 may operate in a linear region. In other words, the sixth transistor TR6 may supply the driving current ID generated by the first transistor TR1 to the organic light emitting diode OLED during the activation of the emission control signal EM so that the organic light emitting diode OLED may output light. In addition, the sixth transistor TR6 electrically isolates the first transistor TR1 and the organic light emitting diode OLED from each other during the deactivation of the emission control signal EM so that the data signal DATA (more precisely, the data signal compensating the threshold voltage) supplied to the second terminal of the first transistor TR1 may be supplied to the gate terminal of the first transistor TR1.

[0053] The seventh transistor TR7 may include a gate terminal, a first terminal, and a second terminal. The gate terminal may be supplied with a diode initialization signal GB. The first terminal may be supplied with an initialization voltage VINT. The second terminal may be connected to a first terminal of the organic light emitting diode OLED. According to an embodiment, the first terminal may be a source terminal, and the second terminal may be a drain terminal. Alternatively, the first terminal may be a drain terminal, and the second terminal may be a source terminal.

[0054] The seventh transistor TR7 can supply the initialization voltage VINT to the first terminal of the organic light emitting diode OLED during the activation of the diode initialization signal GB. In this case, the seventh transistor TR7 can operate in the linear region. In other words, the seventh transistor TR7 can initialize the first terminal of the organic light emitting diode OLED to the initialization voltage VINT during the activation of the diode initialization signal GB.

[0055] Alternatively, the data initialization signal GI may be the same as (or substantially the same as) the diode initialization signal GB. The operation of initializing the gate terminal of the first transistor TR1 and the operation of initializing the first terminal of the organic light emitting diode OLED may not affect each other. In other words, the operation of initializing the gate terminal of the first transistor TR1 and the operation of initializing the first terminal of the organic light emitting diode OLED may be independent of each other. Therefore, the diode initialization signal GB is not generated separately.

[0056] The storage capacitor CST may include a first terminal and a second terminal. The storage capacitor CST may be connected between the high power voltage ELVDD wiring and the gate terminal of the first transistor TR1. For example, the first terminal of the storage capacitor CST may be connected to the gate terminal of the first transistor TR1, and the second terminal of the storage capacitor CST may be connected to the high power voltage ELVDD wiring. The storage capacitor CST may maintain the voltage level of the gate terminal of the first transistor TR1 during the inactivation of the scan signal GW. The inactivation period of the scan signal GW may include the activation period of the emission control signal EM, and the drive current ID generated by the first transistor TR1 during the activation of the emission control signal EM may be supplied to the organic light emitting diode OLED. Therefore, the drive current ID generated by the first transistor TR1 may be supplied to the organic light emitting diode OLED based on the voltage level maintained by the storage capacitor CST.

[0057] The implementation is not limited to Figure 1 The above pixel configuration explained in . The number of transistors and the combination of transistors in the pixel unit can be changed variously.

[0058] refer to Figure 1 and Figure 2 The pixel unit of the display device according to the embodiment may include an active pattern AP, a first gate electrode GE1, a first scan line SL1, a second scan line SL2, a third scan line SL3, a capacitor electrode pattern CP, a shielding pattern SP, an initialization voltage wiring Vint, a data line DL and a power wiring PL.

[0059] The first scan line SL1 can transmit Figure 1A portion of the active pattern AP overlapped with the first scan line SL1 may correspond to channels of the second transistor TR2 and the third transistors TR3_1 and TR3_2.

[0060] The second scan line SL2 can transmit Figure 1 A portion of the active pattern AP overlapped with the second scan line SL2 may correspond to channels of the fourth transistors TR4_1 and TR4_2 and the seventh transistor TR7.

[0061] The third scan line SL3 can transmit Figure 1 A portion of the active pattern AP overlapped with the third scan line SL3 may correspond to channels of the fifth transistor TR5 and the sixth transistor TR6.

[0062] A portion of the active pattern AP overlapped with the first gate electrode GE1 may correspond to a channel of the first transistor TR1. The first gate electrode GE1 may be electrically connected to a portion of the active pattern AP corresponding to an output terminal of the fourth transistors TR4_1 and TR4_2 through a first connection wiring CL1.

[0063] For example, the first to third scan lines SL1 , SL2 , and SL3 may extend in the first direction D1 .

[0064] According to an embodiment, the first gate electrode GE1 and the first to third scan lines SL1, SL2, and SL3 may be formed in the same layer. For example, the first gate electrode GE1 and the first to third scan lines SL1, SL2, and SL3 may be referred to as a first gate metal pattern. However, the embodiment is not limited thereto. For example, at least one of the first gate electrode GE1 and the first to third scan lines SL1, SL2, and SL3 may be formed or located in a different layer from the others.

[0065] The capacitor electrode pattern CP may be electrically connected to the power wiring PL to receive the high power voltage ELVDD. The capacitor electrode pattern CP may overlap the first gate electrode GE1 to form a storage capacitor CST. The capacitor electrode pattern CP may be formed on or located on the first gate electrode GE1 and may include an opening OP overlapping the first gate electrode GE1. The first connection wiring CL1 may electrically contact the first gate electrode GE1 through the opening OP.

[0066] According to an embodiment, the opening OP may not overlap with the channel of the first transistor TR1 in a plan view. For example, the opening OP may be spaced apart from the active pattern AP in a plan view.

[0067] The shielding pattern SP may overlap the active pattern AP between the channels of the third transistors TR3_1 and TR3_2. The shielding pattern SP may be electrically connected to the power wiring PL to receive the high power voltage ELVDD.

[0068] Initialization voltage wiring Vint can be transmitted Figure 1 The initialization voltage VINT explained in.

[0069] According to an embodiment, the capacitor electrode pattern CP, the shielding pattern SP, and the initialization voltage wiring Vint may be formed in or located in the same layer. For example, the capacitor electrode pattern CP, the shielding pattern SP, and the initialization voltage wiring Vint may be referred to as a second gate metal pattern. However, embodiments according to the present disclosure are not limited thereto. For example, at least one of the capacitor electrode pattern CP, the shielding pattern SP, and the initialization voltage wiring Vint may be formed in a different layer from the others.

[0070] Data line DL can transmit Figure 1 The data line DL may be electrically connected to the active pattern AP to transfer the data signal DATA to the second transistor TR2.

[0071] Power supply wiring PL can be transmitted Figure 1 The power wiring PL may be electrically connected to the active pattern AP to transfer the high power voltage ELVDD to the fifth transistor TR5.

[0072] For example, the data lines DL and the power wirings PL may extend in a second direction D2 crossing the first direction D1.

[0073] According to an embodiment, the first connection wiring CL1, the data line DL, and the power wiring PL may be formed in the same layer. For example, the first connection wiring CL1, the data line DL, and the power wiring PL may be referred to as a first source metal pattern. The first source metal pattern may further include a second connection wiring CL2 and a third connection wiring CL3. The second connection wiring CL2 may electrically connect the sixth transistor TR6 to the organic light emitting diode OLED. The third connection wiring CL3 may electrically connect the initialization voltage wiring Vint to the active pattern AP. However, embodiments according to the present disclosure are not limited thereto. For example, at least one of the first to third connection wirings CL1, CL2, and CL3, the data line DL, and the power wiring PL may be located in a different layer from the others.

[0074] The pixel unit of the display device according to the embodiment may further include another active layer and / or another metal layer in addition to the active pattern AP, the first gate metal pattern, the second gate metal pattern, and the first source metal pattern.

[0075] Figure 3A cross-sectional view illustrating a driving element and a light emitting element of a display device according to an embodiment. Figure 3 The drive elements can be partially explained. For example, Figure 3 A driving transistor and a switching transistor may be shown. For example, the driving transistor and the switching transistor may correspond to Figure 1 and Figure 2 The first transistor TR1 and the fifth transistor TR5 of the pixel unit illustrated in FIG.

[0076] The buffer layer 120 may be located on the base substrate 110. The active pattern may be located on the buffer layer 120.

[0077] For example, the base substrate 110 may include glass, quartz, sapphire, or a polymer material, etc. According to an embodiment, the base substrate 110 may include a transparent rigid material such as glass.

[0078] The buffer layer 120 can prevent or reduce the penetration of impurities, moisture or external gas from the bottom of the base substrate 110, and can reduce the roughness of the upper surface of the base substrate 110. For example, the buffer layer 120 may include an inorganic material such as silicon oxide or silicon nitride. For example, the buffer layer 120 may include a lower layer including silicon nitride and an upper layer including silicon oxide. According to an embodiment, the base substrate 110 may include a plurality of regions having different upper surface heights. Therefore, the upper surface of the buffer layer 120 may have different heights, depending on the different heights of the base substrate 110.

[0079] The active pattern may include a channel region, a source region, and a drain region. For example, the active pattern may include channel regions CH1 and CH2, source regions SR1 and SR2 electrically connected to the channel regions CH1 and CH2, and drain regions DR1 and DR2 electrically connected to the channel regions CH1 and CH2. The source regions SR1 and SR2 and the drain regions DR1 and DR2 may be used as source terminals and drain terminals, respectively.

[0080] According to an embodiment, the active pattern may include a first active area AP1 and a second active area AP2. The first active area AP1 may include a first channel area CH1, a first source area SR1, and a first drain area DR1. The second active area AP2 may include a second channel area CH2, a second source area SR2, and a second drain area DR2. For example, the first active area AP1 and the second active area AP2 may be formed in the same pattern to be continuously connected to each other. For example, the first source area SR1 of the first active area AP1 may be connected to the second drain area DR2 of the second active area AP2. However, embodiments according to the present disclosure are not limited thereto. For example, the first active area AP1 and the second active area AP2 may be defined by different patterns spaced apart from each other.

[0081] According to an embodiment, the upper surface of the base substrate 110 and the upper surface of the buffer layer 120 may have a height variation. Therefore, the active regions on the buffer layer 120 may be located at different heights. According to an embodiment, the first channel region CH1 or the first active region AP1 including the first channel region CH1 may be arranged to be higher than the second channel region CH2 or the second active region AP2 including the second channel region CH2.

[0082] The first gate metal pattern may be located on the active pattern. For example, the first gate metal pattern may include a first gate electrode GE1 overlapping the first channel region CH1 and a second gate electrode GE2 overlapping the second channel region CH2. The first insulating layer 130 may be located between the active pattern and the first gate metal pattern.

[0083] The active pattern and the gate electrode may define a plurality of transistors. For example, Figure 1 and Figure 2 The first transistor TR1 illustrated in FIG. 1 may be defined by the first gate electrode GE1 and the first active area AP1 . Figure 1 and Figure 2 The fifth transistor TR5 explained in the figure may be defined by the second gate electrode GE2 and the second active area AP2. The first transistor TR1 may be a driving transistor that provides a driving current ID to the organic light emitting diode OLED. The fifth transistor TR5 may be a switching transistor that receives an emission control signal EM. The second gate electrode GE2 may be defined by a portion of the third scan line SL3 that transmits the emission control signal EM.

[0084] However, embodiments according to the present disclosure are not limited thereto. For example, at least one of the second transistor TR2, the third transistors TR3_1 and TR3_2, the fourth transistors TR4_1 and TR4_2, the sixth transistor TR6, and the seventh transistor TR7 may be defined by the second gate electrode GE2 and the second active region AP2.

[0085] The second gate metal pattern including the capacitor electrode pattern CP may be located on the first gate metal pattern. For example, the capacitor electrode pattern CP may overlap the first gate electrode GE1.

[0086] The second insulating layer 140 may be located between the first gate metal pattern and the second gate metal pattern. The third insulating layer 150 may be located on the second gate metal pattern.

[0087] For example, the active pattern may include silicon or a metal oxide semiconductor. According to an embodiment, the active pattern may include polysilicon (polycrystalline silicon, polysilicon), which may be doped with n-type impurities or p-type impurities.

[0088] According to an embodiment, the active pattern may include a metal oxide semiconductor. For example, the active pattern may include a two-component compound (AB x), ternary compounds (AB x C y ) or four-component compound (AB x C y D z ), which contains indium (In), zinc (Zn), gallium (Ga), tin (Sn), titanium (Ti), aluminum (Al), hafnium (Hf), zirconium (Zr) and / or magnesium (Mg). For example, the active pattern may include zinc oxide (ZnO x ), gallium oxide (GaO x ), titanium oxide (TiO x ), tin oxide (SnO x ), indium oxide (InO x ), indium gallium oxide (IGO), indium zinc oxide (IZO), indium tin oxide (ITO), gallium zinc oxide (GZO), zinc magnesium oxide (ZMO), zinc tin oxide (ZTO), zinc zirconium oxide (ZnZr x O y ), indium gallium zinc oxide (IGZO), indium zinc tin oxide (IZTO), indium gallium hafnium oxide (IGHO), tin aluminum zinc oxide (TAZO) or indium gallium tin oxide (IGTO), etc.

[0089] The first insulating layer 130, the second insulating layer 140, and the third insulating layer 150 may each include silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. In addition, the first insulating layer 130, the second insulating layer 140, and the third insulating layer 150 may each include an insulating metal oxide, such as aluminum oxide, tantalum oxide, hafnium oxide, zirconium oxide, or titanium oxide. For example, the first insulating layer 130, the second insulating layer 140, and the third insulating layer 150 may each have a single-layer structure or a multi-layer structure including silicon nitride and / or silicon oxide.

[0090] For example, the first gate metal pattern and the second gate metal pattern may each include gold (Au), silver (Ag), aluminum (Al), copper (Cu), nickel (Ni), platinum (Pt), magnesium (Mg), chromium (Cr), tungsten (W), molybdenum (Mo), titanium (Ti), tantalum (Ta) or an alloy thereof, and may each have a single-layer structure or a multi-layer structure including different metal layers.

[0091] The first source metal pattern may be located on the third insulating layer 150. The first source metal pattern may include a power wiring PL that passes through the insulating layer thereunder to electrically contact the active pattern. For example, the power wiring PL may electrically contact the second source region SR2. The first source metal pattern may further include at least one connection wiring including a first connection wiring CL1 electrically connected to the first gate electrode GE1 and the active pattern.

[0092] For example, the first source metal pattern may include gold (Au), silver (Ag), aluminum (Al), copper (Cu), nickel (Ni), platinum (Pt), magnesium (Mg), chromium (Cr), tungsten (W), molybdenum (Mo), titanium (Ti), tantalum (Ta) or an alloy thereof, and may have a single-layer structure or a multi-layer structure including different metal layers. According to an embodiment, the first source metal pattern may have a multi-layer structure including at least an aluminum layer.

[0093] The fourth insulating layer 160 may be located on the first source metal pattern. The fourth insulating layer 160 may cover the structure below it to planarize the substrate. The fourth insulating layer 160 may include an organic material. For example, the fourth insulating layer 160 may include an organic insulating material such as phenolic resin, acrylic resin, polyimide resin, polyamide resin, siloxane resin or epoxy resin. The fourth insulating layer 160 may be called a through-hole insulating layer or an organic insulating layer.

[0094] The light emitting element EL may be located on the fourth insulating layer 160. The light emitting element EL may include a first electrode EL1, an organic layer OL located on the first electrode EL1, and a second electrode EL2 located on the organic layer OL. The light emitting element EL may be electrically connected to the transistor. For example, the light emitting element EL may be electrically connected to the drain terminal of the sixth transistor TR6.

[0095] The pixel defining layer PDL may be located on the fourth insulating layer 160. The pixel defining layer PDL may include an opening overlapping at least a portion of the first electrode EL1. At least a portion of the organic layer OL may be located in the opening of the pixel defining layer PDL. According to an embodiment, the organic layer OL may include a common layer continuously extending throughout a plurality of pixel regions, or may have a pattern shape located within a pixel region. The pixel defining layer PDL may include an organic material.

[0096] The first electrode EL1 may be used as an anode. For example, the first electrode EL1 may be formed as a transmissive electrode or a reflective electrode according to the emission type of the display device. When the first electrode EL1 is a transmissive electrode, the first electrode EL1 may include indium tin oxide, indium zinc oxide, zinc tin oxide, indium oxide, zinc oxide, or tin oxide, etc. When the first electrode EL1 is a reflective electrode, the first electrode EL1 may include gold (Au), silver (Ag), aluminum (Al), copper (Cu), nickel (Ni), platinum (Pt), magnesium (Mg), chromium (Cr), tungsten (W), molybdenum (Mo), titanium (Ti), or a combination thereof, and may have a stacked structure further including a material that can be used for a transmissive electrode.

[0097] The organic layer OL may include at least an emission layer, and may further include at least one of a hole injection layer (HIL), a hole transport layer (HTL), an electron transport layer (ETL), and an electron injection layer (EIL). For example, the organic layer OL may include a low molecular weight organic compound or a high molecular weight organic compound.

[0098] According to an embodiment, the organic layer OL may emit red light, green light, or blue light. According to an embodiment, the organic layer OL may emit white light. The organic layer OL emitting white light may have a multilayer structure including a red emission layer, a green emission layer, and a blue emission layer, or a single layer structure including a mixture of a red emission material, a green emission material, and a blue emission material.

[0099] The second electrode EL2 may be used as a cathode. The second electrode EL2 may be formed as a transmissive electrode or a reflective electrode according to the emission type of the display device. For example, the second electrode EL2 may include a metal, a metal alloy, a metal nitride, a metal fluoride, a conductive metal oxide, or a combination thereof.

[0100] For example, the second electrode EL2 may be formed as a common layer continuously extending across a plurality of pixel regions.

[0101] The encapsulation layer EN may be located on the second electrode EL2. The encapsulation layer EN may have a stacked structure of an inorganic film and an organic film. For example, the encapsulation layer EN may include a first inorganic film, an organic film located on the first inorganic film, and a second inorganic film located on the organic film.

[0102] For example, the organic film may include a cured polymer resin, such as poly (meth) acrylate, etc. For example, the cured polymer resin may be formed by a cross-linking reaction of a monomer. For example, the inorganic film may include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, tantalum oxide, hafnium oxide, zirconium oxide, titanium oxide, or a combination thereof.

[0103] The base substrate 110 includes at least one polymer film. For example, the base substrate 110 may include an upper polymer film 102, a lower polymer film 104 located below the upper polymer film 102, a lower barrier layer 106 located between the upper polymer film 102 and the lower polymer film 104, an upper barrier layer 108 located between the upper polymer film 102 and the active pattern, and an adhesion enhancement layer 107 located between the upper polymer film 102 and the lower barrier layer 106.

[0104] For example, the upper polymer film 102 may be referred to as a first polymer film, and the lower polymer film 104 may be referred to as a second polymer film. The upper barrier layer 108 may be referred to as a first barrier layer, and the lower barrier layer 106 may be referred to as a second barrier layer. Herein, terms such as "first" and "second" are used to distinguish elements, rather than to refer to specific elements.

[0105] The upper polymer film 102 and the lower polymer film 104 may each include a polymer material. For example, the upper polymer film 102 and the lower polymer film 104 may each include polyethylene terephthalate, polyethylene naphthalate, polyether ketone, polycarbonate, polyarylate, polyether sulfone, polyimide, polybenzoxazole, polybenzobisoxazole, polybenzimidazole, polybenzothiazole or a combination thereof. According to an embodiment, the upper polymer film 102 and the lower polymer film 104 may each include polyimide.

[0106] The lower barrier layer 106 and the upper barrier layer 108 may each include an inorganic material. For example, the lower barrier layer 106 and the upper barrier layer 108 may each include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, tantalum oxide, hafnium oxide, zirconium oxide, titanium oxide, or a combination thereof. For example, the lower barrier layer 106 and the upper barrier layer 108 may each include silicon oxide.

[0107] The adhesion enhancing layer 107 may increase adhesion of the upper polymer film 102 and the lower barrier layer 106. For example, the adhesion enhancing layer 107 may include amorphous silicon.

[0108] According to an embodiment, the upper polymer film 102 may have a thickness variation. For example, the first thickness T1 of the first region A1 overlapping the first channel region CH1 may be greater than the thickness of other regions. For example, the first thickness T1 of the first region A1 may be greater than the second thickness T2 of the second region A2 overlapping the second channel region CH2. According to an embodiment, the second region A2 is not limited to the region overlapping the second channel region CH2. For example, the second region A2 may include a peripheral region adjacent to the first region A1 or a region overlapping the channel of another transistor.

[0109] According to an embodiment, the lower polymer film 104 may have a uniform thickness.

[0110] For example, refer to Figure 4 and Figure 5 , the gate voltage applied to the second gate electrode GE2 located on the second channel region CH2 may be used as a bias voltage. For example, a fringe field (caused by the bias voltage) may be formed between the first active region AP1 and the second active region AP2 by the dipole polarization of the upper polymer film 102 and the bias voltage. Figure 4 and Figure 5 For example, when the second active region AP2 defines the fifth transistor TR5, a fringe field may be formed by the emission control signal EM applied to the second gate electrode GE2.

[0111] refer to Figure 5 , when the thickness of the upper polymer film 102 increases under the first channel region CH1, the dielectric constant changes. As a result, Figure 4Compared to the structure explained in the embodiment (in which the upper polymer film 102 has a uniform thickness), under the first channel region CH1, the direction of the fringe field can be tilted to be closer to the horizontal direction. In addition, because the first channel region CH1 is arranged to be higher than the second channel region CH2, the influence of the fringe field on the first channel region CH1 can be reduced. Therefore, the charge accumulated at the lower interface of the first channel region CH1 by the fringe field can be reduced. Therefore, the variation of the driving voltage can be reduced, thereby improving the reliability of the display device. For example, according to an embodiment, the image sticking quality factor (ISFOM) related to the medium / long term afterimage of the display device can be improved.

[0112] According to an embodiment, the ratio of the first thickness T1 to the second thickness T2 in the upper polymer film 102 may be at least 1.2 to achieve a sufficient effect of changing the fringe field. For example, the ratio of the first thickness T1 to the second thickness T2 in the upper polymer film 102 may be 1.2 to 1.5. When the ratio of the first thickness T1 to the second thickness T2 is less than 1.2, the effect may be small. When the ratio of the first thickness T1 to the second thickness T2 is greater than 1.5, the pattern formed on the base substrate 110 may be disconnected due to the height difference, or an additional process may be required to compensate for the height difference. For example, the difference between the first thickness T1 and the second thickness T2 may be to

[0113] Figures 6 to 8 A cross-sectional view for explaining a method for manufacturing a base substrate of a display device according to an embodiment.

[0114] refer to Figure 6 , a lower barrier layer 106 is formed on the lower polymer film 104. An adhesion enhancing layer 107 is formed on the lower barrier layer 106. A polymer common layer 102' is formed on the adhesion enhancing layer 107.

[0115] The lower polymer film 104 may be formed on a carrier substrate. For example, the carrier substrate may include a rigid material, such as glass. The carrier substrate may be removed after the pixel structure is formed.

[0116] For example, a composition including a polymer or a polymer precursor may be coated on a carrier substrate and then dried and / or cured to form the lower polymer film 104. According to an embodiment, the composition may include polyimide or a polyimide precursor, such as polyamic acid. The polymer common layer 102' may be formed on the adhesion enhancement layer 107 by a process similar to that used to form the lower polymer film 104.

[0117] The mask PR may be formed on the polymer common layer 102' in the first area A1. For example, the mask PR may be formed of a photoresist composition.

[0118] refer to Figure 7 , the exposed portion of the polymer common layer 102' is partially etched to reduce the thickness of the exposed portion. For example, the exposed portion of the polymer common layer 102' may be dry-etched.

[0119] Since the first area A1 is covered by the mask PR, the thickness of the first area A1 may be maintained. As a result, the upper polymer film 102 may have a first thickness T1 in the first area A1 and a second thickness T2 less than the first thickness T1 in the remaining area.

[0120] refer to Figure 8 , an upper barrier layer 108 is formed on the upper polymer film 102 to form a base substrate 110. For example, the lower barrier layer 106 may include an inorganic material such as silicon oxide. When the upper polymer film 102 has a thickness variation, the upper surface of the upper polymer film 102 may have a height variation. Therefore, the upper surface of the upper barrier layer 108 and the upper surface of the base substrate 110 may have a height variation.

[0121] The driving element, the light emitting element and the encapsulation layer may be formed on the base substrate 110, such as Figure 3 Explained in.

[0122] Fig. 9 A plan view of a first region of a base substrate for explaining a display device according to an embodiment.

[0123] According to an embodiment, the first area A1 of the base substrate 110 may be selectively Figure 2 In order to form the base substrate 110, when the mask PR is formed by photolithography, the same exposure mask as the exposure mask used to form the second gate metal pattern including the capacitor electrode pattern CP may be used. Therefore, the first region A1 may have the same (or substantially the same) planar shape as the second gate metal pattern including the capacitor electrode pattern CP.

[0124] For example, the edge of the first area A1 of the base substrate 110 may extend along the edge of the capacitor electrode pattern CP. Fig. 9 In addition, the first area A1 may further overlap at least one of the shielding pattern SP and the initialization voltage wiring Vint. In addition, the opening overlap area OA of the base substrate 110 overlapping the opening OP of the capacitor electrode pattern CP and surrounded by the first area A1 may have a thickness less than that of the first area A1.

[0125] According to an embodiment, the opening overlap area OA may not overlap the first channel region CH1 so that the first area A1 may completely overlap the first channel region CH1. For example, in a plan view, the opening overlap area OA may be spaced apart from the first channel region CH1.

[0126] Fig.10 and Fig.11 A cross-sectional view for explaining a method for manufacturing a base substrate of a display device according to an embodiment.

[0127] refer to Fig.10 , the polymer common layer 102 a is formed on the adhesion enhancing layer 107 located on the lower polymer film 104 and the lower barrier layer 106 .

[0128] refer to Fig.11 , the polymer pattern 102b is formed on the polymer common layer 102a. For example, a composition including a polymer or a polymer precursor may be partially coated on the polymer common layer 102a, and then dried and / or cured to form the polymer pattern 102b. For example, a polyimide (PI) coating method using the coating device 200 may be used to form the polymer pattern 102b.

[0129] For example, the polymer pattern 102b located in the first area A1 may have the same (or substantially the same) planar shape as the second gate metal pattern including the capacitor electrode pattern CP. Fig. 9 For example, the edge of the polymer pattern 102b of the base substrate 110 may extend along the edge of the capacitor electrode pattern CP. In addition, the polymer pattern 102b may further overlap at least one of the shielding pattern SP and the initialization voltage wiring Vint.

[0130] However, the embodiments according to the present disclosure are not limited thereto. For example, the polymer pattern 102 b may be selectively formed in a region overlapping the first gate electrode GE1 .

[0131] When the polymer pattern 102 b is selectively formed in the first area A1 , the upper polymer film 102 including the polymer pattern 102 b may have a first thickness T1 in the first area A1 , and a second thickness T2 less than the first thickness T1 in the remaining area.

[0132] Fig.12 A cross-sectional view illustrating a driving element and a light emitting element of a display device according to an embodiment.

[0133] refer to Fig.12 The display device includes a base substrate 110, a driving element, and a light emitting element. In addition to the base substrate 110, the display device may have Figure 2 and Figure 3 Therefore, some repeated explanations may be omitted.

[0134] The base substrate 110 includes at least one polymer film. For example, the base substrate 110 may include an upper polymer film 102, a lower polymer film 104 located below the upper polymer film 102, a lower barrier layer 106 located between the upper polymer film 102 and the lower polymer film 104, an upper barrier layer 108 covering the upper surface of the upper polymer film 102, and an adhesion enhancement layer 107 located between the upper polymer film 102 and the lower barrier layer 106.

[0135] The adhesion enhancing layer 107 and the lower barrier layer 106 may each include an opening overlapping the first area A1. The upper polymer film 102 may include a protrusion filling the opening. Therefore, the first thickness T1 of the upper polymer film 102 in the first area A1 may be greater than the second thickness T2 of the upper polymer film 102 in the remaining area. The first area A1 may overlap with the first channel region CH1 defining the channel of the driving transistor.

[0136] The upper polymer film 102 may contact the lower polymer film 104 through the openings of the adhesion enhancement layer 107 and the lower barrier layer 106 .

[0137] When the adhesion enhancing layer 107 including amorphous silicon is disposed under the upper polymer film 102, the fringe field may be increased by the adhesion enhancing layer 107. According to an embodiment, since the adhesion enhancing layer 107 is removed under the first channel region CH1, the fringe field affecting the first channel region CH1 may be reduced.

[0138] Fig.13 , Fig.14 and Fig.15 To illustrate the use of manufacturing Fig.12 A cross-sectional view of a method for forming a base substrate of a display device is illustrated in FIG.

[0139] refer to Fig.13 The lower barrier layer 106 is formed on the lower polymer film 104. The adhesion enhancing layer 107 is formed on the lower barrier layer 106. The mask PR is formed on the adhesion enhancing layer 107.

[0140] The mask PR may be formed of a photoresist composition and may include an opening overlapping the first region A1. For example, when the mask PR is formed by photolithography, the same exposure mask as the exposure mask used to form the second gate metal pattern including the capacitor electrode pattern CP may be used (the type of the photoresist composition may be opposite). Therefore, the first region A1 may have the same (or substantially the same) planar shape as the second gate metal pattern, such as Fig. 9 For example, the edge of the first area A1 of the base substrate 110 may extend along the edge of the capacitor electrode pattern CP. Fig. 9 In addition, the first area A1 may further overlap at least one of the shielding pattern SP and the initialization voltage wiring Vint.

[0141] refer to Fig.14 , the adhesion enhancing layer 107 and the lower barrier layer 106 below the adhesion enhancing layer 107 are partially removed below the opening of the mask PR. Therefore, an opening is formed through the adhesion enhancing layer 107 and the lower barrier layer 106.

[0142] refer to Fig.15 , a composition including a polymer or a polymer precursor is coated on the adhesion enhancing layer 107 , and then dried and / or cured to form the upper polymer film 102 .

[0143] The upper polymer film 102 includes protrusions filling the openings of the adhesion enhancing layer 107 and the lower barrier layer 106. Therefore, the upper polymer film 102 has a first thickness T1 in the first area A1, and has a second thickness T2 less than the first thickness T1 in the remaining area.

[0144] refer to Fig.16 , the base substrate may include a lower barrier layer 106 that does not include an opening in the first area A1. The adhesion enhancement layer 107 may be located between the upper polymer film 102 and the lower barrier layer 106, and may include an opening that overlaps the first area A1. Therefore, the upper polymer film 102 may include a protrusion that fills the opening of the adhesion enhancement layer 107, and may be completely spaced apart from the lower polymer film 104.

[0145] According to an embodiment, the lower barrier layer 106 completely covers the upper surface of the lower polymer film 104. Therefore, impurities such as moisture or other contaminants may be prevented from moving into the upper polymer film 102.

[0146] Fig.17 A cross-sectional view illustrating a driving element and a light emitting element of a display device according to an embodiment. Fig.18 To illustrate the use of manufacturing Fig.17 A cross-sectional view of a method for forming a base substrate of a display device is illustrated in FIG.

[0147] refer to Fig.17 The display device includes a base substrate 110, a driving element, and a light emitting element. In addition to the base substrate 110, the display device may have Figure 2 and Figure 3 Therefore, some repeated explanations may be omitted.

[0148] The base substrate 110 includes at least one polymer film. For example, the base substrate 110 may include an upper polymer film 102, a lower polymer film 104 located below the upper polymer film 102, a lower barrier layer 106 located between the upper polymer film 102 and the lower polymer film 104, an upper barrier layer 108 covering the upper surface of the upper polymer film 102, and an adhesion enhancement layer 107 located between the upper polymer film 102 and the lower barrier layer 106.

[0149] According to an embodiment, the display device includes the field blocking pattern 109a in the first area A1 of the upper polymer film 102. The first area A1 may overlap the first channel region CH1 of the first active region AP1 that may define a channel of the driving transistor.

[0150] According to an embodiment, the field blocking pattern 109 a may be doped with ions so that the field blocking pattern 109 a may have greater conductivity than other regions of the upper polymer film 102 .

[0151] refer to Fig.18 , the field blocking pattern 109a may be formed by an ion implantation method. For example, a mask MK including an opening overlapping the first area A1 may be located on the upper polymer film 102. Ions may be provided to the first area A1 of the upper polymer film 102 through the mask MK to form the field blocking pattern 109a doped with ions. Therefore, the field blocking pattern 109a may have a cross-section recessed from the upper surface of the upper polymer film 102.

[0152] For example, the mask MK may have the same (or substantially the same) shape as an exposure mask used to form the second gate metal pattern including the capacitor electrode pattern CP. Therefore, the field blocking pattern 109a may have the same (or substantially the same) planar shape as the second gate metal pattern, such as Fig. 9 For example, the edge of the field blocking pattern 109a may extend along the edge of the capacitor electrode pattern CP. Fig. 9 In addition, the field blocking pattern 109a may further overlap at least one of the shielding pattern SP and the initialization voltage wiring Vint.

[0153] For example, the ions may include a p+ dopant, such as boron, or an n+ dopant, such as a phosphor.

[0154] refer to Fig.19, the base substrate 110 of the display device may include an upper polymer film 102, a lower polymer film 104 located below the upper polymer film 102, a lower barrier layer 106 located between the upper polymer film 102 and the lower polymer film 104, an upper barrier layer 108 covering the upper surface of the upper polymer film 102, and an adhesion enhancement layer 107 located between the upper polymer film 102 and the lower barrier layer 106. The display device further includes a field blocking pattern 109b located between the upper barrier layer 108 and the upper polymer film 102.

[0155] The field barrier pattern 109b may include a semiconductive material or a conductive material. For example, the field barrier pattern 109b may include amorphous silicon. For example, the field barrier pattern 109b may include phosphine. For example, the field barrier pattern 109b may include metal.

[0156] According to an embodiment, a layer including a semiconductive material or a conductive material is formed on the upper polymer film 102, and then patterned to form a field blocking pattern 109b. For example, an exposure mask used to form a mask pattern on the layer may be the same (or substantially the same) as an exposure mask used to form a second gate metal pattern including the capacitor electrode pattern CP. Therefore, the field blocking pattern 109b may have the same (or substantially the same) planar shape as the second gate metal pattern, such as Fig. 9 Explained in.

[0157] According to an embodiment, a field blocking pattern having greater conductivity than a polymer film may be located below a channel region of a driving element. Thus, a fringe field applied to the channel region may be blocked or reduced. Thus, a change in characteristics of the driving element may be prevented or reduced.

[0158] When the field barrier pattern is completely formed on the upper surface of the upper polymer film, display quality may be deteriorated due to horizontal crosstalk. According to an embodiment, since the field barrier pattern is selectively arranged under the channel region, horizontal crosstalk is not caused.

[0159] In addition, because the field barrier pattern is located between the upper barrier layer and the upper polymer film, the distance between the field barrier pattern and the channel region may be large. Therefore, even if the field barrier pattern is in a floating state, the channel region is not affected by the field barrier pattern. Therefore, even if there is no other wiring that provides a constant voltage, the fringe field applied to the channel region can be effectively blocked. For example, the distance between the field barrier pattern and the channel region may be at least 1000 Å. Or at least

[0160] Aspects of the embodiments include an organic light-emitting display device. However, the embodiments according to the present disclosure are not limited thereto. For example, aspects of the embodiments may include various display devices, such as an electroluminescent display device or a micro LED display device.

[0161] The embodiments may be applied to various display devices. For example, aspects of the embodiments may be applied to vehicle display devices, ship display devices, aircraft display devices, portable communication devices, display devices for display or for information transmission, medical display devices, etc.

[0162] The foregoing is an illustration of an embodiment and should not be construed as limiting thereof. Although embodiments have been described, it will be readily appreciated by those skilled in the art that many modifications are possible in the embodiments without substantially departing from the novel teachings and aspects of the inventive concept. Therefore, all such modifications are intended to be included within the scope of the inventive concept. Therefore, it is to be understood that the foregoing is an illustration of various embodiments and should not be construed as being limited to the specific embodiments disclosed, and modifications to the disclosed embodiments and other embodiments are intended to be included within the scope of the inventive concept, as set forth in the appended claims and their equivalents.

Claims

1. A display device, comprising: a base substrate comprising a first polymer film; an active pattern on the base substrate and including a first channel region and a second channel region; as well as a first gate electrode overlapping the first channel region; as well as a second gate electrode overlapping the second channel region, The first polymer film has a first thickness in a first region overlapping the first channel region, and has a second thickness smaller than the first thickness in a second region different from the first region and overlapping the second channel region.

2. The display device according to claim 1, further comprising a light emitting element, wherein a driving transistor defined by the first channel region and the first gate electrode is configured to provide a driving current to the light emitting element, A source terminal or a drain terminal of the switch transistor defined by the second channel region and the second gate electrode is electrically connected to a source terminal or a drain terminal of the drive transistor. The display device of claim 2 , wherein the second gate electrode is configured to receive an emission control signal. The display device according to claim 2 , wherein the light emitting element comprises an organic light emitting diode. The display device of claim 1 , wherein a ratio of the first thickness to the second thickness is at least 1.

2.

6. The display device according to claim 5, wherein the difference between the first thickness and the second thickness is to 7. The display device according to claim 1, wherein the base substrate further comprises: A second polymer film is below the first polymer film, and an adhesion enhancing layer is between the first polymer film and the second polymer film and includes amorphous silicon. 8 . The display device of claim 1 , further comprising a capacitor electrode pattern, wherein an edge of the first region extends along an edge of the capacitor electrode pattern. 9 . The display device of claim 1 , wherein a height of the first channel region is greater than a height of the second channel region.

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