A dimming control circuit and a dimming control chip thereof

Abstract

The present application provides a dimming control circuit and a dimming control chip thereof, wherein the dimming control circuit comprises a starting point control unit, a cycle control unit and a control logic unit; the starting point control unit is used to receive a load voltage, generate a timing start signal according to a preset reference voltage and the load voltage, and transmit the timing start signal to the cycle control unit; the cycle control unit is used to send a switching cycle end signal to the control logic unit after a first time length starting from the moment when the timing start signal is received; the control logic unit is used to generate a disconnection drive signal when the load voltage reaches a peak value, the disconnection drive signal is used to control a power control device in the load circuit to disconnect; and, after the power control device is disconnected, a closing drive signal is generated according to the received switching cycle end signal, the closing drive signal is used to control the power control device to close, thereby eliminating ripples.

Description

Technical Field

[0001] The present application relates to the field of dimming control technology, and in particular to a dimming control circuit and a dimming control chip thereof. Background Art

[0002] With the advent of an intelligent society, people are no longer satisfied with ordinary LED lighting, but have an urgent need for intelligent lighting, which has led to the emergence of LED intelligent dimming.

[0003] When the current LED intelligent dimming control circuit uses discontinuous conduction mode (DCM) for dimming, the dimming output current and the time length T CRM and time length T DCM The ratio of is linearly related, where the time length T in the traditional dimming control circuit CRM The time period from when the switch is closed to when the load current drops from the maximum to 0 is T. DCM It is the time period from the last closure of the switch to the next closure. In this dimming mode, since the inductor current in the load circuit will oscillate when it discharges to 0, the starting value of the load current will be inconsistent each time the switch is closed during the subsequent dimming process. This makes the subsequent load current from the starting point to the maximum and then to 0 The time length T CRM And the time length T from the last closure of the switch to the next closure DCM As a result, the dimming output current shows nonlinear fluctuations, and then the current ripple phenomenon occurs. Summary of the invention

[0004] The purpose of the embodiments of the present application is to provide a dimming control circuit and a dimming control chip thereof, so as to solve the ripple phenomenon existing in the current dimming method.

[0005] In a first aspect, the present invention provides a dimming control circuit, comprising: a starting point control unit, a cycle control unit and a control logic unit; the starting point control unit is used to receive a load voltage, generate a timing start signal according to a preset reference voltage and the load voltage, and transmit the timing start signal to the cycle control unit; the cycle control unit is used to send a switching cycle end signal to the control logic unit after a first time length starting from the moment when the timing start signal is received; the control logic unit is used to generate a disconnection drive signal when the load voltage reaches a peak value, the disconnection drive signal is used to control the power control device in the load circuit to disconnect; and, after the power control device is disconnected, generate a closing drive signal according to the received switching cycle end signal, the closing drive signal is used to control the power control device to close.

[0006] In the dimming control circuit designed above, the scheme designs that the cycle control unit sends a switching cycle end signal to the control logic unit after the first time length from the moment of receiving the timing start signal transmitted by the starting point control unit. The control logic unit disconnects the power control device of the load circuit when the load voltage is at a peak value. After the power control device is disconnected, the power control device is closed according to the switching cycle end signal sent by the cycle control unit. Since the timing start signal is generated by the starting point control unit according to the received load voltage and the preset reference voltage, and since the preset reference voltage is fixed, the voltage value of the load voltage reaching the preset reference voltage in each cycle is the same, so that in each switching cycle, the value of the load current is the same when the timing start signal is generated, so that the timing starting point of each cycle is the same; at the same time, since the first time length is fixed, the timing starting point is also fixed, so the time period T of the first time length starting from the moment of the timing start signal DCM is also fixed; in addition, in each switching cycle, the load current increases linearly when the power control device is closed, and decreases linearly after the power control device is disconnected. Since the control logic unit disconnects the power control device of the load circuit when the load voltage is at a peak value, the peak value of the load current is fixed, so that the time length T from the timing start point to the load current peak value and then to the load current dropping from the maximum to 0 CRM Also fixed, due to T CRM is fixed, T DCM is also fixed, therefore, the time ratio related to the dimming output current is fixed, so that the dimming output current is fixed without fluctuation, thereby eliminating ripple.

[0007] In an optional implementation of the first aspect, the starting point control unit is further used to send an inverted level signal of the timing start signal to the period control unit when the load current drops from a maximum to 0; the period control unit is further used to send the switching cycle end signal to the control logic unit after a second time length starting from the moment when the inverted level signal of the timing start signal is received, wherein the second time length is equal to the difference between the first time length and the time length from the generation of the timing start signal to the generation of the inverted level signal.

[0008] In an optional implementation of the first aspect, the dimming control circuit also includes a demagnetization detection unit, which is connected to the starting point control unit; the demagnetization detection unit is used to receive the load current of the load circuit, and generate a demagnetization completion signal when the load current drops from a maximum to 0, and transmit the demagnetization completion signal to the starting point control unit; the starting point control unit is used to send an inverted level signal of the timing start signal to the period control unit according to the demagnetization completion signal, a preset reference voltage and the load voltage.

[0009] In an optional implementation of the first aspect, the starting point control unit includes: a timing comparator, a first NOR gate, a second NOR gate and a first inverter; the positive input terminal of the timing comparator is used to receive the load voltage, the inverting input terminal of the timing comparator is used to receive the preset reference voltage, the output terminal of the timing comparator is connected to the first input terminal of the first NOR gate, the output terminal of the first NOR gate is respectively connected to the input terminal of the first inverter and the first input terminal of the second NOR gate, the second input terminal of the second NOR gate is connected to the demagnetization detection unit, the output terminal of the second NOR gate is connected to the second input terminal of the first NOR gate, and the output terminal of the first inverter is connected to the period control unit.

[0010] In an optional implementation of the first aspect, the cycle control unit includes a cycle control comparator and a logic circuit; the logic circuit is used to control the cycle control comparator to not work when the timing start signal is received; and drive the cycle control comparator to work when the inverted level signal of the timing start signal is received, so that the cycle control comparator sends the switching cycle end signal to the control logic unit after the second time length.

[0011] In an optional implementation of the first aspect, the cycle control unit is further used to receive a dimming signal; the cycle control unit is used to adjust the second time length according to the dimming signal to adjust the switching cycle length of the power control device and thereby adjust the brightness of the load circuit.

[0012] In an optional implementation of the first aspect, the cycle control unit also includes a pulse generating circuit, a cycle control comparator, a switch circuit, a first charge and discharge circuit, and a second charge and discharge circuit; the output end of the starting point control unit is respectively connected to the pulse generating circuit and the input end of the logic circuit, the output end of the logic circuit is respectively connected to the enable end of the cycle control comparator and the switch circuit, the first end of the switch circuit is used to connect to a reference signal source, the second end of the switch circuit is respectively connected to the inverting input end of the cycle control comparator and the first charge and discharge circuit, the non-phase input end of the cycle control comparator is connected to the second charge and discharge circuit and receives the dimming signal, and the cycle control The output end of the cycle control comparator is connected to the control logic unit, and the output end of the pulse generating circuit is respectively connected to the first charge and discharge circuit and the second charge and discharge circuit; the pulse generating circuit is used to send a pulse signal to the first charge and discharge circuit and the second charge and discharge circuit according to the timing start signal; the first charge and discharge circuit is used to discharge when receiving the pulse signal so as to reset the voltage of the inverting input end of the cycle control comparator connected to the first charge and discharge circuit; the second charge and discharge circuit is used to discharge when receiving the pulse, and charge according to the received dimming signal after discharging so as to increase the voltage of the non-phase input end of the cycle control comparator connected to the second charge and discharge circuit.

[0013] In an optional implementation of the first aspect, the logic circuit includes a second inverter; the input end of the second inverter is connected to the output end of the starting point control unit, and the output end of the second inverter is respectively connected to the enable end of the period control comparator and the switching circuit.

[0014] Preferably, the switching circuit includes a third controllable switch tube, the control end of the third controllable switch tube is connected to the output end of the second inverter, the first end of the third controllable switch tube is connected to the external power supply, and the second end of the third controllable switch tube is connected to the inverting input end of the period control comparator and the first charge and discharge circuit.

[0015] Preferably, the first charging and discharging circuit includes a first controllable switch tube and a first capacitor, the second end of the third controllable switch tube is respectively connected to the first end of the first capacitor and the first end of the first controllable switch tube, the second end of the first capacitor and the second end of the first controllable switch tube are connected and then grounded, and the control end of the first controllable switch tube is connected to the pulse generating circuit.

[0016] Preferably, the second charge and discharge circuit includes a second controllable switch tube and a second capacitor, the dimming signal is respectively connected to the non-phase input terminal of the period control comparator, the first end of the second capacitor and the first end of the second controllable switch tube, the second end of the second controllable switch tube is connected to the second end of the second capacitor and then grounded, and the control end of the second controllable switch tube is connected to the pulse generating circuit.

[0017] In an optional implementation of the first aspect, the dimming control circuit also includes a load peak control unit, an input end of the load peak control unit is used to receive the load voltage, and an output end of the load peak control unit is connected to the control logic unit; the load peak control unit is used to send a load peak signal to the control logic unit when the load voltage reaches a peak value, so that the control logic unit generates the disconnection drive signal according to the load peak signal; and send an opposite level signal of the load peak signal to the control logic unit when the load voltage is not at a peak value, so that the control logic unit generates the closing drive signal according to the opposite level signal of the load peak signal and the switching cycle end signal.

[0018] In an optional implementation of the first aspect, the control logic unit includes a control logic circuit and a drive circuit, a first input end of the control logic circuit is connected to an output end of the period control unit, and a second input end of the control logic circuit is connected to an output end of the load peak control unit; the output end of the control logic circuit is connected to the control end of the power control device through the drive circuit.

[0019] In an optional implementation of the first aspect, the control logic circuit includes a third inverter, a fourth inverter, a fifth inverter, a first NAND gate, a second NAND gate, a third NAND gate, a fourth NAND gate and an AND gate; the output end of the load peak control unit is respectively connected to the second input end of the second NAND gate and the first input end of the third NAND gate; the second input end of the third NAND gate is connected to the output end of the fourth NAND gate, the output end of the third NAND gate is respectively connected to the first input end of the fourth NAND gate and the input end of the fifth inverter, and the output end of the fifth inverter is connected to the second input end of the AND gate; the first input end of the second NAND gate is connected to the output end of the first NAND gate, the output end of the second NAND gate is respectively connected to the second input end of the first NAND gate and the input end of the fourth inverter, the first input end of the first NAND gate is connected to the output end of the third inverter, the input end of the third inverter is connected to the output end of the period control unit, the output end of the fourth inverter is connected to the first input end of the AND gate, and the output end of the AND gate is connected to the input end of the drive circuit.

[0020] In a second aspect, the present invention provides a dimming control chip, wherein the dimming control chip includes a dimming control circuit as described in any of the aforementioned embodiments. Since the dimming control chip includes a dimming control circuit as described in any of the optional embodiments of the first aspect, the dimming control chip can solve the ripple phenomenon caused by dimming in the current DCM mode, thereby improving the LED dimming effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments of the present application will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0022] Figure 1 A first structural diagram of a dimming control circuit provided in an embodiment of the present application;

[0023] Figure 2 A second structural diagram of the dimming control circuit provided in an embodiment of the present application;

[0024] Figure 3 A third structural diagram of the dimming control circuit provided in an embodiment of the present application;

[0025] Figure 4 A schematic diagram of the signal timing provided in the embodiment of the present application;

[0026] Figure 5 A fourth structural diagram of a dimming control circuit provided in an embodiment of the present application;

[0027] Figure 6 A fifth structural diagram of a dimming control circuit provided in an embodiment of the present application;

[0028] Figure 7 A sixth structural diagram of a dimming control circuit provided in an embodiment of the present application;

[0029] Figure 8 A seventh structural diagram of a dimming control circuit provided in an embodiment of the present application;

[0030] Fig. 9 The eighth structural diagram of the dimming control circuit provided in the embodiment of the present application;

[0031] Fig.10 A schematic diagram of the structure of the dimming control chip provided in an embodiment of the present application.

[0032] Icons: 1-dimming control chip; 10-starting point control unit; 20-cycle control unit; 2021-logic circuit; 2022-pulse generating circuit; 2023-switching circuit; 2024-first charge and discharge circuit; 2025-second charge and discharge circuit; 30-control logic unit; 301-control logic circuit; 302-driving circuit; 40-demagnetization detection unit; 50-load peak control unit; 60-signal conversion unit; 4-load circuit; 41-load working circuit; 42-power control device; 43-load detection circuit; L1-timing comparator; L2-cycle control comparator; L3-load peak comparator; O1-first NOR gate; O2-second NOR gate; F1-first inverter; F2-second inverter; F3-third inverter; F4-fourth inverter; F5-fifth inverter; F6-sixth inverter; M0-MOS tube; M1-first controllable switch tube; M2-second controllable switch tube; M3-third controllable switch tube; C-capacitor; C1-first capacitor; C2-second capacitor; A1-first NAND gate; A2-second NAND gate; A3-third NAND gate; A4-fourth NAND gate; A5-AND gate; G1-inductor; Q1-diode; Iref-reference signal source. DETAILED DESCRIPTION

[0033] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application.

[0034] First embodiment

[0035] The present application provides a dimming control circuit, which is used to perform dimming control on a load in a load circuit. Figure 1 As shown, the load circuit 4 includes a load working circuit 41, a power control device 42 and a load detection circuit 43 connected in sequence. Specifically, the load working circuit 41 can be as follows Figure 1 The LED lamp, inductor G1, capacitor C and diode Q1 are shown, and the power control device 42 can be as follows Figure 1 The MOS tube M0 shown in the figure, the load detection circuit 43 can be as follows Figure 1The resistor R1 shown, the positive electrode of the LED lamp is respectively connected to the cathode of the diode Q1, the first end of the capacitor C and the power supply, the negative electrode of the LED lamp is respectively connected to the second end of the capacitor C and the first end of the inductor G1, the second end of the inductor G1 is connected to the anode of the diode Q1, the anode of the diode Q1 is also connected to the drain of the MOS tube M0, and the source of the MOS tube M0 is grounded through the resistor R1. On the basis of the load circuit 4 of the above circuit topology, the dimming control circuit designed in this application dims the LED lamp in the load working circuit 41. It should be noted here that the load circuit 4 described above is only a specific implementation structure of the current load circuit, and the dimming control circuit designed in this application can dim any load circuit currently working in the DCM mode.

[0036] like Figure 1 As shown, the dimming control circuit designed in the present application includes a starting point control unit 10, a cycle control unit 20 and a control logic unit 30. The input end of the starting point control unit 10 is used to receive the load voltage, the output end of the starting point control unit 10 is connected to the input end of the cycle control unit 20, the output end of the cycle control unit 20 is connected to the input end of the control logic unit 30, and the output end of the control logic unit 30 is connected to the control end of the power control device 42, that is, the control logic unit 30 is connected to the gate of the MOS tube M0.

[0037] The above description of the starting point control unit 10 is used to receive the load voltage, specifically, as Figure 1 As shown, based on the aforementioned load circuit 4, the input end of the starting point control unit 10 can be connected to the connection end between the load detection circuit 43 and the power control device 42, so as to sample the voltage of the connection end between the load detection circuit 43 and the power control device 42 to obtain the load voltage Vcs.

[0038] After receiving the load voltage Vcs, the starting point control unit 10 generates a timing start signal Star according to the load voltage Vcs and the preset reference voltage Vref and transmits the timing start signal Star to the cycle control unit 20. As a possible implementation, the starting point control unit 10 sends the timing start signal Star to the cycle control unit 20 when the load voltage Vcs is greater than the preset reference voltage Vref; as another possible implementation, the starting point control unit 10 sends the timing start signal Star to the cycle control unit when the load voltage Vcs is less than the preset reference voltage Vref.

[0039] After receiving the timing start signal Star, the cycle control unit 20 sends a switching cycle end signal to the control logic unit 30 after a first time length starting from the moment of receiving the timing start signal Star.

[0040] The control logic unit 30 generates a disconnect drive signal when the load voltage Vcs reaches a peak value, and the disconnect drive signal is transmitted to the power control device 42, so that the power control device 42 is disconnected; after the power control device 42 is disconnected, the control logic unit 30 generates a closing drive signal according to the received switching cycle end signal, and the closing drive signal is transmitted to the power control device 42, so that the power control device 42 is converted from disconnected to closed.

[0041] Since the dimming control circuit designed in the present application is for the discontinuous conduction mode, in the discontinuous conduction mode, the power control device 42 is turned on and off from time to time. When the power control device 42 is closed, since the load working circuit 41 has the inductor G1 and the capacitor C, the load current Ics gradually increases from the time the power control device 42 is closed until the power control device 42 is disconnected. After the power control device 42 is disconnected, the load current Ics gradually decreases from the maximum value. Since the load working circuit 41 has the inductor G1 and the capacitor C, the load current Ics oscillates after being reduced to 0.

[0042] In the dimming control circuit designed as described above in the present application, assuming that in the initial state, the power control device 42 is closed, the load current Ics gradually increases, so that the load voltage Vcs gradually increases. Assuming that the load voltage Vcs is greater than the preset reference voltage Vref and a timing start signal is output as an example, in the process of the load voltage Vcs gradually increasing, when the load voltage Vcs is greater than the preset reference voltage Vref, the starting point control unit 10 generates a timing start signal and sends it to the period control unit 20, and the period control unit 20 starts timing from the moment the timing start signal is received.

[0043] Since the power control device 42 is closed, the load current Ics continues to increase, and the load voltage Vcs also continues to increase. When the load voltage Vcs reaches a peak value, the control logic unit 30 controls the power control device 42 to be disconnected.

[0044] After the power control device 42 is disconnected, the load current Ics gradually decreases, and the load voltage Vcs jumps to 0. The cycle control unit 20 starts timing from the moment when the timing start signal is received, and sends a switching cycle end signal to the control logic unit 30 after the first time length from the start of timing, so that the control logic unit 30 converts the disconnected power control device 42 to a closed state according to the switching cycle end signal, thereby making the power control device 42 close again and enter the next cycle.

[0045] After the power control device 42 enters the next cycle, the load current Ics and the load voltage Vcs continue to increase. When the load voltage Vcs is greater than the preset reference voltage Vref, the starting point control unit 10 generates a timing start signal and sends it to the cycle control unit 20 to start timing, thereby repeating the above process.

[0046] In the above process, since the timing starts from the moment when the cycle control unit 20 receives the timing start signal, the timing start point is the moment when the cycle control unit 20 receives the timing start signal.

[0047] The timing start signal is generated based on the load voltage and the preset reference voltage. In each switching cycle, the load voltage increases linearly when the power control device 42 is closed, and drops from the maximum to 0 after the power control device 42 is disconnected. Therefore, the voltage value of the load voltage reaching the preset reference voltage is the same in each cycle, so that the load current value in each cycle at the time when the timing start signal is generated is the same.

[0048] Since the timing starting point of each cycle is the same, the cycle control unit 20 sends a switching cycle end signal after the first time length from the moment of receiving the timing start signal, so that the control logic unit 30 controls the power control device 42 to be disconnected. Since the first time length is fixed, the timing starting point is also fixed. Therefore, the present application solution sets the time length T from the timing starting point to the time when the power control device 42 is closed in the next cycle. DCM Also fixed.

[0049] Since in this scheme the control logic unit 30 controls the power control device 42 to disconnect when the load voltage reaches a peak value, the load current Ics increases linearly to a fixed peak value after the power control device 42 is closed in each switching cycle, and then the power control device 42 is disconnected, and the load current Ics drops from the fixed peak value to 0 and then oscillates.

[0050] Since the load current value at the timing start point of each cycle is the same, the peak value of the load current Ics is also fixed, and the load current Ics changes linearly before it drops from the maximum to 0, the time length T from the timing start point to the time point when the load current Ics drops from the maximum to 0 is CRM is fixed.

[0051] On the basis of the above, due to T CRM is fixed, T DCM is also fixed, therefore, the time ratio related to the dimming output current is fixed, so that the dimming output current is fixed without fluctuation, that is, the ripple is eliminated.

[0052] In the dimming control circuit designed above, the cycle control unit 20 of this scheme sends a switching cycle end signal to the control logic unit 30 after the first time length from the moment of receiving the timing start signal Star transmitted by the starting point control unit 10. The control logic unit 30 disconnects the power control device 42 of the load circuit 4 when the load voltage is at a peak value. After the power control device 42 is disconnected, the power control device 42 is closed according to the switching cycle end signal sent by the cycle control unit 20. Since the timing start signal Star is generated by the starting point control unit 10 according to the received load voltage and the preset reference voltage, and since the preset reference voltage Vref is fixed, the voltage value of the load voltage Vcs reaching the preset reference voltage Vref in each cycle is the same, so that in each switching cycle, the value of the load current Ics is the same when the timing start signal Star is generated, so that the timing starting point of each cycle is the same; at the same time, since the first time length is fixed, the timing starting point is also fixed, so the time period T of the first time length starting from the moment of the timing start signal Star DCM Also fixed; in addition, in each switching cycle, the load current Ics increases linearly when the power control device 42 is closed, and decreases linearly after the power control device 42 is disconnected, and because the control logic unit 30 disconnects the power control device 42 of the load circuit 4 when the load voltage is at a peak value, the peak value of the load current Ics is fixed, so that the time length T from the timing start point to the load current Ics reaching a peak value and then to the load current Ics dropping from a maximum value to 0 CRM Also fixed, due to T CRM is fixed, T DCM is also fixed, therefore, the time ratio related to the dimming output current is fixed, so that the dimming output current is fixed without fluctuation, thereby eliminating ripple.

[0053] In an optional implementation manner of the present embodiment, the starting point control unit 10 is also used to send an inverted level signal of the timing start signal to the period control unit 20 when the load current drops from the maximum to 0. For example, assuming that the timing start signal is a high level signal, then the inverted level signal is a low level signal; assuming that the timing start signal is a low level signal, then the inverted level signal is a high level signal.

[0054] The cycle control unit 20 sends the switching cycle end signal to the control logic unit 30 after the second time length from the moment when the inverted level signal is received. Since the inverted level signal is generated at the moment when the load current Ics drops from the maximum to 0, the time length from the generation of the timing start signal to the generation of the inverted level signal is the aforementioned T CRM , that is, the second time length T = the first time length T DCM -T CRM.

[0055] As a possible implementation, Figure 2 As shown, the dimming control circuit also includes a demagnetization detection unit 40, which is connected to the starting point control unit 10 and is used to send a demagnetization completion signal to the starting point control unit 10 when the load current Ics drops from the maximum to 0, and the starting point control unit 10 sends an inverted level signal of the timing start signal Star to the period control unit 20 according to the demagnetization completion signal.

[0056] As a possible implementation, the starting point control unit 10 can be designed as follows Figure 3 The structure shown is used to achieve the aforementioned functions.

[0057] The starting point control unit 10 includes a timing comparator L1 , a first NOR gate O1 , a second NOR gate O2 , and a first inverter F1 .

[0058] The non-inverting input terminal of the timing comparator L1 is used to receive the load voltage Vcs, the inverting input terminal of the timing comparator L1 is used to receive the preset reference voltage Vref, the output terminal of the timing comparator L1 is connected to the first input terminal of the first NOR gate O1, the output terminal of the first NOR gate O1 is respectively connected to the input terminal of the first inverter F1 and the first input terminal of the second NOR gate O2, the second input terminal of the second NOR gate O2 is connected to the demagnetization detection unit 40, the output terminal of the second NOR gate O2 is connected to the second input terminal of the first NOR gate O1, and the output terminal of the first inverter F1 is connected to the cycle control unit 20.

[0059] The starting point control unit 10 of the above structure is as follows: Figure 4 The timing diagram shown takes the timing start signal as a high level signal as an example, assuming that the timing start signal is generated when the load voltage Vcs is greater than the preset reference voltage Vref, the positive input terminal of the timing comparator L1 receives the load voltage Vcs, and when the load voltage Vcs at the positive input terminal is greater than the preset reference voltage Vref at the negative input terminal, the timing comparator L1 sends a high level signal to the first input terminal of the first NOR gate O1. After the first NOR gate O1 receives the high level signal, the first NOR gate O1 outputs a low level signal to the first inverter F1, and the low level signal is inverted by the first inverter F1 to generate a high level signal, thereby generating the timing start signal.

[0060] When the load current Ics drops from the maximum to 0, the second input terminal of the second NOR gate O2 receives the demagnetization completion signal. The demagnetization completion signal changes from a low level to a high level signal when the load current Ics drops from the maximum to 0. The second NOR gate O2 outputs a low level signal to the second input terminal of the first NOR gate O1. When the load current is 0, the load voltage Vcs is also 0, which is less than the preset reference voltage Vref. At this time, the timing comparator L1 outputs a low level signal, and the first input terminal and the second input terminal of the first NOR gate O1 both input low level signals. Then the first NOR gate O1 outputs a high level signal to the first inverter F1. The first inverter F1 inverts the high level signal and outputs a low level signal to generate an inverted level signal of the timing start signal.

[0061] In an optional implementation of this embodiment, the cycle control unit 20 can also receive a dimming signal, and the cycle control unit 20 can adjust the second time length T according to the dimming signal, thereby adjusting the switching cycle length of the power control device 42, thereby adjusting the brightness of the load circuit 4.

[0062] As a possible implementation, the cycle control unit 20 may be designed as follows: Figure 5 The structure shown is used to achieve the aforementioned functions.

[0063] like Figure 5 As shown, the cycle control unit 20 includes a logic circuit 2021, a pulse generating circuit 2022, a switch circuit 2023, a first charge and discharge circuit 2024, a second charge and discharge circuit 2025 and a cycle control comparator L2.

[0064] The output end of the starting point control unit 10 is respectively connected to the pulse generating circuit 2022 and the input end of the logic circuit 2021, the output end of the logic circuit 2021 is respectively connected to the enable end of the cycle control comparator L2 and the switch circuit 2023, the reference signal source Iref is respectively connected to the inverting input end of the cycle control comparator L2 and the first charge and discharge circuit 2024 through the switch circuit 2023, the positive input end of the cycle control comparator L2 is connected to the second charge and discharge circuit 2025, and the positive input end of the cycle control comparator L2 receives the dimming signal, the output end of the cycle control comparator L2 is connected to the control logic unit 30, and the output end of the pulse generating circuit 2022 is respectively connected to the first charge and discharge circuit 2024 and the second charge and discharge circuit 2025.

[0065] The cycle control unit 20 of the above structure takes the timing start signal as a high level signal as an example. Figure 4As shown in the timing diagram, the timing start signal is transmitted to the pulse generating circuit 2022, so that the pulse generating circuit 2022 sends a short pulse signal Rset to the first charging and discharging circuit 2024 and the second charging and discharging circuit 2025, and the first charging and discharging circuit 2024 and the second charging and discharging circuit 2025 discharge according to the short pulse signal Rset, wherein the discharge time is the same as the pulse duration time.

[0066] As a possible implementation, Figure 6 As shown, the first charge and discharge circuit 2024 may include a first capacitor C1 and a first controllable switch tube M1, and the second charge and discharge circuit 2025 may include a second capacitor C2 and a second controllable switch tube M2. The control ends of the first controllable switch tube M1 and the second controllable switch tube M2 are both connected to the pulse generating circuit 2022, so that the first controllable switch tube M1 and the second controllable switch tube M2 are closed when receiving a short-time pulse signal Rset, thereby discharging the first capacitor C1 and the second capacitor C2.

[0067] After the first charge-discharge circuit 2024 is discharged, the logic circuit 2021 controls the switch circuit 2023 and the reference signal source Iref to charge the first charge-discharge circuit 2024 according to the timing start signal.

[0068] As a possible implementation, Figure 6 As shown, the logic circuit 2021 may be a second inverter F2, the control switch circuit 2023 may be a third controllable switch tube M3, the input end of the second inverter F2 is connected to the output end of the starting point control unit 10, the output end of the second inverter F2 is connected to the control end of the third controllable switch tube M3, the reference signal source Iref is connected to the first capacitor C1 through the third controllable switch tube M3, so that when the timing start signal is received, the second inverter F2 drives the third controllable switch tube M3 to close, so that the reference signal source Iref charges the first capacitor C1; specifically, when the timing start signal is a high level signal, the first controllable switch tube M1 and the second controllable switch tube M2 may be as follows Figure 6 The third controllable switch tube M3 is a PMOS tube; when the timing start signal is a low level signal, the model of the controllable switch tube can be adaptively adjusted.

[0069] After the second charge and discharge circuit 2025 is discharged, the second charge and discharge circuit 2025 may be charged according to the received dimming signal, wherein the dimming signal is externally input.

[0070] As a possible implementation, Figure 5 , Figure 6 , Figure 8As shown in FIG9 , the dimming control circuit may further include a signal conversion unit 60 , which is used to receive a dimming signal and convert the dimming signal into a corresponding current signal In to charge the second charge and discharge circuit 2025 .

[0071] According to the aforementioned connection relationship, the first end of the second capacitor C2 can be connected to the signal conversion unit 60 to receive the current signal In corresponding to the dimming signal, so as to charge the second capacitor C2 according to the current signal In corresponding to the dimming signal.

[0072] The output end of the second inverter F2 is also connected to the enable end of the cycle control comparator L2. When the second inverter F2 receives the timing start signal, it controls the cycle control comparator L2 to stop working according to the timing start signal, so that the cycle control comparator L2 sends an inverted level signal of the switching cycle end signal to the control logic unit 30.

[0073] When the inverted signal of the timing start signal Star is received by the second inverter F2, the second inverter F2 controls the period control comparator L2 to start working, and controls the third controllable switch tube M3 to be disconnected, so that the reference signal source Iref stops charging the first capacitor C1, so that the voltage in the first capacitor C1 is fixed, that is, the voltage at the inverting input terminal of the period control comparator L2 is fixed.

[0074] Since the cycle control comparator L2 outputs a high level signal when the voltage at the non-phase input terminal is greater than or equal to the voltage at the inverting input terminal, when the voltage after the dimming signal charges the second capacitor is equal to or greater than the voltage at the inverting input terminal, the cycle control comparator L2 outputs a switching cycle end signal.

[0075] In the cycle control unit designed above, since the cycle control comparator L2 starts working only when the inverted level signal of the timing start signal is generated, the time length from the start of its work to the voltage at the positive input terminal being equal to the voltage at the inverting input terminal is the aforementioned second time length T, and the time length for the voltage at the positive input terminal to be equal to the voltage at the inverting input terminal depends on the time length for the voltage charged by the dimming signal to the second charge and discharge circuit 2025 to reach the voltage at the inverting input terminal. Therefore, the second time length T can be changed by changing the dimming signal, thereby adjusting the switching cycle length of the power control device, thereby controlling the load current size when the power control device is closed next time, thereby adjusting the brightness of the load circuit.

[0076] As a possible implementation, Figure 7 As shown, the designed dimming control circuit further includes a load peak control unit 50 , an input end of the load peak control unit 50 is used to receive a load voltage, and an output end of the load peak control unit 50 is connected to the control logic unit 30 .

[0077] The load peak control unit 50 sends a load peak signal to the control logic unit 50 when the load voltage is at a peak value, and sends an opposite level signal of the load peak signal to the control logic unit 50 when the load voltage is not at a peak value. For example, when the load peak signal is a high level signal, the opposite level signal of the load peak signal is a low level signal; when the load peak signal is a low level signal, the opposite level signal of the load peak signal is a high level signal.

[0078] As a possible implementation, Figure 8 and 9 As shown, the load peak control unit 50 can be a load peak comparator L3, the inverting input terminal of the load peak comparator L3 can receive the load voltage Vcs, and the non-phase input terminal of the load peak comparator L3 can receive the first dimming signal, and then the peak value of the load current can be adjusted by adjusting the first dimming signal, thereby realizing the brightness adjustment of the LED lamp.

[0079] Specifically, Figure 8 and Fig. 9 As shown, the first dimming signal can be sent to the aforementioned signal conversion unit 60, and the signal conversion unit 60 converts the first dimming signal into a corresponding voltage signal Vn, thereby transmitting the voltage signal Vn corresponding to the first dimming signal to the non-inverting input terminal of the load peak comparator L3, thereby adjusting the peak value of the load current. The first dimming signal can be the same signal as the aforementioned dimming signal, or they can be different signals.

[0080] In an optional implementation of this embodiment, if Figure 8 As shown, the control logic unit 30 includes a control logic circuit 301 and a drive circuit 302, the first input end of the control logic circuit 301 is connected to the output end of the cycle control unit 20, the second input end of the control logic circuit 301 is connected to the output end of the load peak control unit 50, the output end of the control logic circuit 301 is connected to the drive circuit 302, and the output end of the drive circuit 302 is connected to the control end of the power control device 42.

[0081] When the control logic circuit 301 receives a load peak signal, it controls the drive circuit 302 to drive the power control device 42 to open according to the load peak signal; when the control logic circuit 301 receives a switching cycle end signal and an opposite level signal of the load peak signal, it controls the drive circuit 302 to drive the power control device 42 to close according to the switching cycle end signal and the opposite level signal of the load peak signal.

[0082] As a possible implementation, Fig. 9As shown, the control logic circuit 301 includes a third inverter F3, a fourth inverter F4, a fifth inverter F5, a first NAND gate A1, a second NAND gate A2, a third NAND gate A3, a fourth NAND gate A4 and an AND gate A5;

[0083] The output end of the load peak control unit 50 is respectively connected to the second input end of the second NAND gate A2 and the first input end of the third NAND gate A3, the second input end of the third NAND gate A3 is connected to the output end of the fourth NAND gate A4, the output end of the third NAND gate A3 is respectively connected to the first input end of the fourth NAND gate A4 and the input end of the fifth inverter F5, the output end of the fifth inverter F5 is connected to the second input end of the NAND gate A5;

[0084] The first input terminal of the second NAND gate A2 is connected to the output terminal of the first NAND gate A1, the output terminal of the second NAND gate A2 is respectively connected to the second input terminal of the first NAND gate A1 and the input terminal of the fourth inverter F4, the first input terminal of the first NAND gate A1 is connected to the output terminal of the third inverter F3, the input terminal of the third inverter F3 is connected to the output terminal of the cycle control unit 20, and the output terminal of the fourth inverter F4 is connected to the first input terminal of the AND gate A5.

[0085] The control logic circuit 301 designed above is Figure 4 Taking the case where the switching cycle end signal in the timing diagram is a high level signal and the load peak signal is a low level signal as an example, when the load voltage Vcs gradually increases so that the timing start signal is generated, the third inverter F3 does not receive the switching cycle end signal, that is, the third inverter F3 receives the inverted level signal of the switching cycle end signal, which is a low level signal. The third inverter F3 converts the low level signal into a high level signal and transmits it to the first input end of the first NAND gate A1. The second input end of the first NAND gate A1 is preset with a low level signal, so that the first NAND gate A1 outputs a high level signal to the first input end of the second NAND gate A2. Since the power control device 42 is closed at this time, the load voltage is not 0. The second input end of the second NAND gate A2 receives the opposite level signal of the load peak signal transmitted by the load peak control unit 50, which is a high level signal. Since both input ends of the second NAND gate A2 receive high level signals, the second NAND gate A2 outputs a low level signal to the fourth inverter F4. The low level signal is converted into a high level signal by the fourth inverter F4 and transmitted to the first end of the AND gate A5.

[0086] The first end of the third NAND gate A3 receives an opposite level signal of the load peak signal, which is a high level signal. The second end of the third NAND gate A3 is preset with a high level signal, so that the third NAND gate A3 outputs a low level signal to the fifth inverter F5. The low level signal is converted into a high level signal by the fifth inverter and transmitted to the second end of the AND gate A5.

[0087] The first terminal and the second terminal of the AND gate A5 both receive a high level signal, causing it to output a high level signal, thereby causing the driving circuit 302 to drive the power control device to be continuously turned on.

[0088] In the process that the load current gradually increases but has not reached the maximum, the load voltage Vcs has not reached the peak value. Therefore, the load peak control unit 50 still outputs the opposite level signal of the load peak signal. Since the timing has not reached the first time length, the cycle control unit 20 still outputs the inverted signal of the switching cycle end signal, so that when the load current gradually increases to reach the maximum, the control logic unit 30 continues to control the power control device 42 to turn on.

[0089] When the load current Ics reaches the maximum, that is, the load voltage Vcs reaches the maximum, the load peak control unit 50 outputs a load peak signal, which is a low-level signal. On the one hand, the low-level signal is transmitted to the first end of the third NAND gate A3. Since a high-level signal is input to the second end of the third NAND gate A3, the third NAND gate A3 outputs a high-level signal to the fifth inverter F5. The high-level signal is converted by the fifth inverter F5 to output a low-level signal to the second end of the AND gate A5.

[0090] On the other hand, the load peak signal is transmitted to the second end of the second NAND gate A2. Since the first end of the second NAND gate A2 receives a high level signal, the second NAND gate A2 outputs a high level signal to the fourth inverter F4. After the high level signal is converted by the fourth inverter F4, it outputs a low level signal to the first end of the AND gate A5.

[0091] Since low-level signals are input to both ends of the AND gate A5, the AND gate A5 outputs a low-level signal to the driving circuit 302, thereby controlling the power control device 42 to be disconnected.

[0092] After the power control device 42 is disconnected, the load current Ics gradually decreases, and the demagnetization detection unit 40 collects and detects the load current Ics. When it is detected that the load current changes from the maximum to 0, a high-level demagnetization completion signal is sent to the second NOR gate O2 in the starting point control unit 10, so that the starting point control unit 10 sends the inverted signal of the timing start signal to the cycle control unit 20, so that the cycle control comparator L2 in the cycle control unit 20 starts to work and sends a switching cycle end signal to the control logic circuit 301 after the second time length T.

[0093] The high-level switching cycle end signal is inverted to a low level by the third inverter F3 and then transmitted to the first end of the first NAND gate A1. The second end of the first NAND gate A1 is a high-level signal in the previous state, so that the first NAND gate A1 outputs a high-level signal, and the high-level signal is transmitted to the second end of the second NAND gate A2. Since the load voltage is 0 at this time, the load peak control unit 50 inputs the opposite level signal of the high-level load peak signal to the first end of the second NAND gate A2, so that the second NAND gate A2 outputs a low-level signal. The low-level signal is inverted by the fourth inverter F4 and then transmitted as a high-level signal to the first end of the AND gate A5.

[0094] The opposite level signal of the high level load peak signal is also transmitted to the first end of the third NAND gate A3. The output end of the third NAND gate A3 is a high level signal in the previous state. The high level signal is transmitted to the first end of the fourth NAND gate A4. The second end of the fourth NAND gate A4 inputs a low level signal when the load current is 0, so that the fourth NAND gate A4 inputs a high level signal to the second end of the third NAND gate A3. In this way, the two ends of the third NAND gate A3 receive the high level signal and output a low level signal. The low level signal is inverted by the fifth inverter F5 and then outputs a high level signal to the second end of the AND gate A5. As a possible implementation, Fig. 9 As shown, the second end of the fourth NAND gate A4 can be connected to the demagnetization detection unit 40 through the sixth inverter F6, so as to receive a low level signal when the load current is 0, and receive a high level signal when the load current is not 0.

[0095] Since high-level signals are input to both ends of the AND gate A5, the AND gate A5 sends a high-level signal to the power control device 42, thereby controlling the power control device 42 to switch from disconnection to conduction again.

[0096] In the dimming control circuit designed above, the cycle control unit 20 of this scheme sends a switching cycle end signal to the control logic unit 30 after the first time length from the moment of receiving the timing start signal Star transmitted by the starting point control unit 10. The control logic unit 30 disconnects the power control device 42 of the load circuit 4 when the load voltage is at a peak value. After the power control device 42 is disconnected, the power control device 42 is closed according to the switching cycle end signal sent by the cycle control unit 20. Since the timing start signal Star is generated by the starting point control unit 10 according to the received load voltage and the preset reference voltage, and since the preset reference voltage Vref is fixed, the voltage value of the load voltage Vcs reaching the preset reference voltage Vref in each cycle is the same, so that in each switching cycle, the value of the load current Ics is the same when the timing start signal Star is generated, so that the timing starting point of each cycle is the same; at the same time, since the first time length is fixed, the timing starting point is also fixed, so the time period T of the first time length starting from the moment of the timing start signal Star DCM Also fixed; in addition, in each switching cycle, the load current Ics increases linearly when the power control device 42 is closed, and decreases linearly after the power control device 42 is disconnected, and because the control logic unit 30 disconnects the power control device 42 of the load circuit 4 when the load voltage is at a peak value, the peak value of the load current Ics is fixed, so that the time length T from the timing start point to the load current Ics reaching a peak value and then to the load current Ics dropping from a maximum value to 0 CRM Also fixed, due to T CRM is fixed, T DCM is also fixed, therefore, the time ratio related to the dimming output current is fixed, so that the dimming output current is fixed without fluctuation, thereby eliminating ripple.

[0097] Second embodiment

[0098] like Fig.10 As shown, the present application provides a dimming control chip 1, which includes the dimming control circuit described in any optional implementation manner in the first embodiment. Since the designed dimming control chip 1 has the dimming control circuit in the first embodiment, the designed dimming control chip 1 can solve the ripple phenomenon caused by dimming in the current DCM mode, thereby improving the LED dimming effect.

[0099] In this document, relational terms such as first and second, etc. are used merely to distinguish one entity or operation from another entity or operation, but do not necessarily require or imply any such actual relationship or order between these entities or operations.

Claims

1. A dimming control circuit, characterized in that: The dimming control circuit comprises: a starting point control unit (10), a cycle control unit (20) and a control logic unit (30); The starting point control unit (10) is used to receive a load voltage, generate a timing start signal according to a preset reference voltage and the load voltage, and transmit the timing start signal to the period control unit (20); The cycle control unit (20) is used to send a switching cycle end signal to the control logic unit (30) after a first time length starting from the moment when the timing start signal is received; The control logic unit (30) is used to generate a disconnection drive signal when the load voltage reaches a peak value, the disconnection drive signal is used to control the power control device in the load circuit to disconnect; and after the power control device is disconnected, generate a closing drive signal according to the received switching cycle end signal, the closing drive signal is used to control the power control device to close; The starting point control unit (10) is further used to send an inverted level signal of the timing start signal to the period control unit (20) when the load current drops from a maximum value to 0; The cycle control unit (20) is further configured to send the switching cycle end signal to the control logic unit (30) after a second time length starting from the moment when the inverted level signal of the timing start signal is received, wherein the second time length is equal to the difference between the first time length and the time length from the generation of the timing start signal to the generation of the inverted level signal; The dimming control circuit further comprises a demagnetization detection unit (40), and the demagnetization detection unit (40) is connected to the starting point control unit (10); The demagnetization detection unit (40) is used to receive the load current of the load circuit, generate a demagnetization completion signal when the load current drops from a maximum value to 0, and transmit the demagnetization completion signal to the starting point control unit (10); The starting point control unit (10) is used to send an inverted level signal of the timing start signal to the period control unit (20) according to the demagnetization completion signal, a preset reference voltage and the load voltage; The starting point control unit (10) comprises: a timing comparator (L1), a first NOR gate (O1), a second NOR gate (O2) and a first inverter (F1); The positive input end of the timing comparator (L1) is used to receive the load voltage, the negative input end of the timing comparator (L1) is used to receive the preset reference voltage, the output end of the timing comparator (L1) is connected to the first input end of the first NOR gate (O1), the output end of the first NOR gate (O1) is respectively connected to the input end of the first inverter (F1) and the first input end of the second NOR gate (O2), the second input end of the second NOR gate (O2) is connected to the demagnetization detection unit (40), the output end of the second NOR gate (O2) is connected to the second input end of the first NOR gate (O1), and the output end of the first inverter (F1) is connected to the cycle control unit (20); The cycle control unit (20) comprises a cycle control comparator (L2) and a logic circuit (2021); The logic circuit (2021) is used to control the cycle control comparator (L2) not to work when receiving the timing start signal; and drive the cycle control comparator (L2) to work when receiving the inverted level signal of the timing start signal, so that the cycle control comparator (L2) sends the switching cycle end signal to the control logic unit after the second time length; The period control unit (20) is also used to receive a dimming signal; The cycle control unit (20) is used to adjust the second time length according to the dimming signal to adjust the switching cycle length of the power control device and thus adjust the brightness of the load circuit; The cycle control unit (20) further comprises a pulse generating circuit (2022), a switch circuit (2023), a first charge and discharge circuit (2024) and a second charge and discharge circuit (2025); The output end of the starting point control unit (10) is respectively connected to the pulse generating circuit (2022) and the input end of the logic circuit (2021); the output end of the logic circuit (2021) is respectively connected to the enable end of the cycle control comparator (L2) and the switch circuit (2023); the first end of the switch circuit (2023) is used to be connected to a reference signal source; the second end of the switch circuit (2023) is respectively connected to the inverting input end of the cycle control comparator (L2) and the first charge and discharge circuit (2024); the non-phase input end of the cycle control comparator (L2) is connected to the second charge and discharge circuit (2025) and is used to receive the dimming signal; the output end of the cycle control comparator (L2) is connected to the control logic unit (30); the output end of the pulse generating circuit (2022) is respectively connected to the first charge and discharge circuit (2024) and the second charge and discharge circuit (2025); The pulse generating circuit (2022) is used to generate a pulse signal according to the timing start signal; The first charge and discharge circuit (2024) is used to discharge when receiving the pulse signal, so as to reset the voltage at the inverting input terminal of the period control comparator (L2) connected to the first charge and discharge circuit (2024); The second charge and discharge circuit (2025) is used to perform discharge reset when receiving the pulse, and to charge according to the received dimming signal after discharge reset, so as to increase the voltage at the non-phase input terminal of the period control comparator (L2) connected to the second charge and discharge circuit (2025); The logic circuit (2021) comprises a second inverter (F2); The input end of the second inverter (F2) is connected to the output end of the starting point control unit (10), and the output end of the second inverter (F2) is respectively connected to the enable end of the cycle control comparator (L2) and the switch circuit (2023); The switch circuit (2023) comprises a third controllable switch tube (M3), a control end of the third controllable switch tube (M3) is connected to the output end of the second inverter (F2), a first end of the third controllable switch tube (M3) is connected to an external power supply, and a second end of the third controllable switch tube (M3) is respectively connected to the inverting input end of the period control comparator (L2) and the first charge and discharge circuit (2024); The first charge and discharge circuit (2024) comprises a first controllable switch tube (M1) and a first capacitor (C1); the second end of the third controllable switch tube (M3) is respectively connected to the first end of the first capacitor (C1) and the first end of the first controllable switch tube (M1); the second end of the first capacitor (C1) and the second end of the first controllable switch tube (M1) are connected and then grounded; and the control end of the first controllable switch tube (M1) is connected to the pulse generating circuit (2022); The second charge and discharge circuit (2025) comprises a second controllable switch tube (M2) and a second capacitor (C2); the dimming signal is respectively connected to the non-phase input end of the period control comparator (L2), the first end of the second capacitor (C2) and the first end of the second controllable switch tube (M2); the second end of the second controllable switch tube (M2) is connected to the second end of the second capacitor (C2) and then grounded; and the control end of the second controllable switch tube (M2) is connected to the pulse generating circuit (2022); The dimming control circuit further comprises a load peak control unit (50), wherein an input end of the load peak control unit (50) is used to receive the load voltage, and an output end of the load peak control unit (50) is connected to the control logic unit (30); The load peak control unit (50) is used to send a load peak signal to the control logic unit (30) when the load voltage reaches a peak value, so that the control logic unit (30) generates the disconnection drive signal according to the load peak signal; and to send an inverted level signal of the load peak signal to the control logic unit (30) when the load voltage is not at a peak value, so that the control logic unit (30) generates the closing drive signal according to the inverted level signal of the load peak signal and the switching cycle end signal; The control logic unit (30) comprises a control logic circuit (301) and a drive circuit (302), wherein a first input end of the control logic circuit (301) is connected to an output end of the cycle control unit (20), and a second input end of the control logic circuit (301) is connected to an output end of the load peak control unit (50); The output end of the control logic circuit (301) is connected to the control end of the power control device through the drive circuit (302); The control logic circuit (301) comprises a third inverter (F3), a fourth inverter (F4), a fifth inverter (F5), a first NAND gate (A1), a second NAND gate (A2), a third NAND gate (A3), a fourth NAND gate (A4) and an AND gate (A5); The output end of the load peak control unit (50) is respectively connected to the second input end of the second NAND gate (A2) and the first input end of the third NAND gate (A3); The second input end of the third NAND gate (A3) is connected to the output end of the fourth NAND gate (A4), the output end of the third NAND gate (A3) is respectively connected to the first input end of the fourth NAND gate (A4) and the input end of the fifth inverter (F5), and the output end of the fifth inverter (F5) is connected to the second input end of the AND gate (A5); The first input end of the second NAND gate (A2) is connected to the output end of the first NAND gate (A1), the output end of the second NAND gate (A2) is respectively connected to the second input end of the first NAND gate (A1) and the input end of the fourth inverter (F4), the first input end of the first NAND gate (A1) is connected to the output end of the third inverter (F3), the input end of the third inverter (F3) is connected to the output end of the cycle control unit (20), and the output end of the fourth inverter (F4) is connected to the first input end of the AND gate (A5); The output end of the AND gate (A5) is connected to the input end of the driving circuit (302).

2. A dimming control chip, characterized in that: The dimming control chip includes the dimming control circuit according to claim 1.

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