Display device and method of manufacturing the same

Abstract

The present application relates to a display device and a method for manufacturing a display device. The display device may include: a substrate including a display area and a non-display area; and at least one pixel, which is arranged in the display area and includes a light-emitting area that emits light. The pixel may include: a plurality of first electrodes, which are arranged on the substrate and arranged in a column direction; a second electrode, which is spaced apart from the first electrode; a first connection line, which extends in the column direction and connects each of the first electrodes to a first electrode adjacent thereto; a light-emitting element, which is electrically connected to at least one of the first electrodes and at least one of the second electrodes; and an insulating pattern, which overlaps with the first connection line. In an embodiment of the present invention, each of the second electrodes may include: a bridging pattern, which extends in a row direction intersecting the column direction and overlaps with the insulating pattern; and at least two sub-electrodes, which are electrically connected to each other through the bridging pattern.

Description

Technical Field

[0001] The present disclosure relates to a display device including an ultra-small light emitting element and a method of manufacturing the display device. Background Art

[0002] Light-emitting diodes can have relatively satisfactory durability even under harsh environmental conditions and have satisfactory performance in terms of lifespan and brightness.

[0003] In order to apply LEDs to lighting devices, display devices, etc., it is necessary to connect the LEDs to electrodes so that a voltage of a power source can be applied to the LEDs. Various studies have been conducted on the arrangement relationship between LEDs and electrodes with respect to the application purpose of LEDs, methods of reducing the space required for electrodes, or methods of manufacturing LEDs. Summary of the invention

[0004] Technical issues

[0005] The object of the present disclosure is to provide a display device, wherein the light emitting elements are aligned in different directions in the emission area so that a uniform light output distribution can be achieved in the entire area of ​​the display device. In addition, the object of the present disclosure is to provide a method of manufacturing a display device.

[0006] Technical Solution

[0007] A display device according to an embodiment of the present disclosure may include: a substrate including a display area and a non-display area; and at least one pixel disposed in the display area and including an emission area formed to emit light.

[0008] According to an embodiment of the present disclosure, a pixel may include: a plurality of first electrodes, arranged on a substrate and arranged in a column direction; a second electrode, spaced apart from the first electrode; a first connecting line, extending in the column direction and connecting each of the first electrodes to an adjacent first electrode; a light emitting element, electrically connected to at least one of the first electrodes and each of at least one of the second electrodes; and an insulating pattern, overlapping the first connecting line.

[0009] According to an embodiment of the present disclosure, in a plan view, each of the first electrodes and each of the second electrodes may be alternately disposed in a column direction in the emission region.

[0010] According to an embodiment of the present disclosure, each of the second electrodes may include: a bridge pattern extending in a row direction crossing the column direction and overlapping the insulating pattern; and at least two sub-electrodes electrically connected to each other through the bridge pattern.

[0011] According to an embodiment of the present disclosure, the bridge pattern and the sub-electrode may be integrated with each other and form at least one of the second electrodes.

[0012] According to an embodiment of the present disclosure, at least one of the first electrodes may be disposed between two second electrodes adjacent thereto in a column direction.

[0013] According to an embodiment of the present disclosure, the insulation pattern may be disposed on the bridge pattern.

[0014] According to an embodiment of the present disclosure, the first connection line and the first electrode may be provided on different layers.

[0015] According to an embodiment of the present disclosure, the first connection line may be disposed on the insulation pattern and electrically disconnected from the bridge pattern.

[0016] According to an embodiment of the present disclosure, the first connection line may include a first portion overlapping the insulating pattern and a second portion other than the first portion. The second portion of the first connection line may be electrically connected to the first electrode.

[0017] According to an embodiment of the present disclosure, the pixel may further include: a first capping layer disposed on the first electrode; a second capping layer disposed on the second electrode; and a third capping layer disposed on the first connection line.

[0018] According to an embodiment of the present disclosure, the first capping layer and the second capping layer may be disposed on the same layer, and the third capping layer may be disposed on a different layer from the first capping layer and the second capping layer.

[0019] According to an embodiment of the present disclosure, the pixel may further include a second connection line electrically connected to the second electrode. The second connection line may include: a 2-1 connection line extending in the row direction; and a 2-2 connection line extending in the column direction. The 2-2 connection line may be integrated with the second electrode.

[0020] According to an embodiment of the present disclosure, the second connection line and the first connection line may be disposed on different layers.

[0021] According to an embodiment of the present disclosure, the pixel may further include: a partition wall disposed under each of the first electrode and the second electrode; a first contact electrode electrically connecting at least one of the first electrodes to one of the opposite ends of the light-emitting element; and a second contact electrode electrically connecting at least one of the second electrodes to the other of the opposite ends of the light-emitting element.

[0022] According to an embodiment of the present disclosure, the pixel may further include an insulating layer disposed on an upper surface of the light emitting element. The first contact electrode and the second contact electrode may be spaced apart from each other on the insulating layer and electrically disconnected from each other.

[0023] According to an embodiment of the present disclosure, the first electrode and the first connection line may be integrated with each other.

[0024] According to an embodiment of the present disclosure, the insulation pattern may be disposed on the first connection line, and the bridge pattern may be disposed on the insulation pattern.

[0025] According to an embodiment of the present disclosure, the first electrode and the second electrode may be provided on different layers from each other.

[0026] According to an embodiment of the present disclosure, a pixel may include: a first capping layer disposed on each of the first electrode and the first connection line; and a second capping layer disposed on the second electrode. The first capping layer and the second capping layer may be disposed on different layers from each other.

[0027] A method of manufacturing a display device according to an embodiment of the present disclosure may include providing a substrate including at least one pixel, the pixel having an emission region and a non-emission region; and forming a display element layer that emits light in the emission region of the pixel.

[0028] According to an embodiment of the present disclosure, forming a display element layer may include: forming a first electrode, a second electrode, and a first connecting line electrically connected to the second electrode in an emission region; forming an insulating pattern partially overlapping the second electrode; forming a second connecting line electrically connected to the first electrode on the insulating pattern; aligning a light-emitting element between at least one of the first electrodes and at least one of the second electrodes; and forming a first contact electrode and a second contact electrode, the first contact electrode electrically connecting at least one of the first electrodes and one of the opposite ends of the light-emitting element, and the second contact electrode electrically connecting at least one of the second electrodes and the remaining one of the opposite ends of the light-emitting element.

[0029] Beneficial Effects

[0030] Embodiments of the present disclosure may provide a display device in which light emitting elements are aligned in various directions so that uniform light output distribution can be achieved in the entire area, and a method of manufacturing the display device.

[0031] The effects of the present disclosure are not limited to the foregoing, and other various effects are expected herein. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1a is a perspective view schematically showing a light emitting element according to an embodiment of the present disclosure.

[0033] Figure 1b It is shown Figure 1a Schematic cross-sectional view of a light-emitting element.

[0034] Figure 1c is a perspective view schematically showing a light emitting element according to an embodiment of the present disclosure.

[0035] Figure 1d It is shown Figure 1c Schematic cross-sectional view of a light-emitting element.

[0036] Figure 1e is a perspective view schematically showing a light emitting element according to an embodiment of the present disclosure.

[0037] Figure 1f It is shown Figure 1e Schematic cross-sectional view of a light-emitting element.

[0038] Figure 2 A display device according to an embodiment of the present disclosure is shown, and in particular, Figure 2 It is shown that the use Figures 1a to 1f A schematic plan view of a display device using any one of the light-emitting elements shown in FIG. 1 as a light source.

[0039] Figure 3a to Figure 3c It is shown that the Figure 2 Schematic circuit diagrams of various embodiments of the electrical connection relationships of components in any one of the pixels shown in FIG.

[0040] Figure 4 It is schematically shown Figure 2 1 is a plan view of three pixels adjacent to each other in the row direction among the pixels shown in .

[0041] Figure 5 Only shows Figure 4 Schematic plan view of first electrodes and second electrodes in first to third pixels and light emitting elements aligned between the first electrodes and the second electrodes.

[0042] Figure 6 It is along Figure 4 A schematic cross-sectional view taken along line II'.

[0043] Figure 7 It is along Figure 4 A schematic cross-sectional view taken along line II-II'.

[0044] Figure 8 It shows Figure 7 The first electrode and the second electrode are arranged on the same layer, and correspond to Figure 4 Schematic cross-sectional view along line II-II'.

[0045] Fig. 9 Shows Figure 7Another shape of the partition wall (or bank pattern) shown in FIG. Figure 4 Schematic cross-sectional view along line II-II'.

[0046] Fig.10 It is along Figure 4 A schematic cross-sectional view taken along line III-III'.

[0047] Figures 11a to 11i It is shown in sequence that the manufacturing Figure 4 A schematic plan view of the first pixel method shown in FIG.

[0048] Figures 12a to 12n It is shown in sequence that the manufacturing Figure 6 A schematic cross-sectional view of a first pixel method is shown in FIG.

[0049] Fig.13a and Fig.13b Shows Figure 5 1 and 2 are embodiments of a first pixel, and are plan views schematically showing the first pixel including only some components of a display element layer.

[0050] Fig.14 A display device according to an embodiment of the present disclosure is shown, and corresponds to Figure 4 Schematic plan view of a first pixel among first to third pixels.

[0051] Fig.15 It is along Fig.14 Schematic cross-sectional view taken along line IV-IV'.

[0052] Fig.16 It is along Fig.14 A schematic cross-sectional view taken along line V-V'. DETAILED DESCRIPTION

[0053] Since the present disclosure allows various changes and multiple embodiments, specific embodiments will be described in detail in the drawings and written descriptions. However, this is not intended to limit the present disclosure to a specific mode of practice, and it should be understood that all changes, equivalents and substitutions that do not depart from the technical scope of the present disclosure are included in the present disclosure.

[0054] Throughout the present disclosure, in each of the drawings and embodiments of the present disclosure, the same reference numerals represent the same components. In order to clearly illustrate, the size of the elements in the drawings may be exaggerated. It should be understood that although the terms "first", "second", etc. can be used in this article to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, without departing from the teachings of the present disclosure, the first element discussed below can be referred to as the second element. Similarly, the second element can also be referred to as the first element. In the present disclosure, the singular form is also intended to include the plural form, unless the context clearly indicates otherwise.

[0055] It should also be understood that when used in this specification, the terms "comprise", "include", "have", etc. specify the presence of the features, wholes, steps, operations, elements, components and / or combinations thereof, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or combinations thereof. In addition, when a first part such as a layer, a film, a region or a plate is disposed on a second part, the first part may not only be directly disposed on the second part, but also a third part may be interposed between them. In addition, when it is indicated that a first part such as a layer, a film, a region or a plate is formed on a second part, the surface of the second part on which the first part is formed is not limited to the upper surface of the second part, but may include other surfaces of the second part such as a side surface or a lower surface. On the contrary, when a first part such as a layer, a film, a region or a plate is below the second part, the first part may not only be directly below the second part, but also a third part may be interposed between them.

[0056] The embodiments of the present disclosure and required details are described with reference to the accompanying drawings to describe the present disclosure in detail so that those skilled in the art can easily practice the present disclosure. In addition, a singular form may include a plural form as long as it is not specifically mentioned in a sentence.

[0057] Figure 1a is a perspective view schematically showing a light emitting element according to an embodiment of the present disclosure. Figure 1b It is shown Figure 1a Schematic cross-sectional view of a light-emitting element. Figure 1c is a perspective view schematically showing a light emitting element according to an embodiment of the present disclosure. Figure 1d It is shown Figure 1c Schematic cross-sectional view of a light-emitting element. Figure 1e is a perspective view schematically showing a light emitting element according to an embodiment of the present disclosure. Figure 1f It is shown Figure 1e Schematic cross-sectional view of a light-emitting element.

[0058] For the purpose of explanation, reference will be made to Figure 1a to Figure 1d The cylindrical light emitting element is described and will be referred to hereinafter Figure 1e and Figure 1f A light-emitting element having a core-shell structure is described. In the embodiments of the present disclosure, the type and / or shape of the light-emitting element is not limited to Figures 1a to 1f The embodiment shown in .

[0059] refer to Figure 1a to Figure 1d The light emitting element LD according to the embodiment of the present disclosure may include a first conductive semiconductor layer 11, a second conductive semiconductor layer 13, and an active layer 12 interposed between the first conductive semiconductor layer 11 and the second conductive semiconductor layer 13. For example, the light emitting element LD may be implemented as an emission stack formed by sequentially stacking the first conductive semiconductor layer 11, the active layer 12, and the second conductive semiconductor layer 13.

[0060] In an embodiment of the present disclosure, the light emitting element LD may be formed in a shape extending in one direction. If the direction in which the light emitting element LD extends is defined as a longitudinal direction, the light emitting element LD may have a first end and a second end in the extending direction. One of the first conductive semiconductor layer 11 and the second conductive semiconductor layer 13 may be disposed on one end (or the first end) of the light emitting element LD, and the other of the first conductive semiconductor layer 11 and the second conductive semiconductor layer 13 may be disposed on the other end (or the second end) of the light emitting element LD.

[0061] Although the light emitting element LD may be provided in the form of a cylinder, the shape of the light emitting element LD is not limited thereto. The light emitting element LD may have a rod-like shape or a bar-like shape extending in the longitudinal direction (i.e., having an aspect ratio greater than 1). For example, the length L of the light emitting element LD in the longitudinal direction may be greater than its diameter D (or the width of its cross section). The light emitting element LD may include a light emitting diode manufactured to have an ultra-small size, for example, having a length L and / or a diameter D corresponding to a micrometer or nanometer level.

[0062] In an embodiment of the present disclosure, the diameter D of the light emitting element LD may be approximately in the range of 0.5 μm to 6 μm, and the length L thereof may be approximately in the range of 1 μm to 10 μm. However, the size of the light emitting element LD is not limited thereto, and the size of the light emitting element LD may be changed to meet the requirements (or design conditions) of the lighting device or self-emitting display device to which the light emitting element LD is applied.

[0063] The first conductive semiconductor layer 11 may include, for example, at least one n-type semiconductor layer. For example, the first conductive semiconductor layer 11 may include an n-type semiconductor layer including any one semiconductor material of InAlGaN, GaN, AlGaN, InGaN, AlN, and InN and doped with a first conductive dopant such as Si, Ge, or Sn. However, the material forming the first conductive semiconductor layer 11 is not limited thereto, and the first conductive semiconductor layer 11 may be formed of various other materials.

[0064] The active layer 12 may be disposed on the first conductive semiconductor layer 11 and have a single quantum well structure or a multi-quantum well structure. The position of the active layer 12 may be changed in various ways depending on the type of the light emitting element LD. The active layer 12 may emit light having a wavelength range from 400 nm to 900 nm, and a double heterostructure may be used. In an embodiment of the present disclosure, a cladding layer (not shown) doped with a conductive dopant may be formed on and / or below the active layer 12. For example, the cladding layer may be formed of an AlGaN layer or an InAlGaN layer. In an embodiment, a material such as AlGaN or AlInGaN may be used to form the active layer 12, and various other materials may be used to form the active layer 12.

[0065] If an electric field of a predetermined voltage or higher is applied to opposite ends of the light emitting element LD, the light emitting element LD emits light by recombination of electron-hole pairs in the active layer 12. Since the light emission of the light emitting element LD can be controlled based on the aforementioned principle, the light emitting element LD can be used as a light source for pixels of various light emitting devices and display devices.

[0066] The second conductive semiconductor layer 13 may be disposed on the active layer 12 and include a semiconductor layer of a type different from that of the first conductive semiconductor layer 11. For example, the second conductive semiconductor layer 13 may include at least one p-type semiconductor layer. For example, the second conductive semiconductor layer 13 may include a p-type semiconductor layer including any one semiconductor material of InAlGaN, GaN, AlGaN, InGaN, AlN, and InN and doped with a second conductive dopant such as Mg. However, the material forming the second conductive semiconductor layer 13 is not limited thereto, and the second conductive semiconductor layer 13 may be formed of various other materials.

[0067] In the embodiments of the present disclosure, Figure 1a and Figure 1b As shown in FIG. 1 , in addition to the first conductive semiconductor layer 11, the active layer 12 and the second conductive semiconductor layer 13, the light emitting element LD may further include an electrode layer 15 disposed on the second conductive semiconductor layer 13. In addition, in the embodiment, as Figure 1c and Figure 1dAs shown in FIG. 1 , the light emitting element LD may further include another electrode layer 16 disposed on one end of the first conductive semiconductor layer 11 in addition to the electrode layer 15 .

[0068] Although each of the electrode layers 15 and 16 may be formed by an ohmic contact electrode, the present disclosure is not limited thereto. The electrode layers 15 and 16 may include a metal or a metal oxide. For example, chromium (Cr), titanium (Ti), aluminum (Al), gold (Au), nickel (Ni), and oxides or alloys thereof may be used alone or in combination with each other. However, the present disclosure is not limited thereto.

[0069] The materials included in the respective electrode layers 15 and 16 may be the same as or different from each other. The electrode layers 15 and 16 may be substantially transparent or translucent. Therefore, light generated from the light emitting element LD may pass through the electrode layers 15 and 16 and then be emitted to the outside of the light emitting element LD.

[0070] In an embodiment of the present disclosure, the light emitting element LD may further include an insulating film 14. However, in some embodiments, the insulating film 14 may be omitted or provided to cover only some of the first conductive semiconductor layer 11, the active layer 12, and the second conductive semiconductor layer 13.

[0071] The insulating film 14 can prevent the active layer 12 from being short-circuited due to contact with a conductive material other than the first conductive semiconductor layer 11 and the second conductive semiconductor layer 13. Due to the insulating film 14, the occurrence of defects on the surface of the light-emitting element LD can be minimized, thereby improving the life and efficiency of the light-emitting element LD. In the case where the light-emitting elements LD are arranged in close contact with each other, the insulating film 14 can prevent an undesirable short circuit from occurring between the light-emitting elements LD. As long as the active layer 12 can be prevented from being short-circuited with an external conductive material, whether the insulating film 14 is provided is not limited.

[0072] like Figure 1a and Figure 1bAs shown in , the insulating film 14 may be disposed on a portion of the light emitting element LD, but not on one of the opposite ends of the light emitting element LD. In this case, the insulating film 14 may expose only the electrode layer 15 disposed on one end (first end) of the second conductive semiconductor layer 13 of the light emitting element LD, and surround the entire side surface of the component except the electrode layer 15. Here, the insulating film 14 may allow at least the opposite end of the light emitting element LD to be exposed to the outside. For example, the insulating film 14 may allow not only the electrode layer 15 disposed on one end (first end) of the second conductive semiconductor layer 13 to be exposed to the outside, but also one end (first end) of the first conductive semiconductor layer 11 to be exposed to the outside. In an embodiment, the insulating film 14 may surround the entire peripheral surface of the component included in the light emitting element LD. For example, the insulating film 14 may surround the corresponding peripheral surfaces of the first conductive semiconductor layer 11, the active layer 12, the second conductive semiconductor layer 13, and the electrode layer 15.

[0073] In an embodiment, if Figure 1c and Figure 1d As shown in , in the case where the electrode layers 15 and 16 are provided on the respective opposite ends of the light emitting element LD, the insulating film 14 may allow at least one region of each of the electrode layers 15 and 16 to be exposed to the outside. As another example, in an embodiment, the insulating film 14 may not be provided.

[0074] In an embodiment of the present disclosure, the insulating film 14 may include a transparent insulating material. For example, the insulating film 14 may include a material selected from SiO 2 、Si 3 N 4 、Al 2 O 3 and TiO 2 At least one insulating material in the group consisting of, but the present disclosure is not limited thereto. In other words, various materials with insulating properties can be used.

[0075] If the insulating film 14 is provided in the light emitting element LD, the active layer 12 can be prevented from being short-circuited with the first electrode and / or the second electrode not shown. Due to the insulating film 14, the occurrence of defects on the surface of the light emitting element LD can be minimized, thereby improving the life and efficiency of the light emitting element LD. In the case where the light emitting elements LD are provided in close contact with each other, the insulating film 14 can prevent an undesirable short circuit from occurring between the light emitting elements LD.

[0076] The light emitting element LD can be used as a light source for various display devices. The light emitting element LD can be manufactured by a surface treatment process. For example, each light emitting element LD can be surface treated so that when a plurality of light emitting elements LD are mixed with a fluid solution (or solvent) and provided to each emission region (e.g., the emission region of each sub-pixel), the light emitting element LD can be uniformly dispersed rather than unevenly aggregated in the solution.

[0077] The light-emitting device including the above-mentioned light-emitting element LD can be used not only in a display device, but also in various devices that require a light source. For example, in the case where the light-emitting element LD is arranged in the emission area of ​​each pixel of the display panel, the light-emitting element LD can be used as the light source of the pixel. However, the application field of the light-emitting element LD is not limited to the above-mentioned example. For example, the light-emitting element LD can also be used in other types of devices (such as lighting equipment) that require a light source.

[0078] Next, we will refer to Figure 1e and Figure 1f A light emitting element LD having a core-shell structure is described. The following description of the light emitting element LD having a core-shell structure will focus on the differences from the above-described embodiment, and components of the light emitting element LD that are not separately explained in the following description may be consistent with those of the foregoing embodiment. The same reference numerals will be used to represent the same components, and similar reference numerals will be used to represent similar components.

[0079] refer to Figure 1e and Figure 1f The light emitting element LD according to an embodiment of the present disclosure may include a first conductive semiconductor layer 11, a second conductive semiconductor layer 13, and an active layer 12 interposed between the first conductive semiconductor layer 11 and the second conductive semiconductor layer 13. In some embodiments, the light emitting element LD may include a light emitting pattern 10 having a core-shell structure and including a first conductive semiconductor layer 11 disposed at the center, an active layer 12 surrounding at least one side of the first conductive semiconductor layer 11, a second conductive semiconductor layer 13 surrounding at least one side of the active layer 12, and an electrode layer 15 surrounding at least one side of the second conductive semiconductor layer 13.

[0080] The light emitting element LD may be formed in a polygonal pyramid shape extending in one direction. In an embodiment of the present disclosure, the light emitting element LD may be arranged in the form of a hexagonal pyramid. If the direction in which the light emitting element LD extends is defined as a longitudinal direction, the light emitting element LD may have a first end (or a lower end) and a second end (or an upper end) in the longitudinal direction. In an embodiment, any one of the first conductive semiconductor layer 11 and the second conductive semiconductor layer 13 may be arranged at the first end (or the lower end) of the light emitting element LD. The other of the first conductive semiconductor layer 11 and the second conductive semiconductor layer 13 may be arranged at the second end (or the upper end) of the light emitting element LD.

[0081] In an embodiment, the light emitting element LD may have a small size corresponding to the nanometer level or the micrometer level, for example, a diameter and / or a length L having a nanometer range or a micrometer range. However, in the present disclosure, the size of the light emitting element LD is not limited thereto, and the size of the light emitting element LD may be changed to meet the requirements (or application conditions) of the lighting device or the self-emitting display device to which the light emitting element LD is applied.

[0082] In an embodiment of the present disclosure, the first conductive semiconductor layer 11 may be disposed at the core (i.e., the center (or middle) portion) of the light emitting element LD. The light emitting element LD may have a shape corresponding to the shape of the first conductive semiconductor layer 11. For example, if the first conductive semiconductor layer 11 has a hexagonal pyramid shape, the light emitting element LD and the light emitting pattern 10 may each also have a hexagonal pyramid shape.

[0083] The active layer 12 may be disposed and / or formed in a shape surrounding the outer peripheral surface of the first conductive semiconductor layer 11 in the longitudinal direction of the light emitting element LD. Specifically, the active layer 12 may be disposed and / or formed in a shape surrounding a region of the first conductive semiconductor layer 11 except for a second end of the opposite ends of the first conductive semiconductor layer 11 disposed at a lower position relative to the longitudinal direction of the light emitting element LD.

[0084] The second conductive semiconductor layer 13 may be disposed and / or formed in a shape surrounding the active layer 12 in the longitudinal direction of the light emitting element LD, and may include a semiconductor layer having a type different from that of the first conductive semiconductor layer 11. For example, the second conductive semiconductor layer 13 may include at least one p-type semiconductor layer.

[0085] In an embodiment of the present disclosure, the light emitting element LD may include an electrode layer 15 surrounding at least one side of the second conductive semiconductor layer 13. The electrode layer 15 may be an ohmic contact electrode electrically connected to the second conductive semiconductor layer 13, but the present disclosure is not limited thereto.

[0086] As described above, the light emitting element LD may have a hexagonal pyramid shape whose opposite ends protrude outward, and may be implemented as a light emitting pattern 10 having a core-shell structure, which includes a first conductive semiconductor layer 11 disposed at a central portion thereof, an active layer 12 surrounding the first conductive semiconductor layer 11, a second conductive semiconductor layer 13 surrounding the active layer 12, and an electrode layer 15 surrounding the second conductive semiconductor layer 13. The first conductive semiconductor layer 11 may be disposed at a first end (or a lower end) of the light emitting element LD having a hexagonal pyramid shape, and the electrode layer 15 may be disposed at a second end (or an upper end) of the light emitting element LD.

[0087] In an implementation, the light emitting element LD may further include an insulating film 14 disposed on the outer peripheral surface of the light emitting pattern 10 having the core-shell structure. The insulating film 14 may include a transparent insulating material.

[0088] Figure 2 A display device according to an embodiment of the present disclosure is shown, and in particular, Figure 2 It is shown that the use Figures 1a to 1f Schematic plan view of a display device using any one of the light-emitting elements shown in FIG. 1 as a light source.

[0089] For the sake of explanation, Figure 2 The structure of the display device is schematically shown by focusing on the display area where the image is displayed. In some embodiments, although not shown in the drawings, at least one driving circuit (eg, a scan driver and a data driver) and / or line may also be provided in the display device.

[0090] refer to Figures 1a to 1f as well as Figure 2 A display device according to an embodiment of the present disclosure may include a substrate SUB, pixels PXL disposed on the substrate SUB and each including at least one light emitting element LD, a driver (not shown) disposed on the substrate SUB and configured to drive the pixels PXL, and a line assembly (not shown) disposed to electrically connect the pixels PXL to the driver.

[0091] According to the method of driving the light emitting element LD, the display device can be classified into a passive matrix type display device and an active matrix type display device. For example, in the case where the display device according to the embodiment is implemented as an active matrix type, each of the pixels PXL may include a driving transistor configured to control the amount of current to be supplied to the light emitting element LD and a switching transistor configured to transmit a data signal to the driving transistor.

[0092] Recently, considering resolution, contrast and operating speed, active matrix display devices capable of selectively turning on each pixel PXL have become mainstream. However, the present disclosure is not limited thereto. For example, a passive matrix display device in which the pixels PXL can be turned on in groups may also employ components (e.g., a first electrode and a second electrode) for driving the light emitting element LD.

[0093] The substrate SUB may include a display area DA and a non-display area NDA.

[0094] In an embodiment, the display area DA may be disposed in the central area of ​​the display device, and the non-display area NDA may be disposed in the peripheral area of ​​the display device in a manner surrounding the display area DA. The positions of the display area DA and the non-display area NDA are not limited thereto, and their positions may be changed.

[0095] The display area DA may be an area in which pixels PXL for displaying an image are disposed. The non-display area NDA may be an area in which a driver for driving the pixels PXL and some of line components for coupling (or connecting) the pixels PXL to the driver are disposed.

[0096] The display area DA may have various shapes. For example, the display area DA may be provided in various forms, such as a closed polygon including sides formed by linear lines, a circle, an ellipse, etc. including sides formed by curved lines, and a semicircle, a semiellipse, etc. including sides formed by linear lines and curved lines.

[0097] The non-display area NDA may be disposed on at least one side of the display area DA. In an embodiment of the present disclosure, the non-display area NDA may surround the periphery of the display area DA.

[0098] The substrate SUB may include a transparent insulating material allowing light to be transmitted.

[0099] The substrate SUB may be a rigid substrate. For example, the rigid substrate SUB may be one of a glass substrate, a quartz substrate, a glass ceramic substrate, and a crystallized glass substrate.

[0100] The substrate SUB may be a flexible substrate. Here, the flexible substrate SUB may be a film substrate or a plastic substrate including a polymer organic material. For example, the flexible substrate SUB may include at least one of polystyrene, polyvinyl alcohol, polymethyl methacrylate, polyether sulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, cellulose triacetate, and cellulose acetate propionate.

[0101] However, the material forming (constituting) the substrate SUB may be changed, and the material constituting the substrate SUB may include, for example, fiber reinforced plastic (FRP).

[0102] One area of ​​the substrate SUB is set as a display area DA in which the pixels PXL are disposed, and another area thereof is set as a non-display area NDA. For example, the substrate SUB may include a display area DA including a pixel area on which corresponding pixels PXL are formed, and a non-display area NDA disposed around the display area DA.

[0103] The pixels PXL may be disposed in the display area DA on the substrate SUB. In an embodiment of the present disclosure, the pixels PXL may be arranged in a stripe structure or a PENTILE TM The arrangement structure is arranged in the display area DA, but the present disclosure is not limited thereto.

[0104] Each pixel PXL may include a light emitting element LD configured to be driven in response to a corresponding scan signal and a corresponding data signal. The light emitting element LD may have a small size corresponding to a micrometer or nanometer level and be electrically connected in parallel with a light emitting element LD disposed near it, but the present disclosure is not limited thereto. The light emitting element LD may form a light source of each pixel PXL.

[0105] Each of the pixels PXL may include at least one light source driven by a predetermined control signal (eg, a scan signal and a data signal) and / or a predetermined power source (eg, a first driving power source and a second driving power source). Figures 1a to 1f The light emitting element LD shown in each of the embodiments has, for example, at least one ultra-small rod-type light emitting element LD corresponding to a small size of nanometer or micrometer order. However, in the embodiments of the present disclosure, the type of light emitting element LD that can be used as the light source of the pixel PXL is not limited thereto.

[0106] In an embodiment of the present disclosure, the color, type, and / or number of the pixels PXL are not particularly limited. For example, the color of light emitted from each pixel PXL may be changed in various ways.

[0107] The driver may provide a signal to each pixel PXL through the line assembly and thus control the operation of the pixel PXL. Figure 2 In the figure, the wire components are omitted for ease of explanation.

[0108] The driver may include a scan driver, an emission driver, a data driver, and a timing controller, wherein the scan driver is configured to provide a scan signal to the pixel PXL through a scan line, the emission driver is configured to provide an emission control signal to the pixel PXL through an emission control line, and the data driver is configured to provide a data signal to the pixel PXL through a data line. The timing controller may control the scan driver, the emission driver, and the data driver.

[0109] Figure 3a to Figure 3c It is shown that the Figure 2 Schematic circuit diagrams of various embodiments of the electrical connection relationships of components in any one of the pixels shown in FIG.

[0110] For example, Figure 3a to Figure 3c Various embodiments of electrical connection relationships of components included in the pixel PXL that may be employed in an active display device are shown. However, the types of components included in the pixel PXL applicable to the embodiments of the present disclosure are not limited thereto.

[0111] exist Figure 3a to Figure 3c In, not only Figure 2 The components in each of the pixels PXL shown in FIG. 1 and the region in which the components are disposed are included in the definition of the term “pixel PXL”. In an embodiment, Figure 3a to Figure 3c Each pixel PXL shown in FIG. 1 may be set to Figure 2 The pixels PXL may have substantially the same or similar structures.

[0112] refer to Figures 1a to 1f , Figure 2 as well as Figure 3a to Figure 3c Each pixel PXL (hereinafter referred to as a "pixel") may include an emission unit EMU configured to generate light having brightness corresponding to a data signal. The pixel PXL may further selectively include a pixel circuit 144 configured to drive the emission unit EMU.

[0113] In an embodiment, the emission unit EMU may include a light emitting element LD electrically connected in parallel between a first power line PL1 to which a voltage of a first driving power source VDD is applied and a second power line PL2 to which a voltage of a second driving power source VSS is applied. For example, the emission unit EMU may include a first electrode EL1 (or "first alignment electrode") electrically connected to the first driving power source VDD via the first power line PL1, a second electrode EL2 (or "second alignment electrode") electrically connected to the second driving power source VSS via the second power line PL2, and a light emitting element LD electrically connected in parallel to each other between the first electrode EL1 and the second electrode EL2 in the same direction. In an embodiment of the present disclosure, the first electrode EL1 may be an anode electrode, and the second electrode EL2 may be a cathode electrode.

[0114] In an embodiment of the present disclosure, each of the light-emitting elements LD included in the emission unit EMU may include a first end electrically connected to a first driving power source VDD through a first electrode EL1 and a second end electrically connected to a second driving power source VSS through a second electrode EL2. The first driving power source VDD and the second driving power source VSS may have different potentials. For example, the first driving power source VDD may be set to a high potential power source, and the second driving power source VSS may be set to a low potential power source. Here, during the emission period of the pixel PXL, the potential difference between the first driving power source VDD and the second driving power source VSS may be set to a value equal to or greater than the threshold voltage of the light-emitting element LD.

[0115] As described above, the light emitting elements LD electrically connected in parallel to each other between the first electrode EL1 and the second electrode EL2 in the same direction (e.g., in the forward direction) can form a corresponding effective light source, wherein voltages having different potentials are respectively supplied to the first electrode EL1 and the second electrode EL2. The effective light source can be gathered to form an emission unit EMU of the pixel PXL.

[0116] The light emitting element LD of the emission unit EMU can emit light having a brightness corresponding to the driving current provided thereto by the pixel circuit 144. For example, during each frame period, the pixel circuit 144 can provide the emission unit EMU with a driving current corresponding to the grayscale level of the corresponding frame data. The driving current provided to the emission unit EMU can be shunted into the light emitting elements LD electrically connected to each other in the same direction. Therefore, each of the light emitting elements LD can emit light having a brightness corresponding to the current applied thereto, so that the emission unit EMU can emit light having a brightness corresponding to the driving current.

[0117] although Figure 3a to Figure 3cAn embodiment in which the light-emitting elements LD are electrically connected to each other between the first driving power source VDD and the second driving power source VSS in the same direction is shown, but the present disclosure is not limited thereto. In an embodiment, in addition to the light-emitting element LD forming the corresponding effective light source, the emission unit EMU may also include at least one invalid light source. For example, at least one reverse light-emitting element (not shown) may be further electrically connected between the first electrode EL1 and the second electrode EL2 of the emission unit EMU. The reverse light-emitting element, together with the light-emitting element LD forming the effective light source, may be electrically connected to each other in parallel between the first electrode EL1 and the second electrode EL2. Here, the reverse light-emitting element may be electrically connected between the first electrode EL1 and the second electrode EL2 in a direction opposite to the direction of the light-emitting element LD. Even when a predetermined driving voltage (e.g., a driving voltage in a normal direction) is applied between the first electrode EL1 and the second electrode EL2, the reverse light-emitting element remains disabled. Therefore, current does not substantially flow through the reverse light-emitting element.

[0118] The pixel circuit 144 may be electrically connected to the scan line Si and the data line Dj of the corresponding pixel PXL. For example, if the pixel PXL is disposed in the i-th row (where i is a natural number) and the j-th column (where j is a natural number) of the display area DA, the pixel circuit 144 of the pixel PXL may be electrically connected to the i-th scan line Si and the j-th data line Dj of the display area DA. In an embodiment, as shown in FIG. Figure 3a As shown in FIG. 1 , the pixel circuit 144 may include a first transistor T1, a second transistor T2 and a storage capacitor Cst. However, the structure of the pixel circuit 144 is not limited to Figure 3a The structure of the embodiment shown in .

[0119] A first terminal of the first transistor T1 (switching transistor) may be electrically connected to the data line Dj, and a second terminal thereof may be electrically connected to the first node N1. Here, the first terminal and the second terminal of the first transistor T1 are different from each other, and for example, in the case where the first terminal is a source electrode, the second terminal is a drain electrode. A gate electrode of the first transistor T1 may be electrically connected to the scan line Si.

[0120] In the case where a scan signal having a voltage (e.g., a low level voltage) capable of turning on the first transistor T1 is provided from the scan line Si, the first transistor T1 is turned on to electrically connect the data line Dj with the first node N1. Here, a data signal of a corresponding frame is provided to the data line Dj, whereby the data signal is transmitted to the first node N1. The data signal transmitted to the first node N1 may be charged into the storage capacitor Cst.

[0121] A first terminal of the second transistor T2 (driving transistor) may be electrically connected to the first driving power supply VDD, and a second terminal thereof may be electrically connected to the first electrode EL1 for the light emitting element LD. A gate electrode of the second transistor T2 may be electrically connected to the first node N1. Thus, the second transistor T2 may control the amount of driving current to be supplied to the light emitting element LD in response to the voltage of the first node N1.

[0122] A first electrode of the storage capacitor Cst may be electrically connected to the first driving power source VDD, and a second electrode thereof may be electrically connected to the first node N1. The storage capacitor Cst charges a voltage corresponding to a data signal supplied to the first node N1 and maintains the charged voltage until a data signal of a subsequent frame is supplied.

[0123] Figure 3a A pixel circuit 144 is shown, which includes a first transistor T1 configured to transmit a data signal to the pixel PXL, a storage capacitor Cst configured to store the data signal, and a second transistor T2 configured to provide a driving current corresponding to the data signal to the light emitting element LD.

[0124] However, the present disclosure is not limited thereto, and the structure of the pixel circuit 144 may be changed in various ways. For example, the pixel circuit 144 may further include at least one transistor element or other circuit elements, such as a transistor element configured to compensate for the threshold voltage of the second transistor T2, a transistor element configured to initialize the first node N1, and / or a transistor element configured to control the emission time of the light emitting element LD, and other circuit elements such as a boost capacitor for increasing the voltage of the first node N1.

[0125] In addition, despite the Figure 3a , the transistors (eg, the first transistor T1 and the second transistor T2) included in the pixel circuit 144 are shown as being formed of P-type transistors, but the present disclosure is not limited thereto. In other words, at least one of the first transistor T1 and the second transistor T2 included in the pixel circuit 144 may be changed to an N-type transistor.

[0126] Next, refer to Figures 1a to 1f , Figure 2 and Figure 3b , the first transistor T1 and the second transistor T2 according to the embodiment of the present disclosure may be formed of N-type transistors. Figure 3b The configuration and operation of the pixel circuit 144 shown in FIG. Figure 3a The configuration and operation of the pixel circuit 144 may differ at least in that the connection positions of some components are changed due to the change in transistor type. Therefore, a detailed description thereof will be omitted below.

[0127] In the embodiment of the present disclosure, the configuration of the pixel circuit 144 is not limited to Figure 3a and Figure 3b For example, it can be implemented with Figure 3c The pixel circuit 144 is configured in the same manner as in the embodiment shown in FIG.

[0128] like Figure 3c As shown in , the pixel circuit 144 can be electrically connected to the scan line Si and the data line Dj of the pixel PXL. For example, if the pixel PXL is disposed in the i-th row and the j-th column of the display area DA, the pixel circuit 144 of the pixel PXL can be electrically connected to the i-th scan line Si and the j-th data line Dj of the display area DA.

[0129] In an embodiment, the pixel circuit 144 may also be electrically connected to at least one scan line. For example, the pixel PXL disposed in the i-th row of the display area DA may also be electrically connected to the i-1th scan line Si-1 and / or the i+1th scan line Si+1. In an embodiment, the pixel circuit 144 may be electrically connected not only to the first driving power supply VDD and the second driving power supply VSS, but also to a third power supply. For example, the pixel circuit 144 may be electrically connected to the initialization power supply Vint.

[0130] The pixel circuit 144 may include first to seventh transistors T1 to T7 and a storage capacitor Cst.

[0131] The first electrode (e.g., source electrode) of the first transistor (driving transistor) may be electrically connected to the first driving power source VDD via the fifth transistor T5, and the second electrode (e.g., drain electrode) thereof may be electrically connected to one end of the light emitting element LD via the sixth transistor T6. The gate electrode of the first transistor T1 may be electrically connected to the first node N1. The first transistor T1 may control a driving current flowing between the first driving power source VDD and the second driving power source VSS via the light emitting element LD in response to a voltage of the first node N1.

[0132] The second transistor T2 (switching transistor) may be electrically connected between the j-th data line Dj electrically connected to the pixel PXL and the source electrode of the first transistor T1. The gate electrode of the second transistor T2 may be electrically connected to the i-th scan line Si electrically connected to the pixel PXL. In the case where a scan signal having a gate-on voltage (e.g., a low-level voltage) is provided from the i-th scan line Si, the second transistor T2 may be turned on to electrically connect the j-th data line Dj to the source electrode of the first transistor T1. Therefore, if the second transistor T2 is turned on, the data signal provided from the j-th data line Dj may be transmitted to the first transistor T1.

[0133] The third transistor T3 may be electrically connected between the drain electrode of the first transistor T1 and the first node N1. The gate electrode of the third transistor T3 may be electrically connected to the i-th scan line Si. In the case where a scan signal having a gate-on voltage is provided from the i-th scan line Si, the third transistor T3 may be turned on to electrically connect the drain electrode of the first transistor T1 to the first node N1.

[0134] The fourth transistor T4 may be electrically connected between the first node N1 and the initialization power line IPL to which the voltage of the initialization power supply Vint is to be applied. The gate electrode of the fourth transistor T4 may be electrically connected to a previous scan line, for example, the i-1th scan line Si-1. In the case where a scan signal having a gate-on voltage is provided to the i-1th scan line Si-1, the fourth transistor T4 may be turned on so that the voltage of the initialization power supply Vint may be transmitted to the first node N1. Here, the initialization power supply Vint may have a voltage equal to or less than the minimum voltage of the data signal.

[0135] The fifth transistor T5 may be electrically connected between the first driving power source VDD and the first transistor T1. The gate electrode of the fifth transistor T5 may be electrically connected to a corresponding emission control line, for example, the i-th emission control line Ei. When an emission control signal having a gate cut-off voltage is supplied to the i-th emission control line Ei, the fifth transistor T5 may be turned off, and the fifth transistor T5 may be turned on in other cases.

[0136] The sixth transistor T6 may be electrically connected between the first transistor T1 and the first end of the light emitting element LD. The gate electrode of the sixth transistor T6 may be electrically connected to the i-th emission control line Ei. When the emission control signal having the gate-off voltage is supplied to the i-th emission control line Ei, the sixth transistor T6 may be turned off, and the sixth transistor T6 may be turned on in other cases.

[0137] The seventh transistor T7 may be electrically connected between the initialization power line IPL and the first end of the light emitting element LD. The gate electrode of the seventh transistor T7 may be electrically connected to any one of the scan lines of the subsequent stage, for example, to the i+1th scan line Si+1. When a scan signal having a gate-on voltage is supplied to the i+1th scan line Si+1, the seventh transistor T7 may be turned on so that the voltage of the initialization power supply Vint may be supplied to the first end of the light emitting element LD.

[0138] The storage capacitor Cst may be electrically connected between the first driving power source VDD and the first node N1. The storage capacitor Cst may store a voltage corresponding to both the data signal applied to the first node N1 during each frame period and the threshold voltage of the first transistor T1.

[0139] Despite Figure 3c, the transistors (eg, the first to seventh transistors T1 to T7) included in the pixel circuit 144 are shown to be formed of P-type transistors, but the present disclosure is not limited thereto. For example, at least one of the first to seventh transistors T1 to T7 may be changed to an N-type transistor.

[0140] although Figure 3a to Figure 3c An embodiment is shown in which all light emitting elements LD of each emission unit EMU are electrically connected in parallel to each other, but the present disclosure is not limited thereto. In an embodiment, the emission unit EMU may include at least one series connection stage, the series connection stage including a plurality of light emitting elements LD electrically connected in parallel to each other. In other words, the emission unit EMU may be formed as a series / parallel combination structure.

[0141] The structure of the pixel PXL applicable to the present disclosure is not limited to Figure 3a to Figure 3c , and the corresponding pixel PXL may have various structures. In the embodiment of the present disclosure, each pixel PXL may be configured in a passive light-emitting display device or the like. In this case, the pixel circuit 144 may be omitted, and the opposite ends of the light-emitting element LD included in the emission unit EMU may be directly electrically connected to the scan lines Si-1, Si and Si+1, the data line Dj, the first power line PL1 to which the voltage of the first driving power VDD is applied, the second power line PL2 to which the voltage of the second driving power VSS is applied, and / or a predetermined control line.

[0142] Figure 4 It is schematically shown Figure 2 1 is a plan view of three pixels adjacent to each other in the row direction among the pixels shown in . Figure 5 Only shows Figure 4 Schematic plan view of first electrodes and second electrodes in first to third pixels and light emitting elements aligned therebetween. Figure 6 It is along Figure 4 A schematic cross-sectional view taken along line II'. Figure 7 It is along Figure 4 A schematic cross-sectional view taken along line II-II'. Figure 8 It shows Figure 7 In the embodiment shown in FIG. 1 , the first electrode and the second electrode are arranged on the same layer, and Figure 8 is corresponding to Figure 4 Schematic cross-sectional view along line II-II'. Fig. 9 Shows Figure 7 Another shape of the partition wall (or bank pattern) shown in FIG. Fig. 9 is corresponding to Figure 4 Schematic cross-sectional view along line II-II'. Fig.10 It is along Figure 4A schematic cross-sectional view taken along line III-III'.

[0143] exist Figure 4 and Figure 5 , for the sake of explanation, illustration of a transistor electrically connected to a light emitting element and a signal line electrically connected to the transistor is omitted.

[0144] Figure 4 and Figure 5 The first pixel to the third pixel shown in each of the above may refer to three pixels adjacent to each other in the first direction. Here, the first pixel among the first pixel to the third pixel may refer to a pixel arranged in the jth column of the i-th row. The second pixel may refer to a pixel arranged in the j+1th column of the i-th row. The third pixel may refer to a pixel arranged in the j+2th column of the i-th row.

[0145] In addition, despite Figures 4 to 10 A simplified structure of each of the first to third pixels is shown, for example, each electrode is shown to have only a single electrode layer, and each insulating layer is shown to have only a single insulating layer, but the present disclosure is not limited thereto.

[0146] In addition, in an embodiment of the present disclosure, the term "pixel (pixel) PXL" or "pixels (pixels) PXL" will be used to specify at least one pixel of the first pixel to the third pixel. In an embodiment of the present disclosure, the phrase "components are arranged and / or formed on the same layer" may mean that the components are formed by the same process.

[0147] refer to Figures 1a to 10 , the display device according to the embodiment of the present disclosure may include a substrate SUB on which the first pixel PXL1 , the second pixel PXL2 , and the third pixel PXL3 are disposed.

[0148] In an embodiment of the present disclosure, the first pixel PXL1 may be a red pixel, the second pixel PXL2 may be a green pixel, and the third pixel PXL3 may be a blue pixel. However, the present disclosure is not limited thereto. In an embodiment, the first pixel PXL1 may be a green pixel or a blue pixel, the second pixel PXL2 may be a blue pixel or a red pixel, and the third pixel PXL3 may be a red pixel or a green pixel.

[0149] Each of the first to third pixels PXL1 to PXL3 may include an emission area EMA configured to emit light and a peripheral area disposed around the periphery of the emission area EMA. The emission area EMA may refer to an area from which light is emitted, and the peripheral area may refer to an area from which light is not emitted. In an embodiment of the present disclosure, the pixel area of ​​each of the first to third pixels PXL1 to PXL3 may include the emission area EMA and the peripheral area of ​​the corresponding pixel.

[0150] The substrate SUB, the pixel circuit layer PCL, and the display element layer DPL may be disposed in a pixel region of each of the first to third pixels PXL1 to PXL3 .

[0151] The pixel circuit layer PCL of each of the first to third pixels PXL1 to PXL3 may include a buffer layer BFL disposed on a substrate SUB, at least one transistor T disposed on the buffer layer BFL, and a driving voltage line DVL. In addition, the pixel circuit layer PCL of each of the first to third pixels PXL1 to PXL3 may further include a passivation layer PSV disposed on the transistor T and the driving voltage line DVL.

[0152] The substrate SUB may be a rigid substrate or a flexible substrate.

[0153] The buffer layer BFL may prevent impurities from diffusing into the transistor T. The buffer layer BFL may be provided in a single-layer structure or a multi-layer structure having at least two layers. In the case where the buffer layer BFL has a multi-layer structure, each layer may be formed of the same material or different materials. Depending on the material and / or process conditions of the substrate SUB, the buffer layer BFL may be omitted.

[0154] The transistor T may include a first transistor T1(T) and a second transistor T2(T). In an embodiment of the present disclosure, the first transistor T1(T) may be a driving transistor electrically connected to the light emitting element LD of the corresponding pixel PXL and configured to drive the light emitting element LD. The second transistor T2(T) may be a switching transistor configured to switch the first transistor T1(T).

[0155] Each of the first transistor T1(T) and the second transistor T2(T) may include a semiconductor layer SCL, a gate electrode GE, a first terminal SE, and a second terminal DE. The first terminal SE may be a source electrode or a drain electrode, and the second terminal DE may be another electrode. For example, in the case where the first terminal SE is a source electrode, the second terminal DE may be a drain electrode.

[0156] The semiconductor layer SCL may be disposed on the buffer layer BFL. The semiconductor layer SCL may include a first region in contact with the first terminal SE and a second region in contact with the second terminal DE. A region between the first region and the second region may be a channel region.

[0157] The semiconductor layer SCL may be a semiconductor pattern formed of polysilicon, amorphous silicon, an oxide semiconductor, etc. The channel region may be an intrinsic semiconductor as an undoped semiconductor pattern. Each of the first region and the second region may be a semiconductor pattern doped with impurities.

[0158] The gate electrode GE may be disposed on the semiconductor layer SCL with the gate insulating layer GI interposed therebetween.

[0159] Each of the first terminal SE and the second terminal DE may respectively contact the first and second regions of the semiconductor layer SCL through corresponding contact holes passing through the interlayer insulating layer ILD and the gate insulating layer GI.

[0160] In an embodiment of the present disclosure, at least one transistor T included in the pixel circuit layer PCL of each of the first pixel PXL1 to the third pixel PXL3 may be formed by an LTPS thin film transistor, but the present disclosure is not limited thereto. In some embodiments, at least one transistor T may be formed by an oxide semiconductor thin film transistor. In addition, in an embodiment of the present disclosure, the transistor T is shown as a case of a thin film transistor having a top gate structure, but the present disclosure is not limited thereto. In an embodiment, the transistor T may be a thin film transistor having a bottom gate structure.

[0161] The driving voltage line DVL may be disposed on the interlayer insulating layer ILD, but the present disclosure is not limited thereto. In some embodiments, the driving voltage line DVL may be disposed on any one of the insulating layers included in the pixel circuit layer PCL. The second driving power source ( Figure 3a A voltage of VSS) may be applied to the driving voltage line DVL. In an embodiment of the present disclosure, Figure 3a to Figure 3c As shown in each of , the driving voltage line DVL may be a second power line PL2 to which a voltage of a second driving power source VSS is applied.

[0162] The passivation layer PSV may include a first contact hole CH1 exposing a portion of the second terminal DE of the first transistor T1 (T) and a second contact hole CH2 exposing a portion of the driving voltage line DVL.

[0163] The display element layer DPL of each of the first to third pixels PXL1 to PXL3 may include a partition wall PW, a first electrode EL1, a second electrode EL2, a first connection line CNL1 and a second connection line CNL2, and first to third capping layers CPL1 to CPL3. In addition, the display element layer DPL of each of the first to third pixels PXL1 to PXL3 may also selectively include at least one first contact electrode CNE1 directly electrically connected to the first electrode EL1 and at least one second contact electrode CNE2 directly electrically connected to the second electrode EL2.

[0164] The partition wall PW may be a support member or an insulating pattern supporting each of the first electrode EL1 and the second electrode EL2 to change the surface profile of each of the first electrode EL1 and the second electrode EL2 so that light emitted from the light emitting element LD can travel more efficiently in the image display direction of the display device.

[0165] The partition wall PW may be disposed and / or formed on the passivation layer PSV of the emission area EMA of each of the first pixel PXL1 to the third pixel PXL3. The partition wall PW may include an inorganic insulating layer formed of an inorganic material or an organic insulating layer formed of an organic material. In an embodiment, the partition wall PW may include a single organic insulating layer and / or a single inorganic insulating layer, but the present disclosure is not limited thereto. For example, the partition wall PW may have a multilayer structure formed by stacking at least one organic insulating layer and at least one inorganic insulating layer.

[0166] The partition wall PW may have a trapezoidal cross-section in which its width decreases upward from one surface of the passivation layer PSV, but the present disclosure is not limited thereto. Fig. 9 As shown in , the partition wall PW may include a curved surface and have a cross section having a semi-elliptical shape, a semi-circular shape, etc., and its width decreases upward from one surface of the passivation layer PSV. In the schematic cross-sectional view, the shape of each of the partition walls PW is not limited to the above example, and can be changed in various ways within the range that the efficiency of light emitted from each of the light emitting elements LD can be improved. The partition walls PW adjacent to each other can be arranged on the same plane on the passivation layer PSV and have the same height.

[0167] In an embodiment of the present disclosure, the partition wall PW may include a first partition wall (or a first bank pattern) PW1 disposed under each of the first electrodes EL1 and a second partition wall (or a second bank pattern) PW2 disposed under each of the second electrodes EL2. The first partition wall PW1 and the second partition wall PW2 may be disposed at positions spaced apart from each other by a predetermined distance on one surface of the passivation layer PSV.

[0168] The first partition wall PW1 may be disposed on the passivation layer PSV at a position spaced apart from the adjacent first partition wall PW1 in the second direction DR2 (eg, “column direction”). The second partition wall PW2 may also be disposed on the passivation layer PSV at a position spaced apart from the adjacent second partition wall PW2 in the second direction DR2.

[0169] The display element layer DPL of each of the first to third pixels PXL1 to PXL3 may further include a bank (not shown) disposed to surround the emission area EMA of the corresponding pixel PXL in a peripheral region of the corresponding pixel PXL (e.g., a non-emission region in which the light emitting element LD is not disposed). The bank may be a structure configured to define (or divide) the emission area EMA of each of the first to third pixels PXL1 to PXL3, and may be, for example, a pixel defining layer. The bank may include at least one light shielding material and / or a reflective material, and thus prevent a light leakage defect in which light (or light rays) leaks between adjacent pixels PXL.

[0170] In an embodiment, a reflective material layer may be formed on the embankment to further enhance the efficiency of light emitted from each of the pixels PXL. Although the embankment may be formed and / or disposed on a layer different from that of the partition wall PW, the present disclosure is not limited thereto. In an embodiment, the embankment may be formed and / or disposed on the same layer as that of the partition wall PW.

[0171] The first connection line CNL1 may be disposed and / or formed to drive each of the first to third pixels PXL1 to PXL3 independently from the adjacent pixels PXL only in the corresponding pixel PXL, and be electrically and / or physically separated from the first connection line CNL1 disposed and / or formed in each of the adjacent pixels PXL.

[0172] In an embodiment of the present disclosure, the first connection line CNL1 may include a 1-1 connection line CNL1_1 extending in a first direction DR1 (e.g., a “row direction”) and a 1-2 connection line CNL1_2 extending in a second direction DR2 in each of the first to third pixels PXL1 to PXL3. Specifically, the 1-1 connection line CNL1_1 and the 1-2 connection line CNL1_2 may be integral with each other and electrically and / or physically connected to each other. In the case where the 1-1 connection line CNL1_1 and the 1-2 connection line CNL1_2 are integral with each other, the 1-1 connection line CNL1_1 may be a region of the 1-2 connection line CNL1_2, or the 1-2 connection line CNL1_2 may be a region of the 1-1 connection line CNL1_1.

[0173] The 1-2nd connection line CNL1_2 may be electrically and / or physically connected to the first electrode EL1. The 1-2nd connection line CNL1_2 may be disposed on the first electrode EL1, and the insulating pattern INSP is interposed between the 1-2nd connection line CNL1_2 and the first electrode EL1 and overlaps the first electrode EL1. The 1-2nd connection line CNL1_2 may include a first portion A corresponding to the insulating pattern INSP and a second portion B excluding the first portion A. The second portion B of the 1-2nd connection line CNL1_2 may be a portion corresponding to the first electrode EL1 and a portion electrically and / or physically connected to the first electrode EL1.

[0174] The 1-2 connection line CNL1_2 may be electrically connected to the second terminal DE of the first transistor T1(T) of the pixel circuit layer PCL of each of the first to third pixels PXL1 to PXL3 through the first contact hole CH1 passing through the passivation layer PSV. Therefore, the signal (or voltage) applied to the first transistor T1(T) may be transmitted to the 1-2 connection line CNL1_2 of the corresponding pixel PXL.

[0175] The second connection line CNL2 may be commonly provided to the first to third pixels PXL1 to PXL3. The first to third pixels PXL1 to PXL3 provided in the same row in the first direction DR1 may be commonly electrically connected to the second connection line CNL2. The second connection line CNL2 may be electrically connected to the driving voltage line DVL of the pixel circuit layer PCL of each of the first to third pixels PXL1 to PXL3 through the second contact hole CH2 passing through the passivation layer PSV. Therefore, the voltage of the second driving power source VSS applied to the driving voltage line DVL may be transmitted to the second connection line CNL2 commonly provided to the first to third pixels PXL1 to PXL3.

[0176] In an embodiment of the present disclosure, the second connection line CNL2 may include a 2-1 connection line CNL2_1 extending in the first direction DR1 and a 2-2 connection line CNL2_2 extending in the second direction DR2 in each of the first to third pixels PXL1 to PXL3. Specifically, the 2-1 connection line CNL2_1 and the 2-2 connection line CNL2_2 may be integral with each other and electrically and / or physically connected to each other. In the case where the 2-1 connection line CNL2_1 and the 2-2 connection line CNL2_2 are integral with each other, the 2-1 connection line CNL2_1 may be a region of the 2-2 connection line CNL2_2, or the 2-2 connection line CNL2_2 may be a region of the 2-1 connection line CNL2_1.

[0177] In an embodiment of the present disclosure, the first connection line CNL1 and the second connection line CNL2 may be disposed on respective layers different from each other. Specifically, the first connection line CNL1 may be disposed and / or formed on the first electrode EL1. The second connection line CNL2 may be disposed on the same layer as that of the first electrode EL1. In an embodiment of the present disclosure, the phrase "disposed and / or formed on different layers" may mean that components are formed by different processes.

[0178] Each of the first electrode EL1 and the second electrode EL2 may be disposed in the emission area EMA of each of the first pixel PXL1 to the third pixel PXL3, and disposed in the second direction DR2. The first electrode EL1 and the second electrode EL2 may be disposed on the same surface and spaced apart from each other by a predetermined distance. In a plan view, the first electrode EL1 and the second electrode EL2 may be alternately disposed in the second direction DR2. For example, the first electrode EL1 may be disposed in an odd-numbered row in the emission area EMA of each of the first pixel PXL1 to the third pixel PXL3, and the second electrode EL2 may be disposed in an even-numbered row in the emission area EMA of the corresponding pixel PXL.

[0179] The first electrode EL1 may be disposed in the second direction DR2. Each of the first electrodes EL1 may be spaced apart from the first electrode EL1 adjacent to the second direction DR2. In other words, each of the first electrodes EL1 may be electrically and / or physically separated from the first electrode EL1 adjacent to the second direction DR2. The first electrodes EL1 disposed in the second direction DR2 may be electrically connected to each other through the first connection line CNL1. In an embodiment of the present disclosure, the first connection line CNL1 may be disposed and / or formed on the first electrode EL1 to electrically connect the first electrodes EL1 adjacent to each other in the second direction DR2. The signal (or voltage) applied to the first connection line CNL1 may be transmitted to each of the first electrodes EL1 electrically connected to each other through the first connection line CNL1.

[0180] Although in an embodiment of the present disclosure, each of the first electrodes EL1 may have a rhombus shape including four sides in a plan view, the present disclosure is not limited thereto. In an embodiment, the first electrode EL1 may be changed in various shapes. Each of the first electrodes EL1 may have a surface profile corresponding to the shape of the first partition wall PW1 disposed thereunder. Each of the first electrodes EL1 may have a surface area wide enough (or large enough) to completely cover the first partition wall PW1.

[0181] The second electrode EL2 may be disposed in the second direction DR2. In an embodiment of the present disclosure, the second electrode EL2 may be disposed on the same layer as the second connection line CNL2, and may be electrically and / or physically connected to the second electrode EL2 adjacent thereto in the second direction DR2 through the second connection line CNL2. In other words, each of the second electrodes EL2 may be electrically and / or physically connected to the second electrode EL2 adjacent thereto in the second direction DR2 through the second connection line CNL2.

[0182] In an embodiment of the present disclosure, each of the second electrodes EL2 may be integral with the second connection line CNL2 and electrically and / or physically connected to the second connection line CNL2. In the case where the second connection line CNL2 and the second electrode EL2 are integral with each other, the second connection line CNL2 may be set as a predetermined region of the second electrode EL2, or the second electrode EL2 may be set as a predetermined region of the second connection line CNL2. The second electrode EL2 may be bifurcated from the 2-2nd connection line CNL2_2 in the first direction DR1. As described above, since the second connection line CNL2 and the second electrode EL2 are electrically connected to each other, the voltage of the second driving power supply VSS applied to the second connection line CNL2 may be transmitted to each of the second electrodes EL2.

[0183] In an embodiment of the present disclosure, each of the second electrodes EL2 may include an intermediate electrode CTE, at least one bridge pattern BRP, and at least one sub-electrode.

[0184] The sub-electrodes of each of the second electrodes EL2 may include a first sub-electrode EL2_1 and a second sub-electrode EL2_2, which are arranged in the first direction DR1 and are electrically and / or physically connected by the bridge pattern BRP. Although for the purpose of explanation, Figure 4 and Figure 5 It is shown that each of the second electrodes EL2 includes only two sub-electrodes EL2_1 and EL2_2, but the present disclosure is not limited thereto. In an embodiment, each of the second electrodes EL2 may include more sub-electrodes. In the case where each of the second electrodes EL2 includes more sub-electrodes (e.g., three sub-electrodes), each of the second electrodes EL2 may include two bridge patterns BRP configured to connect the three sub-electrodes.

[0185] In an embodiment of the present disclosure, each of the second electrodes EL2 may include i (where i is a natural number of one or more) bridge patterns BRP and i+1 (where i is a natural number of one or more) sub-electrodes.

[0186] The intermediate electrode CTE of each of the second electrodes EL2 may be an intermediate medium configured to electrically and / or physically connect the 2-2 connection line CNL2_2 and the first sub-electrode EL2_1. One end of the intermediate electrode CTE of each of the second electrodes EL2 may be electrically connected to the 2-2 connection line CNL2_2, and the other end thereof may be electrically connected to the first sub-electrode EL2_1. In an embodiment of the present disclosure, the intermediate electrode CTE of each of the second electrodes EL2 may be integrally provided and / or formed with the 2-2 connection line CNL2_2. In this case, the intermediate electrode CTE of each of the second electrodes EL2 may be a predetermined region of the 2-2 connection line CNL2_2.

[0187] The bridge pattern BRP of each of the second electrodes EL2 may be an intermediate medium, which is disposed between the first sub-electrode EL2_1 and the second sub-electrode EL2_2 and is configured to electrically connect and / or physically connect the first sub-electrode EL2_1 and the second sub-electrode EL2_2. One end of the bridge pattern BRP of each of the second electrodes EL2 may be electrically connected to the first sub-electrode EL2_1, and the other end thereof may be electrically connected to the second sub-electrode EL2_2. In an embodiment of the present disclosure, the bridge pattern BRP of each of the second electrodes EL2 may be integrally disposed and / or formed with the first sub-electrode EL2_1 and the second sub-electrode EL2_2. In this case, the bridge pattern BRP of each of the second electrodes EL2 may be a predetermined region of the first sub-electrode EL2_1 or a predetermined region of the second sub-electrode EL2_2.

[0188] In an embodiment of the present disclosure, an insulating pattern INSP may be disposed and / or formed on the bridge pattern BRP of each of the second electrodes EL2. The bridge pattern BRP of each of the second electrodes EL2 may be electrically separated or insulated from the 1-2nd connection line CNL1_2 disposed and / or formed thereon by the insulating pattern INSP.

[0189] The first sub-electrode EL2_1 and the second sub-electrode EL2_2 of each of the second electrodes EL2 may be arranged in the first direction DR1 and electrically connected through the bridge pattern BRP. One end of the first sub-electrode EL2_1 of each of the second electrodes EL2 may be electrically connected to the intermediate electrode CTE, and the other end thereof may be electrically connected to the first side of the bridge pattern BRP. The second sub-electrode EL2_2 of each of the second electrodes EL2 may be electrically connected to the second side of the bridge pattern BRP.

[0190] In an embodiment of the present disclosure, the first sub-electrode EL2_1 and the second sub-electrode EL2_2 of each of the second electrodes EL2 may have a rhombus shape, but the present disclosure is not limited thereto. In an embodiment, its shape may be changed into various forms. In addition, each of the first sub-electrode EL2_1 and the second sub-electrode EL2_2 of each of the second electrodes EL2 may have the same shape as that of the first electrode EL1, but the present disclosure is not limited thereto, and in an embodiment, it may have a shape different from that of the first electrode EL1. The first sub-electrode EL2_1 and the second sub-electrode EL2_2 of each of the second electrodes EL2 may have a surface profile corresponding to the shape of the second partition wall PW2 disposed thereunder. In addition, the first sub-electrode EL2_1 and the second sub-electrode EL2_2 of each of the second electrodes EL2 may have a surface area wide enough (or large enough) to completely cover the second partition wall PW2.

[0191] The intermediate electrode CTE, the bridge pattern BRP, the first sub-electrode EL2_1, and the second sub-electrode EL2_2 of each of the second electrodes EL2 may be integrated with each other and electrically and / or physically connected to each other. The second electrode EL2 may be disposed on the same plane at a position spaced a predetermined distance from the first electrode EL1, so that the second electrode EL2 is electrically and / or physically separated from the first electrode EL1. Although in the aforementioned embodiment, the second electrode EL2 and the first electrode EL1 are shown as being disposed on the same layer, the present disclosure is not limited thereto. In an embodiment, the second electrode EL2 and the first electrode EL1 may be disposed on different layers.

[0192] In an embodiment of the present disclosure, each of the first electrode EL1 and the second electrode EL2 may function as an alignment electrode for aligning the light emitting element LD in the emission area EMA of each of the first to third pixels PXL1 to PXL3 .

[0193] Before the light emitting element LD is aligned in the emission area EMA of each of the first pixel PXL1 to the third pixel PXL3, a first alignment voltage may be applied to each of the first electrodes EL1 through the first connection line CNL1, and a second alignment voltage may be applied to each of the second electrodes EL2 through the second connection line CNL2. The first alignment voltage and the second alignment voltage may have different voltage levels. For example, the first alignment voltage may be a ground voltage, and the second alignment voltage may be an AC voltage.

[0194] Since predetermined alignment voltages having different voltage levels are respectively applied to each of the first and second electrodes EL1 and EL2, an electric field may be formed between the first and second electrodes EL1 and EL2. Therefore, the light emitting element LD may be aligned between the first and second electrodes EL1 and EL2 by the electric field.

[0195] After the light emitting element LD is aligned in the emission area EMA of each of the first to third pixels PXL1 to PXL3 , each of the first and second electrodes EL1 and EL2 may function as a driving electrode for driving the light emitting element LD.

[0196] Each of the first and second electrodes EL1 and EL2 may be made of a material having a predetermined reflectivity to allow light emitted from opposite ends EP1 and EP2 of each of the light emitting elements LD to travel in an image display direction (eg, forward direction) of the display device.

[0197] In an embodiment of the present disclosure, the first electrode EL1 , the second electrode EL2 , and the second connection line CNL2 may be disposed on the same layer and formed of the same material.

[0198] The first electrode EL1, the second electrode EL2, and the second connection line CNL2 may be formed of a conductive material having a predetermined reflectivity. The conductive material may include a metal (such as Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Ti) or an alloy thereof, a transparent conductive oxide (such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), or indium tin zinc oxide (ITZO)) and a conductive polymer such as PEDOT. In the case where each of the first electrode EL1, the second electrode EL2, and the second connection line CNL2 includes a transparent oxide or a conductive polymer, a separate conductive layer made of an opaque metal may be provided to reflect light emitted from the light emitting element LD in the image display direction of the display device. The material of each of the first electrode EL1, the second electrode EL2, and the second connection line CNL2 is not limited to the aforementioned materials.

[0199] In addition, although each of the first electrode EL1, the second electrode EL2, and the second connection line CNL2 is formed by a single layer, the present disclosure is not limited thereto. In an embodiment, the first electrode EL1, the second electrode EL2, and the second connection line CNL2 may be formed as a multilayer structure formed by stacking two or more materials of metal, alloy, conductive oxide, and conductive polymer. Each of the first electrode EL1, the second electrode EL2, and the second connection line CNL2 may be formed by a multilayer structure including at least two layers to minimize distortion caused by signal delay when a signal (or voltage) is transmitted to the opposite ends EP1 and EP2 of each of the light emitting elements LD. For example, each of the first electrode EL1, the second electrode EL2, and the second connection line CNL2 may be formed by a multilayer structure in which layers are stacked in the order of ITO / Ag / ITO.

[0200] As described above, since each of the first electrode EL1 and the second electrode EL2 has a shape corresponding to the shape of the partition wall PW disposed thereunder, light emitted from the opposite ends EP1 and EP2 of each of the light emitting elements LD can be reflected by the first electrode EL1 and the second electrode EL2 and travel more efficiently in the image display direction of the display device. Therefore, the efficiency of light emitted from each of the light emitting elements LD can be further increased.

[0201] In an embodiment of the present disclosure, the partition wall PW and the first electrode EL1 and the second electrode EL2 can each be used as a reflective component configured to guide the light emitted from the light emitting element LD in a desired direction and thus increase the light efficiency of the display device. In other words, the partition wall PW and the first electrode EL1 and the second electrode EL2 can each be used as a reflective component configured to enable the light emitted from the light emitting element LD to travel in the image display direction of the display device, thereby enhancing the light output efficiency of the light emitting element LD.

[0202] One of the first electrode EL1 and the second electrode EL2 may be an anode electrode, and the other electrode may be a cathode electrode. In an embodiment of the present disclosure, the first electrode EL1 may be an anode electrode, and the second electrode EL2 may be a cathode electrode.

[0203] In an embodiment of the present disclosure, the first connection line CNL1 may be disposed and / or formed on a layer different from that of the first electrode EL1, the second electrode EL2, and the second connection line CNL2. In other words, the first connection line CNL1 may be formed by a process different from that of the first electrode EL1, the second electrode EL2, and the second connection line CNL2.

[0204] In an embodiment of the present disclosure, the first connection line CNL1 may be disposed and / or formed on the insulating pattern INSP and electrically insulated from the second electrode EL2. Specifically, the 1-2 connection line CNL1_2 of the first connection line CNL1 may be disposed and / or formed on the insulating pattern INSP and electrically insulated from the second electrode EL2. The 1-2 connection line CNL1_2 may partially overlap with the second electrode EL2, with the insulating pattern INSP interposed therebetween. In detail, the 1-2 connection line CNL1_2 may overlap with the bridge pattern BRP of each of the second electrodes EL2, with the insulating pattern INSP interposed therebetween.

[0205] The insulating pattern INSP may be disposed between the bridge pattern BRP of each of the second electrodes EL2 and the 1-2 connection line CNL1_2, and overlap the bridge pattern BRP and each of the 1-2 connection lines CNL1_2. The insulating pattern INSP may cover the bridge pattern BRP of each of the second electrodes EL2, and thus prevent the 1-2 connection line CNL1_2 and the bridge pattern BRP from being electrically connected to each other. Therefore, each of the first electrodes EL1 connected to the 1-2 connection line CNL1_2 may be separated from each of the second electrodes EL2 without being electrically connected thereto.

[0206] In an embodiment of the present disclosure, the insulating pattern INSP may have a width W wider (or larger) than the lateral width of the 1-2nd connection line CNL1_2. Here, the lateral width of the 1-2nd connection line CNL1_2 may refer to the width of the 1-2nd connection line CNL1_2 extending in the first direction DR1 in a plan view and a cross-sectional view. In a plan view, the insulating pattern INSP may have a rectangular shape corresponding to the shape of the bridge pattern BRP of each of the second electrodes EL2, but the present disclosure is not limited thereto. In an embodiment, the shape of the insulating pattern INSP may be changed in various ways within a range in which its width W is wider (or larger) than the lateral width of the 1-2nd connection line CNL1_2 and sufficiently covers the bridge pattern BRP of each of the second electrodes EL2.

[0207] In an embodiment of the present disclosure, the insulating pattern INSP may be an inorganic insulating layer including an inorganic material. For example, the inorganic insulating layer may include silicon oxide (SiO x ) and silicon nitride (SiN x ) at least one of.

[0208] Each of the light emitting elements LD may be formed of a light emitting diode made of a material having an inorganic crystal structure and having an ultra-small size corresponding to, for example, a nanometer or micrometer level. The light emitting element LD may be aligned between the first electrode EL1 and the second electrode EL2 in each of the first to third pixels PXL1 to PXL3.

[0209] Although at least two or tens of light emitting elements LD are aligned in the emission area EMA of each of the first to third pixels PXL1 to PXL3, the present disclosure is not limited thereto. In an embodiment, the number of light emitting elements LD disposed in each of the first to third pixels PXL1 to PXL3 may be changed in various ways.

[0210] Each of the light emitting elements LD may include a cylindrical light emitting element manufactured by an etching method or a core-shell light emitting element manufactured by a growth scheme.

[0211] In the case where each of the light emitting elements LD is a cylindrical light emitting element, each of the light emitting elements LD may include an emission stack (or stacking pattern) formed by sequentially stacking a first conductive semiconductor layer 11, an active layer 12, a second conductive semiconductor layer 13, and an electrode layer 15 in a longitudinal direction of each of the light emitting elements LD. In the case where each of the light emitting elements LD is a core-shell light emitting element, each of the light emitting elements LD may include an emission pattern 10 having a first conductive semiconductor layer 11 disposed in a central portion, an active layer 12 surrounding at least one side of the first conductive semiconductor layer 11, a second conductive semiconductor layer 13 surrounding at least one side of the active layer 12, and an electrode layer 15 surrounding at least one side of the second conductive semiconductor layer 13.

[0212] Each of the light emitting elements LD may include a first end EP1 and a second end EP2. Any one of the first conductive semiconductor layer 11 and the second conductive semiconductor layer 13 may be disposed at the first end EP1 of each of the light emitting elements LD, and the other of the first conductive semiconductor layer 11 and the second conductive semiconductor layer 13 may be disposed at the second end EP2 thereof. Each of the light emitting elements LD may emit colored light or white light.

[0213] The light emitting element LD may be aligned between at least one of the first electrode EL1 and the second electrode EL2 by an electric field formed between the first electrode EL1 and the second electrode EL2 in the emission area EMA of each of the first to third pixels PXL1 to PXL3 .

[0214] In detail, after an electric field has been formed between the first electrode EL1 and the second electrode EL2 in the emission area EMA of each of the first pixel PXL1 to the third pixel PXL3, the light emitting element LD can be input into the emission area EMA by spraying and / or applying a fluid solvent mixed with the light emitting element LD by an inkjet printing method or the like.

[0215] In the case where the light emitting element LD is input into the emission area EMA of each of the first pixel PXL1 to the third pixel PXL3, the self-alignment of the light emitting element LD may be caused by the electric field formed between each of the first electrode EL1 and each of the second electrode EL2. Therefore, the light emitting element LD may be aligned between at least one of the first electrode EL1 and at least one of the second electrode EL2. In other words, the light emitting element LD may be aligned in different directions in the target area (e.g., in the emission area EMA of each of the first pixel PXL1 to the third pixel PXL3).

[0216] As described above, if each of the first electrode EL1 and the second electrode EL2 has a rhombus shape, and the first electrode EL1 and the second electrode EL2 are alternately arranged in the second direction DR2, one of the first electrodes EL1 may be arranged between two second electrodes EL2 adjacent to each other in the second direction DR2. Therefore, one first electrode EL1 may be surrounded by the first sub-electrode EL2_1 and the second sub-electrode EL2_2 included in each of the two second electrodes EL2. In other words, one first electrode EL1 may be surrounded by four sub-electrodes. In this case, the light emitting element LD may be aligned in four directions around one first electrode EL1.

[0217] The first capping layer CPL1 may be disposed and / or formed on each of the first electrodes EL1. The first capping layer CPL1 may prevent the first electrode EL1 from being damaged due to defects or the like caused in the process of manufacturing the display device, and may further enhance the adhesion between each of the first electrodes EL1 and the passivation layer PSV. The first capping layer CPL1 may be formed of a transparent conductive material such as indium zinc oxide (IZO) to minimize the loss of light emitted from each of the light emitting elements LD and reflected by the first electrode EL1 in the image display direction of the display device.

[0218] The first capping layer CPL1 and the first electrode EL1 disposed thereunder may have the same shape. For example, in the case where each of the first electrodes EL1 has a rhombus shape, the first capping layer CPL1 may also have a rhombus shape. However, the present disclosure is not limited thereto. In an embodiment, the first capping layer CPL1 and the first electrode EL1 may have different shapes. The first capping layer CPL1 may have a wider (or larger) surface area (or size) than each of the first electrodes EL1 to fully cover each of the first electrodes EL1 disposed thereunder.

[0219] The second capping layer CPL2 may be disposed and / or formed on the second electrode EL2 and the second connection line CNL2. The second capping layer CPL2 may prevent the second electrode EL2 and the second connection line CNL2 from being damaged due to defects or the like caused in a process of manufacturing the display device, and may further enhance adhesion between the passivation layer PSV and each of the second electrode EL2 and the second connection line CNL2.

[0220] As described above, since each of the second electrodes EL2 includes the intermediate electrode CTE, the first sub-electrode EL2_1 and the second sub-electrode EL2_2, and the bridge pattern BRP, the second capping layer CPL2 may have a surface area (or size) wider (or larger) than the surface area (or size) of each of the second electrodes EL2 to cover all of the intermediate electrode CTE, the first sub-electrode EL2_1 and the second sub-electrode EL2_2, and the bridge pattern BRP of each of the second electrodes EL2. In addition, the second capping layer CPL2 may have a surface area (or size) wider (or larger) than the surface area (or size) of each of the 2-1 connection line CNL2_1 and the 2-2 connection line CNL2_2 of the second connection line CNL2 to cover the 2-1 connection line CNL2_1 and the 2-2 connection line CNL2_2.

[0221] In an embodiment of the present disclosure, the second capping layer CPL2 may be disposed on the same layer as that of the first capping layer CPL1 and may be formed of the same material as that of the first capping layer CPL1. In other words, the second capping layer CPL2 may be disposed by the same process as that of the first capping layer CPL1. In an embodiment of the present disclosure, the first capping layer CPL1 and the second capping layer CPL2 may be disposed at positions spaced apart from each other on the same plane. Therefore, the first capping layer CPL1 and the second capping layer CPL2 may be electrically and / or physically separated from each other.

[0222] The third capping layer CPL3 may be disposed and / or formed on the first connection line CNL1. The third capping layer CPL3 may prevent the first connection line CNL1 from being damaged due to defects caused in a process of manufacturing the display device, etc., and may further enhance adhesion between each of the first connection lines CNL1 and the passivation layer PSV.

[0223] In an embodiment of the present disclosure, the third capping layer CPL3 may have a shape corresponding to that of the first connection wire CNL1, and have a surface area (or size) wider (or larger) than that of each of the 1-1 connection wire CNL1_1 and the 1-2 connection wire CNL1_2 of the first connection wire CNL1 to cover the 1-1 connection wire CNL1_1 and the 1-2 connection wire CNL1_2. The third capping layer CPL3 may be formed of a transparent conductive material such as indium zinc oxide (IZO) to minimize the loss of light emitted from the light emitting element LD in the same manner as the first capping layer CPL1 and the second capping layer CPL2.

[0224] In an embodiment of the present disclosure, the third capping layer CPL3 and the first capping layer CPL1 and the second capping layer CPL2 may be disposed and / or formed on different layers. Therefore, the third capping layer CPL3 may be electrically and / or physically separated from each of the first capping layer CPL1 and the second capping layer CPL2.

[0225] The light emitting element LD may be aligned between at least one of the first electrodes EL1 and at least one of the second electrodes EL2 in the emission area EMA of each of the first pixel PXL1 to the third pixel PXL3. Specifically, any one of the opposite ends EP1 and EP2 of the light emitting element LD may be electrically connected to at least one first electrode EL1, and the other of the opposite ends EP1 and EP2 of the light emitting element LD may be electrically connected to at least one second electrode EL2. Therefore, the signal (or voltage) of the first transistor T1 (T) of the pixel circuit layer PCL of each of the first pixel PXL1 to the third pixel PXL3 may be applied to any one of the opposite ends EP1 and EP2 of the light emitting element LD via at least one first electrode EL1. The voltage of the second driving power supply VSS of the driving voltage line DVL may be applied to the other of the opposite ends EP1 and EP2 of the light emitting element LD via at least one second electrode EL2.

[0226] The light emitting element LD may form an effective light source for each of the first to third pixels PXL1 to PXL3. For example, if a driving current flows through each of the first to third pixels PXL1 to PXL3 during each frame period, the light emitting element LD electrically connected to the first and second electrodes EL1 and EL2 of the corresponding pixel PXL may emit light having a brightness corresponding to the driving current.

[0227] The above-mentioned light emitting element LD may be aligned on the first insulating layer INS1 in the emission area EMA of each of the first to third pixels PXL1 to PXL3 .

[0228] The first insulating layer INS1 may be formed and / or disposed under each of the light emitting elements LD, which are aligned between at least one of the first electrodes EL1 and at least one of the second electrodes EL2 in the emission area EMA of each of the first to third pixels PXL1 to PXL3. The first insulating layer INS1 may be filled into a space between the passivation layer PSV and each of the light emitting elements LD to stably support the light emitting element LD and prevent the light emitting element LD from being removed from the passivation layer PSV.

[0229] In the emission area EMA of each of the first to third pixels PXL1 to PXL3, the first insulating layer INS1 may expose a predetermined area of ​​each of the first electrodes EL1 and cover a remaining area except the exposed predetermined area to protect the remaining area of ​​each of the first electrodes EL1. In addition, the first insulating layer INS1 may expose a predetermined area of ​​the second electrode EL2 and cover a remaining area except the exposed predetermined area to protect the remaining area of ​​the second electrode EL2. In addition, the first insulating layer INS1 may be formed in a peripheral area of ​​each of the first to third pixels PXL1 to PXL3 and / or disposed on the passivation layer PSV to protect components disposed in the peripheral area.

[0230] The first insulating layer INS1 may be formed of an inorganic insulating layer including an inorganic material or an organic insulating layer including an organic material. Although in an embodiment of the present disclosure, the first insulating layer INS1 may be formed of an inorganic insulating layer having an advantage in protecting the light emitting element LD from the pixel circuit layer PCL of each of the first to third pixels PXL1 to PXL3, the present disclosure is not limited thereto. In an embodiment, the first insulating layer INS1 may be formed of an organic insulating layer having an advantage in flattening the support surface of the light emitting element LD.

[0231] As shown in the aforementioned embodiment, in the case where the first capping layer CPL1 is disposed on each of the first electrodes EL1 and the second capping layer CPL2 is disposed on each of the second electrodes EL2, the first insulating layer INS1 may expose a predetermined area of ​​each of the first capping layer CPL1 and the second capping layer CPL2 and cover a remaining area except the exposed predetermined area to protect the remaining area of ​​each of the first capping layer CPL1 and the second capping layer CPL2. In addition, the first insulating layer INS1 may cover the first connection line CNL1 and the second connection line CNL2 in the peripheral area of ​​each of the first to third pixels PXL1 to PXL3 to protect the first connection line CNL1 and the second connection line CNL2.

[0232] The second insulating layer INS2 may be disposed and / or formed on the light emitting element LD. The second insulating layer INS2 may be disposed and / or formed on each of the light emitting elements LD to cover a portion of the upper surface of each of the light emitting elements LD and expose the opposite ends EP1 and EP2 of each of the light emitting elements LD to the outside. The second insulating layer INS2 may be formed in an independent pattern in the emission area EMA of each of the first to third pixels PXL1 to PXL3, but the present disclosure is not limited thereto.

[0233] The second insulating layer INS2 may be formed of a single layer or a multilayer, and include an inorganic insulating layer including at least one inorganic material or an organic insulating layer including at least one organic material. The second insulating layer INS2 may fix each of the light emitting elements LD aligned in the emission area EMA of each of the first pixel PXL1 to the third pixel PXL3 in place. In an embodiment of the present disclosure, the second insulating layer INS2 may include an inorganic insulating layer having advantages in protecting the active layer 12 of each of the light emitting elements LD from external oxygen, water, and the like. However, the present disclosure is not limited thereto. Depending on the design conditions of the display device to which the light emitting element LD is applied, the second insulating layer INS2 may be formed of an organic insulating layer including an organic material.

[0234] In an embodiment of the present disclosure, after the alignment of the light emitting element LD in the emission area EMA of each of the first pixel PXL1 to the third pixel PXL3 has been completed, the second insulating layer INS2 is formed on the light emitting element LD, so that the light emitting element LD can be prevented from being removed from the aligned position. If there is a space between the first insulating layer INS1 and the light emitting element LD before the second insulating layer INS2 is formed, the space can be filled with the second insulating layer INS2 during the process of forming the second insulating layer INS2. Therefore, the light emitting element LD can be stably supported. Therefore, the second insulating layer INS2 can be formed of an organic insulating layer that has an advantage in filling the space between the first insulating layer INS1 and the light emitting element LD with the second insulating layer INS2.

[0235] In an embodiment of the present disclosure, a second insulating layer INS2 may be formed on each of the light emitting elements LD, thereby preventing the active layer 12 of each of the light emitting elements LD from contacting an external conductive material. The second insulating layer INS2 may cover only a portion of the surface of each of the light emitting elements LD, so that the opposite ends EP1 and EP2 of each of the light emitting elements LD may be exposed to the outside.

[0236] The first contact electrode CNE1 may be disposed and / or formed on the first electrode EL1 of each of the first to third pixels PXL1 to PXL3 to reliably electrically and / or physically connect the first electrode EL1 to one of the opposite ends EP1 and EP2 of each of the light emitting elements LD. The second contact electrode CNE2 may be disposed and / or formed on the second electrode EL2 of each of the first to third pixels PXL1 to PXL3 to reliably electrically and / or physically connect the second electrode EL2 to the other of the opposite ends EP1 and EP2 of each of the light emitting elements LD.

[0237] In an embodiment, each of the first contact electrode CNE1 and the second contact electrode CNE2 may be formed of various transparent conductive materials. For example, each of the first contact electrode CNE1 and the second contact electrode CNE2 may be formed of a transparent conductive material for minimizing the loss of light emitted from each of the light emitting elements LD and reflected by the corresponding electrode in the forward direction of the display device. The transparent conductive material may include at least one of various conductive materials such as ITO, IZO, and ITZO, and may be substantially transparent or translucent to satisfy a predetermined transmittance. The materials of the first contact electrode CNE1 and the second contact electrode CNE2 are not limited to the above materials.

[0238] Each of the first contact electrode CNE1 and the second contact electrode CNE2 may have a rod shape extending in the second direction DR2. The first contact electrode CNE1 may partially overlap one of the opposite ends EP1 and EP2 of each of the light emitting elements LD. The second contact electrode CNE2 may partially overlap the other of the opposite ends EP1 and EP2 of each of the light emitting elements LD.

[0239] In an embodiment of the present disclosure, the first contact electrode CNE1 and the second contact electrode CNE2 may be disposed on respective different layers. In this case, the first contact electrode CNE1 may be disposed and / or formed on the second insulating layer INS2 and covered by the third insulating layer INS3. In addition, the second contact electrode CNE2 may be disposed and / or formed on the third insulating layer INS3 and covered by the fourth insulating layer INS4. The third insulating layer INS3 and the fourth insulating layer INS4 may be formed of any one of an inorganic insulating layer including an inorganic material or an organic insulating layer including an organic material. An overcoat layer OC may be disposed and / or formed on the fourth insulating layer INS4.

[0240] In an embodiment of the present disclosure, the first contact electrode CNE1 may be disposed and / or formed not only on the first electrode EL1 but also on the 1-2 connection line CNL1_2 and thus be electrically connected to the 1-2 connection line CNL1_2. In a plan view, the first contact electrode CNE1 may overlap the bridge pattern BRP and the insulating pattern INSP of each of the first electrode EL1, the 1-2 connection line CNL1_2, and each of the second electrode EL2.

[0241] In the first portion A of the 1-2 connection line CNL1_2, the first insulating layer INS1 may be disposed under the first contact electrode CNE1, the third capping layer CPL3 may be disposed under the first insulating layer INS1, the 1-2 connection line CNL1_2 may be disposed under the third capping layer CPL3, the insulating pattern INSP may be disposed under the 1-2 connection line CNL1_2, the second capping layer CPL2 may be disposed under the insulating pattern INSP, and the bridge pattern BRP of each of the second electrodes EL2 may be disposed under the second capping layer CPL2. In the first portion A of the 1-2 connection line CNL1_2, the first contact electrode CNE1 may be electrically separated from the third capping layer CPL3 and the 1-2 connection line CNL1_2. In addition, in the first portion A of the 1-2 connection line CNL1_2, the first contact electrode CNE1 may be electrically separated from the second capping layer CPL2 and the bridge pattern BRP of each of the second electrodes EL2 by the insulating pattern INSP.

[0242] In the second portion B of the 1-2 connection line CNL1_2, the third capping layer CPL3 may be disposed under the first contact electrode CNE1, the 1-2 connection line CNL1_2 may be disposed under the third capping layer CPL3, the first capping layer CPL1 may be disposed under the 1-2 connection line CNL1_2, the first electrodes EL1 may each be disposed under the first capping layer CPL1, and the first partition wall PW1 may be disposed under each of the first electrodes EL1. Therefore, in the second portion B of the 1-2 connection line CNL1_2, the first contact electrode CNE1, the third capping layer CPL3, the first capping layer CPL1, the 1-2 connection line CNL1_2, and the first electrode EL1 may be electrically and / or physically connected to each other.

[0243] In an embodiment of the present disclosure, the second contact electrode CNE2 may include a 2-1st contact electrode CNE2_1 and a 2-2nd contact electrode CNE2_2.

[0244] The 2-1st contact electrode CNE2_1 may be disposed and / or formed on the first sub-electrode EL2_1 of each of the second electrodes EL2 and thus electrically connected to the first sub-electrode EL2_1. The 2-2nd contact electrode CNE2_2 may be disposed and / or formed on the second sub-electrode EL2_2 of each of the second electrodes EL2 and thus electrically connected to the second sub-electrode EL2_2.

[0245] In a plan view, the 2-1st contact electrode CNE2_1 may overlap the first sub-electrode EL2_1 of each of the second electrodes EL2 and any one of the opposite ends EP1 and EP2 of each of the light emitting elements LD. The 2-1st contact electrode CNE2_1 may electrically connect the first sub-electrode EL2_1 of each of the second electrodes EL2 and any one of the opposite ends EP1 and EP2 of each of the light emitting elements LD.

[0246] In a plan view, the 2-2nd contact electrode CNE2_2 may overlap the second sub-electrode EL2_2 of each of the second electrodes EL2 and any one of the opposite ends EP1 and EP2 of each of the light emitting elements LD. The 2-2nd contact electrode CNE2_2 may electrically connect the second sub-electrode EL2_2 of each of the second electrodes EL2 and any one of the opposite ends EP1 and EP2 of each of the light emitting elements LD.

[0247] Although in the foregoing embodiments, the first contact electrode CNE1 and the second contact electrode CNE2 are shown to be disposed and / or formed on respective different layers, the present disclosure is not limited thereto. Figure 8As shown in , the first contact electrode CNE1 and the second contact electrode CNE2 may be disposed and / or formed on the same layer. In this case, the first contact electrode CNE1 and the second contact electrode CNE2 may be spaced apart from each other by a predetermined distance on the second insulating layer INS2 and thus electrically separated from each other, and may be covered by the third insulating layer INS3. The overcoat layer OC may be disposed and / or formed on the third insulating layer INS3. Here, in the case where the first contact electrode CNE1 and the second contact electrode CNE2 are disposed and / or formed on the same layer, the third insulating layer INS3 may correspond to the fourth insulating layer INS4.

[0248] The overcoat layer OC may be an encapsulation layer configured to mitigate a step difference formed by the partition wall PW, the first and second contact electrodes CNE1 and CNE2, and the first and second electrodes EL1 and EL2 disposed under the overcoat layer OC, and prevent oxygen or water from penetrating the light emitting element LD. In an embodiment, the overcoat layer OC may be omitted in consideration of design conditions of a display device, etc.

[0249] As described above, a predetermined voltage is applied to the opposite ends EP1 and EP2 of each of the light emitting elements LD through the first electrode EL1 and the second electrode EL2, so that each of the light emitting elements LD can emit light by recombination of electron-hole pairs in the active layer 12 of each light emitting element LD. Each of the light emitting elements LD can emit light having a wavelength band ranging from 400 nm to 900 nm, for example.

[0250] In an embodiment of the present disclosure, the first electrode EL1 and the second electrode EL2 disposed in the emission area EMA of each of the first pixel PXL1 to the third pixel PXL3 may be alternately disposed in the second direction DR2, rather than being disposed in the same row. In this case, one of the first electrodes EL1 may be disposed between two second electrodes EL2 adjacent to each other in the second direction DR2. In other words, one first electrode EL1 may be surrounded by four sub-electrodes in the diagonal direction of the one first electrode EL1.

[0251] Here, in the case where one first electrode EL1 and four sub-electrodes surrounding the first electrode EL1 have a rhombus shape, one sub-electrode may correspond to one of the four sides of the one first electrode EL1. For example, based on the first electrode EL1 (hereinafter, referred to as "1-3 electrode") disposed in the third row in the emission area EMA of the first pixel PXL1, the first sub-electrode EL2_1 of the second electrode EL2 (hereinafter, referred to as "2-1 electrode") disposed at the upper side of the 1-3 electrode EL1 may correspond to the first side S1 of the 1-3 electrode EL1, and the second sub-electrode EL2_2 of the 2-1 electrode EL2 may correspond to the second side S2 of the 1-3 electrode EL1. In addition, the first sub-electrode EL2_1 of the second electrode EL2 (hereinafter, referred to as "2-2 electrode") disposed at the lower side of the 1-3 electrode EL1 may correspond to the third side S3 of the 1-3 electrode EL1, and the second sub-electrode EL2_2 of the 2-2 electrode EL2 may correspond to the fourth side S4 of the 1-3 electrode EL1.

[0252] If the 1-3 electrode EL1, the 2-1 electrode EL2, and the 2-2 electrode EL2 are provided with corresponding alignment voltages to align the light emitting element LD, electric fields may be formed between the 1-3 electrode EL1 and the 2-1 electrode EL2 and between the 1-3 electrode EL1 and the 2-2 electrode EL2, respectively. The direction of the electric field formed between the first side S1 of the 1-3 electrode EL1 and the first sub-electrode EL2_1 of the 2-1 electrode EL2 may be different from the direction of the electric field formed between the second side S2 of the 1-3 electrode EL1 and the second sub-electrode EL2_2 of the 2-1 electrode EL2. In addition, the direction of the electric field formed between the third side S3 of the 1-3 electrode EL1 and the first sub-electrode EL2_1 of the 2-2 electrode EL2 may be different from the direction of the electric field formed between the fourth side S4 of the 1-3 electrode EL1 and the second sub-electrode EL2_2 of the 2-2 electrode EL2. Here, in order to align the light emitting element LD, the light emitting element LD is put into the emission area EMA of the first pixel PXL1, and the light emitting element LD can be aligned in various directions according to the directions of the electric fields formed between the 1-3 electrode EL1 and the 2-1 electrode EL2 and between the 1-3 electrode EL1 and the 2-2 electrode EL2, respectively.

[0253] Therefore, in the case where each of the first electrodes EL1 and each of the second electrodes EL2 are alternately arranged in the second direction DR2 in the emission area EMA of each of the first pixel PXL1 to the third pixel PXL3 and each of the first electrode EL1 and the second electrode EL2 has a rhombus shape, the light emitting element LD aligned in the emission area EMA of the corresponding pixel PXL can be prevented from being biased in a specific direction (for example, in the first direction DR1 and / or the second direction DR2). Therefore, the light emitted from each of the light emitting elements LD can be prevented from being concentrated in a specific direction. Therefore, the display device in the embodiment of the present disclosure can have a uniform light output distribution over its entire area.

[0254] If each of the first electrode EL1 and the second electrode EL2 has a rod shape extending in the second direction DR2 in the same manner as a conventional display device, an electric field having a predetermined orientation is formed between the first electrode EL1 and the second electrode EL2 when an alignment voltage is applied to the first electrode EL1 and the second electrode EL2, respectively. In this case, the light emitting element LD is aligned in the same direction (e.g., the first direction DR1) in the emission area EMA of each of the first pixel PXL1 to the third pixel PXL3, and the light emitted from each of the light emitting elements LD can travel intensively in the first direction DR1. In other words, the light emitted from each of the light emitting elements LD can be concentrated according to the alignment direction of the light emitting element LD. In the case where the light is concentrated in a specific direction in the emission area EMA of each of the first pixel PXL1 to the third pixel PXL3, the light output distribution can vary with the area of ​​the display device, resulting in image quality defects.

[0255] Accordingly, in the display device according to an embodiment of the present disclosure, the first electrode EL1 and the second electrode EL2 can be alternately arranged in the second direction DR2 in the emission area EMA of each of the first pixel PXL1 to the third pixel PXL3, instead of being arranged in the same direction, so that the light emitting element LD is aligned in different directions to prevent the light emitted from each of the light emitting elements LD from being concentrated in a specific direction.

[0256] Figures 11a to 11i It is shown in sequence that the manufacturing Figure 4 A schematic plan view of the first pixel method shown in FIG. Figures 12a to 12n It is shown in sequence that the manufacturing Figure 6 A schematic cross-sectional view of a first pixel method is shown in FIG.

[0257] refer to Figures 1a to 1f , Figure 2 , Figure 3a , Figure 4 , Figure 6 and Fig.12a , a pixel circuit layer PCL of the first pixel PXL1 is formed on the substrate SUB. The first pixel PXL1 may include an emission area EMA and a peripheral area disposed around the emission area EMA.

[0258] The pixel circuit layer PCL may include a first transistor T1(T), a second transistor T2(T), a driving voltage line DVL, and a passivation layer PSV. The passivation layer PSV may include a first contact hole CH1 exposing the second terminal DE of the first transistor T1(T) and a second contact hole CH2 exposing a portion of the driving voltage line DVL.

[0259] refer to Figures 1a to 1f , Figure 2 , Figure 3a , Figure 4 , Figure 6 , Fig.11a , Fig.12a and Figure 12b , a first partition wall PW1 and a second partition wall PW2 are formed on the passivation layer PSV in the emission area EMA of the first pixel PXL1. The first partition wall PW1 and the second partition wall PW2 may be spaced apart from each other by a predetermined distance on the passivation layer PSV. The first partition wall PW1 and the second partition wall PW2 may be formed of an inorganic insulating layer including an inorganic material or an organic insulating layer including an organic material.

[0260] refer to Figures 1a to 1f , Figure 2 , Figure 3a , Figure 4 , Figure 6 , Fig.11b , Fig.11c and Figures 12a to 12c , a first electrode EL1 , a second electrode EL2 , and a second connection line CNL2 are formed on the passivation layer PSV including the first partition wall PW1 and the second partition wall PW2 .

[0261] Each of the first electrodes EL1 may be spaced apart from adjacent first electrodes EL1 in the second direction DR2 by a predetermined distance. In addition, each of the first electrodes EL1 may be spaced apart from the second connection line CNL2 and each of the second electrodes EL2 by a predetermined distance. In an embodiment of the present disclosure, one of the first electrodes EL1 may be disposed between two adjacent second electrodes EL2 in the second direction DR2.

[0262] In a plan view, the first and second sub-electrodes EL2_1 and EL2_2 of each of the first and second electrodes EL1 and EL2 may have a rhombus shape. Thus, the first and second sub-electrodes EL2_1 and EL2_2 of each of the first and second electrodes EL1 and EL2 may have four sides.

[0263] The second connection lines CNL2 may include a 2-1th connection line CNL2_1 extending in the first direction DR1 and a 2-2nd connection line CNL2_2 extending in the second direction DR2 crossing the first direction DR1 .

[0264] Each of the second electrodes EL2 may include an intermediate electrode CTE electrically connected to the 2-2 th connection line CNL2_2, a first sub-electrode EL2_1 electrically connected to the intermediate electrode CTE, a bridge pattern BRP electrically connected to the first sub-electrode EL2_1, and a second sub-electrode EL2_2 electrically connected to the bridge pattern BRP. The bridge pattern BRP of each of the second electrodes EL2 may be disposed between the first sub-electrode EL2_1 and the second sub-electrode EL2_2 of each of the second electrodes EL2.

[0265] The second partition wall PW2 may be disposed under each of the first sub-electrode EL2_1 and the second sub-electrode EL2_2. The first partition wall PW1 may be disposed under each of the first electrodes EL1. In a plan view, each of the first electrodes EL1 may overlap the first partition wall PW1. Each of the first sub-electrode EL2_1 and the second sub-electrode EL2_2 may overlap the second partition wall PW2.

[0266] Subsequently, a first capping layer CPL1 is formed on the first electrode EL1, and a second capping layer CPL2 is formed on each of the second electrode EL2 and the second connection line CNL2. In an embodiment of the present disclosure, the first capping layer CPL1 and the second capping layer CPL2 may include the same material and be formed by the same process.

[0267] The first capping layer CPL1 may cover each of the first electrodes EL1 and overlap each of the first electrodes EL1 in a plan view. The second capping layer CPL2 may cover all of the second electrodes EL2 and the second connection lines CNL2 and overlap each of the second electrodes EL2 and the second connection lines CNL2 in a plan view.

[0268] refer to Figures 1a to 1f , Figure 2 , Figure 3a , Figure 4 , Figure 6 , Fig.11d and Figures 12a to 12d, after applying an insulating material layer (not shown) to the passivation layer PSV on which the first capping layer CPL1 and the second capping layer CPL2 are formed, the insulating material layer is patterned by a mask process to form a bridge pattern BRP covering only each of the second electrodes EL2 and an insulating pattern INSP of the second capping layer CPL2 disposed on the bridge pattern BRP.

[0269] The insulating pattern INSP may be an inorganic insulating layer including an inorganic material.

[0270] refer to Figures 1a to 1f , Figure 2 , Figure 3a , Figure 4 , Figure 6 , Fig.11e and Figures 12a to 12e The first connection lines CNL1 are formed on the passivation layer PSV on which the insulating pattern INSP is formed. The first connection lines CNL1 may include a 1-1th connection line CNL1_1 extending in the first direction DR1 and a 1-2th connection line CNL1_2 extending in the second direction DR2.

[0271] The 1-2nd connection line CNL1_2 may extend in the second direction DR2 and cover the first electrode EL1 disposed in the same column therewith, and may be electrically connected to each of the first electrodes EL1. In detail, the 1-2nd connection line CNL1_2 may be disposed and / or formed on the bridge pattern BRP of each of the second electrodes EL2, with the insulating pattern INSP interposed therebetween. The bridge pattern BRP of each of the second electrodes EL2 may be covered by the insulating pattern INSP and electrically separated from the 1-2nd connection line CNL1_2. In other words, the bridge pattern BRP of each of the second electrodes EL2 may be electrically insulated from the 1-2nd connection line CNL1_2 by the insulating pattern INSP.

[0272] The 1-2 th connection line CNL1_2 may be electrically connected to the second terminal DE of the first transistor T1 (T) through the first contact hole CH1 of the passivation layer PSV.

[0273] Subsequently, a third capping layer CPL3 is formed on the first connection line CNL1.

[0274] The third capping layer CPL3 may be formed of a transparent conductive material and formed directly on the first connection line CNL1 and electrically and / or physically connected to the first connection line CNL1. The third capping layer CPL3 and the first and second capping layers CPL1 and CPL2 may include the same material.

[0275] refer to Figures 1a to 1f , Figure 2 , Figure 3a , Figure 4 , Figure 6 and Figures 12a to 12f A first insulating material layer INSM1 is formed on the passivation layer PSV on which the third capping layer CPL3 is formed. The first insulating material layer INSM1 may be formed of an inorganic insulating layer including an inorganic material or an organic insulating layer including an organic material.

[0276] refer to Figures 1a to 1f , Figure 2 , Figure 3a , Figure 4 , Figure 6 , Fig.11f and Figures 12a to 12g , corresponding alignment voltages are applied to the first and second electrodes EL1 and EL2 through the first and second connection lines CNL1 and CNL2 , respectively, and an electric field is formed between each of the first electrodes EL1 and each of the second electrodes EL2 .

[0277] When DC power or AC power having a predetermined voltage and period is repeatedly applied to each of the first electrode EL1 and the second electrode EL2 several times through the first connection line CNL1 and the second connection line CNL2, an electric field can be formed between the first electrode EL1 and the second electrode EL2 by the potential difference between the first electrode EL1 and the second electrode EL2.

[0278] After an electric field is formed between the first electrode EL1 and the second electrode EL2 formed in the emission area EMA of the first pixel PXL1, the light emitting element LD is provided by an inkjet printing method or the like. For example, the light emitting element LD can be provided to the emission area EMA of the first pixel PXL1 by providing a nozzle above the passivation layer PSV and dripping a solvent including the light emitting element LD onto the passivation layer PSV through the nozzle. Here, the solvent may be any one of acetone, water, alcohol, and toluene, but the present disclosure is not limited thereto. For example, the solvent may include a material that can evaporate at room temperature or evaporate by heating. In addition, the solvent may have the form of ink or paste. The method of providing the light emitting element LD is not limited to the method of the aforementioned embodiment. The scheme of providing the light emitting element LD may be changed in various ways.

[0279] After providing the light emitting element LD to the emission area EMA of the first pixel PXL1 , the solvent may be removed.

[0280] In the case where the light emitting element LD is put into the emission area EMA of the first pixel PXL1, the self-alignment of the light emitting element LD can be caused by the electric field formed between the first electrode EL1 and the second electrode EL2. Therefore, the light emitting element LD can be aligned between at least one of the first electrodes EL1 and at least one of the second electrodes EL2. In other words, the light emitting element LD can be aligned in various directions in the target area (for example, the emission area EMA of the first pixel PXL1). Specifically, each of the light emitting elements LD can be aligned on the first insulating material layer INSM1 in the emission area EMA of the first pixel PXL1.

[0281] refer to Figures 1a to 1f , Figure 2 , Figure 3a , Figure 4 , Figure 6 , Figure 11g and Figure 12a to Figure 12h After the light emitting element LD is aligned in the emission area EMA of the first pixel PXL1, the 1-1th connection line CNL1_1 is divided into parts between the first pixel PXL1 and the pixel PXL adjacent to the first pixel PXL1, so that the first pixel PXL1 can be driven independently from the adjacent pixels PXL.

[0282] After the separation process of the 1-1th connection line CNL1_1, an insulating material layer (not shown) is applied to the first insulating material layer INSM1 and the light emitting element LD, and the insulating material layer is patterned by a mask process to form a second insulating material layer INSM2. The second insulating material layer INSM2 may be formed of an inorganic insulating layer including an inorganic material or an organic insulating layer including an organic material.

[0283] The second insulating material layer INSM2 may cover the first insulating material layer INSM1 disposed on each of the first sub-electrode EL2_1 and the second sub-electrode EL2_2 disposed on each of the second electrodes EL2. In addition, the second insulating material layer INSM2 may expose the first insulating material layer INSM1 disposed on each of the first electrodes EL1 and the first insulating material layer INSM1 disposed on the 1-1 connection wire CNL1_1. In addition, the second insulating material layer INSM2 may expose any one of the opposite ends EP1 and EP2 of each of the light emitting elements LD to the outside.

[0284] refer to Figures 1a to 1f , Figure 2 , Figure 3a , Figure 4 , Figure 6 and Figures 12a to 12i, after disposing a mask (not shown) over the second insulating material layer INSM2 , a first insulating material pattern INSM1 ′ is formed by patterning a portion of the first insulating material layer INSM1 exposed to the outside using the mask.

[0285] The first insulating material pattern INSM1' may expose at least one region of the first capping layer CPL1 disposed on each of the first electrodes EL1 to the outside and cover the remaining region except for the at least one region. In addition, the first insulating material pattern INSM1' may expose at least one region of the third capping layer CPL3 disposed on the first capping layer CPL1.

[0286] refer to Figures 1a to 1f , Figure 2 , Figure 3a , Figure 4 , Figure 6 , Fig.11h and Figures 12a to 12j , a first contact electrode CNE1 is formed on exposed portions of the first and third capping layers CPL1 and CPL3 and one of the opposite ends EP1 and EP2 of each light emitting element LD by a sputtering method or the like.

[0287] The first contact electrode CNE1 may be disposed on an exposed portion of the first capping layer CPL1 and electrically connected to each of the first electrodes EL1 disposed under the first capping layer CPL1. The first contact electrode CNE1 may be disposed on an exposed portion of the third capping layer CPL3 and electrically connected to each of the 1-2 connection wires CNL1_2 disposed under the third capping layer CPL3. In addition, the first contact electrode CNE1 may be electrically connected to one of the exposed opposite ends EP1 and EP2 of each of the light emitting elements LD.

[0288] refer to Figures 1a to 1f , Figure 2 , Figure 3a , Figure 4 , Figure 6 and Figures 12a to 12k , after disposing a mask (not shown) over the passivation layer PSV on which the first contact electrode CNE1 is formed, the second insulating layer INS2 is formed by patterning the second insulating material layer INSM2 using the mask.

[0289] The second insulating layer INS2 may cover at least a portion of the upper surface of each of the light emitting elements LD so that the other of the opposite ends EP1 and EP2 of each of the light emitting elements LD may be exposed to the outside.

[0290] Thereafter, after forming an insulating material layer (not shown) on the second insulating layer INS2, a mask (not shown) is disposed over the insulating material layer, and then the insulating material layer is patterned by a process using the mask to form a third insulating layer INS3. The third insulating layer INS3 may cover the first contact electrode CNE1 to protect the first contact electrode CNE1 from the outside, and may expose the first insulating material pattern INSM1' on the second electrode EL2 and the other of the opposite ends EP1 and EP2 of each of the light emitting elements LD to the outside.

[0291] refer to Figures 1a to 1f , Figure 2 , Figure 3a , Figure 4 , Figure 6 and Figures 12a to 12l , after disposing a mask (not shown) over the passivation layer PSV including the third insulating layer INS3 , the first insulating layer INS1 is formed by patterning the exposed portion of the first insulating material pattern INSM1 ′.

[0292] The first insulating layer INS1 may expose at least one region of the second capping layer CPL2 disposed on each of the second electrodes EL2 to the outside and cover the remaining region except the one region.

[0293] refer to Figures 1a to 1f , Figure 2 , Figure 3a , Figure 4 , Figure 6 , Fig.11i and Figure 12a to Figure 12m A second contact electrode CNE2 is formed on the other of the exposed opposite ends EP1 and EP2 of each of the light emitting elements LD and the second capping layer CPL2.

[0294] The second contact electrode CNE2 may include a 2-1st contact electrode CNE2_1 and a 2-2nd contact electrode CNE2_2. In a plan view, the 2-1st contact electrode CNE2_1 and the 2-2nd contact electrode CNE2_2 may be spaced apart from each other by a predetermined distance with the first contact electrode CNE1 interposed therebetween.

[0295] The second contact electrode CNE2 may be electrically connected to the first sub-electrode EL2_1 and the second sub-electrode EL2_2 of each of the second electrodes EL2 disposed under the second capping layer CPL2 through the second capping layer CPL2 .

[0296] refer to Figures 1a to 1f , Figure 2 , Figure 3a , Figure 4 , Figure 6 and Figures 12a to 12n, a fourth insulating layer INS4 is formed on the entire surface of the passivation layer PSV including the second contact electrode CNE2.

[0297] The fourth insulating layer INS4 may include an inorganic insulating layer made of an inorganic material or an organic insulating layer made of an organic material. Although the fourth insulating layer INS4 may have a single-layer structure as shown in the drawings, the present disclosure is not limited thereto. For example, the fourth insulating layer INS4 may have a multi-layer structure.

[0298] Subsequently, an overcoat layer OC is formed on the fourth insulating layer INS4.

[0299] Fig.13a and Fig.13b Shows Figure 5 1 and 2 are embodiments of a first pixel, and are plan views schematically showing the first pixel including only some components of a display element layer.

[0300] although Fig.13a and Fig.13b 1 shows a simplified structure of the first pixel PXL1, for example, only the first and second electrodes, the first and second connection lines, the light emitting element, and the insulating pattern included in the display element layer of the first pixel PXL1 are shown, but the present disclosure is not limited thereto.

[0301] In addition, Fig.13a and Fig.13b In the figure, for the sake of explanation, the illustration of the pixel circuit layer (including at least one transistor and a signal line electrically connected to the transistor) electrically connected to the light emitting element is omitted.

[0302] Fig.13a and Fig.13b The following description of the embodiment of will focus on the differences from the description of the previous embodiment to avoid repeated explanations. Fig.13a and Fig.13b Components that are not separately explained in the following description of the embodiment of the present invention correspond to the components of the aforementioned embodiment. The same reference numerals will be used to represent the same components, and similar reference numerals will be used to represent similar components.

[0303] refer to Figures 1a to 1f , Figure 2 , Fig.13a and Fig.13b , the first pixel PXL1 may include a first electrode EL1, a second electrode EL2, a plurality of light emitting elements LD, and a first connection line CNL1 and a second connection line CNL2. Fig.13a and Fig.13b , but the first pixel PXL1 may further include a first partition wall (refer to Figure 4PW1), a second partition wall (reference Figure 4 PW2), a first capping layer (reference Figure 4 CPL1), a second capping layer (reference Figure 4 CPL2), a third capping layer (reference Figure 4 CPL3), a first contact electrode (reference Figure 4 CNE1) and a second contact electrode (reference Figure 4 of CNE2).

[0304] The first electrode EL1 may be disposed in the emission area EMA of the first pixel PXL1 and disposed at a position spaced apart from the first electrode EL1 adjacent in the second direction DR2 (e.g., the “column direction”). In a plan view, each of the first electrodes EL1 may have a circular shape, but the shape of each of the first electrodes EL1 is not limited to that of the aforementioned embodiment. In an embodiment, as shown in FIG. Fig.13b As shown in , the first electrode EL1 may have a polygonal shape including a pentagonal shape. In addition, in an embodiment, each of the first electrodes EL1 may have an elliptical shape, a hexagonal shape, or the like.

[0305] The 1-2 connection line CNL1_2 of the first connection line CNL1 may be disposed and / or formed on the first electrode EL1 disposed in the second direction DR2. The 1-2 connection line CNL1_2 may extend in the second direction DR2 and thus electrically connect the first electrodes EL1 spaced apart from each other in the second direction DR2.

[0306] Each of the second electrodes EL2 may be disposed in the emission area EMA of the first pixel PXL1 and at a position spaced apart from the second electrode EL2 adjacent in the second direction DR2. Each of the second electrodes EL2 may include an intermediate electrode CTE electrically connected to the second connection line CNL2, a first sub-electrode EL2_1 electrically connected to the intermediate electrode CTE, a bridge pattern BRP electrically connected to the first sub-electrode EL2_1, and a second sub-electrode EL2_2 electrically connected to the bridge pattern BRP.

[0307] Each of the first sub-electrode EL2_1 and the second sub-electrode EL2_2 may be provided in various shapes. Fig.13a As shown in FIG. 1 , the first sub-electrode EL2_1 and the second sub-electrode EL2_2 may have a circular shape, or as shown in FIG. Fig.13bAs shown in , the first sub-electrode EL2_1 and the second sub-electrode EL2_2 may have a pentagonal shape. In addition, the first sub-electrode EL2_1 and the second sub-electrode EL2_2 may each have the same shape as the first electrode EL1, but the present disclosure is not limited thereto and may have a shape different from that of the first electrode EL1.

[0308] In an embodiment of the present disclosure, the insulation pattern INSP may be disposed on the bridge pattern BRP of each of the second electrodes EL2 .

[0309] In an embodiment of the present disclosure, since the 1-2 connection line CNL1_2 is disposed on the bridge pattern BRP of each of the second electrodes EL2 with the insulation pattern INSP interposed therebetween, the 1-2 connection line CNL1_2 and the bridge pattern BRP of each of the second electrodes EL2 may be electrically insulated from each other.

[0310] In an embodiment of the present disclosure, the first electrode EL1 and the second electrode EL2 may be alternately arranged in the second direction DR2, rather than being arranged in the same row. In this case, one of the first electrodes EL1 may be arranged between two second electrodes EL2 adjacent thereto in the second direction DR2, so that one first electrode EL1 may be surrounded by the first sub-electrode EL2_1 and the second sub-electrode EL2_2 of each of the two second electrodes EL2 in the diagonal direction. Here, if corresponding alignment voltages are provided to the first electrode EL1 and the second electrode EL2, respectively, an electric field may be formed in different directions between the first electrode EL1 and the second electrode EL2, so that the light emitting element LD may be aligned in different directions in the emission area EMA of the first pixel PXL1. Therefore, the light emitted from each of the light emitting elements LD may travel in different directions without being concentrated in a specific direction.

[0311] Fig.14 A display device according to an embodiment of the present disclosure is shown, and corresponds to Figure 4 Schematic plan view of a first pixel among first to third pixels. Fig.15 It is along Fig.14 Schematic cross-sectional view taken along line IV-IV'. Fig.16 It is along Fig.14 A schematic cross-sectional view taken along line V-V'.

[0312] Fig.14 The configuration of the first pixel shown in Figure 4 The configuration of the first pixel may differ at least in that the first connection line is integrally provided with the first electrode (integrated) and the first electrode and the second electrode are formed by different processes.

[0313] Therefore, to avoid redundant explanations, Figures 14 to 16 The description of the first pixel will focus on the differences from the description of the previous embodiment to avoid repeated description. Components that are not explained separately in the following description of this embodiment are consistent with the components of the previous embodiment. The same reference numerals will be used to represent the same components, and similar reference numerals will be used to represent similar components.

[0314] although Figures 14 to 16 The structure of the first pixel is simply illustrated, for example, in which it is illustrated that each electrode is formed of a single electrode layer and each insulating layer is formed of a single insulating layer, but the present disclosure is not limited thereto.

[0315] refer to Figures 1a to 1f , Figure 2 , Figure 3a , Figures 14 to 16 , the first pixel PXL1 may include a substrate SUB, a pixel circuit layer PCL disposed on the substrate SUB, and a display element layer DPL disposed on the pixel circuit layer PCL.

[0316] The pixel circuit layer PCL may include at least one transistor T, a driving voltage line DVL (see Figure 6 ) and a passivation layer PSV. Here, the transistor T may include a first transistor T1 (T) as a driving transistor and a second transistor T2 (T) as a switching transistor.

[0317] The display element layer DPL may include first and second partition walls PW1 and PW2, first and second electrodes EL1 and EL2, first and second connection lines CNL1 and CNL2, a plurality of light emitting elements LD, first and second contact electrodes CNE1 and CNE2, an insulating pattern INSP, and first and second capping layers CPL1 and CPL2.

[0318] The first connection line CNL1 may include a 1-1 connection line CNL1_1 extending in the first direction DR1 and a 1-2 connection line CNL1_2 extending in the second direction DR2. The 1-2 connection line CNL1_2 may be electrically connected to the second terminal DE of the first transistor T1 (T) of the pixel circuit layer PCL through a first contact hole CH1 passing through the passivation layer PSV.

[0319] In an embodiment of the present disclosure, the 1-2 connection line CNL1_2 may be integrated with the first electrode EL1. In the case where the 1-2 connection line CNL1_2 is integrated with the first electrode EL1, the 1-2 connection line CNL1_2 may be a predetermined region of the first electrode EL1, or the first electrode EL1 may be a predetermined region of the 1-2 connection line CNL1_2. In the case where the 1-2 connection line CNL1_2 and the first electrode EL1 are integrated, the 1-2 connection line CNL1_2 and the first electrode EL1 may form an electrode column extending in the second direction DR2 in the emission area EMA of the first pixel PXL1.

[0320] The first connection line CNL1 and the first electrode EL1 may include the same material and be formed through the same process. In other words, the first connection line CNL1 and the first electrode EL1 may be disposed on the same layer.

[0321] The first capping layer CPL1 may be disposed on each of the first connection line CNL1 and the first electrode EL1. The first capping layer CPL1 may be formed of a transparent conductive material and cover the first connection line CNL1 and the first electrode EL1. The first capping layer CPL1 may strengthen the adhesive force between the first connection line CNL1 and the passivation layer PSV, and also strengthen the adhesive force between the first electrode EL1 and the passivation layer PSV.

[0322] The insulating pattern INSP may be disposed on the first capping layer CPL1 on the 1-2 connection line CNL1_2 and overlap the first capping layer CPL1 and the 1-2 connection line CNL1_2. In an embodiment of the present disclosure, the insulating pattern INSP may overlap a region of the 1-2 connection line CNL1_2 without overlapping the first electrode EL1.

[0323] The second connection line CNL2 may include a 2-1 connection line CNL2_1 extending in the first direction DR1 and a 2-2 connection line CNL2_2 extending in the second direction DR2. The 2-2 connection line CNL2_2 may be integrated with the second electrode EL2. In the case where the 2-2 connection line CNL2_2 is integrated with the second electrode EL2, the 2-2 connection line CNL2_2 may be a predetermined region of the second electrode EL2, or the second electrode EL2 may be a predetermined region of the 2-2 connection line CNL2_2.

[0324] The second electrode EL2 and the second connection line CNL2 may be disposed on the pixel circuit layer PCL (including the insulating pattern INSP). In an embodiment of the present disclosure, the second electrode EL2 and the second connection line CNL2 may be formed by a process different from that of the first electrode EL1 and the first connection line CNL1. Therefore, the second electrode EL2 and the second connection line CNL2 may be disposed and / or formed on a layer different from that of the first electrode EL1 and the first connection line CNL1.

[0325] Each of the second electrodes EL2 may include an intermediate electrode CTE electrically connected to the 2-2 th connection line CNL2_2, a first sub-electrode EL2_1 electrically connected to the intermediate electrode CTE, a bridge pattern BRP electrically connected to the first sub-electrode EL2_1, and a second sub-electrode EL2_2 electrically connected to the bridge pattern BRP. In an embodiment of the present disclosure, the bridge pattern BRP of each of the second electrodes EL2 may be disposed on the insulating pattern INSP.

[0326] Since the bridge pattern BRP of each of the second electrodes EL2 is disposed on the 1-2 th connection line CNL1_2 with the insulation pattern INSP interposed therebetween, the bridge pattern BRP of each of the second electrodes EL2 and the 1-2 th connection line CNL1_2 may be electrically insulated from each other.

[0327] The second capping layer CPL2 may be disposed on the second electrode EL2 and the second connection line CNL2. The second capping layer CPL2 may be formed of a transparent conductive material and cover the second connection line CNL2 and the second electrode EL2. The second capping layer CPL2 may strengthen the adhesion between the second connection line CNL2 and the passivation layer PSV, and also strengthen the adhesion between the second electrode EL2 and the passivation layer PSV. In an embodiment of the present disclosure, the second capping layer CPL2 may be formed by a process different from that of the first capping layer CPL1. Therefore, the second capping layer CPL2 and the first capping layer CPL1 may be disposed and / or formed on respective different layers.

[0328] The second contact electrode CNE2 may be disposed on the second electrode EL2. The second contact electrode CNE2 may include a 2-1st contact electrode CNE2_1 and a 2-2nd contact electrode CNE2_2. In a plan view, the 2-1st contact electrode CNE2_1 may overlap with the first sub-electrode EL2_1 of each of the second electrodes EL2 and any one of the opposite ends EP1 and EP2 of each of the light emitting elements LD. In a plan view, the 2-2nd contact electrode CNE2_2 may overlap with the second sub-electrode EL2_2 of each of the second electrodes EL2 and any one of the opposite ends EP1 and EP2 of each of the light emitting elements LD.

[0329] A third insulating layer INS3 may be disposed and / or formed on the second contact electrode CNE2.

[0330] The first contact electrode CNE1 may be disposed on one electrode column formed by the first electrode EL1 and the 1-2 connection wire CNL1_2 being integrated with each other. In a plan view, the first contact electrode CNE1 may overlap the other of the opposite ends EP1 and EP2 of each of the first electrode EL1 and each of the light emitting elements LD.

[0331] The first contact electrode CNE1 and the second contact electrode CNE2 may be formed by different processes. For example, after a process of forming the third insulating layer INS3 on the second contact electrode CNE2, the first contact electrode CNE1 may be formed on the first electrode EL1 and the 1-2 connection line CNL1_2. Therefore, the first contact electrode CNE1 and the second contact electrode CNE2 may be disposed and / or formed on different layers.

[0332] Although in the foregoing embodiment, it is described that the first contact electrode CNE1 is formed after the process of forming the second contact electrode CNE2, the present disclosure is not limited thereto. In an embodiment, the second contact electrode CNE2 may be formed after the first contact electrode CNE1 is formed. In addition, in an embodiment, the first contact electrode CNE1 and the second contact electrode CNE2 may be formed by the same process.

[0333] In an embodiment of the present disclosure, the first electrode EL1 and the second electrode EL2 may be alternately arranged in the second direction DR2, rather than being arranged in the same row. In this case, one of the first electrodes EL1 may be arranged between two second electrodes EL2 adjacent thereto in the second direction DR2, so that one first electrode EL1 may be surrounded by the first sub-electrode EL2_1 and the second sub-electrode EL2_2 of each of the two second electrodes EL2 in a diagonal direction. Specifically, in the case where the first sub-electrode EL2_1 and the second sub-electrode EL2_2 of each of the first electrode EL1 and the second electrode EL2 have a rhombus shape, the light emitting element LD may be aligned in various directions in the emission area EMA of the first pixel PXL1, rather than being biased in a specific direction (e.g., the first direction DR1).

[0334] Therefore, it is possible to prevent light emitted from each of the light emitting elements LD from being concentrated in a specific direction.Therefore, the display device in the embodiment of the present disclosure can have a uniform light output distribution over its entire area.

[0335] While various embodiments have been described above, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the present disclosure.

[0336] Therefore, the embodiments disclosed in this specification are only for illustrative purposes, rather than limiting the technical scope of the present disclosure. The scope of the present invention to be protected should be defined by the appended claims.

Claims

1. Display equipment, including: A substrate including a display area and a non-display area; as well as at least one pixel disposed in the display area and comprising an emission area formed to emit light, wherein The pixels include: A first electrode, disposed on the substrate and arranged in a column direction; a second electrode spaced apart from the first electrode; a first connection line extending in the column direction and connecting each of the first electrodes to an adjacent first electrode; a light emitting element electrically connected to each of at least one of the first electrodes and at least one of the second electrodes; and an insulating pattern overlapping the first connecting line, and In a plan view, each of the first electrodes and each of the second electrodes are alternately arranged in the column direction in the emission region, Wherein, each of the second electrodes comprises: a bridge pattern extending in a row direction crossing the column direction and overlapping the insulation pattern; and At least two sub-electrodes are electrically connected to each other through the bridge pattern.

2. The display device according to claim 1, wherein: The bridge pattern and the sub-electrode are integrated with each other and form the at least one of the second electrodes.

3. The display device according to claim 2, wherein: The at least one of the first electrodes is disposed between two of the second electrodes adjacent thereto in the column direction.

4. The display device according to claim 1, wherein: The insulating pattern is disposed on the bridge pattern.

5. The display device according to claim 4, wherein: The first connection line and the first electrode are disposed on different layers.

6. The display device according to claim 5, wherein: The first connection line is disposed on the insulation pattern and is electrically disconnected from the bridge pattern.

7. The display device according to claim 6, wherein The first connection line includes a first portion overlapping the insulating pattern and a second portion excluding the first portion, and The second portion of the first connecting line is electrically connected to the first electrode.

8. The display device according to claim 5, wherein: The pixel also includes: A first capping layer, disposed on the first electrode; A second capping layer is disposed on the second electrode; and A third capping layer is arranged on the first connecting line.

9. The display device according to claim 8, wherein: The first capping layer and the second capping layer are disposed on the same layer, and the third capping layer is disposed on a different layer from the first capping layer and the second capping layer.

10. The display device according to claim 1, wherein The pixel further includes a second connection line electrically connected to the second electrode, and The second connecting line comprises: A 2-1st connecting line extending in the row direction; as well as A 2-2 connection line extending in the column direction, and The 2-2 connecting line is integrated with the second electrode.

11. The display device according to claim 10, wherein: The second connection line and the first connection line are arranged on different layers.

12. The display device according to claim 10, wherein: The pixel also includes: a partition wall disposed below each of the first electrode and the second electrode; a first contact electrode electrically connecting the at least one of the first electrodes to one of the opposite ends of the light emitting element; and A second contact electrode electrically connects the at least one of the second electrodes to the other of the opposite ends of the light emitting element.

13. The display device according to claim 12, wherein The pixel further includes an insulating layer disposed on an upper surface of the light emitting element, and The first contact electrode and the second contact electrode are spaced apart from each other on the insulating layer and are electrically disconnected from each other.

14. The display device according to claim 2, wherein: The first electrode and the first connection line are integrated with each other.

15. The display device according to claim 14, wherein: The insulating pattern is disposed on the first connection line, and the bridge pattern is disposed on the insulating pattern.

16. The display device according to claim 15, wherein: The first electrode and the second electrode are provided on different layers from each other.

17. The display device according to claim 14, wherein: The pixels include: a first capping layer disposed on each of the first electrode and the first connecting line; and a second capping layer, disposed on the second electrode, and Wherein, the first capping layer and the second capping layer are arranged on different layers from each other.

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