A power management architecture, chip and power management method

Abstract

The present invention discloses a power management architecture, a chip and a power management method. The architecture sends an enable signal through a first reset pin and a second reset pin to wake up a first power domain power module and a second power domain power module respectively, so that the power architecture can be recovered from a state where the first power domain power module and the second power domain power module are unable to supply power due to suspension of operation, thereby improving the functionality of the power architecture and making the power architecture stronger and more stable; the VDD1 power module and the VDD2 power module wake up each other through interactive operations, and the function is powerful; the low-power power domain and the high-power power domain are independent of each other, do not affect each other, and are more robust.

Description

Technical Field

[0001] The present invention relates to the field of circuit design, and in particular to a power management architecture, a chip and a power management method. Background Art

[0002] With the continuous expansion of domestic chip consumption market demand, the chip self-sufficiency rate continues to increase, and SOC and MCU products corresponding to various application requirements emerge in an endless stream and continue to replace foreign products; the power management module (PMU) is the core part of the chip power supply and is crucial to a good product; with the continuous improvement of the performance of electronic products, the power consumption requirements of various chips are also constantly increasing, and various new power management architectures have naturally emerged. However, the stability of the existing power architecture is poor. When a component in the circuit fails to work, it cannot be awakened, resulting in the failure of the power supply. Summary of the invention

[0003] To solve the above problems, the present invention provides a power management architecture, chip and power management method, which can reduce the power consumption of the power management architecture while enhancing the stability of the power management architecture, and restore the working state according to an external signal when the power management architecture fails to work. The specific technical solutions of the present invention are as follows:

[0004] A power management architecture, comprising a first power domain interface, a second power domain interface, a first power domain power module, a second power domain power module, a VDD1 power domain, a VDD2 power domain and a power selection switch; the first power domain interface and the second power domain interface are connected to the first power domain power module through the power selection switch, and the first power domain power module is connected to the VDD1 power module; the second power domain interface is connected to the second power domain power module, and the second power domain power module is connected to the VDD2 power module; the first power domain power module is provided with a first reset pin, and the first reset pin and the VDD2 power module are used to send an enable signal to wake up the first power domain power module; the second power domain power module is provided with a second reset pin, and the second reset pin and the VDD1 power module are used to send an enable signal to wake up the second power domain power module.

[0005] Compared with the existing technology, the technical solution of the present application wakes up the first power domain power module and the second power domain power module respectively by sending an enable signal through the first reset pin and the second reset pin at the same time, or, sends an enable signal through one of the first reset pin or the second reset pin to wake up the corresponding power domain power module, and then wakes up the other power domain power module through the VDD1 power module or the VDD2 power module, so that the power architecture can recover from the state where the first power domain power module and the second power domain power module are unable to supply power due to the suspension of operation, thereby improving the functionality of the power architecture and making the power architecture stronger and more stable; the VDD1 power module and the VDD2 power module wake up each other through interactive operations, and the function is powerful; the low-power power domain and the high-power power domain are independent of each other, do not affect each other, and are more robust.

[0006] Furthermore, the first power domain power supply module includes a low-power bandgap reference source, a first power comparator, a first wake-up module, a first low-voltage difference linear regulator and a first source follower; the low-power bandgap reference source is respectively connected to the first power comparator, the first low-voltage difference linear regulator and the first source follower; the first wake-up module is respectively connected to the first power comparator, the first low-voltage difference linear regulator and the first source follower; the output ends of the first low-voltage difference linear regulator and the first source follower are commonly connected to the VDD1 power supply module, for outputting the voltage VDD1 to the VDD1 power supply module, so that the VDD1 power supply module generates a low-voltage power domain.

[0007] Furthermore, the first wake-up module includes 5 input terminals and 2 output terminals, the input terminals of the first wake-up module are respectively connected to the first reset pin, the first power comparator, the VDD1 power module and the VDD2 power module, and 2 of the input terminals of the first wake-up module are connected to the VDD1 power module, and the output terminals of the first wake-up module are respectively connected to the first low voltage difference linear regulator and the first source follower.

[0008] Furthermore, the VDD1 power supply module includes a logic circuit, the logic circuit includes three output terminals, two of which are respectively connected to the first wake-up module for sending signals to adjust the states of the first low voltage difference linear regulator and the first source follower, and another output terminal of the logic circuit is connected to the second power domain power supply module for sending signals to wake up the second power domain power supply module. Compared with the existing technology, the external wake-up mechanism can completely shut down the logic power supply to achieve lower power consumption.

[0009] Furthermore, the first power comparator includes an input end and an output end, the input end of the first power comparator is connected to the low-power bandgap reference source, the output end of the first power comparator is connected to the first wake-up module, and the first power comparator is used to compare the reference voltage generated by the low-power bandgap reference source with the input voltage input by the first power domain interface or the second power domain interface, and output a voltage signal to the first wake-up module according to the comparison result.

[0010] Furthermore, the second power domain power supply module includes a bandgap reference source, a second power comparator, a second wake-up module, a second low voltage difference linear regulator and a second source follower; the bandgap reference source is respectively connected to the second power comparator, the second low voltage difference linear regulator and the second source follower; the second wake-up module is respectively connected to the second power comparator, the second low voltage difference linear regulator and the second source follower; the output ends of the second low voltage difference linear regulator and the second source follower are commonly connected to the VDD2 power supply module, for outputting the voltage VDD2 to the VDD2 power supply module, so that the VDD2 power supply module generates a low voltage power domain.

[0011] Furthermore, the second wake-up module includes 5 input terminals and 2 output terminals, the output terminals of the second wake-up module are respectively connected to the second reset pin, the second power comparator, the VDD1 power module and the VDD2 power module, and 2 of the input terminals of the second wake-up module are connected to the VDD2 power module, and the output terminals of the second wake-up module are respectively connected to the second low voltage difference linear regulator and the second source follower.

[0012] Furthermore, the VDD2 power supply module includes a logic circuit, which includes three output terminals, two of which are respectively connected to the second wake-up module for sending signals to adjust the states of the second low-voltage difference linear regulator and the second source follower, and another output terminal in the logic circuit is connected to the first power domain power supply module for sending signals to wake up the first power domain power supply module.

[0013] Furthermore, the second power comparator includes an input end and an output end, the input end of the second power comparator is connected to the bandgap reference source, the output end of the second power comparator is connected to the second wake-up module, and the second power comparator is used to compare the reference voltage generated by the received bandgap reference source with the input voltage input by the second power domain interface, and output a voltage signal to the second wake-up module based on the comparison result.

[0014] Furthermore, the first power domain interface and the second power domain interface are both connected to the high voltage power domain, the first power domain interface is used to connect to the energy storage power domain, and the second power domain interface is used to connect to the external power domain.

[0015] Furthermore, the power selection switch is used to select the power domain for power supply according to the output voltage of the first power domain interface and the second power domain interface. If the output voltage of the second power domain interface is within a set range, the power selection switch selects the second power domain interface to supply power to the first power domain power module. The external power domain is used for power supply first, so that the stored power can be saved efficiently and is highly practical.

[0016] A chip includes the above power management architecture.

[0017] A step-by-step power management method, the method comprising the following steps: a power selection switch selects a power domain interface for power supply according to whether a first power domain interface and a second power domain interface are connected to a voltage; if the first power domain interface is connected to a voltage and the second power domain interface is not connected to a voltage, the power selection switch selects the first power domain interface to supply power to a first power domain power module, so that the first power domain can receive an enable signal of a first reset pin to control a first low voltage difference linear regulator; if the second power domain interface is connected to a voltage and the first power domain interface is not connected to a voltage, the power selection switch selects the second power domain interface to supply power to the first power domain power module, so that the first power domain can receive an enable signal of a first reset pin to control a first low voltage difference linear regulator; if the second power domain interface is connected to a voltage and the first power domain interface is not connected to a voltage, the power selection switch selects the second power domain interface to supply power to the first power domain power module, so that the first The power domain can receive an enable signal from a first reset pin to control a first low voltage difference linear regulator, and the second power domain interface simultaneously supplies power to a second power domain power module, so that the second power domain can receive an enable signal from a second reset pin to control a second low voltage difference linear regulator; if both the first power domain interface and the second power domain interface are connected to voltage, when the output voltage of the second power domain interface is within a set range, the power selection switch selects the second power domain interface to supply power to the first power domain power module; when the output voltage of the second power domain interface is not within a set range, the power selection switch selects the first power domain interface to supply power to the first power domain power module. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 A schematic diagram of the structure of a power management architecture according to an embodiment of the present invention.

[0019] Figure 2 A circuit diagram of a wake-up module according to another embodiment of the present invention. DETAILED DESCRIPTION

[0020] In order to make the purpose, technical scheme and advantages of the present invention clearer, the present invention will be described and illustrated in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described below are only used to explain the present invention and are not used to limit the present invention. In addition, it can also be understood that for ordinary technicians in the field, some changes such as design, manufacturing or production on the technical content disclosed in the present invention are just conventional technical means, and should not be understood as the content disclosed in this application is insufficient.

[0021] Unless otherwise defined, the technical terms or scientific terms involved in the present invention should be understood by people with ordinary skills in the technical field to which this application belongs. The words "one", "a", "a kind of", "the" and the like involved in this application do not represent quantitative restrictions and may represent the singular or plural. The terms "include", "comprise", "have" and any of their variations involved in this application are intended to cover non-exclusive inclusions, such as: a process, method, system product or device comprising a series of steps or modules is not limited to the listed steps or units, but may also include steps or modules that are not listed, or may also include other steps or units inherent to these processes, methods, products or devices. The terms "first", "second", "third" and the like involved in this application are merely used to distinguish similar correspondences and do not represent a specific ordering of objects.

[0022] In one embodiment of the present invention, a power management architecture is provided, such as Figure 1As shown, the architecture includes a first power domain interface VCC1, a second power domain interface VCC2, a first power domain power module VSL POWER DOMAIN, a second power domain power module VCC2 POWER DOMAIN, a VDD1 power module VDD1 POWER DOMAIN, a VDD2 power module VDD2POWER DOMAIN and a power selection switch POWER SWITCH; the first power domain interface VCC1 and the second power domain interface VCC2 are connected to the first power domain power module VSL POWER DOMAIN through the power selection switch POWER SWITCH, and the first power domain power module VSL POWER DOMAIN is connected to the VDD1 power module VDD1POWER DOMAIN; the second power domain interface VCC2 is connected to the second power domain power module VCC2 POWER DOMAIN, and the second power domain power module VCC2 POWER DOMAIN is connected to the VDD2 power module VDD2 POWER DOMAIN; the first power domain power module VSL POWER DOMAIN DOMAIN is provided with a first reset pin nRSTA, and the first reset pin nRSTA and the VDD2 power module VDD2POWER DOMAIN are used to send an enable signal to wake up the first power domain power module VSL POWER DOMAIN; the second power domain power module VCC2 POWER DOMAIN is provided with a second reset pin nRSTB, and the second reset pin nRSTB and the VDD1 power module VDD1 POWER DOMAIN are used to send an enable signal to wake up the second power domain power module VCC2POWER DOMAIN. The technical solution of the present application wakes up the first power domain power module and the second power domain power module respectively by sending an enable signal through the first reset pin and the second reset pin at the same time, or, sends an enable signal through one of the first reset pin or the second reset pin to wake up the corresponding power domain power module, and then wakes up the other power domain power module through the VDD1 power module or the VDD2 power module, so that the power architecture can be recovered from the state where the first power domain power module and the second power domain power module are unable to supply power due to the suspension of operation, thereby improving the functionality of the power architecture and making the power architecture stronger and more stable; the VDD1 power module and the VDD2 power module wake up each other through interactive operations, and the function is powerful; the low-power power domain and the high-power power domain are independent of each other, do not affect each other, and are more robust.

[0023] A step-by-step power management method, wherein the first power domain interface VCC1 and the second power domain interface VCC2 are connected to a high voltage power domain, wherein the first power domain interface VCC1 is used to connect to an energy storage power domain, which is generally a power supply source with limited energy such as a battery, and is related to the standby capability of the product, and has relatively high requirements for low power consumption; the second power domain interface VCC2 is used to connect to an external power domain, which is generally a power supply provided by an adapter through an external LDO or DC-DC. Generally, this power domain has a relatively large power consumption, and is the power domain that provides power when the chip is in normal high-performance operation. The power selection switch POWER SWITCH is used to select a power domain for power supply according to the output voltage of the first power domain interface VCC1 and the second power domain interface VCC2. If the output voltage of the second power domain interface VCC2 is within a set range, the power selection switch POWERSWITCH selects the second power domain interface VCC2 to supply power to the first power domain power module VSL POWER DOMAIN. When the first power domain interface VCC1 and the second power domain interface VCC2 are turned on at the same time, as long as the second power domain interface VCC2 is not lower than a certain voltage value, the first power domain power module VSL POWER DOMAIN will always choose the second power domain interface VCC2 for power supply, otherwise it will choose the first power domain interface VCC1 for power supply, thereby saving the energy of the battery that provides the first power domain interface VCC1. The external power domain is used for power supply first, so that the stored power can be saved efficiently and is highly practical.

[0024] Specifically, when the second power domain interface VCC2 is not powered and the first power domain interface VCC1 is powered, the first power domain power module VSL POWER DOMAIN selects the first power domain interface VCC1 for power supply through the power selection switch POWER SWITCH, and the first power domain power module VSL POWER DOMAIN has only one low power bandgap reference source LPBG and power comparator POWER CMP1 to work, and both modules can achieve nA level power consumption according to existing technologies. On this basis, the first low voltage difference linear regulator LDO1 can be awakened through the external first reset pin nRSTA to generate voltage VDD1 for power supply, and the logic circuit LOGIC of the VDD1 power module VDD1 POWER DOMAIN can perform subsequent logic control work. When the second power domain interface VCC2 is powered and the first power domain interface VCC1 is not powered, the first power domain power module VSLPOWER DOMAIN selects the second power domain interface VCC2 for power supply through the power selection switch POWER SWITCH. At this time, the above operation can also be performed in the first power domain power module VSL POWER DOMAIN, and the second power comparator POWERCMP2DMOS2 and the second low voltage difference linear regulator LDO2 can be turned off at the same time and do not work. It only needs to send an enable signal through the external second reset pin nRSTB or the logic circuit LOGIC of the VDD1 power module VDD1 POWER DOMAIN to turn on the second low voltage difference linear regulator LDO2, generate VDD2, and then perform subsequent logic control. In this architecture, the VDD1 power module VDD1 POWER DOMAIN and the VDD2 power module VDD2POWER DOMAIN under the first power domain power module VSL POWER DOMAIN and the second power domain power module VCC2 POWER DOMAIN each have four states: DMOS / LPLDO and LDO are not turned on, only DMOS is turned on, only LDO is turned on, and both DMOS and LDO are turned on. They can be freely combined according to load requirements.Compared with the existing technology, the technical solution of the present application sends an enable signal through the first reset pin nRSTA and the second reset pin nRSTB to wake up the first power domain power module VSL POWER DOMAIN and the second power domain power module VCC2 POWERDOMAIN respectively, so that the power architecture can be restored from the state where the first power domain power module VSL POWER DOMAIN and the second power domain power module VCC2 POWER DOMAIN are unable to supply power due to the suspension of operation, thereby improving the functionality of the power architecture and making the power architecture stronger and more stable; the VDD1 power module VDD1 POWER DOMAIN and the VDD2 power module VDD2POWER DOMAIN wake up each other through interactive operations, and the function is powerful; the low-power power domain and the high-power power domain are independent of each other, do not affect each other, and are more robust.

[0025] As one of the embodiments, the first power domain power module VSL POWER DOMAIN includes a low power bandgap reference source LPBG, a first power comparator POWER CMP1, a first wake-up module WAKEUP MODULE, a first low voltage difference linear regulator LDO1 and a first source follower DMOS1; the low power bandgap reference source LPBG has three output ends, and the three output ends are respectively connected to the first power comparator POWER CMP1, the first low voltage difference linear regulator LDO1 and the first source follower DMOS1; the first power comparator POWER CMP1 includes an input end and an output end, the input end of the first power comparator POWER CMP1 is connected to the low power bandgap reference source LPBG, the output end of the first power comparator POWER CMP1 is connected to the first wake-up module WAKEUP MODULE, and the first power comparator POWER CMP1 is used to compare the reference voltage generated by the low power bandgap reference source LPBG with the input voltage of the first power domain interface VCC1 or the second power domain interface VCC2, and output a voltage signal to the first wakeup module WAKEUP MODULE according to the comparison result.

[0026] Specifically, the first power domain interface VCC1 and the second power domain interface VCC2 can be powered on separately or together; wherein, when the first power domain interface VCC1 is powered on separately, the first power domain power module VSL POWER DOMAIN is always powered, the first power domain power module VSL POWER DOMAIN selects the first power domain interface VCC1 as the power supply through the power selection switch POWER SWITCH, the low power bandgap reference source LPBG starts automatically, and the first power comparator POWER CMP1 uses the reference voltage generated by the low power bandgap reference source LPBG to determine whether the first power domain interface VCC1 is powered on to the required voltage level, and then generates a VSL_OK signal. The VSL_OK signal generated by the first power comparator POWER CMP1 is sent to the first wake-up module WAKEUP MODULE. The first wake-up module WAKEUP MODULE enables the first low voltage difference linear regulator LDO1 to generate a low voltage power domain VDD1 through the SR trigger under the first power domain power module VSLPOWER DOMAIN. Thereafter, the state of the first source follower DMOS1 or the first low voltage difference linear regulator LDO1 can be adjusted through the logic circuit LOGIC in the VDD1 power domain. The first source follower DMOS1 and the first low voltage difference linear regulator LDO1 can be turned off, on, or only one of them can be turned on at the same time.

[0027] Specifically, the first wake-up module WAKEUP MODULE is respectively connected to the first power comparator POWER CMP1, the first low voltage difference linear regulator LDO1 and the first source follower DMOS1; the output ends of the first low voltage difference linear regulator LDO1 and the first source follower DMOS1 are commonly connected to the VDD1 power module VDD1 POWER DOMAIN, for outputting the voltage VDD1 to the VDD1 power module VDD1POWER DOMAIN, so that the VDD1 power module VDD1 POWER DOMAIN generates a low voltage power domain. The first wake-up module WAKEUP MODULE includes 5 input ends and 2 output ends, the output ends of the first wake-up module WAKEUP MODULE are respectively connected to the first reset pin nRSTA, the first power comparator POWER CMP1, the VDD1 power module VDD1 POWER DOMAIN and the VDD2 power module VDD2POWER DOMAIN, and 2 input ends of the input ends of the first wake-up module WAKEUP MODULE are connected to the VDD1 power module VDD1 POWER DOMAIN, and the output ends of the first wake-up module WAKEUP MODULE are respectively connected to the first low voltage difference linear regulator LDO1 and the first source follower DMOS1.

[0028] Specifically, the VDD1 power module VDD1 POWER DOMAIN includes a logic circuit LOGIC, and the logic circuit LOGIC includes 3 output terminals, 2 of which are respectively connected to the first wake-up module WAKEUPMODULE, for sending signals to adjust the states of the first low-dropout linear regulator LDO1 and the first source follower DMOS1, and another output terminal in the logic circuit LOGIC is connected to the second power domain power module VCC2 POWER DOMAIN, for sending signals to wake up the second power domain power module VCC2POWER DOMAIN. Compared with the existing technology, the external wake-up mechanism can completely shut down the logic power supply to achieve lower power consumption.

[0029] As one of the embodiments, the second power domain power module VCC2 POWER DOMAIN includes a bandgap reference source BG, a second power comparator POWER CMP2, a second wake-up module WAKEUP MODULE, a second low voltage difference linear regulator LDO2 and a second source follower DMOS2; the bandgap base source BG has three output ends, and the three output ends are respectively connected to the second power comparator POWER CMP2, the second low voltage difference linear regulator LDO2 and the second source follower DMOS2; the second power comparator POWER CMP2 includes an input end and an output end, the input end of the second power comparator POWER CMP2 is connected to the bandgap reference source BG, the output end of the second power comparator POWER CMP2 is connected to the second wake-up module WAKEUP MODULE, and the second power comparator POWER CMP2 is used to compare the reference voltage generated by the bandgap reference source BG with the input voltage of the second power domain interface VCC2, and output a voltage signal to the second wake-up module WAKEUP MODULE according to the comparison result.

[0030] Specifically, when the first power domain interface VCC2 is powered on, the first power domain power module VSL POWER DOMAIN selects the first power domain interface VCC1 as the power source through the power selection switch POWER SWITCH, and works according to the above-mentioned workflow when the first power domain interface VCC1 is powered on. The bandgap reference source BG in the second power domain power module VCC2 POWER DOMAIN is self-started, and the second power comparator POWER CMP2 uses the reference voltage generated by the bandgap reference source BG to determine whether the second power domain interface VCC2 is powered on to the required voltage level, and generates a VCC2_OK signal. The VCC2_OK signal generated by the second power comparator POWERCMP2 is sent to the second wake-up module WAKEUP MODULE. The second wake-up module WAKEUP MODULE enables the second low voltage difference linear regulator LDO2 to generate the low voltage power domain VDD2 through the SR trigger under the second power domain power module VCC2 POWER DOMAIN. Thereafter, the state of the second source follower DMOS2 or the second low voltage difference linear regulator LDO2 can be changed through the logic circuit LOGIC in the VDD2 power module VDD2 POWER DOMAIN. The second source follower DMOS2 and the second low voltage difference linear regulator LDO2 can be turned off, turned on, or only one of them can be turned on at the same time.

[0031] Specifically, the second wake-up module WAKEUP MODULE is respectively connected to the second power comparator POWER CMP2, the second low voltage difference linear regulator LDO2 and the second source follower DMOS2; the output ends of the second low voltage difference linear regulator LDO2 and the second source follower DMOS2 are commonly connected to the VDD2 power module VDD2 POWER DOMAIN, for outputting the voltage VDD2 to the VDD2 power module VDD2POWER DOMAIN, so that the VDD2 power module VDD2 POWER DOMAIN generates a low voltage power domain. The second wake-up module WAKEUP MODULE includes 5 input ends and 2 output ends, the output ends of the second wake-up module WAKEUP MODULE are respectively connected to the second reset pin nRSTB, the second power comparator POWER CMP2, the VDD1 power module VDD1 POWER DOMAIN and the VDD2 power module VDD2POWER DOMAIN, and 2 of the input ends of the second wake-up module WAKEUP MODULE are connected to the VDD2 power module VDD2 POWER DOMAIN, and the output ends of the second wake-up module WAKEUP MODULE are respectively connected to the second low voltage difference linear regulator LDO2 and the second source follower DMOS2.

[0032] Specifically, the VDD2 power supply module VDD2 POWER DOMAIN includes a logic circuit LOGIC, and the logic circuit LOGIC includes 3 output terminals, 2 of which are respectively connected to the second wake-up module WAKEUPMODULE, for sending signals to adjust the states of the second low-voltage difference linear regulator LDO2 and the second source follower DMOS2, and another output terminal in the logic circuit LOGIC is connected to the first power domain power supply module VSL POWER DOMAIN, for sending signals to wake up the first power domain power supply module VSL POWER DOMAIN. The structures of the VDD1 power supply module VDD1 POWERDOMAIN and the VDD2 power supply module VDD2 POWER DOMAIN are the same. The first low-voltage difference linear regulator LDO1 and the second low-voltage difference linear regulator LDO2 can be replaced with a DC-DC switching power supply structure to adapt to power supply with different requirements.

[0033] like Figure 2 As stated, Figure 2 The circuit structure diagram of the wake-up module is shown in FIG. 1. The first wake-up module WAKEUP MODULE and the second wake-up module WAKEUP MODULE have the same structure and work content. In the circuit, the EN_LDO_I and EN_DMOS_I interfaces are connected to the EN_LDO and EN_DMOS in the top-level architecture of the PMU, that is, they are used to receive the enable signal from the logic circuit LOGIC of the power module. Then the WAKEUP interface is used to receive the enable signal of another power module (EN_LDO2 in the logic circuit LOGIC of the VDD1 power module VDD1 POWER DOMAIN, EN_LDO1 in the logic circuit LOGIC of the VDD2 power module VDD2 POWER DOMAIN). VCC_OK is the power-on voltage detection signal, which is generated by the power comparator POWER CMP. VCC_OK equals 1, indicating that the power-on is completed. The nRST interface is the control signal connected to the reset pin.

[0034] A chip includes the above power management architecture.

[0035] Obviously, the above-mentioned embodiments are only part of the embodiments of the present invention, rather than all the embodiments, and the technical solutions between the various embodiments can be combined with each other. In the above-mentioned embodiments of the present invention, the descriptions of the various embodiments have different focuses. For the parts that are not described in detail in a certain embodiment, please refer to the relevant descriptions of other embodiments. In the several embodiments provided by the present invention, it should be understood that the disclosed technical content can be implemented in other ways. Among them, the device embodiments described above are only schematic. For example, the division of the circuit can be a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed.

[0036] It should also be noted that the various specific technical features described in the above specific embodiments can be combined in any suitable manner without contradiction. To avoid unnecessary repetition, the embodiments of the present invention will not further describe various possible combinations.

[0037] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A power management architecture, characterized in that: The architecture includes a first power domain interface, a second power domain interface, a first power domain power module, a second power domain power module, a VDD1 power module, a VDD2 power module and a power selection switch; The first power domain interface and the second power domain interface are connected to the first power domain power module through a power selection switch, and the first power domain power module is connected to the VDD1 power module; The second power domain interface is connected to a second power domain power module, and the second power domain power module is connected to a VDD2 power module; The first power domain power module is provided with a first reset pin, and the first reset pin and the logic generated in the VDD2 power module are used to send an enable signal to wake up the first power domain power module; The second power domain power module is provided with a second reset pin, and the second reset pin and the logic generated in the VDD1 power module are used to send an enable signal to wake up the second power domain power module.

2. The power management architecture according to claim 1, characterized in that: The first power domain power supply module includes a low power bandgap reference source, a first power comparator, a first wake-up module, a first low voltage drop linear regulator and a first source follower; The low power bandgap reference is respectively connected to the first power comparator, the first low voltage drop linear regulator and the first source follower; The first wake-up module is respectively connected to the first power comparator, the first low voltage drop linear regulator and the first source follower; The output ends of the first low voltage difference linear regulator and the first source follower are commonly connected to the VDD1 power supply module for outputting the voltage VDD1 to the VDD1 power supply module so that the VDD1 power supply module generates a low voltage power supply domain.

3. The power management architecture according to claim 2, characterized in that: The first wake-up module includes 5 input terminals and 2 output terminals, the input terminals of the first wake-up module are respectively connected to the first reset pin, the first power comparator, the VDD1 power module and the VDD2 power module, and 2 of the input terminals of the first wake-up module are connected to the VDD1 power module, and the output terminals of the first wake-up module are respectively connected to the first low voltage difference linear regulator and the first source follower.

4. The power management architecture according to claim 3, characterized in that: The VDD1 power supply module includes a logic circuit, which includes three output terminals. Two output terminals in the logic circuit are respectively connected to the first wake-up module for sending signals to adjust the states of the first low-voltage difference linear regulator and the first source follower, and another output terminal in the logic circuit is connected to the second power domain power supply module for sending signals to wake up the second power domain power supply module.

5. The power management architecture according to claim 2, characterized in that: The first power comparator includes an input end and an output end, the input end of the first power comparator is connected to the low-power bandgap reference source, the output end of the first power comparator is connected to the first wake-up module, and the first power comparator is used to compare the reference voltage generated by the low-power bandgap reference source with the input voltage input by the first power domain interface or the second power domain interface, and output a voltage signal to the first wake-up module according to the comparison result.

6. The power management architecture according to claim 1, characterized in that: The second power domain power supply module includes a bandgap reference source, a second power comparator, a second wake-up module, a second low-dropout linear regulator, and a second source follower; The bandgap reference source is respectively connected to the second power comparator, the second low voltage drop linear regulator and the second source follower; The second wake-up module is respectively connected to the second power comparator, the second low-dropout linear regulator and the second source follower; The output ends of the second low voltage difference linear regulator and the second source follower are commonly connected to the VDD2 power supply module for outputting the voltage VDD2 to the VDD2 power supply module so that the VDD2 power supply module generates a low voltage power supply domain.

7. The power management architecture according to claim 6, characterized in that: The second wake-up module includes 5 input terminals and 2 output terminals, the output terminals of the second wake-up module are respectively connected to the second reset pin, the second power comparator, the VDD1 power module and the VDD2 power module, and 2 of the input terminals of the second wake-up module are connected to the VDD2 power module, and the output terminals of the second wake-up module are respectively connected to the second low voltage difference linear regulator and the second source follower.

8. The power management architecture according to claim 7, characterized in that: The VDD2 power supply module includes a logic circuit, which includes three output terminals. Two output terminals in the logic circuit are respectively connected to the second wake-up module for sending signals to adjust the states of the second low voltage difference linear regulator and the second source follower, and another output terminal in the logic circuit is connected to the first power domain power supply module for sending signals to wake up the first power domain power supply module.

9. The power management architecture according to claim 6, characterized in that: The second power comparator includes an input end and an output end, the input end of the second power comparator is connected to the bandgap reference source, the output end of the second power comparator is connected to the second wake-up module, and the second power comparator is used to compare the reference voltage generated by the received bandgap reference source with the input voltage input by the second power domain interface, and output a voltage signal to the second wake-up module according to the comparison result.

10. The power management architecture according to claim 1, wherein: The first power domain interface and the second power domain interface are both connected to the high voltage power domain, the first power domain interface is used to connect to the energy storage power domain, and the second power domain interface is used to connect to the external power domain.

11. The power management architecture according to claim 10, characterized in that: The power selection switch is used to select a power domain for power supply according to the output voltages of the first power domain interface and the second power domain interface. If the output voltage of the second power domain interface is within a set range, the power selection switch selects the second power domain interface to power the first power domain power module.

12. A chip, characterized in that: The chip comprises the power management architecture described in any one of claims 1 to 11.

13. A step-by-step power management method, characterized in that: The method comprises the following steps: The power selection switch selects a power domain interface for power supply according to whether the first power domain interface and the second power domain interface are connected to voltage; If the first power domain interface is connected to a voltage and the second power domain interface is not connected to a voltage, the power selection switch selects the first power domain interface to supply power to the first power domain power module, so that the first power domain can receive an enable signal from the first reset pin to control the first low voltage drop linear regulator; If the second power domain interface is connected to voltage and the first power domain interface is not connected to voltage, the power selection switch selects the second power domain interface to supply power to the first power domain power module, so that the first power domain can receive the enable signal of the first reset pin to control the first low voltage difference linear regulator, and the second power domain interface simultaneously supplies power to the second power domain power module, so that the second power domain can receive the enable signal of the second reset pin to control the second low voltage difference linear regulator; If both the first power domain interface and the second power domain interface are connected to voltage, when the output voltage of the second power domain interface is within the set range, the power selection switch selects the second power domain interface to supply power to the first power domain power module; when the output voltage of the second power domain interface is not within the set range, the power selection switch selects the first power domain interface to supply power to the first power domain power module.

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