Semiconductor device including laminated substrate and method for manufacturing the same

Abstract

The present invention provides a semiconductor device including a stacked substrate and a method for manufacturing the semiconductor device. A semiconductor device includes a second semiconductor substrate vertically stacked on a first semiconductor substrate. The first semiconductor substrate includes a first diffusion barrier layer covering a first surface of a main body of the first semiconductor substrate, and a first through hole having a third surface exposed to a second surface of the first diffusion barrier layer. The second semiconductor substrate includes a second semiconductor substrate main body, a second diffusion barrier layer directly bonded to the second surface of the first diffusion barrier layer, and a front pad having a smaller surface area than the third surface of the first through hole and directly bonded to the third surface of the first through hole.

Description

Technical Field

[0001] The present disclosure generally relates to a semiconductor packaging technology, and more particularly, to a semiconductor device including a stacked substrate and a method of manufacturing the semiconductor device. Background Art

[0002] Semiconductor devices are used in various electronic applications. Semiconductor devices can be used in personal computers, mobile phones, cameras, etc. Semiconductor devices can be manufactured by depositing semiconductor material layers, conductive layers, dielectric layers, or insulating layers on a semiconductor substrate or semiconductor wafer and patterning these layers to form circuit components and elements, and by dividing the semiconductor substrate or wafer into individual chips and packaging the individual chips in a package.

[0003] As the integration density of various electronic components such as transistors, capacitors, and diodes increases and smaller packages are required, three-dimensional (3D) semiconductor devices have recently been developed. 3D semiconductor devices have been developed in packaging forms such as package-on-package (PoP) or system-in-package (SiP). Summary of the invention

[0004] One aspect of the present disclosure provides a semiconductor device including a first semiconductor substrate and a second semiconductor substrate vertically stacked on the first semiconductor substrate.

[0005] The first semiconductor substrate may include: a first semiconductor substrate body; a first diffusion barrier layer covering a first surface of the first semiconductor substrate body; and a first through hole having a third surface exposed to the second surface of the first diffusion barrier layer.

[0006] The second semiconductor substrate may include: a second semiconductor substrate body, which is arranged on the first semiconductor substrate body; a second diffusion barrier layer, which covers the fourth surface of the second semiconductor substrate body facing the first semiconductor substrate body, and a portion of the fifth surface of the second diffusion barrier layer is directly bonded to the second surface of the first diffusion barrier layer; and a front pad, which has a sixth surface exposed to the fifth surface of the second diffusion barrier layer, the sixth surface has a smaller surface area than the third surface of the first through hole, and is directly bonded to the third surface of the first through hole of the first semiconductor substrate.

[0007] One aspect of the present disclosure provides a semiconductor device including a first semiconductor substrate and a second semiconductor substrate vertically stacked on the first semiconductor substrate.

[0008] The first semiconductor substrate may include: a first semiconductor substrate body; a first diffusion barrier layer covering a first surface of the first semiconductor substrate body; and a first through hole having a third surface exposed to the second surface of the first diffusion barrier layer.

[0009] The second semiconductor substrate may include: a second semiconductor substrate body, which is arranged on the first semiconductor substrate body; a second diffusion barrier layer, which covers a fourth surface of the second semiconductor substrate body facing the first semiconductor substrate body and has a fifth surface locally and directly bonded to the second surface of the first diffusion barrier layer; a front pad, which has a sixth surface and is bonded to the third surface of the first through hole, the sixth surface is exposed to the fifth surface of the second diffusion barrier layer, and has a smaller surface area than the third surface of the first through hole; and a second through hole, which is electrically connected to the front pad and passes through the second semiconductor substrate body.

[0010] In a method for manufacturing a semiconductor device according to one aspect of the present disclosure, a second semiconductor substrate may be stacked on a first semiconductor substrate. The method for manufacturing the semiconductor device may include: forming a first semiconductor substrate including a first diffusion barrier layer covering a first surface of a main body of the first semiconductor substrate and a first through hole having a third surface exposed to a second surface of the first diffusion barrier layer; forming a second semiconductor substrate including a second diffusion barrier layer covering a fourth surface of a main body of the second semiconductor substrate, and a front pad having a sixth surface exposed to a fifth surface of the second diffusion barrier layer, the sixth surface having a smaller surface area than the third surface of the first through hole; and stacking the second semiconductor substrate on the first semiconductor substrate to directly bond a portion of the fifth surface of the second diffusion barrier layer to the second surface of the first diffusion barrier layer, and directly bond the sixth surface of the front pad to the third surface of the first through hole. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 is a cross-sectional view illustrating a semiconductor device according to an embodiment.

[0012] Figure 2 It is an example Figure 1 A cross-sectional view of a first semiconductor substrate of a semiconductor device.

[0013] Figure 3 It is an example Figure 1 A cross-sectional view of a second semiconductor substrate of a semiconductor device.

[0014] Figure 4 It is an example Figure 1 FIG. 4 is a cross-sectional view of an enlarged bonding structure of a first through hole and a front pad.

[0015] Figure 5 is a cross-sectional view illustrating copper contamination in a bonding structure of a via hole and a pad according to a comparative example.

[0016] Figure 6 is a cross-sectional view illustrating a semiconductor device according to an embodiment.

[0017] Figures 7 to 10 This is an example of manufacturing Figure 1 A cross-sectional view of process steps of a method for fabricating a semiconductor device.

[0018] Fig.11 is a block diagram illustrating an electronic system employing a memory card including a package according to an embodiment.

[0019] Fig.12 is a block diagram illustrating an electronic system including a package according to an embodiment. DETAILED DESCRIPTION

[0020] The terms used herein may correspond to words selected in consideration of their functions in the proposed embodiments, and the meanings of these terms may be interpreted differently according to the ordinary technicians in the field to which the embodiments belong. If the terms are defined in detail, these terms may be interpreted according to the definitions. Unless otherwise defined, the terms used herein (including technical terms and scientific terms) have the same meanings as those generally understood by ordinary technicians in the field to which the embodiments belong.

[0021] It will be understood that although the terms "first", "second", "third", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element, and are not used to indicate a specific order or quantity of elements.

[0022] It should also be understood that when an element or layer is referred to as being "on," "over," "under," "beneath," or "outside" another element or layer, the element or layer may be directly in contact with the other element or layer, or intervening elements or layers may be present. Other words used to describe the relationship between elements or layers should be interpreted in a similar manner (e.g., "between" versus "directly between" or "adjacent" versus "directly adjacent").

[0023] Spatially relative terms such as "under," "beneath," "lower," "above," "upper," "top," "bottom," and the like may be used to describe the relationship of an element and / or feature to another element and / or feature, such as shown in the accompanying drawings. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and / or operation in addition to the orientations depicted in the accompanying drawings. For example, when the device in the accompanying drawings is turned over, an element described as under and / or below another element or feature will be oriented above the other element or feature. The device may be oriented in other ways (rotated 90 degrees or other orientations), and the spatially relative descriptors used herein shall be interpreted accordingly.

[0024] According to various embodiments, the semiconductor package may include an electronic device such as a semiconductor chip or a semiconductor wafer. The semiconductor chip or semiconductor wafer may be obtained by separating a semiconductor substrate such as a wafer into a plurality of pieces using a dicing process. The semiconductor chip may correspond to a memory chip, a logic chip, an application specific integrated circuit (ASIC) chip, an application processor (AP), a graphics processing unit (GPU), a central processing unit (CPU), or a system on chip (SoC). The memory chip may include a dynamic random access memory (DRAM) circuit, a static random access memory (SRAM) circuit, a NAND flash memory circuit, a NOR flash memory circuit, a magnetic random access memory (MRAM) circuit, a resistive random access memory (ReRAM) circuit, a ferroelectric random access memory (FeRAM) circuit, or a phase change random access memory (PcRAM) circuit integrated on a semiconductor substrate. The logic chip may include a logic circuit integrated on a semiconductor substrate. The semiconductor package may be used in communication systems such as mobile phones, electronic systems related to biotechnology or medical health, or wearable electronic systems. The semiconductor package may be applicable to the Internet of Things (IoT).

[0025] Throughout the specification, the same reference numerals refer to the same elements. Even though a reference numeral may not be mentioned or described with reference to a drawing, it may be mentioned or described with reference to another drawing. In addition, even though a reference numeral may not be shown in a drawing, it may be shown in another drawing.

[0026] Figure 1 is a cross-sectional view illustrating a semiconductor device 10 according to an embodiment. Figure 2 It is an example Figure 1 A cross-sectional view of a first semiconductor substrate of a semiconductor device. Figure 3 It is an example Figure 1 1 is a cross-sectional view of a second semiconductor substrate 200 of a semiconductor device.

[0027] Reference Figure 1 , the semiconductor device 10 may include a first semiconductor substrate 100 and a second semiconductor substrate 200. The second semiconductor substrate 200 may be substantially vertically stacked on the first semiconductor substrate 100. The first semiconductor substrate 100 may have a shape of a single semiconductor wafer separated from a semiconductor wafer. The second semiconductor substrate 200 may have a shape of a single semiconductor wafer separated from a semiconductor wafer. The semiconductor device 10 may have a structure in which semiconductor wafers or semiconductor substrates 100 and 200 are three-dimensionally stacked. The semiconductor device 10 may have a structure in which other semiconductor substrates are placed above the semiconductor substrate at the wafer level. In another embodiment, each of the first semiconductor substrate 100 and the second semiconductor substrate 200 may have a semiconductor wafer shape.

[0028] The second semiconductor substrate 200 may be directly bonded to the first semiconductor substrate 100. Since the opposing surfaces of the second semiconductor substrate 200 and the first semiconductor substrate 100 are in close contact with each other, the second semiconductor substrate 200 and the first semiconductor substrate 100 may be bonded to each other without intervening other separation members therebetween. A separate adhesive material or underfill material is not introduced to the bonding interface where the second semiconductor substrate 200 is directly bonded to the first semiconductor substrate 100. Directly bonding the substrates in this manner may indicate a method of hybrid bonding substrates.

[0029] Figure 2 It is an example Figure 1 FIG. 1 is a cross-sectional view of a first semiconductor substrate 100 of a semiconductor device 10 .

[0030] Reference Figure 2 and Figure 1 , the first semiconductor substrate 100 may include a first semiconductor substrate body 110, a first through hole 120, and a first diffusion barrier layer 140. The first semiconductor substrate 100 may further include a second multilayer interconnect structure 131, a connection pad 150, and an external connector 160. The first semiconductor substrate 100 may also include a first side barrier layer 126 and a first buffer layer 125.

[0031] The first semiconductor substrate body 110 may include silicon (Si) or other semiconductor materials. The first semiconductor substrate body 110 may include a first surface 110B and a seventh surface 110F facing each other in the up-down direction. The seventh surface 110F of the first semiconductor substrate body 110 may be a front side providing an active area (not shown) in which an integrated circuit element is integrated. The first surface 110B of the first semiconductor substrate body 110 may be a rear side located on the opposite side of the seventh surface 110F. No integrated circuit is integrated on the first surface 110B of the first semiconductor substrate body 110.

[0032] The first diffusion barrier layer 140 may be provided to cover the first surface 110B of the first semiconductor substrate body 110. The first diffusion barrier layer 140 may include a dielectric material or an insulating material. The first diffusion barrier layer 140 may include a diffusion barrier material capable of reducing or preventing the diffusion of copper (Cu) ions relative to silicon oxide. The first diffusion barrier layer 140 may include a silicon nitride (Si3N4) layer. In an embodiment, the first diffusion barrier layer 140 may include a silicon carbonitride (SiCN) layer. Another dielectric layer may be further introduced between the first diffusion barrier layer 140 and the first surface 110B of the first semiconductor substrate body 110.

[0033] The first through hole 120 may be introduced as a vertical connection element substantially penetrating the first semiconductor substrate body 110 in the up-down direction. The first through hole 120 may be introduced as a through silicon via (TSV) element. The first through hole 120 may be provided as a conductive pattern extending from the seventh surface 110F of the first semiconductor substrate body 110 to at least the first surface 110B. The first through hole 120 may extend to protrude above the first surface 110B of the first semiconductor substrate body 110. The first through hole 120 may further extend to substantially penetrate the first diffusion barrier layer 140.

[0034] The third surface 120B at the end of the first through hole 120 may be exposed to the second surface 140B of the first diffusion barrier layer 140. The third surface 120B at the end of the first through hole 120 and the second surface 140B of the first diffusion barrier layer 140 may have substantially the same surface height. The third surface 120B at the end of the first through hole 120 and the second surface 140B of the first diffusion barrier layer 140 may provide an overall flat surface connected to each other without a step therebetween.

[0035] The first through hole 120 may include copper (Cu) having a lower resistivity than aluminum (Al) or polysilicon. The first side barrier layer 126 may be provided to cover the side surface 120S of the first through hole 120. The first side barrier layer 126 may be introduced as a layer that effectively prevents copper (Cu) ions from diffusing from the side surface 120S of the first through hole 120 toward the first semiconductor substrate body 110. The first side barrier layer 126 may effectively prevent the first semiconductor substrate body 110 from being contaminated by copper (Cu) by isolating the first semiconductor substrate body 110 from the first through hole 120.

[0036] The first buffer layer 125 may be disposed on one side of the first side barrier layer 126. The first buffer layer 125 may be disposed between the first diffusion barrier layer 140 and the first side barrier layer 126 and between the first semiconductor substrate body 110 and the first side barrier layer 126. The first side barrier layer 126 may be located between the first diffusion barrier layer 140 and the first through hole 120 while substantially isolating the first semiconductor substrate body 110 from the first through hole 120.

[0037] The first side barrier layer 126 may be formed of a diffusion barrier material that prevents copper (Cu) ions of the first through hole 120 from diffusing. The first side barrier layer 126 may include a tantalum nitride (TaN) layer. The first buffer layer 125 may be introduced as a layer that isolates the first side barrier layer 126 from the first semiconductor substrate body 110. The first buffer layer 125 may be introduced as a layer that relieves or reduces stress that may occur between the first side barrier layer 126 and the first semiconductor substrate body 110. The first buffer layer 125 may be introduced as a layer that relieves or reduces stress that may be involved between the first through hole 120 and the first semiconductor substrate body 110. The first buffer layer 125 may include a silicon oxide (SiO2) layer made of a material such as tetraethoxysilane (TEOS).

[0038] The first semiconductor substrate 100 may further include a second multilayer interconnect structure 131 electrically connected to the first through hole 120. The second multilayer interconnect structure 131 may be disposed over the seventh surface 110F of the first semiconductor substrate body 110. The second multilayer interconnect structure 131 may include a plurality of interconnect layers connected to each other. The second multilayer interconnect structure 131 may be located in the first dielectric layer 132 and may be insulated by the first dielectric layer 132. Some portions of the second multilayer interconnect structure 131 may be electrically connected to the first through hole 120. Other portions of the second multilayer interconnect structure 131 may be electrically connected to an integrated circuit element (not shown) integrated over the seventh surface 110F of the first semiconductor substrate body 110.

[0039] The first semiconductor substrate 100 may further include a connection pad 150 disposed above the seventh surface 110F of the first semiconductor substrate body 110. The connection pad 150 may be provided to be electrically connected to a conductive pattern of the second multilayer interconnect structure 131. The connection pad 150 may be provided to be a conductive pattern including a metal material such as aluminum (Al) or copper (Cu). The second dielectric layer 180 may be provided to cover and protect the first dielectric layer 132 while exposing the connection pad 150. The second dielectric layer 180 may be introduced as a passivation layer.

[0040] The external connector 160 may be connected to the connection pad 150. The external connector 160 may be introduced as a connection element that electrically connects the semiconductor device 10 to one or more other external electronic devices or electronic modules or one or more other printed circuit boards (PCBs). The external connector 160 may be introduced as a connection element such as a conductive bump or a solder ball.

[0041] Figure 3 It is an example Figure 1 1 is a cross-sectional view of a second semiconductor substrate 200 of a semiconductor device 10.

[0042] Reference Figure 3and Figure 1 The second semiconductor substrate 200 may include a second semiconductor substrate body 210, a second diffusion barrier layer 280, and a front pad 260. The second semiconductor substrate 200 may further include a base pad 250 and a first multilayer interconnect structure 231. The second semiconductor substrate 200 may further include a second through hole 220, a second side barrier layer 226, and a second buffer layer 225.

[0043] The second semiconductor substrate body 210 may be disposed on the first semiconductor substrate body 110. The second semiconductor substrate body 210 may include silicon (Si) or other semiconductor materials. The second semiconductor substrate body 210 may include a fourth surface 210F and a tenth surface 210B facing each other in the up-down direction. The fourth surface 210F of the second semiconductor substrate body 210 may be a front side providing an active region (not shown), in which an integrated circuit element (not shown) is integrated. The tenth surface 210B of the second semiconductor substrate body 210 may be a rear side located on the opposite side of the fourth surface 210F. No integrated circuit is integrated on the tenth surface 210B of the second semiconductor substrate body 210.

[0044] The second diffusion barrier layer 280 may be provided to cover the fourth surface 210F of the second semiconductor substrate body 210. The fourth surface 210F of the second semiconductor substrate body 210 may be a surface facing the first semiconductor substrate body 110. The second diffusion barrier layer 280 may be introduced as a layer facing the first diffusion barrier layer 140. The second diffusion barrier layer 280 may include a fifth surface 280F facing the second surface 140B of the first diffusion barrier layer 140. The fifth surface 280F of the second diffusion barrier layer 280 or a portion of the fifth surface 280F may be directly bonded to the second surface 140B of the first diffusion barrier layer 140. The second surface 140B of the first diffusion barrier layer 140 and the fifth surface 280F of the second diffusion barrier layer 280 may be surfaces directly bonded to each other by direct bonding. No adhesive layer or other layer is interposed between the second surface 140B and the fifth surface 280F. For direct bonding, the second diffusion barrier layer 280 and the first diffusion barrier layer 140 may be introduced as layers of substantially the same dielectric material.

[0045] The second diffusion barrier layer 280 may include a dielectric material or an insulating material. The second diffusion barrier layer 280 may include a diffusion barrier material capable of reducing or preventing copper (Cu) ions from diffusing relative to silicon oxide. The second diffusion barrier layer 280 may include a silicon nitride (Si3N4) layer. In an embodiment, the second diffusion barrier layer 280 may include a silicon carbonitride (SiCN) layer. One or more other dielectric layers may be further introduced between the second diffusion barrier layer 280 and the fourth surface 210F of the second semiconductor substrate body 210.

[0046] The front pad 260 may be disposed to be exposed by the second diffusion barrier layer 280. The front pad 260 may be a conductive pattern having a sixth surface 260F exposed to a fifth surface 280F of the second diffusion barrier layer 280. The sixth surface 260F of the front pad 260 and the fifth surface 280F of the second diffusion barrier layer 280 may have substantially the same surface height. The sixth surface 260F of the front pad 260 and the fifth surface 280F of the second diffusion barrier layer 280 may provide overall flat surfaces connected to each other without a step therebetween.

[0047] The front pad 260 may be a conductive pattern that substantially vertically penetrates the second diffusion barrier layer 280. The sixth surface 260F of the front pad 260 may be directly bonded to the third surface 120B of the first through hole 120 of the first semiconductor substrate 100. The sixth surface 260F of the front pad 260 and the third surface 120B of the first through hole 120 may be surfaces that are directly bonded to each other by direct bonding. There is no adhesive layer or other layer interposed between the sixth surface 260F of the front pad 260 and the third surface 120B of the first through hole 120. In order to allow the sixth surface 260F of the front pad 260 and the third surface 120B of the first through hole 120 to be directly bonded and coupled to each other, the front pad 260 and the first through hole 120 may include substantially the same conductive material. The front pad 260 and the first through hole 120 may each include a conductive layer containing copper (Cu).

[0048] In order to increase the possibility that the front pad 260 will be located in the area of ​​the third surface 120B of the first through hole 120 without leaving the area of ​​the third surface 120B, the surface area A1 of the sixth surface 260F of the front pad 260 may be smaller than the surface area A3 of the third surface 120B of the first through hole 120. The front pad 260 may be formed as a conductive pattern having a diameter smaller than the diameter of the first through hole 120. Therefore, when the second semiconductor substrate 200 is vertically stacked on the first semiconductor substrate 100, the margin that the front pad 260 can be located in the area of ​​the third surface 120B of the first through hole 120 without leaving the area of ​​the third surface 120B of the first through hole 120 may be improved. The alignment margin of the second semiconductor substrate 200 with respect to the first semiconductor substrate 100 may be improved.

[0049] The surface area A1 of the sixth surface 260F of the front pad 260 is smaller than the surface area A3 of the third surface 120B of the first through hole 120, so that some portions of the second diffusion barrier layer 280 can extend to cover the portion of the third surface 120B of the first through hole 120 that is exposed outside the sixth surface 260F of the front pad 260. Therefore, by the covering portion of the second diffusion barrier layer 280, copper (Cu) ions can be effectively blocked or prevented from diffusing from the portion of the third surface 120B of the first through hole 120 that is exposed outside the sixth surface 260F of the front pad 260 to other regions.

[0050] The front pad 260 may be connected to the base pad 250. The base pad 250 may be introduced as a conductive pattern supporting the front pad 260. The base pad 250 may be a conductive pattern having a line width greater than that of the front pad 260. The base pad 250 may include the same conductive material as the front pad 260. The base pad 250 may include a metal pad containing copper (Cu). The base pad 250 may be a metal pad containing aluminum (Al).

[0051] The first multilayer interconnect structure 231 may be electrically connected to the base pad 250. The first multilayer interconnect structure 231 may be disposed over the fourth surface 210F of the second semiconductor substrate body 210. The first multilayer interconnect structure 231 may include a plurality of interconnect layers connected to each other. The first multilayer interconnect structure 231 may be located in the second dielectric layer 232 and may be isolated by the second dielectric layer 232. Some portions of the first multilayer interconnect structure 231 may be electrically connected to an integrated circuit element (not shown) integrated over the fourth surface 210F of the second semiconductor substrate body 210.

[0052] Other portions of the first multilayer interconnect structure 231 may be electrically connected to the second through-hole 220. The second through-hole 220 may be introduced as a vertical connection element that substantially vertically penetrates the second semiconductor substrate body 210. The second through-hole 220 may be introduced as a through-silicon via (TSV) element. The second through-hole 220 may be provided as a conductive pattern extending from the fourth surface 210F of the second semiconductor substrate body 210 at least to the tenth surface 210B. The second through-hole 220 may extend to protrude above the tenth surface 210B of the second semiconductor substrate body 210. The second through-hole 220 may further extend to substantially vertically penetrate the third diffusion barrier layer 240. The eighth surface 220B at the end of the second through-hole 220 may be exposed to the eleventh surface 240B of the third diffusion barrier layer 240. The surface area A2 of the eighth surface 220B at the end of the second through-hole 220 may be greater than the surface area A1 of the sixth surface 260F of the front pad 260. The surface area A2 of the eighth surface 220B at the end of the second through-hole 220 may be greater than the surface area A1 of the sixth surface 260F of the front pad 260. Figure 2The surface areas A3 of the third surfaces 120B of the first through holes 120 in FIG. 1 are substantially the same.

[0053] The third diffusion barrier layer 240 may be provided to cover the tenth surface 210B of the second semiconductor substrate body 210. The third diffusion barrier layer 240 may be provided as a layer including a dielectric material or an insulating material. The third diffusion barrier layer 240 may include a diffusion barrier material capable of reducing or preventing copper (Cu) ions from diffusing relative to silicon oxide. The third diffusion barrier layer 240 may include a silicon nitride (Si3N4) layer. In an embodiment, the third diffusion barrier layer 240 may include a silicon carbonitride (SiCN) layer.

[0054] The second through hole 220 may include copper (Cu) having a lower resistivity than aluminum (Al) or polysilicon. The second side barrier layer 226 may be provided to cover the side surface 220S of the second through hole 220. The second side barrier layer 226 may be introduced as a layer that effectively prevents copper (Cu) ions from diffusing from the side surface 220S of the second through hole 220 to the second semiconductor substrate body 210. The second buffer layer 225 may be provided on the side surface of the second side barrier layer 226. The second side barrier layer 226 may be formed of a diffusion barrier material that prevents the diffusion of copper (Cu) ions of the second through hole 220. The second side barrier layer 226 may include a tantalum nitride (TaN) layer. The first buffer layer 225 may include a silicon oxide (SiO2) layer prepared from a material such as tetraethoxysilane (TEOS).

[0055] Figure 4 It is an example Figure 1 FIG. 1 is a cross-sectional view of an enlarged bonding structure of the first through hole 120 and the front pad 260. FIG. Figure 5 2 is a cross-sectional view illustrating copper contamination in a bonding structure 1R of a through hole 12L and a pad 26U according to a comparative example.

[0056] Reference Figure 4, the second semiconductor substrate 200 can be directly bonded to the first semiconductor substrate 100 while being stacked on the first semiconductor substrate 100. The surface area A3 of the third surface 120B of the first through hole 120 is larger than the surface area A1 of the sixth surface 260F of the front pad 260, so that the alignment margin M of the front pad 260 relative to the first through hole 120 can be improved according to the difference between the diameter of the first through hole 120 and the diameter of the front pad 260. The larger the difference between the surface area A3 of the third surface 120B of the first through hole 120 and the surface area A1 of the sixth surface 260F of the front pad 260, the larger the difference between the diameter of the first through hole 120 and the diameter of the front pad 260 and the alignment margin M of the front pad relative to the first through hole can be increased. The larger the alignment margin M, the higher the possibility that the front pad 260 will be located within the third surface 120B of the first through hole 120. As the alignment margin M increases, the possibility that the front pad 260 overlaps the first buffer layer 125 outside the third surface 120B of the first through hole 120 can be reduced.

[0057] In accordance with Figure 5 In the bonding structure 1R of the through hole 12L and the pad 26U of the comparative example, the diameter D1 of the pad 26U of the upper semiconductor substrate 1U is larger than the diameter D2 of the through hole 12L of the lower semiconductor substrate 1L. In this case, the pad 26U of the upper semiconductor substrate 1U may overlap with the buffer layer 15L of the lower semiconductor substrate 1L. When the pad 26U is formed of copper (Cu), copper (Cu) ions may diffuse from the pad 26U to the lower semiconductor substrate body 11L through the silicon oxide of the buffer layer 15L. Due to the diffusion of copper (Cu) ions, the lower semiconductor substrate body 11L may be contaminated by copper (Cu) ions.

[0058] However, in Figure 4 In the bonding structure of the first through hole 120 and the front pad 260, the front pad 260 has a smaller diameter than the first through hole 120, so that the front pad 260 can be located within the third surface 120B of the first through hole 120. Therefore, the possibility of the front pad 260 overlapping with the first buffer layer 125 can be reduced, thereby reducing or preventing copper (Cu) ions from diffusing from the front pad 260 containing copper (Cu) to the first semiconductor substrate body 110. Therefore, the occurrence of copper (Cu) contamination in the first semiconductor substrate body 110 can be effectively suppressed, prevented or reduced.

[0059] The diameter of the front pad 260 may be 1 / 2 to 1 / 6 times the diameter of the first through hole 120. The surface area A1 of the sixth surface 260F of the front pad 260 is 1 / 4 to 1 / 36 times the surface area A3 of the third surface 120B of the first through hole 120. The front pad 260 may have a diameter of about 1.0 μm to 2.0 μm, and the first through hole 120 may have a diameter of 4.0 μm to 6.0 μm.

[0060] Figure 6 is a cross-sectional view illustrating a semiconductor device 30 according to an embodiment.

[0061] and Figure 4 and Figure 5 Refer to Figure 6 , the semiconductor device 30 may include a structure in which the third semiconductor substrate 200-1 is directly bonded to a structure in which the second semiconductor substrate 200 is directly bonded to the first semiconductor substrate 100. The structure in which the second semiconductor substrate 200 is directly bonded to the first semiconductor substrate 100 may have the same Figure 1 The third semiconductor substrate 200-1 may have a substantially same structure as the semiconductor device 10 of the reference Figure 1 and Figure 3 The second semiconductor substrate 200 is described to have substantially the same structure.

[0062] The third semiconductor substrate 200-1 may include another front pad 360 corresponding to the front pad 260 of the second semiconductor substrate 200. The ninth surface 360F of the front pad 360 of the third semiconductor substrate 200-1 may be directly bonded to the eighth surface 220B at the end of the second through hole 220.

[0063] Figures 7 to 10 This is an example of manufacturing Figure 1 1 is a cross-sectional view of a process step of a method for manufacturing a semiconductor device 10 .

[0064] Reference Figure 7 A first multilayer interconnect structure 231 may be formed over the fourth surface 210F of the second semiconductor substrate body 210 of the second semiconductor substrate 200. A base pad 250 may be formed to be connected to the first multilayer interconnect structure 231. A second through hole 220 may be provided in the second semiconductor substrate body 210.

[0065] Reference Figure 8 , a second diffusion barrier layer 280 may be formed to cover the fourth surface 210F of the second semiconductor substrate body 210. The second diffusion barrier layer 280 may be formed to cover the second dielectric layer 232 insulating the first multilayer interconnect structure 231. A resist pattern 290 may be formed on the fifth surface 280F of the second diffusion barrier layer 280. The resist pattern 290 may be formed on the front pad ( Figure 1 The resist pattern 290 may be formed by coating, exposing, and developing a photoresist layer.

[0066] Portions of the second diffusion barrier layer 280 exposed by the resist pattern 290 may be selectively removed to form damascene holes 280H. A selective etching process using the resist pattern 290 as an etching mask may be performed to form damascene holes 280H in the second diffusion barrier layer 280.

[0067] Reference Fig. 9 , a conductive layer 260L may be formed to fill the damascene hole 280H. The conductive layer 260L may be formed by a copper (Cu) electroplating process. The conductive layer 260L may be partially removed to a certain thickness so that a portion of the conductive layer remains in the damascene hole 280H. In an embodiment, the conductive layer 260L may be partially removed to a predetermined thickness so that a portion of the conductive layer remains in the damascene hole 280H. The remaining portion of the conductive layer may be patterned as a front pad ( Figure 3 260). Front pad ( Figure 3 260) can be patterned to be located in the mosaic hole ( Figure 3 The term "predetermined" as used herein for a parameter (such as a predetermined thickness) means that the value of the parameter is determined before the parameter is used in a process or algorithm. For some embodiments, the value of the parameter is determined before the process or algorithm begins. In other embodiments, the value of the parameter is determined during the process or algorithm but before the parameter is used in the process or algorithm.

[0068] Reference Fig.10 The second semiconductor substrate 200 may be formed to include a second diffusion barrier layer 280 substantially covering the fourth surface 210F of the second semiconductor substrate body 210 and a front pad 260, wherein a sixth surface 260F exposed to the fifth surface 280F of the second diffusion barrier layer 280 in the front pad has a smaller surface area Al than the third surface 120B of the first through hole 120.

[0069] The first semiconductor substrate 100 may be formed to include a first diffusion barrier layer 140 covering a first surface 110B of the first semiconductor substrate body 110 , and a first through hole 120 in which a third surface 120B is exposed to a second surface 140B of the first diffusion barrier layer 140 .

[0070] The second semiconductor substrate 200 may be stacked on the first semiconductor substrate 100. While a portion of the fifth surface 280F of the second diffusion barrier layer 280 is directly bonded to the second surface 140B of the first diffusion barrier layer 140, the sixth surface 260F of the front pad 260 may be directly bonded to the third surface 120B of the first through hole 120. Therefore, since the first semiconductor substrate 100 and the second semiconductor substrate 200 are directly bonded, the semiconductor device 10 including the stack of the first semiconductor substrate 100 and the second semiconductor substrate 200 may be implemented.

[0071] Fig.11 7800 is a block diagram illustrating an electronic system including a memory card 7800 using at least one of the semiconductor packages according to the embodiments. The memory card 7800 includes a memory 7810 such as a nonvolatile memory device and a memory controller 7820. The memory 7810 and the memory controller 7820 may store data or read out the stored data. At least one of the memory 7810 and the memory controller 7820 may include at least one of the semiconductor packages according to the embodiments.

[0072] The memory 7810 may include a nonvolatile memory device to which the technology of the embodiments of the present disclosure is applied. The memory controller 7820 may control the memory 7810 in response to a read / write request from the host 7830 so that stored data is read out or stored.

[0073] Fig.12 8710 is a block diagram illustrating an electronic system 8710 including at least one of the semiconductor packages according to the embodiment. The electronic system 8710 may include a controller 8711, an input / output device 8712, and a memory 8713. The controller 8711, the input / output device 8712, and the memory 8713 may be connected to each other through a bus 8715 that provides a path through which data moves.

[0074] In an embodiment, the controller 8711 may include one or more microprocessors, digital signal processors, microcontrollers, and / or logic devices capable of performing the same functions as these components. The controller 8711 or the memory 8713 may include at least one of the semiconductor packages according to the embodiments of the present disclosure. The input / output device 8712 may include at least one selected from a keypad, a keyboard, a display device, a touch screen, etc. The memory 8713 is a device for storing data. The memory 8713 may store data and / or commands to be executed by the controller 8711, etc.

[0075] The memory 8713 may include a volatile memory device such as a DRAM and / or a non-volatile memory device such as a flash memory. For example, the flash memory may be installed in an information processing system such as a mobile terminal or a desktop computer. The flash memory may constitute a solid state drive (SSD). In this case, the electronic system 8710 may stably store a large amount of data in the flash memory system.

[0076] The electronic system 8710 may further include an interface 8714 configured to send and receive data to and from a communication network. The interface 8714 may be of a wired type or a wireless type. For example, the interface 8714 may include an antenna, or a wired or wireless transceiver.

[0077] The electronic system 8710 may be implemented as a mobile system, a personal computer, an industrial computer, or a logic system that performs various functions. For example, the mobile system may be any one of a personal digital assistant (PDA), a portable computer, a tablet computer, a mobile phone, a smart phone, a wireless phone, a laptop computer, a memory card, a digital music system, and an information transmission / reception system.

[0078] If the electronic system 8710 is a device capable of performing wireless communications, the electronic system 8710 can be used in a communication system using technology such as CDMA (Code Division Multiple Access), GSM (Global System for Mobile Communications), NADC (North American Digital Cellular), E-TDMA (Enhanced Time Division Multiple Access), WCDMA (Wideband Code Division Multiple Access), CDMA2000, LTE (Long Term Evolution), or Wibro (Wireless Broadband Internet).

[0079] These concepts have been disclosed in conjunction with some of the embodiments described above. Those skilled in the art will appreciate that various modifications, additions, and substitutions may be made without departing from the scope and spirit of the present disclosure. Therefore, the embodiments disclosed in this specification should not be considered from a restrictive point of view but from an exemplary point of view. The scope of the concept is not limited to the above description, but is defined by the appended claims, and all different features within the scope of equivalents should all be interpreted as being included in the concept.

[0080] CROSS-REFERENCE TO RELATED APPLICATIONS

[0081] This application claims priority from Korean Application No. 10-2020-0062611, filed on May 25, 2020, which is hereby incorporated by reference in its entirety.

Claims

1. A semiconductor device, comprising: a first semiconductor substrate; as well as a second semiconductor substrate vertically stacked on the first semiconductor substrate, Wherein, the first semiconductor substrate comprises: a first semiconductor substrate body; a first diffusion barrier layer covering a first surface of the first semiconductor substrate body; and a first through hole having a third surface exposed to the second surface of the first diffusion barrier layer, Wherein, the second semiconductor substrate comprises: a second semiconductor substrate body, the second semiconductor substrate body being disposed on the first semiconductor substrate body; a second diffusion barrier layer covering a fourth surface of the second semiconductor substrate body facing the first semiconductor substrate body, a portion of a fifth surface of the second diffusion barrier layer being directly bonded to the second surface of the first diffusion barrier layer; and a front pad having a sixth surface exposed to the fifth surface of the second diffusion barrier layer, the sixth surface having a smaller surface area than the third surface of the first through hole and directly bonded to the third surface of the first through hole of the first semiconductor substrate, wherein the second semiconductor substrate is directly bonded to the first semiconductor substrate, The first diffusion barrier layer includes at least one of silicon nitride Si3N4 and silicon carbonitride SiCN, and the second diffusion barrier layer includes at least one of silicon nitride Si3N4 and silicon carbonitride SiCN.

2. The semiconductor device according to claim 1, wherein A portion of the second diffusion barrier layer extends to cover a portion of the third surface of the first via hole exposed outside the sixth surface of the front pad.

3. The semiconductor device according to claim 1, wherein The first through hole extends to penetrate the first diffusion barrier layer and the first semiconductor substrate body.

4. The semiconductor device according to claim 2, further comprising: a first side barrier layer, the first side barrier layer covering a side surface of the first through hole; as well as A first buffer layer is disposed between the first diffusion barrier layer and the first side barrier layer and between the first semiconductor substrate body and the first side barrier layer.

5. The semiconductor device according to claim 4, wherein: The first via comprises copper (Cu), the first side barrier layer comprises tantalum nitride (TaN), and the first buffer layer comprises silicon oxide (SiO 2 ).

6. The semiconductor device according to claim 1, wherein The front pad includes copper Cu.

7. The semiconductor device according to claim 1, further comprising a base pad connected to the front pad, in, The base pad is wider than the front pad.

8. The semiconductor device according to claim 7, wherein: The base pad includes the same material as the front pad.

9. The semiconductor device according to claim 7, wherein: The base pad includes at least one of copper (Cu) and aluminum (Al). 10 . The semiconductor device according to claim 7 , further comprising a first multi-layer interconnect structure electrically connected to the base pad.

11. The semiconductor device according to claim 1, further comprising: a second multilayer interconnect structure disposed on a seventh surface of the first semiconductor substrate body opposite to the first surface and electrically connected to the first through hole; a connection pad connected to the second multi-layer interconnect structure; as well as An external connector is connected to the connection pad.

12. A semiconductor device, comprising: a first semiconductor substrate; as well as a second semiconductor substrate vertically stacked on the first semiconductor substrate, Wherein, the first semiconductor substrate comprises: a first semiconductor substrate body; a first diffusion barrier layer covering a first surface of the first semiconductor substrate body; and a first through hole having a third surface exposed to the second surface of the first diffusion barrier layer, Wherein, the second semiconductor substrate comprises: a second semiconductor substrate body, the second semiconductor substrate body being disposed on the first semiconductor substrate body; a second diffusion barrier layer covering a fourth surface of the second semiconductor substrate body facing the first semiconductor substrate body, a portion of a fifth surface of the second diffusion barrier layer being directly bonded to the second surface of the first diffusion barrier layer; a front pad having a sixth surface exposed to the fifth surface of the second diffusion barrier layer, the sixth surface having a smaller surface area than the third surface of the first through hole and directly bonded to the third surface of the first through hole of the first semiconductor substrate; and a second through hole electrically connected to the front pad and penetrating the second semiconductor substrate body, wherein the second semiconductor substrate is directly bonded to the first semiconductor substrate, The first diffusion barrier layer includes at least one of silicon nitride Si3N4 and silicon carbonitride SiCN, and the second diffusion barrier layer includes at least one of silicon nitride Si3N4 and silicon carbonitride SiCN.

13. The semiconductor device according to claim 12, further comprising: a base pad connected to the front pad, the base pad being wider than the front pad; a first multi-layer interconnect structure electrically connected to the base pad, Wherein, the second through hole is electrically connected to the first multi-layer interconnection structure. 14 . The semiconductor device according to claim 13 , further comprising a third semiconductor substrate including another front pad having a ninth surface directly bonded to the eighth surface at an end of the second through hole.

15. The semiconductor device according to claim 12, further comprising: a second multi-layer interconnect structure disposed on a seventh surface of the first semiconductor substrate body opposite to the first surface and electrically connected to the first through hole; a connection pad connected to the second multi-layer interconnect structure; as well as An external connector is connected to the connection pad.

16. The semiconductor device according to claim 12, wherein: A portion of the second diffusion barrier layer extends to cover a portion of the third surface of the first via hole exposed outside the sixth surface of the front pad.

17. A method for manufacturing a semiconductor device, the method comprising the steps of: forming a first semiconductor substrate including a first diffusion barrier layer covering a first surface of a first semiconductor substrate body and a first through hole having a third surface exposed to a second surface of the first diffusion barrier layer; forming a second semiconductor substrate including a second diffusion barrier layer covering a fourth surface of a second semiconductor substrate body facing the first semiconductor substrate body and a front pad having a sixth surface exposed to a fifth surface of the second diffusion barrier layer, the sixth surface having a smaller surface area than the third surface of the first through hole; as well as laminating the second semiconductor substrate on the first semiconductor substrate to directly bond a portion of the fifth surface of the second diffusion barrier layer to the second surface of the first diffusion barrier layer and to directly bond the sixth surface of the front pad to the third surface of the first through hole, wherein the second semiconductor substrate is directly bonded to the first semiconductor substrate, The first diffusion barrier layer includes at least one of silicon nitride Si3N4 and silicon carbonitride SiCN, and the second diffusion barrier layer includes at least one of silicon nitride Si3N4 and silicon carbonitride SiCN.

18. The method according to claim 17, wherein: The front pad is formed by the following steps: forming a resist pattern on the fifth surface of the second diffusion barrier layer; selectively removing a portion of the second diffusion barrier layer exposed by the resist pattern to form a damascene hole; forming a conductive layer to fill the damascene hole; as well as The conductive layer is removed to a predetermined thickness to pattern the conductive layer into the front pad located in the damascene hole.

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