Three-dimensional flash memory and method of operating the same

Abstract

Disclosed is a three-dimensional flash memory. According to one embodiment, the three-dimensional flash memory has a structure in which a boost area is reduced, a structure to which a small block is applied, a structure to which a COP is applied and a wiring process is simplified, or a structure to which a symmetric U-shaped BiCs is applied.

Description

TECHNICAL FIELD

[0001] Embodiments below relate to a three-dimensional (3D) flash memory and an operating method thereof. BACKGROUND

[0002] A flash memory device is an electrically erasable programmable read-only memory (EEPROM) that can be generally used in, for example, a computer, a digital camera, an MPEG-1 audio layer 3 (MP3) player, a game system, a memory stick, etc. The flash memory device electrically controls input and output of data by Fowler-Nordheim (F-N) tunneling or hot electron injection.

[0003] In detail, referring to FIG. 1 showing an array of a conventional three-dimensional (3D) flash memory, Figure 1 The array of the 3D flash memory can include a common source line CSL, a bit line BL, and a plurality of cell strings CSTR connected in parallel between the common source line CSL and the bit line BL.

[0004] The bit line BL can be arranged two-dimensionally, and the plurality of cell strings CSTR can be connected in parallel to each bit line BL. The cell strings CSTR can be commonly connected to the common source line CSL. That is, the plurality of cell strings CSTR can be between a plurality of bit lines BL and one common source line CSL. In this case, the common source line CSL can be provided as a plurality, and the plurality of common source lines CSL can be arranged two-dimensionally between electrode structures 215. Here, the same voltage can be applied to the plurality of common source lines CSL. Alternatively, each of the plurality of common source lines CSL can be electrically controlled.

[0005] Each cell string CSTR can include a ground select transistor GST connected to the common source line CSL, a string select transistor SST connected to the bit line BL, and a plurality of memory cell transistors MCT between the ground select transistor GST and the string select transistor SST. Further, the ground select transistor GST, the string select transistor SST, and the memory cell transistor MCT can be connected in series.

[0006] The common source line CSL can be commonly connected to a source of the ground select transistor GST. Further, a ground select line GSL, a plurality of word lines (e.g., WL0 to WL3), and a plurality of string select lines SSL between the common source line CSL and the bit line BL can be used as electrode layers of the ground select transistor GST, the memory cell transistor MCT, and the string select transistor SST, respectively. Further, each memory cell transistor MCT can include a storage element. Hereinafter, the string select line SSL can be expressed as an upper select line (USL), and the ground select line GSL can be expressed as a lower select line (LSL).

[0007] Meanwhile, in order to meet consumers' demands for superior performance and low prices, conventional 3D NAND flash memory increases integration density by vertically stacking cells.

[0008] For example, a reference is made to the structure of a conventional 3D flash memory. Figure 2 Conventional 3D NAND flash memory is fabricated by arranging electrode structures 215 on a substrate 200, with interlayer insulating layers 211 and horizontal structures 250 alternately and repeatedly arranged in the electrode structures 215. The interlayer insulating layers 211 and horizontal structures 250 can extend in a first direction. The interlayer insulating layer 211 can be, for example, a silicon oxide film. The lowermost interlayer insulating layer 211a can have a smaller thickness than the other interlayer insulating layers 211. Each horizontal structure 250 may include a first barrier insulating film 242, a second barrier insulating film 243, and an electrode layer 245. Multiple electrode structures 215 can be provided, and the multiple electrode structures 215 can be arranged to face each other in a second direction intersecting the first direction. The first direction and the second direction can respectively correspond to... Figure 2 The x-axis and y-axis. Trench 240, configured to space multiple electrode structures 215 apart from each other, may extend between the multiple electrode structures 215 in a first direction. Common source line CSL may be arranged by forming heavily doped impurity regions in the substrate 200 exposed by trench 240. Although not shown, an insulating film may be further disposed to fill trench 240.

[0009] Vertical structures 230 can be configured to pass through electrode structures 215. As an example, in a view viewed from above, vertical structures 230 can be arranged in a matrix in both a first and a second direction. In another example, vertical structures 230 can be arranged in the second direction and positioned in a zigzag pattern in the first direction. Each vertical structure 230 may include a protective film 224, a charge storage film 225, a tunnel insulating film 226, and a channel layer 227. In an example, the channel layer 227 can be arranged in the form of a hollow tube. In this case, a buried film 228 can be further disposed to fill the interior of the channel layer 227. A drain region D can be on the channel layer 227, and a conductive pattern 229 can be formed on the drain region D and connected to a bit line BL. The bit line BL can extend in a direction intersecting the horizontal electrode 250 (e.g., the second direction). In an example, vertical structures 230 arranged in the second direction can be connected to a bit line BL.

[0010] The first barrier insulating film 242 and the second barrier insulating film 243 included in the horizontal structure 250, and the charge storage film 225 and the tunnel insulating film 226 included in the vertical structure 230, can be defined by an oxide-nitride-oxide (ONO) layer, which is the information storage element of the 3D flash memory. That is, a portion of the information storage element can be included in the vertical structure 230, and the remainder can be included in the horizontal structure 250. In the example of the information storage element, the charge storage film 225 and the tunnel insulating film 226 can be included in the vertical structure 230, and the first barrier insulating film 242 and the second barrier insulating film 243 can be included in the horizontal structure 250.

[0011] The epitaxial pattern 222 may be located between the substrate 200 and the vertical structure 230. The epitaxial pattern 222 may connect the substrate 200 to the vertical structure 230. The epitaxial pattern 222 may contact at least one layer of the horizontal structure 250. That is, the epitaxial pattern 222 may contact the lowermost horizontal structure 250a. According to another embodiment, the epitaxial pattern 222 may contact multiple layers (e.g., two layers) of the horizontal structure 250. Simultaneously, when the epitaxial pattern 222 contacts the lowermost horizontal structure 250a, the lowermost horizontal structure 250a may be arranged to have a greater thickness than the other horizontal structures 250. The lowermost horizontal structure 250a that contacts the epitaxial pattern 222 may correspond to a reference. Figure 1 The ground selection line GSL of the described 3D flash memory array, and the remaining horizontal structures 250 that are in contact with the vertical structure 230 may correspond to multiple word lines (e.g., WL0 to WL3).

[0012] Each extensional pattern 222 may have a recessed sidewall 222a. Therefore, the lowest horizontal structure 250a in contact with the extensional pattern 222 may be arranged along the contour of the recessed sidewall 222a. That is, the lowest horizontal structure 250a may be arranged in an inwardly convex shape along the recessed sidewall 222a of the extensional pattern 222.

[0013] In conventional 3D NAND flash memory with the above structure, the boosting area increases with the increase in the vertical stacking number of cells. This leads to problems such as reduced speed and increased power consumption during programming operations related to the pass voltage applied to the unselected word line, and increased body potential rise time and hole injection time during erase operations.

[0014] Therefore, a technology is needed to solve the above problems.

[0015] Meanwhile, block-based techniques have been proposed to improve the efficiency of erase operations in 3D NAND flash memory. A block refers to the smallest unit in which the memory area to be erased is grouped.

[0016] However, a problem arises in applying small blocks: word line routing, configured to control the application of voltage to the vertical structure 230 in the 3D NAND flash memory, must be provided independently for each word line corresponding to a small block. Therefore, because word line routing is provided independently for each word line, sufficient space must be allocated for arranging the word line routing, resulting in a reduction in integration density.

[0017] Therefore, a technique is needed to overcome the problems and drawbacks caused by applying small blocks to the structure of conventional 3D flash memory.

[0018] Furthermore, in recent years, 3D structures in which cells are vertically stacked to increase integration density have been applied to meet consumer demands for superior performance and low cost. A reference is shown for a conventional 3D flash memory. Figure 16 The 3D NAND flash memory 1600 has a structure including a channel layer 1610 formed in a vertical direction, a charge storage layer 1620 formed around the channel layer 1610, a plurality of electrode layers 1630 connected to the charge storage layer 1620 and stacked in a horizontal direction, and a plurality of insulating layers 1640 interposed between the plurality of electrode layers 1630 to alternate with the plurality of electrode layers 1630. Hereinafter, the charge storage layer 1620 and the channel layer 1610, as components directly related to data storage and retrieval, may be referred to as a memory cell string.

[0019] The conventional 3D flash memory 1600 with the above structure can apply cell-on-periphery (COP) technology to bury the memory cell transistors 1650 (transistors directly related to the data storage and read operations of the memory cell string or transistors used to connect the memory cell string to the source electrode) and at least one peripheral transistor 1660 (transistors excluding the memory cell transistors 1650 among the transistors related to the operation of the 3D flash memory 1600) in the substrate 1670, thereby improving space utilization and increasing integration density.

[0020] However, conventional 3D flash memory 1600 has the disadvantage of complex wiring process because the memory cell transistor 1650 and at least one peripheral portion transistor 1660 are not distinguished and are buried in the substrate 1670.

[0021] Therefore, there is a need to propose a COP technology for 3D flash memory that overcomes this drawback in its application.

[0022] Furthermore, because Figure 20 and Figure 21The Bit Cost Scalable (BiCS) structure shown is applied to 3D NAND flash memory, thus further improving integration density. In the 3D NAND flash memory 200 to which the BiCS structure is applied, the string 2010 has an asymmetric structure with different heights at both ends of the U-shape, as shown in the figure. Therefore, one end of these two ends is connected to a drain line formed to extend in the x-axis direction, and the other end is connected to a source line formed to extend in the y-axis direction.

[0023] Therefore, in the 3D flash memory 2000 with a conventional BiCS structure, various problems may occur due to the string 2010 with its asymmetric structure (such as weak recognition margin due to reduced cell current during read operations, reduced speed due to increased boost area during programming operations, increased power consumption related to the pass voltage applied to the word lines due to the increased number of unselected word lines, and increased body potential rise time and hole injection time during erase operations).

[0024] Therefore, a technique is needed to solve the various problems caused by strings with asymmetric structures. Summary of the Invention

[0025] Technical issues

[0026] The implementation proposes a three-dimensional (3D) flash memory and its operation method, which reduces the boost area to improve speed during programming operations, reduces power consumption associated with the pass voltage applied to the unselected word line, and reduces the body potential rise time and hole injection time during erase operations.

[0027] More specifically, the embodiment proposes a 3D flash memory and a method of operating the same, which uses at least one of a plurality of word lines as an intermediate signal line (MSL), the intermediate signal line (MSL) being configured to shut off a portion of at least one string to perform a programming operation on a specific memory cell in the remaining portion of the string, and configured to exhaust the portion of the at least one string to perform an erasure operation on the remaining portion of the string.

[0028] Furthermore, the implementation proposes a 3D flash memory that improves integration density and the efficiency of erase operations.

[0029] More specifically, the implementation proposes a 3D flash memory that applies small blocks while allowing word line routing to be shared between word lines.

[0030] Furthermore, the implementation proposes a 3D flash memory that utilizes a peripheral cell circuit (COP) technology with simplified wiring.

[0031] More specifically, the embodiment proposes a 3D flash memory in which a substrate on which at least one string of memory cells extends is formed to be divided into a cell region and a peripheral region, at least one memory cell transistor associated with the at least one string of memory cells is formed in the cell region, and at least one peripheral region transistor is formed in the peripheral region.

[0032] The implementation proposes a technique for fundamentally solving various problems caused by strings with asymmetric structures.

[0033] More specifically, the embodiments propose a 3D flash memory and a method of operating the same, wherein in at least one string formed in a U-shape to include a horizontal portion and a vertical portion relative to a substrate, the vertical portion is symmetrical about the horizontal portion.

[0034] Furthermore, the implementation proposes a 3D flash memory and its operation method, in which a word line among multiple word lines positioned adjacent to the upper part of the horizontal portion of at least one string is used as the MSL, thus reducing the boost area and effectively solving various problems caused by strings with asymmetrical structures.

[0035] Technical solution

[0036] According to one embodiment, a three-dimensional (3D) flash memory includes: at least one string formed on a substrate to extend in one direction, wherein the at least one string includes at least one channel layer formed to extend in one direction and a charge storage layer formed around the at least one channel layer; and a plurality of word lines connected to the at least one string in a vertical direction. At least one of the plurality of word lines serves as an intermediate signal line (MSL), the intermediate signal line being configured to turn off a portion of the at least one string to perform a programming operation on a specific memory cell on the remaining portion of the string, and configured to deplete a portion of the at least one string to perform an erase operation on the remaining portion of the string.

[0037] According to one aspect of this disclosure, the 3D flash memory can shut down the portion of the at least one string by applying a shutdown voltage to the MSL for shutting down the channel, and perform programming operations on the specific memory cells on the remaining portion of the string.

[0038] According to another aspect of this disclosure, the 3D flash memory can deplete said partial region of said at least one string by applying a blocking voltage to the MSL for depleting the channel, and perform an erase operation on the remaining partial region.

[0039] According to another aspect of this disclosure, the 3D flash memory can perform an erase operation on the remaining portion of the region by floating the MSL and word lines located in the portion of the at least one string and applying a ground voltage to the word lines located in the remaining portion of the region.

[0040] According to one embodiment, a 3D flash memory for application to small blocks includes: a plurality of memory cell strings formed on a substrate to extend in one direction, each memory cell string including a channel layer and a charge storage layer surrounding the channel layer; a plurality of word lines connected in a vertical direction to the plurality of memory cell strings, the plurality of word lines being grouped into a plurality of word line groups to correspond to a plurality of small blocks respectively; and at least one switching element connected to word line wiring configured to control the plurality of word lines, the at least one switching element being configured to selectively apply a voltage to any one of the plurality of word line groups.

[0041] According to one aspect of this disclosure, word line routing can be shared among the plurality of blocks.

[0042] According to one embodiment, a 3D flash memory for application to small blocks includes: at least one memory cell string formed on a substrate to extend in one direction, each memory cell string including a channel layer and a charge storage layer surrounding the channel layer; a plurality of word lines connected in a vertical direction to the at least one memory cell string, the plurality of word lines being grouped into a plurality of word line groups to correspond to a plurality of small blocks respectively, the vertical storage regions of the at least one memory cell string being grouped into the plurality of small blocks; and at least one switching element connected to word line wiring configured to control the plurality of word lines, the at least one switching element being configured to selectively apply a voltage to any one of the plurality of word line groups.

[0043] According to one aspect of this disclosure, word line routing can be shared among the plurality of blocks.

[0044] According to one embodiment, a 3D flash memory with peripheral cell circuitry (COP) applied thereto includes: a substrate; and at least one memory cell string formed on the substrate extending in one direction, the at least one memory cell string including at least one channel layer and at least one charge storage layer surrounding the at least one channel layer. The substrate is formed to be divided into cell regions and peripheral portion regions, at least one memory cell transistor associated with the at least one memory cell string is formed in the cell regions, and at least one peripheral portion transistor is formed in the peripheral portion regions, wherein the at least one peripheral portion transistor is a remaining transistor among the transistors associated with the operation of the 3D flash memory that excludes the at least one memory cell transistor.

[0045] According to one aspect of this disclosure, the substrate can be formed as a multilayer structure in which a bulk polycrystalline silicon substrate serving as a unit region is stacked on a silicon substrate serving as a peripheral portion region.

[0046] According to another aspect of this disclosure, the substrate may be formed as a single layer, the cell region may be in a central portion, the at least one memory cell is strung on the substrate in the central portion, and the peripheral portion region may be in a peripheral portion surrounding the cell region on the substrate.

[0047] According to one embodiment, a 3D flash memory includes: at least one string formed in a U-shape to include a horizontal portion and a vertical portion relative to a substrate, the at least one string including a charge storage layer formed as a hollow tube extending and a channel layer filling the interior of the charge storage layer; a plurality of word lines orthogonal to and connected to the vertical portion of the at least one string; and two bit lines formed to extend parallel to the horizontal portion of the at least one string, the two bit lines being connected to both ends of the at least one string.

[0048] According to one aspect of this disclosure, each of the two bit lines can be selectively used as a drain line or a source line.

[0049] According to another aspect of this disclosure, the two bit lines can be on the same plane because the two ends of the at least one string are at the same height.

[0050] According to another aspect of this disclosure, one of the plurality of word lines adjacent to the upper portion of the horizontal portion of the at least one string can be used as a MSL, which is configured to exhaust any one of the vertical portions of the at least one string to perform a programming operation on a specific memory cell on the remaining vertical portion, and is configured to inject holes into all vertical portions of the at least one string to perform an erase operation on the at least one string.

[0051] Beneficial effects

[0052] An implementation may provide a three-dimensional (3D) flash memory and a method of operating the same, which uses at least one of a plurality of word lines as an intermediate signal line (MSL), the MSL being configured to shut off a portion of at least one string to perform a programming operation on a specific memory cell in the remaining portion of the string, and configured to exhaust the portion of the at least one string to perform an erasure operation on the remaining portion of the string.

[0053] Therefore, an implementation method may propose a 3D flash memory and its operation method, which reduces the boost area to increase the speed during programming operations, reduces the power consumption associated with the pass voltage applied to the unselected word line, and reduces the body potential rise time and hole injection time during erase operations.

[0054] Furthermore, the implementation proposes a 3D flash memory that applies small blocks while allowing word line routing to be shared between word lines.

[0055] Therefore, one implementation could propose a 3D flash memory that improves both integration density and erase operation efficiency.

[0056] Furthermore, an implementation method may propose a 3D flash memory that utilizes a simplified COP wiring process.

[0057] More specifically, an embodiment may provide a 3D flash memory in which a substrate on which at least one string of memory cells extends is formed is divided into a cell region and a peripheral region, at least one memory cell transistor associated with the at least one string of memory cells is formed in the cell region, and at least one peripheral region transistor is formed in the peripheral region.

[0058] The embodiments propose a 3D flash memory and a method of operating the same, wherein in at least one string formed in a U-shape to include a horizontal portion and a vertical portion relative to a substrate, the vertical portion is symmetrical about the horizontal portion.

[0059] Therefore, the implementation method can propose a technique that fundamentally solves the various problems caused by strings with asymmetric structures.

[0060] Furthermore, the implementation proposes a 3D flash memory and its operation method, in which a word line among multiple word lines positioned adjacent to the upper part of the horizontal portion of at least one string is used as the MSL. Therefore, the boost area is reduced, thereby effectively solving various problems caused by strings with asymmetrical structures. Attached Figure Description

[0061] Figure 1 This is a schematic circuit diagram of a conventional three-dimensional (3D) flash memory array.

[0062] Figure 2 This is a perspective view of the structure of a conventional 3D flash memory.

[0063] Figure 3 This is a cross-sectional view of a 3D flash memory according to one embodiment.

[0064] Figure 4 and Figure 5 yes Figure 3Cross-sectional views of various examples of 3D flash memory shown.

[0065] Figure 6 This is a flowchart of a 3D flash memory programming operation according to one embodiment.

[0066] Figure 7 and Figure 8 This is a cross-sectional view used to illustrate the programming operation of a 3D flash memory according to one embodiment.

[0067] Figure 9 This is a flowchart of the erasure operation of a 3D flash memory according to one embodiment.

[0068] Figure 10 This is a cross-sectional view used to illustrate the erase operation of a 3D flash memory according to one embodiment.

[0069] Figure 11 This is a flowchart of the erasure operation of 3D flash memory according to another embodiment.

[0070] Figure 12 This is a cross-sectional view used to illustrate the erasure operation of a 3D flash memory according to another embodiment.

[0071] Figure 13 This is a diagram used to illustrate a 3D flash memory according to one embodiment.

[0072] Figure 14 This is a diagram used to illustrate a 3D flash memory according to another embodiment.

[0073] Figure 15a to Figure 15c This is a diagram used to illustrate a 3D flash memory according to yet another embodiment.

[0074] Figure 16 This is a diagram of a standard 3D flash memory.

[0075] Figure 17 This is a vertical cross-sectional view of a 3D flash memory according to one embodiment.

[0076] Figure 18 This is a vertical cross-sectional view of a 3D flash memory according to another embodiment.

[0077] Figure 19 This is a vertical cross-sectional view of a 3D flash memory according to yet another embodiment.

[0078] Figure 20 This is a cross-sectional view of a 3D flash memory with a conventional BiCS structure applied to it.

[0079] Figure 21 This is a top view of the 3D flash memory with a conventional BiCS structure applied to it.

[0080] Figure 22This is a cross-sectional view of a 3D flash memory according to one embodiment.

[0081] Figure 23 This is a top view of a 3D flash memory according to one embodiment.

[0082] Figure 24 This is a flowchart of a method for operating 3D flash memory according to one embodiment.

[0083] Figure 25a and Figure 25b This is a cross-sectional view used to illustrate a 3D flash memory including intermediate signal lines (MSL) according to one embodiment.

[0084] Figure 26 This is a flowchart of a programming operation method for 3D flash memory according to one embodiment.

[0085] Figure 27 This is a cross-sectional view used to illustrate a programming operation method for 3D flash memory according to one embodiment.

[0086] Figure 28 This is a flowchart of a 3D flash memory erasure operation method according to one embodiment.

[0087] Figure 29 This is a cross-sectional view illustrating an erasure operation method for 3D flash memory according to one embodiment.

[0088] Figure 30 This is a flowchart of a 3D flash memory reading operation method according to one embodiment.

[0089] Figure 31 This is a cross-sectional view used to illustrate a method for reading 3D flash memory according to one embodiment. Detailed Implementation

[0090] In the following description, embodiments will be described in detail with reference to the accompanying drawings. However, this disclosure is not limited to these embodiments. Furthermore, the same reference numerals in each figure refer to the same elements.

[0091] Furthermore, the terminology used herein is for the purpose of properly describing exemplary embodiments of this disclosure and may vary depending on the intent of the user or operator or the conventions of the art to which this disclosure pertains. Therefore, the terminology used herein should be defined based on the entirety of this specification.

[0092] Figure 3 This is a cross-sectional view of a 3D flash memory according to one embodiment. Figure 4 and Figure 5 yes Figure 3 Cross-sectional views of various examples of 3D flash memory shown.

[0093] Reference Figure 3According to one embodiment, the 3D flash memory 300 may include at least one string (e.g., 310 and 320) formed on a substrate to extend in one direction and a plurality of word lines 330 connected in a vertical direction to the strings 310 and 320.

[0094] Strings 310 and 320 may include channel layers 311 and 321 formed extending in one direction, and charge storage layers 312 and 322 formed surrounding the channel layers 311 and 321. Charge storage layers 312 and 322 may be components configured to store charge due to voltage applied through multiple word lines 330. In the 3D flash memory 300, charge storage layers 312 and 322 may serve as data storage units and have, for example, an oxide-nitride-oxide (ONO) structure. Channel layers 311 and 321 may be formed of monocrystalline silicon or polycrystalline silicon and are both arranged in the form of hollow tubes. In this case, a buried film (not shown) may be further disposed to fill the channel layers 311 and 321. Therefore, strings 310 and 320 may include memory cells corresponding to multiple word lines 330 connected in the vertical direction, respectively.

[0095] Multiple word lines 330 can be formed of conductive materials (such as tungsten (W), titanium (Ti), tantalum (Ta), copper (Cu), or gold (Au)) and perform programming and erasing operations by applying voltage to the memory cells corresponding to them respectively. Multiple insulating layers (not shown) may be between the multiple word lines 330.

[0096] Here, the Serial Select line (SSL) can be on and connected to the bit lines of strings 310 and 320, and the Ground Select line (GSL) can be below and connected to the source line of strings 310 and 320. However, this disclosure is not limited thereto. The SSL can be below strings 310 and 320, and the GSL can be on strings 310 and 320. That is, in a configuration configured to support a bulk erase scheme, the SSL is fixedly on strings 310 and 320, and the GSL is fixedly below strings 310 and 320. However, in a configuration configured to support a Gate-Induced Drain Leakage (GIDL) erase scheme, the SSL and GSL can be adaptively positioned on or below strings 310 and 320.

[0097] In this embodiment, the 3D flash memory 300 is characterized in that at least one word line 331 of the plurality of word lines 330 is used as an intermediate signal line (MSL) configured to apply a signal to reduce the boost area. More specifically, the at least one word line 331 can be used as an MSL configured to turn off a portion of at least one string 310 and perform a programming operation on a specific memory cell on the remaining portion, or as an MSL configured to exhaust a portion of at least one string 310 and perform an erasure operation on the remaining portion. Naturally, the at least one word line 331 can be used as an MSL configured to perform both the above-described programming and erasure operations.

[0098] For example, the 3D NAND flash 300 can apply a shutdown voltage to the MSL331 for turning off the channel (more precisely, at least a portion of the channel of a string 310) and perform a programming operation on a specific memory cell in the remaining portion of the channel. In a specific example, the 3D NAND flash 300 can turn off at least a portion of the string 310, apply a pass voltage to the word lines in the remaining portion of the channel, and apply a programming voltage to the word lines corresponding to the specific memory cell in the remaining portion of the channel, thus enabling the 3D NAND flash 300 to perform a programming operation on the specific memory cell. (See also...) Figure 6 to Figure 8 A detailed description is given below. Here, at least one portion of string 310 refers to the region between MSL331 and GSL, and the remaining portion refers to the remaining region of the entire region of at least one string 331 excluding the portion. For example, the remaining portion could be the region between MSL331 and SSL that excludes the region between MSL331 and GSL from the entire region of at least one string 310. Although a structure configured to support a batch erasure scheme in which the positions of SSL and GSL are fixed based on strings 310 and 320 is shown, this disclosure is not limited thereto, and 3D NAND flash can have a structure configured to support a GIDL erasure scheme in which the positions of SSL and GSL adaptively change based on strings 310 and 320.

[0099] In another example, the 3D flash memory 300 can float the MSL331 and word lines in at least one portion of a string 310 and apply a ground voltage to the word lines in the remaining portion of the region, thus enabling the 3D flash memory 300 to perform an erase operation on the remaining region. In a specific example, the 3D flash memory 300 can perform an erase operation on the remaining region by applying an erase voltage to the body region of the substrate. (See also...) Figure 9 and Figure 10A detailed description is provided. In this context, at least one portion of string 310 refers to the region between MSL 331 and GSL, and the remaining portion refers to the remaining region of the entire region of at least one string 310 excluding the portion. In the example, the remaining portion could be the region between MSL331 and SSL that excludes the region between MSL 331 and GSL from the entire region of at least one string 310.

[0100] In yet another example, the 3D flash memory 300 can deplete at least a portion of a string 310 by applying a blocking voltage to the MSL 331 to deplete the channel, and then perform an erase operation on the remaining portion of the region. In a specific example, the 3D flash memory 300 can apply a ground voltage to the word lines in the remaining region and an erase voltage to the body region of the substrate, thus enabling the 3D flash memory 300 to perform an erase operation on the remaining region. (See also...) Figure 11 and Figure 12 A detailed description is given below. Here, at least one portion of string 310 is the region between MSL 331 and SSL, and the remaining portion refers to the remaining region of at least one string 330 excluding the portion. In the example, the remaining portion could be the region of at least one string 310 excluding the region between MSL 331 and SSL, located between MSL 331 and GSL.

[0101] The at least one word line 331 used as the MSL may include a channel region having a different length than the channel region of each of the remaining word lines of the plurality of word lines 330. For example, as Figure 4 As shown, the at least one character line 331 can be formed to have a thickness smaller than the thickness of the remaining character lines 410, such that the at least one character line 331 has a length smaller than the length of each of the remaining character lines 410. In another example, as Figure 5 As shown, the at least one character line 331 can be formed to have a thickness greater than the thickness of the remaining character lines 510, such that the at least one character line 331 has a length greater than the thickness of each of the remaining character lines 510.

[0102] As described above, the 3D flash memory 300 according to the embodiment can use at least one word line 331 of a plurality of word lines 330 as the MSL for applying a signal to reduce the boost area, thus significantly reducing the boosted area in conventional 3D flash memory. Therefore, speed can be increased during programming operations, power consumption associated with the pass voltage applied to unselected word lines can be reduced, and body potential rise time and hole injection time can be reduced during erase operations. A detailed description of the programming and erase operations will be described below.

[0103] Only one MSL 331 is described as being in a direction perpendicular to strings 310 and 320, but this is not a limitation; multiple MSL 331s can be separated from each other in a direction perpendicular to strings 310 and 320. In this case, the above structure and the following operating method can be applied as is.

[0104] Figure 6 This is a flowchart of a 3D flash memory programming operation according to one embodiment. Figure 7 and Figure 8 This is a cross-sectional view used to illustrate the programming operation of a 3D flash memory according to one embodiment.

[0105] Reference Figure 6 In operation S610, the 3D flash memory according to the embodiment applies a shutdown voltage to at least one word line 710, which serves as the MSL among a plurality of word lines, for shutting down the channel (more precisely, a portion of the channel of at least one string), applies a power supply voltage to the SSL connected to the upper or lower portion of the at least one string, and applies a ground voltage to the GSL connected to the upper or lower portion of the at least one string. Hereinafter, the shutdown voltage will be described as a subthreshold voltage having, for example, 0V, but is not limited thereto, and the shutdown voltage can be adjusted to various values ​​capable of shutting down the portion of the at least one string.

[0106] For example, such as Figure 7 As shown, the 3D NAND flash memory can apply a 0V shutdown voltage to the MSL710 to shut down the entire region of string 720 in the area between MSL710 and GSL, and shut down the entire region of string 720 in the area between MSL710 and GSL. Simultaneously, the 3D NAND flash memory can apply a power supply voltage Vcc to string 720, which includes the specific memory cell to be programmed, among multiple strings (e.g., 720 and 730), apply a power supply voltage Vcc to the SSL located at the top of string 720, and apply a 0V ground voltage to the GSL located at the bottom of string 720. As a result, because unlike conventional 3D NAND flash memory where the entire region of a string is boosted, only the upper region of string 720 located above MSL710 (the region between MSL710 and SSL) is boosted due to operation S620 described below, the boost area can be significantly reduced (in the example, when MSL710 is in the middle region of string 720, the boost area is reduced by 1 / 2).

[0107] The above example describes the process of performing programming operations on a specific memory cell located on top of the MSL710 in both a structure configured to support the GIDL erasure scheme and a structure configured to support the batch erasure scheme.

[0108] In another example, such as Figure 8As shown, the 3D NAND flash memory can apply a 0V shutdown voltage to MSL 710 to shut down the entire region of string 720 between MSL 710 and GSL, and shut down the entire region of string 720 between MSL 710 and GSL. Simultaneously, the 3D NAND flash memory can apply a power supply voltage Vcc to string 720, which includes the specific memory cell to be programmed, among multiple strings (e.g., 720 and 730), apply a power supply voltage Vcc to the SSL located at the lower part of string 720, and apply a 0V ground voltage to GSL located at the upper part of string 720. As a result, because unlike the operation of conventional 3D NAND flash memory where the entire region of a string is boosted, only the lower region of string 720 located below MSL 710 (the region between MSL 710 and SSL) is boosted due to operation S620 described below, the boost area can be significantly reduced (in the example, when MSL 710 is in the middle region of string 720, the boost area is reduced by 1 / 2).

[0109] The above example describes the process of performing programming operations on a specific memory cell located under MSL 710 in a structure configured to support the GIDL erasure scheme.

[0110] Subsequently, during the operation of S620, such as Figure 7 or Figure 8 As shown, the 3D flash memory applies a pass voltage Vpass to word line 740 between MSL 710 and SSL, and applies a programming voltage Vpgm to word line 741 corresponding to a specific memory cell between MSL 710 and SSL. Therefore, the 3D flash memory performs a programming operation on the specific memory cell.

[0111] As described above, due to operations S610 and S620, the 3D flash memory according to the embodiment only boosts the region between MSL710 and SSL, and performs programming operations on specific memory cells in that region. Therefore, the 3D flash memory according to the embodiment can improve the speed of programming operations by reducing the boost area and reduce power consumption without applying pass voltage to word lines included in the unboosted region (the region between MSL710 and GSL).

[0112] Figure 9 This is a flowchart of the erasure operation of 3D flash memory according to one embodiment. Figure 10 This is a cross-sectional view used to illustrate the erase operation of a 3D flash memory according to one embodiment.

[0113] Reference Figure 9In operation S910, the 3D flash memory according to the embodiment can float at least one word line 1010, which serves as the MSL, and a word line in a partial region of at least one string 1020. Hereinafter, a partial region of at least one string 1020 refers to the entire region of at least one string 1020 between the GSL and MSL 1010 connected to the lower part of at least one string 1020.

[0114] For example, such as Figure 10 As shown, 3D flash memory can make MSL 1010, word line 1030 between MSL 1010 and GSL, and GSL float.

[0115] Next, in operating the S920, 3D flash memory is directed to... Figure 10 As shown, a ground voltage of 0V is applied to word line 1040 between MSL 1010 and SSL connected to the upper part of at least one string 1020.

[0116] Although not shown as a separate operation, 3D flash memory can enable SSL floating in operation S910 or operation S920.

[0117] As a result, the body potential applied from the body region of the substrate due to the operation S930 described below can pass through the region between GSL and MSL 1010 and reach the region between SSL and MSL1010.

[0118] Subsequently, in operation S930, the 3D flash memory performs an erase operation on the region between MSL 1010 and SSL of at least one string 1020 by applying an erase voltage of 20V to the bulk region of the substrate, as follows. Figure 10 As shown. In the following text, the erase voltage will be described as 20V, but is not limited to this, and the erase voltage can be adjusted to various values ​​through which the erase operation can be performed.

[0119] As described above, because unlike conventional 3D NAND flash memory where the entire region of a string is boosted, only the upper region (the region between MSL1010 and SSL) of at least one string 1020 is boosted, thus the boost area can be significantly reduced (in the example, when MSL 1010 is in the middle region of string 1020, the boost area is reduced by half). Therefore, the 3D NAND flash memory according to the embodiment can reduce the volume potential rise time and hole injection time during erase operations by reducing the boost area.

[0120] Figure 11 This is a flowchart of the erasure operation of 3D flash memory according to another embodiment. Figure 12 This is a cross-sectional view used to illustrate the erasure operation of a 3D flash memory according to another embodiment.

[0121] Reference Figure 11 In operation S1110, according to another embodiment, the 3D flash memory applies a blocking voltage for channel depletion to at least one word line 1210, which serves as the MSL, among a plurality of word lines. Hereinafter, the blocking voltage will be described as 0V, but is not limited thereto, and the blocking voltage can be adjusted to various values ​​capable of depleting a partial region of at least one string. Furthermore, hereafter, a partial region of at least one string 1220 refers to the entire region of at least one string 1220 between the SSL and MSL 1210 connected to the upper part of at least one string 1220.

[0122] Therefore, due to operation S1130 described below, the body potential applied from the body region of the substrate does not reach the region between MSL1210 and SSL. Because unlike conventional 3D flash memory where the entire region of a string is boosted, only the lower region below MSL 1210 (the region between MSL 1210 and GSL) of at least one string 1220 is boosted, the boost area can be significantly reduced (in the example, when MSL 1210 is in the middle region of at least one string 1220, the boost area is reduced by 1 / 2).

[0123] Next, in operation S1220, as follows Figure 12 As shown, the 3D flash memory applies a 0V ground voltage to the word line 1230 between GSL and MSL1210, which is connected to the lower part of at least one string 1220.

[0124] Although not shown as a separate operation, 3D flash memory can float SSL and GSL in operation S1110 or operation S1120.

[0125] Subsequently, the 3D flash memory is processed in operation S1130 as follows: Figure 12 An erase voltage of 20V is applied to the bulk region of substrate 1230 to perform an erase operation on the region between MSL 1210 and GSL of at least one string 1220. Hereinafter, the erase voltage will be described as 20V, but is not limited thereto, and the erase voltage can be adjusted to various values ​​through which the erase operation can be performed.

[0126] As described above, the 3D flash memory according to another embodiment can reduce the volume potential rise time and hole injection time during the erase operation by reducing the boost area.

[0127] Figure 13 This is a diagram used to illustrate a 3D flash memory according to one embodiment. In the following text, for the sake of brevity, ... Figure 13 The image shows a top view of the top surface of the 3D flash memory 1300.

[0128] Reference Figure 13 The 3D flash memory 1300 may include a plurality of memory cell strings formed on a substrate and extending in one direction, and a plurality of word lines connected to the plurality of memory cell strings in a vertical direction.

[0129] As shown in the figure, each of the plurality of memory cell strings includes a channel layer and a charge storage layer. The channel layer is formed of monocrystalline silicon or polycrystalline silicon, and the charge storage layer is a component (e.g., an ONO structure) configured to surround the channel layer and store charge from the current supplied through the plurality of word lines.

[0130] The plurality of storage cell strings can be grouped to generate blocks 1310 and 1320. For example, among the plurality of storage cell strings, the first storage cell string 1311 and the second storage cell string 1312 can be grouped to generate the first block 1310, and the third storage cell string 1313 and the fourth storage cell string 1314 can be grouped to generate the second block 1320.

[0131] Therefore, the multiple word lines can be grouped into multiple word line groups to correspond to blocks 1310 and 1320 respectively. For example, the first word line 1321, the second word line 1322, and the third word line 1323 can be grouped to create a first word line group corresponding to the first block 1310, and the fourth word line 1324, the fifth word line 1325, and the sixth word line 1326 can be grouped to create a second word line group corresponding to the second block 1320. The multiple word lines can be formed in a stepped form by using conductive materials (such as tungsten, titanium, tantalum, etc.) while alternating with multiple insulating layers (not shown).

[0132] Therefore, the 3D flash memory 1300 can independently perform an erase operation on each of the plurality of memory cell strings for each of the blocks 1310 and 1320. For example, the erase operations on the first memory cell string 1311 and the second memory cell string 1312, as well as the erase operations on the third memory cell string 1313 and the fourth memory cell string 1314, can be performed independently. The erase operations on the memory cell strings 1311 and 1312 included in the blocks 1310 and 1320, respectively, can be performed simultaneously. For example, the erase operations on the first memory cell string 1311 and the second memory cell string 1312 can be performed simultaneously, and the erase operations on the third memory cell string 1313 and the fourth memory cell string 1314 can be performed simultaneously.

[0133] For this purpose, the 3D flash memory 1300 may include at least one switching element 1340 that selectively applies voltage to one of the plurality of word line groups while connected to word line wiring 1330 configured to control the plurality of word lines. The at least one switching element 1340 may perform a switching operation to connect the word line wiring 1330 to either the first block 1310 or the second block 1320. Thus, the word line wiring 1330 may be connected to the first block 1310 to apply voltage to a first word line group corresponding to the first block 1310 (more precisely, including the first word line 1321, the second word line 1322, and the third word line 1323 in the first word line group), or the word line wiring 1330 may be connected to the second block 1320 to apply voltage to a second word line group corresponding to the second block 1320 (more precisely, including the fourth word line 1324, the fifth word line 1325, and the sixth word line 1326 in the second word line group).

[0134] That is, the 3D flash memory 1300 according to the embodiment can perform an erase operation on each of the first block 1310 and the second block 1320 by selectively applying voltage to either the first block 1310 and the second block 1320 via a switching operation using at least one switching element 1340.

[0135] As described above, at least one switching element 1340 is included in the 3D flash memory 1300. Therefore, word line routing 1330 does not need to be provided for each word line, but is shared between blocks 1310 and 1320 (word line routing 1330 is shared between word line groups corresponding to blocks 1310 and 1320). Thus, the disadvantage of having to ensure space for arranging word line routing can be solved.

[0136] Furthermore, at least one bit line configured to control the plurality of memory cell strings can be shared between blocks 1310 and 1320, and can be selectively connected to any one of blocks 1310 and 1320 by using multiple SSLs (each of which is provided to correspond to one of the plurality of memory cell strings) connected to the at least one bit line. That is, the at least one bit line can be connected to any one of the blocks due to SSL switching operations.

[0137] Furthermore, since the multiple character lines are formed separately from each other and divided by the multiple character line groups, control can be applied to each of the small blocks 1310 and 1320 corresponding to the multiple character line groups respectively. For example, by forming a first character line group and a second character line group that are separate from each other, the first character line 1321, the second character line 1322, and the third character line 1323 can be separated from the fourth character line 1324, the fifth character line 1325, and the sixth character line 1326 and controlled independently.

[0138] Although the above description has described the generation of blocks 1310 and 1320 by grouping the plurality of memory cell strings, this disclosure is not limited thereto; blocks can also be generated by grouping the vertical storage regions of a memory cell string. (Refer to...) Figure 14 Provide a detailed description.

[0139] Figure 14 This is a diagram used to illustrate a 3D flash memory according to another embodiment. In the following text, for the sake of brevity, ... Figure 14 The image shows a cross-sectional view of the 3D Flash 1400.

[0140] Reference Figure 14 According to another embodiment, the 3D flash memory 1400 includes at least one string of memory cells formed extending in one direction on a substrate and a plurality of word lines connected to the at least one string of memory cells in a vertical direction.

[0141] As shown in the figure, each of the at least one memory cell string includes a channel layer and a charge storage layer. The channel layer is formed of monocrystalline silicon or polycrystalline silicon, and the charge storage layer is a component (e.g., an ONO structure) configured to surround the channel layer and store charge from the current supplied through the multiple word lines.

[0142] Here, the at least one storage cell string can be divided into vertical storage regions 1411-1, 1411-2, 1411-3, 1411-4, 1412-1, 1412-2, 1412-3, and 1412-4 corresponding to the multiple word lines. For example, the first storage cell string 1411 can be formed by using the first vertical storage region 1411-1 corresponding to the first word line 1421, the second vertical storage region 1411-2 corresponding to the second word line 1422, the third vertical storage region 1411-3 corresponding to the third word line 1423, and the fourth vertical storage region 1411-4 corresponding to the fourth word line 1424 to form at least one storage cell string. The second storage cell string 1412 can form at least one storage cell string by using a first vertical direction storage region 1412-1 corresponding to the first word line 1421, a second vertical direction storage region 1412-2 corresponding to the second word line 1422, a third vertical direction storage region 1412-3 corresponding to the third word line 1423, and a fourth vertical direction storage region 1412-4 corresponding to the fourth word line 1424.

[0143] Vertical storage regions 1411-1, 1411-2, 1411-3, 1411-4, 1412-1, 1412-2, 1412-3, and 1412-4 can be grouped to generate blocks 1410 and 1420. For example, the first vertical storage region 1411-1 and the second vertical storage region 1411-2 of the first storage cell string 1411, and the first vertical storage region 1412-1 and the second vertical storage region 1412-2 of the second storage cell string 1412 can be grouped to generate a first block 1410. The third vertical storage region 1411-3 and the fourth vertical storage region 1411-4 of the first storage cell string 1411, and the third vertical storage region 1412-3 and the fourth vertical storage region 1412-4 of the second storage cell string 1412 can be grouped to generate a second block 1420.

[0144] Therefore, the multiple word lines can correspond to blocks 1410 and 1420 respectively and be grouped into multiple word line groups. For example, the first word line 1421 and the second word line 1422 can be grouped into a first word line group corresponding to the first block 1410, and the third word line 1423 and the fourth word line 1424 can be grouped to create a second word line group corresponding to the second block 1420. The multiple word lines can be formed in a stepped form by using conductive materials (such as tungsten, titanium, tantalum, etc.) while alternating with multiple insulating layers (not shown).

[0145] Therefore, the 3D flash memory 1400 can independently perform erase operations on each of the vertical storage regions 1411-1, 1411-2, 1411-3, 1411-4, 1412-1, 1412-2, 1412-3, and 1412-4 of the at least one memory cell string for each of the blocks 1410 and 1420. For example, the erase operations on the first vertical storage regions 1411-1 and 1412-1 and the second vertical storage regions 1411-2 and 1412-2 respectively included in the first memory cell string 1411 and the second memory cell string 1412, and the erase operations on the third vertical storage regions 1411-3 and 1412-3 and the fourth vertical storage regions 1411-4 and 1412-4 respectively included in the first memory cell string 1411 and the second memory cell string 1412 can each be performed independently. Erasing operations on the vertical storage regions 1411-1, 1411-2, 1411-3, 1411-4, 1412-1, 1412-2, 1412-3, and 1412-4, respectively, included in blocks 1410 and 1420, can be performed simultaneously. For example, the erasure operation on the first vertical storage region 1411-1 of the first storage cell string 1411 can be performed simultaneously with the erasure operation on its second vertical storage region 1411-2, and the erasure operation on the first vertical storage region 1411-1 of the first storage cell string 1411 can be performed simultaneously with the erasure operation on the first vertical storage region 1412-1 of the second storage cell string 1412.

[0146] For this purpose, the 3D flash memory 1400 may include at least one switching element 1440 that selectively applies voltage to one of the plurality of word line groups while being connected to word line wiring 1430 configured to control the plurality of word lines. The at least one switching element 1440 may perform a switching operation to connect the word line wiring 1430 to either the first block 1410 or the second block 1420. Thus, the word line wiring 1430 may be connected to the first block 1410 to apply voltage to a first word line group corresponding to the first block 1410 (more precisely, including the first word line 1421 and the second word line 1422 in the first word line group), or the word line wiring 1430 may be connected to the second block 1420 to apply voltage to a second word line group corresponding to the second block 1420 (more precisely, including the third word line 1423 and the fourth word line 1424 in the second word line group).

[0147] That is, the 3D flash memory 1400 according to the embodiment can perform an erase operation on each of the first block 1410 and the second block 1420 by selectively applying voltage to either the first block 1410 and the second block 1420 via a switching operation using at least one switching element 1440.

[0148] As described above, at least one switching element 1440 is included in the 3D flash memory 1400. Therefore, word line routing 1430 does not need to be provided for each word line, but is shared between blocks 1410 and 1420 (word line routing 1430 is shared between word line groups corresponding to blocks 1410 and 1420). Thus, the disadvantage of having to ensure space for arranging word line routing can be solved.

[0149] Although the above has described the case of generating small blocks 1410 and 1420 by grouping the vertical storage regions 1411-1, 1411-2, 1411-3, 1411-4, 1412-1, 1412-2, 1412-3, and 1412-4 of the at least one string of storage cells, the above-mentioned reference can be generated by grouping the plurality of strings of storage cells based on the above-described case. Figure 3 The structure is obtained by mixing the described small pieces. (Refer to...) Figure 15a to Figure 15c Provide a detailed description.

[0150] Figure 15a to Figure 15c This is a diagram used to illustrate a 3D flash memory according to yet another embodiment. In the following text, for the sake of brevity, ... Figure 15a The image shows a top view of the top surface of the 3D NAND flash 1400, and for simplicity, in... Figure 15b and Figure 15c The image shows a cross-sectional view of the 3D Flash 1500.

[0151] Reference Figure 15a to 15c According to another embodiment, the 3D flash memory 1500 may include a plurality of memory cell strings formed on a substrate to extend in one direction and a plurality of word lines connected to the plurality of memory cell strings in a vertical direction.

[0152] As shown in the figure, each of the plurality of memory cell strings includes a channel layer and a charge storage layer. The channel layer is formed of monocrystalline silicon or polycrystalline silicon, and the charge storage layer is a component (e.g., an ONO structure) configured to surround the channel layer and store charge from the current supplied through the plurality of word lines.

[0153] Here, the plurality of storage cell strings can be divided into vertical storage regions 1511-1, 1511-2, 1511-3, 1511-4, 1512-1, 1512-2, 1512-3, 1512-4, 1513-1, 1513-2, 1513-3, 1513-4, 1514-1, 1514-2, 1514-3, and 1514-4, respectively, corresponding to the plurality of word lines. For example, among the plurality of storage cell strings, the first storage cell string 1511 may include a first vertical direction storage area 1511-1 corresponding to the first word line 1521, a second vertical direction storage area 1511-2 corresponding to the second word line 1522, a third vertical direction storage area 1511-3 corresponding to the third word line 1523, and a fourth vertical direction storage area 1511-4 corresponding to the fourth word line 1524. The second storage cell string 1512 may include a first vertical direction storage area 1512-1 corresponding to the first word line 1521, a second vertical direction storage area 1512-2 corresponding to the second word line 1522, a third vertical direction storage area 1512-3 corresponding to the third word line 1523, and a fourth vertical direction storage area 1512-4 corresponding to the fourth word line 1524. The third storage cell string 1513 may include a first vertical storage area 1513-1 corresponding to the fifth word line 1525, a second vertical storage area 1513-2 corresponding to the sixth word line 1526, a third vertical storage area 1513-3 corresponding to the seventh word line 1527, and a fourth vertical storage area 1513-4 corresponding to the eighth word line 1528. The fourth storage cell string 1514 may include a first vertical storage area 1514-1 corresponding to the fifth word line 1525, a second vertical storage area 1514-2 corresponding to the sixth word line 1526, a third vertical storage area 1514-3 corresponding to the seventh word line 1527, and a fourth vertical storage area 1514-4 corresponding to the eighth word line 1528.

[0154] Vertical storage regions 1511-1, 1511-2, 1511-3, 1511-4, 1512-1, 1512-2, 1512-3, 1512-4, 1513-1, 1513-2, 1513-3, 1513-4, 1514-1, 1514-2, 1514-3, and 1514-4 can be grouped to generate blocks 1510, 1520, 1530, and 1540. For example, the first vertical storage region 1511-1 and the second vertical storage region 1511-2 of the first storage cell string 1511, and the first vertical storage region 1512-1 and the second vertical storage region 1512-2 of the second storage cell string 1512 can be grouped to generate a first block 1510. The third vertical storage regions 1511-3 and 1511-4 of the first storage cell string 1511, and the third vertical storage regions 1512-3 and 1512-4 of the second storage cell string 1512, can be grouped to generate a second block 1520. The first vertical storage regions 1513-1 and 1513-2 of the third storage cell string 1513, and the first vertical storage regions 1514-1 and 1514-2 of the fourth storage cell string 1514, can be grouped to generate a third block 1530. The third vertical storage regions 1513-3 and 1513-4 of the third storage cell string 1513, and the third vertical storage regions 1514-3 and 1514-4 of the fourth storage cell string 1514, can be grouped to generate a fourth block 1540.

[0155] Therefore, the multiple word lines can correspond to blocks 1510, 1520, 1530, and 1540 respectively, and are grouped into multiple word line groups. For example, the first word line 1521 and the second word line 1522 can be grouped to produce a first word line group corresponding to the first block 1510, the third word line 1523 and the fourth word line 1524 can be grouped to produce a second word line corresponding to the second block 1520, the fifth word line 1525 and the sixth word line 1526 can be grouped to produce a third word line group corresponding to the third block 1530, and the seventh word line 1527 and the eighth word line 1528 can be grouped to produce a fourth word line group corresponding to the fourth block 1540. The multiple word lines can be formed in a stepped form by using conductive materials (such as tungsten, titanium, tantalum, etc.) while alternating with multiple insulating layers (not shown).

[0156] Therefore, the 3D flash memory 1500 can independently perform erase operations on each of the vertical storage regions 1511-1, 1511-2, 1511-3, 1511-4, 1512-1, 1512-2, 1512-3, 1512-4, 1513-1, 1513-2, 1513-3, 1513-4, 1514-1, 1514-2, 1514-3, and 1514-4 of the plurality of memory cell strings for each of the blocks 1510, 1520, 1530, and 1540. For example, erase operations on the first vertical storage region 1511-1 and the second vertical storage region 1511-2 of the first memory cell string 1511, as well as erase operations on the third vertical storage region 1511-3 and the fourth vertical storage region 1511-4 of the first memory cell string 1511, can be performed independently. Erasing operations on the vertical storage regions 1511-1, 1511-2, 1512-1, and 1512-2 included in blocks 1510, 1520, 1530, and 1540, respectively, can be performed simultaneously. For example, erasing operations on the first vertical storage region 1511-1 and the second vertical storage region 1511-2 of the first storage cell string 1511 can be performed simultaneously with erasing operations on the first vertical storage region 1512-1 and the second vertical storage region 1512-2 of the second storage cell string 1512.

[0157] To this end, the 3D flash memory 1500 may include at least one switching element 1560, which can selectively apply voltage to one of the plurality of word line groups while connected to word line wiring 1550 configured to control the plurality of word lines. The at least one switching element 1560 can perform a switching operation to connect the word line wiring 1550 to any one of the first block 1510, the second block 1520, the third block 1530, and the fourth block 1540. Therefore, word line wiring 1550 can be connected to the first block 1510 to apply voltage to the first word line group corresponding to the first block 1510 (more precisely, including the first word line 1521 and the second word line 1522 in the first word line group), word line wiring 1550 can be connected to the second block 1520 to apply voltage to the second word line group corresponding to the second block 1520 (more precisely, including the third word line 1523 and the fourth word line 1524 in the second word line group), word line wiring 1550 can be connected to the third block 1530 to apply voltage to the third word line group corresponding to the third block 1530 (more precisely, including the fifth word line 1525 and the sixth word line 1526 in the third word line group), or word line wiring 1550 can be connected to the fourth block 1540 to apply voltage to the fourth word line group corresponding to the fourth block 1540 (more precisely, including the seventh word line 1527 and the eighth word line 1528 in the fourth word line group).

[0158] That is, the 3D flash memory 1500 according to the embodiment can perform an erase operation on each of the blocks 1510, 1520, 1530 and 1540 by selectively applying voltage to any one of the blocks 1510, 1520, 1530 and 1540 via a switching operation using at least one switching element 1560.

[0159] As described above, because at least one switching element 1560 is included in the 3D flash memory 1500, the word line routing 1550 does not need to be provided for each word line, but is shared among blocks 1510, 1520, 1530, and 1540 (the word line routing 1550 is shared among the word line groups corresponding to blocks 1510, 1520, 1530, and 1540). Therefore, the drawback of needing to ensure sufficient space for arranging the word line routing can be resolved.

[0160] Figure 17 This is a vertical cross-sectional view of a 3D flash memory according to one embodiment.

[0161] Reference Figure 17 According to one embodiment, the 3D flash memory 1700 includes a substrate 1710 and at least one memory cell string 1720.

[0162] Here, at least one memory cell string 1720 may include at least one channel layer 1721 formed on substrate 1710 extending in one direction, and at least one charge storage layer 1722 surrounding the at least one channel layer 1721. The at least one channel layer 1721 may be formed of monocrystalline or polycrystalline silicon and may be formed using a selective epitaxial growth process or a phase change epitaxial growth process utilizing substrate 1710 as a seed. The at least one charge storage layer 1722 may be a component configured to store charge from a current supplied through a plurality of electrode layers 1723. In the example, the at least one charge storage layer 1722 may have an ONO structure. Hereinafter, the at least one charge storage layer 1722 will be described as including only vertical elements extending in one direction orthogonal to substrate 1710, but is not limited thereto. The at least one charge storage layer 1722 may further include horizontal elements parallel to the plurality of electrode layers 1723 in contact with them.

[0163] In this configuration, multiple electrode layers 1723 and multiple insulating layers 1724 can be alternately connected to at least one memory cell string 1720 in the vertical direction. Drain lines (not shown) can be arranged on and connected to the multiple electrode layers 1723 and multiple insulating layers 1724. The multiple electrode layers 1723 can be formed of conductive materials (such as tungsten, titanium, tantalum, etc.), and the multiple insulating layers 1724 can be formed of various materials with insulating properties.

[0164] The structure described above, consisting of at least one storage cell string 1720, multiple electrode layers 1723, and multiple insulating layers 1724, is identical to that of conventional 3D flash memory components; therefore, its detailed description is omitted.

[0165] The substrate 1710 is characterized by being divided into a cell region 1711 and a peripheral portion region 1712. At least one memory cell transistor associated with at least one memory cell string 1720 is formed in the cell region 1711, and at least one peripheral portion transistor, corresponding to the remaining transistors excluding the memory cell transistors among the transistors associated with the operation of the 3D flash memory 1700, is formed in the peripheral portion region 1712. Hereinafter, at least one memory cell transistor refers to a transistor directly associated with data storage and read operations of at least one memory cell string 1720 or a transistor used to connect at least one memory cell string 1720 to a source electrode 1731, and at least one peripheral portion transistor refers to a transistor excluding at least one memory cell transistor 1650 among the transistors associated with the operation of the 3D flash memory 1700. Furthermore, in the following text, when at least one memory cell transistor is referred to as being formed in the cell region 1711, it means that at least one memory cell transistor is buried in the cell region 1711 on the substrate 1710. Furthermore, when at least one peripheral portion transistor is referred to as being formed in the peripheral portion region 1712, it means that at least one peripheral portion transistor is buried in the peripheral portion region 1712 on the substrate 1710. Additionally, for clarity, at least one memory cell transistor formed in the cell region 1711 and at least one peripheral portion transistor formed in the peripheral portion region 1712 are not directly shown.

[0166] More specifically, according to one embodiment, the substrate 1710 can be produced as a multilayer structure in which a bulk polycrystalline silicon substrate 1714 serving as a unit region 1711 is stacked on a silicon substrate 1713 serving as a peripheral partial region 1712.

[0167] Here, the bulk polysilicon substrate 1714 can be used for batch erase operations of the 3D NAND flash memory 1700, wherein an interlayer insulating layer 1730 burying the source electrode 1731 can be located between the bulk polysilicon substrate 1714 and the silicon substrate 1713. Therefore, at least one memory cell transistor formed in the bulk polysilicon substrate 1714, which serves as the cell region 1711, can connect the source electrode 1731 buried in the interlayer insulating layer 1730 to at least one memory cell string 1720.

[0168] Furthermore, the bulk polysilicon substrate 1714 can be used not only for batch erasure operations but also for GIDL erasure operations. The 3D NAND flash 1700, which includes the bulk polysilicon substrate 1714, can support both batch erasure operations and GIDL erasure operations.

[0169] As described above, the 3D flash memory 1700 according to the embodiment can divide the substrate 1710 into a cell region 1711 in which at least one memory cell transistor is formed and a peripheral portion region 1712 in which at least one peripheral portion transistor is formed. Therefore, the wiring process can be simplified in the application of peripheral cell circuit (COP).

[0170] Furthermore, the substrate 1710 is not limited to the multilayer structure described above. It can have various structures divided into unit regions 1711 and peripheral partial regions 1712. (Refer to...) Figure 18 and Figure 19 Provide a detailed description.

[0171] Figure 18 This is a vertical cross-sectional view of a 3D flash memory according to another embodiment.

[0172] Reference Figure 18 ,picture Figure 17 Similar to the 3D flash memory 1700 shown, the 3D flash memory 1800 according to another embodiment may include a substrate 1810 and at least one memory cell string 1820.

[0173] Similarly, at least one memory cell string 1820 may include at least one channel layer 1821 formed on the substrate 1810 and extending in one direction, and at least one charge storage layer 1822 surrounding the at least one channel layer 1821. A plurality of electrode layers 1823 and a plurality of insulating layers 1824 may be alternately connected to at least one memory cell string 1820 in a vertical direction.

[0174] However, the 3D flash memory 1800 according to the embodiment is characterized by including having with Figure 17 The substrate 1810 has a different detailed structure than the 3D flash memory 1700 shown. Naturally, the 3D flash memory 1800 according to the embodiment is different from... Figure 17The 3D flash memory 1700 shown is similar in that the substrate 1810 is formed into a cell region 1811 and a peripheral region 1812. At least one memory cell transistor associated with at least one memory cell string 1820 is formed in the cell region 1811, and at least one peripheral region transistor, corresponding to the remaining transistors excluding the memory cell transistors among the transistors associated with the operation of the 3D flash memory 1800, is formed in the peripheral region 1812. The 3D flash memory 1800 according to this embodiment... Figure 17 The difference in the 3D flash memory 1700 shown is that the substrate 1810 is formed as a single layer.

[0175] More specifically, when the substrate 1810 is formed as a single layer, the cell region 1811 may be on the central portion of the substrate 1810 in which at least one memory cell string 1820 is disposed (the central portion of the substrate 1810 corresponding to the lower portion of at least one memory cell string 1820), and the peripheral region 1812 may be on the peripheral portion of the substrate 1810 surrounding the cell region 1811.

[0176] Here, the interlayer insulating layer 1830 in which the source electrode 1831 is buried may be on the substrate 1810. In this case, at least one memory cell string 1820 may be formed to pass through the interlayer insulating layer 1830 and contact the substrate 1810. The source electrode 1831 may be buried in the peripheral portion of the interlayer insulating layer 1830, excluding the central portion in which at least one memory cell string 1820 is disposed. Therefore, the source electrode 1831 buried in the interlayer insulating layer 1830 may be connected to at least one memory cell string 1820 via at least one memory cell transistor formed in the cell region 1811.

[0177] Furthermore, the substrate 1810 may be formed to have the same width as the electrode layer with the largest width among the plurality of electrode layers 1823. However, this disclosure is not limited thereto; the substrate 1810 may be formed to have a width larger than the width of the plurality of electrode layers 1823, such that at least one peripheral portion transistor is buried in a relatively larger number. (Refer to...) Figure 19 Provide a detailed description.

[0178] Figure 19 This is a vertical cross-sectional view of a 3D flash memory according to another embodiment.

[0179] Reference Figure 19 Although the 3D flash memory 1900 according to another embodiment has the same Figure 18 The 3D flash memory 1800 shown has the same structure, but the difference between the 3D flash memory 1900 and the 3D flash memory 1800 is that the substrate 1910 is formed to be wider than the width of the multiple electrode layers 1920.

[0180] Due to the above structure, and in reference Figure 18 Compared to the described scenario, at least one peripheral transistor can be buried in a greater number within the substrate 1910. In this case, the peripheral region 1911 can be densely distributed in the portions of the substrate 1910 corresponding to the plurality of electrode layers 1920. Furthermore, the density of at least one peripheral transistor formed in the peripheral region 1911 can be higher in the portions of the substrate 1910 corresponding to the plurality of electrode layers 1920 than in the outer portions of the portions of the substrate 1910 corresponding to the plurality of electrode layers 1920.

[0181] Figure 22 This is a cross-sectional view of a 3D flash memory according to one embodiment. Figure 23 This is a top view of a 3D flash memory according to one embodiment.

[0182] Reference Figure 22 and Figure 23 According to one embodiment, the 3D flash memory 2200 includes at least one string 2210, multiple word lines 2220, and two bit lines 2230 and 2240. In the following text, for the sake of brevity, only... Figure 23 The image shows two bit lines, 2230 and 2240, in... Figure 22 Only the contacts of these two bit lines 2230 and 2240 connected to at least one string 2210 are shown.

[0183] At least one string 2210 includes a charge storage layer 2211 formed as a hollow tube extending on a substrate (not shown) and a channel layer 2212 filling the interior of the charge storage layer 2211. The charge storage layer 2211 may be a component configured to store charge due to voltage applied through multiple word lines 2220. In the 3D flash memory 2200, the charge storage layer 2211 may serve as a data storage unit and have, for example, an ONO structure. The channel layer 2212 may be formed of monocrystalline silicon or polycrystalline silicon. Similar to the charge storage layer 2211, the channel layer 2212 may be formed as a hollow tube and further include a buried film (not shown) in the form of a hollow tube. Therefore, at least one string 2210 may include memory cells corresponding to multiple word lines 2220 connected in the vertical direction.

[0184] In this case, at least one string 2210 is characterized in that it has a U-shape and includes a horizontal portion 2213 for the substrate and vertical portions 2214 and 2215, particularly, the vertical portions 2214 and 2215 having a shape symmetrical about the horizontal portion 2213. Hereinafter, when the vertical portions 2214 and 2215 are referred to as symmetrical about the horizontal portion 2213, it means that the vertical portions 2214 and 2215 have the same shape and thickness relative to the horizontal portion 2213, and the ends 2214-1 and 2215-1 of the vertical portions 2214 and 2215 are formed to have the same height. Furthermore, hereinafter, the ends 2214-1 and 2215-1 of the vertical portions 2214 and 2215 refer to the two ends 2214-1 and 2215-1 of the U-shape of at least one string 2210, and are therefore used interchangeably.

[0185] Multiple word lines 2220 may be formed of a conductive material (such as tungsten (W), titanium (Ti), tantalum (Ta), copper (Cu), or gold (Au)) such that the multiple word lines 2220 can be orthogonal to and connected to at least one vertical portion 2214 and 2215 of a string 2210. Therefore, the multiple word lines 2220 can perform programming and erasing operations by applying a voltage to the memory cells corresponding to them respectively. Multiple insulating layers (not shown) may be present between the multiple word lines 2220.

[0186] Two bit lines 2230 and 2240 are connected to the two ends 2214-1 and 2215-1 of at least one string 2210 while extending parallel to the horizontal portion 2213 of at least one string 2210. Here, because the two ends 2214-1 and 2215-1 of at least one string 2210 are symmetrically located at the same height, the two bit lines 2230 and 2240 can be in the same plane. When two bit lines 2230 and 2240 are said to be in the same plane, it means that these two bit lines 2230 and 2240 are formed at the same height and are not layered. For example, the two bit lines 2230 and 2240 can be formed in the same plane to extend in the x-axis direction and connect to the two ends 2214-1 and 2215-1 of at least one string 2210.

[0187] In this case, when the two ends 2214-1 and 2215-1 of at least one string 2210 are said to be connected to two bit lines 2230 and 2240, it means that the channel layer 2212 is connected to the two bit lines 2230 and 2240 located at the two ends 2214-1 and 2215-1 of at least one string 2210. Therefore, in order for the channel layer 2212 at the two ends 2214-1 and 2215-1 of at least one string 2210 to be connected to the two bit lines 2230 and 2240 located in the same plane, the positions of the channel layer 2212 formed on the cross sections of the two ends 2214-1 and 2215-1 of at least one string 2210 can be misaligned with each other. In the example, the channel layer 2212 may be formed to be offset upward on the cross-section of the end 2214-1 of at least one vertical portion (e.g., 2214) of a string 2210, and to be offset downward on the cross-section of the end 2215-1 of the remaining vertical portion (e.g., 2215). Therefore, the channel layer 2212 at both ends 2214-1 and 2215-1 of at least one string 2212 may be connected to two bit lines 2230 and 2240 located in the same plane.

[0188] Each of the two bit lines 2230 and 2240 is characterized in that it is selectively used as either a drain line or a source line. In the following, when each of the two bit lines 2230 and 2240 is referred to as being selectively usable as either a drain line or a source line, it means that each of the two bit lines 2230 and 2240 can be used as either a drain line or a source line depending on the situation. More specifically, it means that in response to one bit line (e.g., 2240) being used as either a drain line or a source line, the other bit line (e.g., 2230) can be used as either a drain line or a source line, excluding the line used by bit line 2240. In the example, when the first bit line 2230 is used as a drain line, the second bit line 2240 can be used as a source line; and when the first bit line 2230 is used as a source line, the second bit line 2240 can be used as a drain line.

[0189] In this configuration, each of the two bit lines 2230 and 2240 can be selectively used as a drain line or a source line based on the required voltage to be applied to the two ends 2214-1 and 2215-1 of at least one string 2210. That is, when performing programming, erasing, or reading operations on the 3D flash memory 2200, each of the two bit lines 2230 and 2240 can be selectively used as a drain line or a source line based on the required voltage to be applied to the two ends 2214-1 and 2215-1 of at least one string 2210. (Refer to...) Figure 24 Provide a detailed description.

[0190] As described above, since the 3D flash memory 2200 according to one embodiment includes at least one string 2210 in which the vertical portions 2214 and 2215 are symmetrical to each other, various problems caused by strings with asymmetrical structures can be fundamentally solved (the problem of weak recognition margin due to reduced cell current during read operation, the problem of reduced speed due to increased boost area during programming operation, the problem of increased power consumption related to the pass voltage applied to the word line due to increased number of unselected word lines, and the problem of increased body potential rise time and increased hole injection time during erase operation).

[0191] Furthermore, the 3D flash memory 2200 can use word lines positioned adjacent to the upper portion of the horizontal portion 2213 of at least one string 2210 among multiple word lines 2220 as MSLs to which signals for programming, erasing, and reading operations are applied. (See also...) Figure 25a Provide a detailed description.

[0192] Figure 24 This is a flowchart of a method for operating 3D flash memory according to one embodiment.

[0193] Reference Figure 24 In operation S2410, based on the required voltage to be applied to both ends of at least one string, depending on which of the programming, erasing, and reading operations will be performed, the 3D flash memory of the embodiment determines whether each bit line will be used as a drain line or a source line.

[0194] For example, in order for 3D flash memory to perform programming operations, the required voltages to be applied to both ends of the at least one string must be a ground voltage and a power supply voltage. Therefore, it can be determined that either of the two bit lines connected to both ends of the at least one string will be used as the source line to which a ground voltage will be applied, and it can be determined that the other bit line will be used as the drain line to which a power supply voltage will be applied.

[0195] Subsequently, in operation S2420, the 3D flash memory applies a voltage to both ends of the at least one string through the two bit lines based on the result of determining whether each of the two bit lines will be used as a drain line or a source line.

[0196] As described above, when controlling programming, erasing, or reading operations on at least one string of a symmetrical structure, the 3D flash memory according to the embodiment selectively uses each of the two bit lines as either a drain line or a source line. Therefore, while fundamentally solving the various problems caused by strings with asymmetrical structures, integration can be facilitated and operational efficiency can be improved.

[0197] Figure 25a and Figure 25bThis is a cross-sectional view of a 3D flash memory including MSL according to one embodiment.

[0198] Reference Figure 25a and Figure 25b 3D Flash 2500 can have the same characteristics as the reference. Figure 22 and Figure 23 The 3D flash memory described has the same structure. For example, like the reference... Figure 22 and Figure 23 Like at least one string of the 3D flash memory described, in at least one string 2510 included in the 3D flash memory 2500, the vertical portions 2511 and 2512 may be symmetrical about the horizontal portion 2513.

[0199] However, compared with the reference Figure 22 and Figure 23 Unlike the described 3D flash memory, the 3D flash memory 2500 is characterized in that one of the multiple word lines 2520, which is positioned adjacent to the upper part of the horizontal portion 2513, is used as the MSL to apply signals for programming, erasing and reading operations.

[0200] Here, the 3D flash memory 2500, including at least one string 2510 with a U-shape, can be considered functionally similar to... Figure 25b The illustrated 3D flash memory 2530 includes at least one string 2531 having a vertical shape. In this case, because the word line 2521 among the multiple word lines 2520 positioned adjacent to the upper part of the horizontal portion 2513 is in the middle region of the string of the 3D flash memory 2530, the word line 2521 among the multiple word lines 2520 positioned adjacent to the upper part of the horizontal portion 2513 will be referred to as MSL below, and can be interchanged as MSL 2521.

[0201] In this configuration, MSL 2521 can exhaust one of the vertical portions 2511 and 2512 of at least one string 2510 (e.g., 2511) and perform a programming operation on a specific memory cell on the other vertical portion (e.g., 2512). Furthermore, MSL 2521 can inject holes into both vertical portions 2511 and 2512 of at least one string 2510 and perform an erase operation on at least one string 2510.

[0202] For example, the 3D flash memory 2500 can apply a ground voltage to the end of any vertical portion (e.g., 2511), apply a power supply voltage to the end of another vertical portion (e.g., 2512), and apply a blocking voltage to the MSL 2521 to deplete the vertical portion 2511. Therefore, the 3D flash memory 2500 can perform programming operations on the specific memory cell on the vertical portion 2512.

[0203] In another example, the 3D flash memory 2500 can apply a blocking voltage to the MSL 2521 to keep the MSL 2521 in an off state, or float the MSL 2521 and then inject holes into both vertical portions 2511 and 2512 by applying an erase voltage to both ends of the vertical portions 2511 and 2512, so that the 3D flash memory 2500 can perform an erase operation on at least one string 2510.

[0204] In another example, the 3D flash memory 2500 can apply a read voltage to the end of any of the vertical portions 2511 and 2512 of at least one string 2510, where a particular memory cell to be read is disposed, and apply a ground voltage to the end of the remaining vertical portions to float the MSL 2521, so that the 3D flash memory 2500 can perform a read operation on the particular memory cell.

[0205] Reference Figure 16 to Figure 31 Provide a detailed description of the programming, erasing, and reading operations of the 3D Flash 2500.

[0206] As described above, the 3D flash memory 2500 according to one embodiment can use a word line 2521, which is positioned adjacent to the upper part of the horizontal portion 2513 among multiple word lines 2520, as the MSL for applying signals for programming, erasing, and reading operations. Therefore, the boosted area in conventional 3D flash memory can be significantly reduced. Consequently, speed can be increased during programming operations, power consumption related to the pass voltage applied to unselected word lines can be reduced, and body potential rise time and hole injection time can be reduced during erasing operations. Furthermore, during reading operations, the problem of weak recognition margin due to reduced cell current can be solved.

[0207] Although the case of using one word line (e.g., 2521) positioned adjacent to the upper part of the horizontal portion 2513 among the multiple word lines 2520 as the MSL has been described above, this disclosure is not limited thereto. One or more word lines located at any position among the multiple word lines 2520 can be used. In this case, the above structure and the following operating method can be applied as is.

[0208] Figure 26 This is a flowchart of a 3D flash memory programming operation method according to one embodiment. Figure 27 This is a cross-sectional view used to illustrate a programming operation method for 3D flash memory according to one embodiment.

[0209] Reference Figure 26 and Figure 27In operation S2610, according to one embodiment, the 3D flash memory can apply a ground voltage to the end of any one of the vertical portions 2711 and 2712 included in at least one string 2710 (e.g., 2711) and apply a power supply voltage to the end of the other vertical portion (e.g., 2712). In this case, the vertical portion 2712 to which the power supply voltage is applied may be the string containing a specific memory cell to be programmed.

[0210] Subsequently, in operation S2620, the 3D flash memory can apply a blocking voltage to the MSL 2720 to deplete the vertical portion 2711 and perform programming operations on specific memory cells on the vertical portion 2712.

[0211] For example, in operation S2610, the 3D flash memory applies a 0V ground voltage to the bit line connected to the end of the vertical portion 2711, and applies a Vcc (e.g., 20V) power supply voltage to the bit line connected to the end of the vertical portion 2712. Simultaneously, in operation S2620, the 3D flash memory applies a blocking voltage to MSL 2720 and turns off MSL 2720. Therefore, the 3D flash memory can perform programming operations by only boosting the vertical portion 2712.

[0212] As described above, because 3D flash memory performs programming operations by boosting only one of the vertical portions 2711 and 2712, the programming speed can be increased and the power consumption associated with the pass voltage applied to the unselected word line can be reduced.

[0213] Furthermore, in operation S2620, the 3D flash memory applies a pass voltage to the remaining word lines among the multiple word lines, excluding the word line corresponding to the specific memory cell, and applies a programming voltage to the word line corresponding to the specific memory cell. Therefore, the 3D flash memory can perform a programming operation on the specific memory cell. Since the operation of applying voltage to the word lines is the same as the operation of conventional 3D flash memory during the programming process, its detailed description is omitted. Similarly, since the various operations of applying voltage to the word lines during the erase and read operations described below are also the same as those operations of conventional 3D flash memory, their detailed descriptions will also be omitted.

[0214] Figure 28 This is a flowchart of a 3D flash memory erasure operation method according to one embodiment. Figure 29 This is a cross-sectional view illustrating an erasure operation method for 3D flash memory according to one embodiment.

[0215] Reference Figure 28 and Figure 29In operation S2810, according to one embodiment, the 3D flash memory applies a blocking voltage to MSL2910 to keep MSL2910 in the off state or to float MSL2910.

[0216] Subsequently, in operation S2820, the 3D flash memory applies an erase voltage to both ends of the vertical portions 2921 and 2922 included in at least one string 2920 and injects holes into both vertical portions 2921 and 2922, thus the 3D flash memory performs an erase operation on at least one string 2920.

[0217] For example, in operation S2810, the 3D flash memory applies a blocking voltage to keep MSL 2910 in the off state, while in operation S2820, it applies an erase voltage of 20V to the two bit lines connected to the vertical portions 2921 and 2922 respectively, and simultaneously injects holes into both vertical portions 2921 and 2922. Therefore, the 3D flash memory can perform an erase operation on at least one string 2920.

[0218] As described above, because 3D flash memory performs an erasure operation by simultaneously injecting holes into vertical portions 2921 and 2922 (each having a length corresponding to half the total length of at least one string 2920), the volume potential rise time and hole injection time can be reduced by half compared to conventional erasure techniques that inject holes into either of the vertical portions 2921 and 2922 to perform an erasure operation on the entire string until the hole injection is complete.

[0219] Figure 30 This is a flowchart of a 3D flash memory reading operation method according to one embodiment. Figure 31 This is a cross-sectional view used to illustrate a method for reading 3D flash memory according to one embodiment.

[0220] Reference Figure 30 and Figure 31 In operation S3010, according to one embodiment, the 3D flash memory applies a read voltage to the end of any vertical portion (e.g., 3112) of the vertical portions 3111 and 3112 of at least one string 110 where the specific memory cell to be read is located, and applies a ground voltage to the end of the remaining vertical portion (e.g., 3111).

[0221] Subsequently, in operation S3020, the 3D flash memory performs a read operation on the specific memory cell by floating the MSL 3120.

[0222] For example, in operation S3010, the 3D NAND flash memory applies a 1V read voltage to the bit line connected to the vertical portion 3112 where the specific memory cell is located, and applies a 0V ground voltage to the bit line connected to the end of the vertical portion 3111. Meanwhile, in operation S3020, the 3D NAND flash memory can keep MSL 3120 in the ON state by floating MSL 3120, and perform a read operation on the specific memory cell.

[0223] As described above, because the 3D flash memory preferentially performs read operations on one of the vertical portions 3111 and 3112 (e.g., 3112), the read operation can be improved, and the problem of weak recognition margin due to reduced cell current can be solved. Furthermore, errors based on electrode orientation can be minimized.

[0224] Although embodiments have been described above with reference to limited embodiments and accompanying drawings, those skilled in the art will understand that various changes and modifications can be made therein from the above description. For example, suitable results may be obtained even when the described techniques are performed in a different order than the described methods and / or even when the described components (e.g., systems, structures, devices, circuits, etc.) are combined in a different form than the described methods or replaced with other components or equivalents.

[0225] Therefore, other implementations, other embodiments, and equivalents of the claims also fall within the scope and spirit of the claims described below.

Claims

1. A three-dimensional flash memory, comprising: At least one string is formed on a substrate to extend in one direction, the at least one string including at least one channel layer formed to extend in one direction and a charge storage layer formed to surround the at least one channel layer; as well as Multiple word lines, connected vertically to the at least one string. At least one of the plurality of word lines is used as an intermediate signal line, the intermediate signal line being configured to shut off a portion of the at least one string to perform a programming operation on the memory cells in the remaining portion of the string and to exhaust the portion of the at least one string to perform an erasure operation on the remaining portion of the string.

2. The three-dimensional flash memory of claim 1, wherein the at least one string is turned off by applying a turn-off voltage to the intermediate signal line for turning off the channel, and the programming operation is performed on the memory cells in the remaining portion of the string.

3. The three-dimensional flash memory of claim 1, wherein the at least one string is depleted by applying a blocking voltage to the intermediate signal line for depleting the channel, and the erasure operation is performed on the remaining portion of the string.

4. The three-dimensional flash memory of claim 1, wherein the erase operation is performed on the remaining portion of the region by floating the intermediate signal lines and word lines located in the portion of the at least one string and applying a ground voltage to the word lines located in the remaining portion of the region.

5. A three-dimensional flash memory, wherein small blocks are applied to the three-dimensional flash memory, the three-dimensional flash memory comprising: Multiple memory cell strings are formed on a substrate to extend in a first direction, each memory cell string including a channel layer and a charge storage layer surrounding the channel layer; Multiple word lines are connected to the plurality of memory cell strings in a second direction perpendicular to the first direction. The multiple word lines are grouped into multiple word line groups to correspond to multiple small blocks respectively. The plurality of memory cell strings are grouped into the plurality of small blocks. as well as At least one switching element is connected to a word line wiring configured to control the plurality of word lines, the at least one switching element being configured to selectively apply a voltage to any one of the plurality of word line groups, and The plurality of word line groups are spaced apart from each other in a third direction perpendicular to both the first direction and the second direction.

6. The three-dimensional flash memory of claim 5, wherein the word line routing is shared among the plurality of blocks.

7. A 3D flash memory, wherein small blocks are applied to the 3D flash memory, the 3D flash memory comprising: At least one string of memory cells is formed on a substrate to extend in a first direction, each string of memory cells including a channel layer and a charge storage layer surrounding the channel layer; Multiple word lines are connected to the at least one memory cell string in a second direction perpendicular to the first direction. The multiple word lines are grouped into multiple word line groups to correspond to multiple small blocks respectively. The vertical storage area of ​​the at least one memory cell string is grouped into the multiple small blocks. as well as At least one switching element is connected to a word line wiring configured to control the plurality of word lines, the at least one switching element being configured to selectively apply a voltage to any one of the plurality of word line groups, and The plurality of word line groups are spaced apart from each other in a third direction perpendicular to both the first direction and the second direction.

8. The three-dimensional flash memory of claim 7, wherein the word line routing is shared among the plurality of blocks.

9. A three-dimensional flash memory, wherein peripheral unit circuitry is applied to the three-dimensional flash memory, the three-dimensional flash memory comprising: Substrate; as well as Multiple memory cell strings are formed on the substrate, each memory cell string extending in one direction, and each of the multiple memory cell strings includes a channel layer and a charge storage layer surrounding the channel layer. The substrate is formed into a cell region and a peripheral region. Multiple memory cell transistors associated with the plurality of memory cell strings are formed in the cell region, and at least one peripheral region transistor is formed in the peripheral region. The at least one peripheral region transistor is a remaining transistor among the transistors associated with the operation of the 3D flash memory, excluding the plurality of memory cell transistors. The substrate is formed as a single layer. The cell region is located in the central portion of the substrate, and the plurality of memory cells are strung together in the central portion of the substrate. The peripheral region is located in the peripheral portion surrounding the unit region on the substrate, and The transistor density of the peripheral transistors formed in the peripheral region is higher in the first portion corresponding to the plurality of electrode layers on the substrate than in the outer portion outside the first portion.

10. A three-dimensional flash memory, comprising: At least one string, formed in a U-shape to include a horizontal portion and a vertical portion relative to a substrate, the at least one string including a charge storage layer formed as a hollow tube extending and a channel layer filling the interior of the charge storage layer; Multiple word lines, orthogonal to and connected to the vertical portion of the at least one string; as well as Two bit lines are formed to extend parallel to the horizontal portion of the at least one string, and the two bit lines are connected to both ends of the at least one string. Wherein, one of the two bit lines is used as the drain line, and the other of the two bit lines is used as the source line, and The vertical portion is symmetrical with respect to the horizontal portion.

11. The three-dimensional flash memory of claim 10, wherein each of the two bit lines is selectively usable as a drain line or a source line.

12. The three-dimensional flash memory of claim 10, wherein the two bit lines are in the same plane because the two ends of the at least one string are at the same height.

13. The three-dimensional flash memory of claim 10, wherein one of the plurality of word lines adjacent to the upper portion of the horizontal portion of the at least one string serves as an intermediate signal line, the intermediate signal line being configured to exhaust any one of the vertical portions of the at least one string to perform a programming operation on the memory cells on the remaining vertical portions, and being configured to inject holes into all of the vertical portions of the at least one string to perform an erase operation on the at least one string.

14. A three-dimensional flash memory, wherein peripheral unit circuitry is applied to the three-dimensional flash memory, the three-dimensional flash memory comprising: Substrate; as well as Multiple memory cell strings are formed on the substrate, each memory cell string extending in one direction, and each of the multiple memory cell strings includes a channel layer and a charge storage layer surrounding the channel layer. The substrate is formed into a cell region, an interlayer insulating layer, and a peripheral region. Multiple memory cell transistors associated with the plurality of memory cell strings are formed in the cell region, with source electrodes buried in the interlayer insulating layer. At least one peripheral transistor is formed in the peripheral region, wherein the at least one peripheral transistor is a remaining transistor among the transistors associated with the operation of the 3D flash memory, excluding the plurality of memory cell transistors. At least one of the plurality of memory cell transistors is connected to the source electrode and at least one of the plurality of memory cell transistors.

15. The three-dimensional flash memory of claim 14, wherein the substrate is formed as a multilayer structure, wherein a bulk polycrystalline silicon substrate serving as the cell region is stacked on a silicon substrate serving as the peripheral portion region in the multilayer structure.

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