Differential Vision Sensor

Abstract

An image sensor comprises an arrangement of pixels, each pixel comprising an acquisition circuit (1), the acquisition circuit (1) comprising: a sensor circuit (11) configured to generate a sensor signal (VLOG) based on a light signal of a photosensor illuminating the pixel; a storage circuit (12) configured to store a storage signal (VSTORE) proportional to the sensor signal (VLOG) during a storage interval; a comparator circuit (13) configured to generate a comparator signal (VCOMP) based on the sensor signal (VLOG) and the storage signal (VSTORE) after a refresh interval. A method of operating an image sensor comprises the steps of: generating a sensor signal (VLOG) based on a light signal of a photosensor illuminating the pixel; storing a storage signal (VSTORE) proportional to the sensor signal (VLOG) during a storage interval; and generating a comparator signal (VCOMP) based on the sensor signal (VLOG) and the storage signal (VSTORE) after a refresh interval.

Description

Technical Field

[0001] The present invention relates to image sensors and methods of operating image sensors. In particular, the present invention relates to a delta vision sensor and corresponding methods. Background Art

[0002] In a conventional camera, an array of photosensitive elements (i.e., an array of pixels) is capable of capturing images at a given frame rate. Newer video standards support 8 megapixels, 33 megapixels, etc., and frame rates of 120 frames per second (fps), 240fps, 300fps, etc., thereby generating video streams with relatively high data rates. In many scenarios, such as when capturing a video stream of a tennis match, the differences between consecutive frames may be relatively small, for example, the differences may only involve the displacement of a moving racket or a flying tennis ball, while the reminder of the scene (e.g., a tennis court) may remain essentially unchanged. Therefore, since parts of the scene remain unchanged, the video stream may include highly redundant data. For example, in order to determine the trajectory of a flying tennis ball relative to the tennis court, processing of the video stream may require powerful video processing equipment.

[0003] Delta vision sensors transmit pixel-level changes only when they occur, providing a low-latency event stream with low bandwidth. The amount of data to be processed is reduced relative to traditional cameras. The processing of the event stream can be implemented by less powerful processing devices than is the case with traditional video streams.

[0004] US7728269 discloses a light array comprising an array of cells. Each cell has a photoelectric sensor that generates a sensor signal according to the light intensity at the cell. A first capacitor is charged by the derivative of the current with respect to time. A threshold detector detects whether the voltage on the first capacitor exceeds a threshold, and generates an output signal if the threshold is exceeded. A discharge device discharges the first capacitor after the output signal is generated. The cell only generates an event when the incident light intensity changes, which reduces the amount of data to be processed.

[0005] US9961291 discloses a pixel acquisition circuit, an image sensor and an image acquisition system. The pixel acquisition circuit includes a photodetection unit, a filter amplifier unit, a sampling and holding unit and an activation control unit. The photodetection unit is used to output a first electrical signal corresponding to the light signal irradiated thereon in real time. The input terminal of the filter amplifier unit is coupled to the output terminal of the photodetector, and can be used to amplify the first electrical signal and filter out signal components below the frequency threshold to output a second electrical signal. The threshold comparison unit is used to determine whether the second electrical signal is greater than the first threshold and / or less than the second threshold, and to generate an activation instruction signal when the second electrical signal is greater than the first threshold or less than the second threshold. The output terminal of the sampling and holding unit is coupled to the interface bus. In response to receiving the activation instruction signal, the activation control unit instructs the sampling and holding unit to acquire and cache the first electrical signal, and sends a transmission request to the interface bus.

[0006] US20160227135 discloses a pixel circuit, which includes a front-end circuit, a transient detector circuit, and an exposure measurement circuit. The front-end circuit includes a photodiode and is configured to transmit a photoreceptor signal from the photodiode exposure. The transient detector circuit is configured to detect a change in the photoreceptor signal. The exposure measurement circuit is configured to measure the photoreceptor signal when the transient detector circuit detects a change in the photoreceptor signal.

[0007] WO 2015 / 036592 discloses a dynamic single photodiode pixel circuit.

[0008] Patrick Lichtsteiner et al. disclosed a 128x128 120dB 15μs delay asynchronous time contrast vision sensor.

[0009] Christian Brandli et al. disclosed a 240x180 130dB 3μs delay global shutter spatiotemporal vision sensor. Summary of the invention

[0010] Improved image sensors and methods of operating image sensors may be needed. In particular, improved delta vision sensors may be needed. In particular, image sensors with improved offset residue in the signal path may be needed. In particular, image sensors with reduced requirements on the implementation of capacitors (in particular, reduced requirements for, for example, linearity, parasitic effects of grounding, etc.) may be needed, so that CMOS capacitors with higher density than metal capacitors used in the prior art may be used. In particular, image sensors with reduced drift rate may be needed. In particular, image sensors with reduced number of comparators may be needed. In particular, image sensors with increased pixel density may be needed.

[0011] The concept of the embodiments of the present invention can be explained as being based on the following observations and recognitions, among others.

[0012] One aspect of the present invention relates to an image sensor, the image sensor comprising an arrangement of pixels, each pixel comprising an acquisition circuit, the acquisition circuit comprising: a sensor circuit configured to generate a sensor signal based on a light signal of a photosensor illuminating the pixel; a storage circuit configured to store a storage signal proportional to the sensor signal during a storage interval; and a comparator circuit configured to generate a comparator signal based on the sensor signal and the storage signal after a refresh interval.

[0013] Another aspect of the invention relates to an image sensor, the image sensor comprising an arrangement of pixels, each pixel comprising an acquisition circuit, the acquisition circuit comprising: a sensor circuit configured to generate a sensor signal based on a light signal of a photosensor illuminating the pixel; a storage circuit configured to store a storage signal proportional to the sensor signal during a storage interval; and a comparator circuit configured to generate a comparator signal based on the sensor signal and the storage signal after a refresh interval. The storage circuit comprises at least one amplifier, the comparator circuit comprises the same at least one amplifier, and the sensor signal is connected to an input of the at least one amplifier, wherein another input of the at least one amplifier is connected to a ground potential, a substrate potential or other common potential via a capacitor.

[0014] Various embodiments may preferably implement the following features.

[0015] In some embodiments, the storage interval is a reset interval or a refresh interval. Storing a storage signal proportional to the sensor signal during the storage interval and comparing the sensor signal to the storage signal after the storage interval can provide a differential vision sensor.

[0016] In some embodiments of the image sensor, the storage signal is connected to ground potential, substrate potential or other common potential via a capacitor. The capacitor has reduced requirements for, for example, linearity, parasitic effects of grounding, etc., so that CMOS capacitors with higher density than metal capacitors can be used.

[0017] In some embodiments of the image sensor, the storage circuit comprises at least one amplifier or high gain amplifier stage, wherein the output of the at least one amplifier or high gain amplifier stage provides the storage signal during the storage interval. The at least one amplifier or high gain amplifier stage may be designed to provide for a particularly improved storage signal.

[0018] In some embodiments of the image sensor, the storage circuit includes a first amplifier and a second amplifier, wherein the first amplifier is connected to the sensor signal and the storage signal, wherein the second amplifier is connected to the output of the first amplifier and a hysteresis signal having a predetermined signal level during a storage interval, wherein a switch connects the output of the second amplifier to the storage signal during the storage interval, and wherein the switch disconnects the output of the second amplifier from the storage signal after the storage interval. The signal levels of the first amplifier, the second amplifier, and the hysteresis signal can be designed to provide for a particularly improved storage signal.

[0019] In some embodiments of the image sensor, the comparator circuit comprises at least one amplifier or high-gain amplification stage, wherein the comparator signal is additionally generated after the storage interval during a first interval as a function of the first offset signal and during a second interval as a function of the second offset signal. The at least one amplifier or high-gain amplification stage may be designed to provide for a particularly improved storage signal.

[0020] In some embodiments of the image sensor, the comparator circuit includes a first amplifier and a second amplifier, wherein the first amplifier is connected to the sensor signal and the storage signal, wherein the second amplifier is connected to the output of the first amplifier and a hysteresis signal, the hysteresis signal having a predetermined first offset signal during the first interval and a predetermined second offset signal during the second interval after the storage interval, wherein the output of the second amplifier is connected to the comparator signal. The first amplifier, the second amplifier, the first offset signal, and the second offset signal can be designed to provide for a particularly improved storage signal.

[0021] In some embodiments of the image sensor, the storage circuit comprises at least one amplifier or high-gain amplifier stage, and the comparator circuit comprises the same at least one amplifier or high-gain amplifier stage. The pixel density may be increased.

[0022] In some embodiments of the image sensor, the storage circuit includes a first amplifier and a second amplifier, wherein the comparator circuit includes the same first amplifier and the same second amplifier. The pixel density may be increased.

[0023] In some embodiments of the image sensor, the acquisition circuit further comprises a first 1-bit storage block connectable to the comparator signal during the first interval and a second 1-bit storage block connectable to the comparator signal during the second interval.

[0024] In some embodiments of the image sensor, the acquisition circuit also includes a first signal line and a second signal line, which are respectively associated with the first 1-bit storage block and the second 1-bit storage block, and are connected to a source voltage or floating according to the bit stored in the corresponding 1-bit storage block and according to the state of the row line.

[0025] In some embodiments of the image sensor, the acquisition circuit further comprises a signal line for refreshing the storage signal.

[0026] In some embodiments of the image sensor, the acquisition circuit further comprises a logic gate for refreshing the storage signal according to the processing of the comparator signal.

[0027] In some embodiments of the image sensor, the acquisition circuit further comprises a readout circuit for reading the sensor signal.

[0028] In some embodiments of the image sensor, the image sensor is a metal oxide semiconductor.

[0029] In some embodiments, the capacitor is a high density capacitor, preferably a MOS capacitor or a polycrystalline-polycrystalline capacitor, wherein more preferably, the bottom plate of the capacitor is shorted to ground potential, substrate potential or other common potential.

[0030] Another aspect of the present invention relates to a method of operating an image sensor, the image sensor comprising an arrangement of pixels, each pixel comprising an acquisition circuit, preferably an acquisition circuit according to the above-mentioned aspect, the method comprising: using the sensor circuit to generate a sensor signal based on a light signal of a photosensor illuminating the pixel; during a storage interval, storing a storage signal proportional to the sensor signal in the storage circuit; and after a refresh interval, using a comparator circuit to generate a comparator signal based on the sensor signal and the storage signal.

[0031] Another aspect of the present invention relates to a method for operating an image sensor, the image sensor comprising an arrangement of pixels, each pixel comprising an acquisition circuit, preferably, a method for operating an image sensor according to the above aspects, the method comprising: using a sensor circuit to generate a sensor signal based on a light signal of a photosensor illuminating the pixel; during a storage interval, storing a storage signal proportional to the sensor signal in the storage circuit; and after a refresh interval, using a comparator circuit to generate a comparator signal based on the sensor signal and the storage signal, wherein the storage circuit comprises at least one amplifier, the comparator circuit comprises at least one identical amplifier, wherein the sensor signal is connected to an input of at least one amplifier, and wherein another input of at least one amplifier is connected to a ground potential, a substrate potential or other common potential via a capacitor.

[0032] Various embodiments may preferably implement the following features.

[0033] In some embodiments of the method, storing the storage signal includes providing the storage signal at an output of the at least one amplifier during a storage interval.

[0034] In some embodiments of the method, the storage circuit includes a first amplifier and a second amplifier, wherein the first amplifier is connected to the sensor signal and the storage signal, wherein the method further includes: providing a hysteresis signal having a predetermined signal level during a storage interval and connecting the second amplifier to the output of the first amplifier and the hysteresis signal; and connecting the output of the second amplifier to the storage signal via a switch during the storage interval; and controlling the switch to disconnect the output of the second amplifier from the storage signal after the storage interval.

[0035] In some embodiments of the method, the comparator circuit comprises at least one amplifier, wherein the method further comprises generating the comparator signal additionally during the first interval as a function of the first offset signal and during the second interval as a function of the second offset signal after the storage interval.

[0036] In some embodiments of the method, the comparator circuit includes a first amplifier and a second amplifier, wherein the method further includes: connecting the first amplifier to the sensor signal and the storage signal; and providing a hysteresis signal having a predetermined first offset signal during the first interval and a predetermined second offset signal during the second interval after the storage interval; and connecting the second amplifier to the output of the first amplifier and the hysteresis signal and connecting the output of the second amplifier to the comparator signal.

[0037] In some embodiments of the method, the method further comprises connecting a first 1-bit storage block of the acquisition circuit to the comparator signal during the first interval and connecting a second 1-bit storage block of the acquisition circuit to the comparator signal during the second interval.

[0038] In some embodiments of the method, the method further includes: associating a first signal line of the acquisition circuit and a second signal line of the acquisition circuit with a first 1-bit storage block and a second 1-bit storage block, respectively, and connecting the first signal line and the second signal line to a source voltage or floating according to the bits stored in the corresponding 1-bit storage blocks and according to the state of the row line.

[0039] In some embodiments of the method, the method further includes refreshing the storage signal using a signal line of the acquisition circuit.

[0040] In some embodiments of the method, the method further comprises refreshing the storage signal based on processing the comparator signal via a logic gate.

[0041] In some embodiments of the method, the acquisition circuit further comprises a readout circuit, wherein the method further comprises reading out a diode signal related to the sensor signal through the readout circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] In the following, advantageous embodiments of the invention are described with reference to the accompanying drawings. However, neither the drawings nor the description should be interpreted as limiting the invention.

[0043] Figure 1 is a schematic block diagram of a single unit of an image sensor according to the prior art;

[0044] Figure 2a is a schematic block diagram of an acquisition circuit of a pixel of an image sensor according to some embodiments of the present invention;

[0045] Figure 2b is a schematic block diagram of an acquisition circuit of a pixel of an image sensor according to some embodiments of the present invention;

[0046] Figure 2c is an alternative structure of a storage circuit and a comparator circuit according to some embodiments of the present invention;

[0047] Figure 2ca is a first implementation of a voltage bias block;

[0048] Figure 2cb is a second implementation of a voltage bias block;

[0049] Figure 2d is another alternative structure of the storage circuit and the comparator circuit according to some embodiments of the present invention;

[0050] Figure 3 is a schematic timing diagram of signals of an acquisition circuit of a pixel of an image sensor according to some embodiments of the present invention;

[0051] Figure 4is a schematic block diagram of a plurality of pixels of an image sensor according to some embodiments of the present invention;

[0052] Figure 5 is a schematic block diagram of four pixels arranged at specific positions of an image sensor according to some embodiments of the present invention;

[0053] Figure 6 is a schematic block diagram of a readout circuit for a pixel of an image sensor according to some embodiments of the present invention.

[0054] The figures are schematic only. The same reference numerals may refer to the same or similar features. DETAILED DESCRIPTION

[0055] Figure 1 is a schematic block diagram of a single unit of an image sensor according to the prior art, for example as disclosed in US9961291. US7728269 can achieve the same functionality. The unit comprises a photodiode D1, a first amplifier stage comprising an amplifier A1, a second amplifier stage comprising an amplifier A2, a threshold detecting stage having thresholds VH, VL, a handshake stage having request lines Row_Req, Col_Req and acknowledgement lines Row_Ack, Col_Ack, and an analog bus Col_analog_bus. The first amplifier stage having amplifier A1 provides a voltage related to the incident light intensity at the photodiode D1. The voltage related to the light intensity at the photodiode D1 is fed to a second amplifier stage having amplifier A2. The second amplifier stage having amplifier A2 comprises a switched capacitor amplifier, which comprises a capacitor CAC and a capacitor C1. The output of the second amplifier stage with amplifier A2 is connected to a threshold stage which provides an OFF (disconnection) signal and an ON (connection) signal according to a comparison of the output with thresholds VH and VL. The OFF signal and the ON signal are fed to a logic gate G1, the output of which is fed to a handshake stage H1 having request / acknowledgement lines Row_Req, Col_Req, Row_Ack, Col_Ack. The analog bus Col_analog_bus is connected to one end of a capacitor CAC via transistors M2, M3. The method according to US9961291 is described in detail. Figure 1 Operation of the circuit. US7728269 is able to achieve the same functionality. The operation of the circuit comprises changing the state of the switch SW of the second amplifier stage. Advantageously, the ratio CAC / C1 is set to be quite high, for example CAC / C1=10.

[0056] As will be further explained below, according to Figure 1 The unit has several disadvantages. One disadvantage is related to the offset residue in the signal path. Another disadvantage is related to the requirements for the implementation of the capacitor CAC, namely that the implementation is required to ensure sufficient linearity and negligible parasitic effects. Another disadvantage is related to the drift rate when the switch SW is disconnected. A further disadvantage is that the threshold stage includes two comparators.

[0057] Note that the term "amplifier" in the following description of the invention is generally applicable to a high gain amplifier stage. As shown below, the invention is insensitive to the actual gain of the high gain stage and is therefore tolerant to variations in manufacturing and operating conditions (supply voltage, temperature).

[0058] Figure 2a 1 is a schematic block diagram of an acquisition circuit 1 of a pixel of an image sensor according to some embodiments of the present invention. A light detection circuit 11 provides a sensor signal VLOG and a diode signal VPD, which depends on the light intensity received at the photosensor of the pixel. The sensor signal VLOG is received in a storage circuit 12 to store a storage signal VSTORE, in particular during a refresh interval. The sensor signal VLOG and the storage signal VSTORE are received in a comparator circuit 13 to generate a comparator signal VCOMP from the sensor signal VLOG and the storage signal VSTORE, in particular after a refresh interval. The comparator signal VCOMP is received in a controller circuit 14, which interacts with an interface bus 16 and controls the storage circuit 12, the comparator circuit 13 and an APS reader 15 (APS: Active Pixel Sensor). The APS reader 15 receives the diode signal VPD and provides an output to the interface bus 16, in particular after a refresh interval.

[0059] Figure 2b is a schematic block diagram of an acquisition circuit 1 of a pixel of an image sensor according to some embodiments of the present invention. The anode of the photodiode D1 is grounded. The cathode of the photodiode D1 is connected to the source of the transistor M2 and the gate of the transistor M1. The cathode of the photodiode D1 provides a diode signal VPD. The source of the transistor M1 is grounded. The drain of the transistor M1 is connected to the gate of the transistor M2, to the inverting input of the first amplifier A1, and to the source voltage VDD via the current source I1. The inverting input of the first amplifier A1 receives the sensor signal VLOG. The diode current ID1 through the photodiode D1 depends on the light intensity at the photodiode D1. The diode current ID1 and the sensor signal VLOG have a logarithmic relationship. The APS readout block 15 (APS: Active Pixel Sensor) is connected to the diode signal VPD.

[0060] In the present disclosure, they are referred to as the inverting input and the non-inverting input of the amplifier, respectively. However, since they can be interchangeable, the inverting input and the non-inverting input can also be referred to as "one input" and "another input" or "first input" and "second input", and according to some examples of the present disclosure, they can be connected in any way.

[0061] Once the op amp is involved in sampling, it is defined as “active”. When the feedback is connected to the inverting input or equivalent, it is defined as “negative feedback”.

[0062] The method comprises the following steps:

[0063] Step 1. Sense the signal at a specific time and store it into C1,

[0064] Step 2. Continuously sense the input, amplify the difference and compare it with a given threshold,

[0065] Step 3. If a state change occurs, store the event in memory and report (output) the state.

[0066] like Figure 2b As shown, the photodiode D1, transistors M1, M2 and current source I1 belong to Figure 2a The light detection circuit 11.

[0067] The examples and embodiments of the present disclosure are described using the term "ground potential (ground)" as a reference potential. However, the present disclosure also includes the use of a common potential different from the ground potential or substrate potential. Therefore, the terms "ground potential", "substrate potential" and "(other) common potential" can be used interchangeably.

[0068] The sensor signal VLOG is connected to the inverting input of the first amplifier A1. The non-inverting input of the first amplifier A1 is connected to the ground potential, substrate potential or other common potential via the capacitor C1. Therefore, one end of the capacitor C1 is connected to the non-inverting input of the first amplifier A1, and the other end of the capacitor C1 is connected to the ground potential. As will be further explained below, the end of the capacitor C1 connected to the non-inverting input of the first amplifier A1 has a storage signal VSTORE.

[0069] The output of the first amplifier A1 is connected to the inverting input of the second amplifier A2. The non-inverting input of the second amplifier A2 is connected to the signal line VHYS, which will be further described below. The output of the second amplifier A2 is connected to the end of the capacitor C1 connected to the non-inverting input of the first amplifier A1 via the switch SW. The switch SW is controlled by the signal line Fresh, which will be further described below. The output of the second amplifier A2 has a comparator signal VCOMP.

[0070] like Figure 2bAs shown, amplifiers A1, A2, switch SW and capacitor C1 belong to Figure 2a The storage circuit 12 (during the refresh interval) and the comparator circuit 13 (after the refresh interval) are configured.

[0071] The comparator signal VCOMP is connected to the switch SW1 and is connected to the switch SW2 via an inverter. The switch SW1 is controlled by the signal line ф1 and the switch SW2 is controlled by the signal line ф2. The signals ф1 and ф2 will be further described below. The other ends of the switches SW1 and SW2 are respectively connected to their respective 1-bit storage blocks. The 1-bit storage blocks are each controlled by the control signal line Reset, which will be further described below. The output of the 1-bit storage block connected to the switch SW1 provides the signal line Up. The output of the 1-bit storage block connected to the switch SW2 provides the signal line Down. The signal line Up is connected to one input of the logic gate G1. The signal line Down is connected to one input of the logic gate G2. The signal line RowSel is connected to the other input of each logic gate G1 and G2. The logic gates G1 and G2 respectively control the switch arranged between the source voltage VDD and the signal line providing the signal Stronger and the switch arranged between the source voltage VDD and the signal line providing the signal Weaker.

[0072] The logic gates G1, G2 and the other logic gates G3, G4, G5 explained below are illustrated in the figure using functional symbols. These logic gates can be implemented in different ways.

[0073] like Figure 2b As shown, switches SW1, SW2, 1-bit storage block, gates G1, G2, G3, G4, G5 belong to Figure 2a Controller circuit 14.

[0074] The signal line Up is also connected to an input of the logic gate G3. The signal line Down is also connected to another input of the logic gate G3. The output of the logic gate G3 is connected to an input of the logic gate G4. Another input of the logic gate G4 is connected to the signal line Refresh, which will be further described below. The output of the logic gate G4 is connected to the input of the logic gate G5. Another input of the logic gate G5 is connected to the above-mentioned signal line Reset. The output of the logic gate G5 provides the above-mentioned signal line Fresh for controlling the switch SW. The logic gates G1, G2, and G4 are AND gates providing a logical AND function, and the logic gates G3 and G5 are OR gates providing a logical OR function.

[0075] Figure 2c Schematically shows an alternative structure of the storage circuit 12 and the comparator circuit 13. Figure 2cAs shown, the sensor signal VLOG is connected to the non-inverting input of the first amplifier A1. The inverting input of the first amplifier A1 is connected to the ground potential via the first capacitor C1. The output of the first amplifier A1 is connected to one end of the first capacitor C1 connected to the inverting input of the first amplifier A1 via the switch SW. The switch SW is controlled by the signal Fresh. The output of the first amplifier A1 is also connected to the non-inverting input of the second amplifier A2 via the second capacitor C2. Figure 2c As shown, the second amplifier A2 is configured as a comparator. The inverting input of the second amplifier A2 is connected to the signal line VHYS. The output of the second amplifier A2 has a comparator signal VCOMP, which is connected to the signal line VHYS. Figure 2b The 1-bit storage block. Figure 2c As shown, the voltage bias block is connected to one end of the second capacitor C2 connected to the non-inverting input of the second amplifier A2. The voltage bias block receives a reference signal VREF. The voltage bias block defines a DC voltage of a VCAC node connected to one end of the second capacitor C2 connected to the non-inverting input of the second amplifier A2. Figure 2ca A first implementation of a voltage biasing block based on a large resistor connected between the reference signal VREF and the VCAC node is shown. Figure 2cb A second embodiment of a voltage biasing block based on a switch connected between a reference signal VREF and a VCAC node and controlled by a signal Fresh is shown.

[0076] Figure 2d Another alternative structure of the storage circuit 12 and the comparator circuit 13 is schematically shown. From the sensor signal VLOG to the VCAC node, according to Figure 2d The structure is equal to Figure 2c The structure of Figure 2d As shown, the VCAC node is connected to the non-inverting input of the upper second amplifier A2UP and the inverting input of the lower second amplifier A2DOWN. Figure 2d As shown, the upper second amplifier A2UP and the lower second amplifier A2DOWN are configured as a comparator. The inverting input of the upper second amplifier A2UP is connected to the reference signal VREF_PLUS. The non-inverting input of the lower second amplifier A2DOWN is connected to the reference signal VREF_MINUS. The output of the upper second amplifier A2UP provides a signal VCOMP_UP connected to a 1-bit storage block. The output of the lower second amplifier A2DOWN provides a signal VCOMP_DOWN, which is inverted and connected to a 1-bit storage block.

[0077] With no second capacitor C2 according to Figure 2b Compared with the structure of Figure 2c and Figure 2d The advantage of the structure is that it has an additional high-pass filter.

[0078] Figure 3 is a schematic timing diagram of signals of an acquisition circuit 1 of a pixel of an image sensor according to some embodiments of the present invention. Figure 3 Includes a schematic timing diagram of the signals on signal lines ф1 and ф2 used to control switches SW1 and SW2. Figure 3 Schematic timing diagram of the signals on the signal line Reset is included. Reset is performed regularly at a predetermined frequency (e.g. 1 Hz). All pixels share the reset. This means that the reset signal will reset all pixels. Figure 3 A schematic timing diagram of a signal on a signal line VHYS connected to a non-inverting input of a second amplifier A2 is included. Figure 3 A schematic timing diagram of the signals on the signal line RowSel connected to the respective inputs of the logic gates G1 and G2 is included. The signals ф1, ф2, Reset and RowSel change between a low state and a high state to control the respective switches or logic gates. The signal VHYS changes between the signal levels VREF, VREF_PLUS and VREF_MINUS. Figure 3 As shown, the transition of the signal RowSel from a high state to a low state defines the beginning and end of a cycle.

[0079] Below, reference Figure 2b and Figure 3 The working principle of the image sensor according to some embodiments of the present invention is described.

[0080] In reset mode, VHYS is set to VREF. All pixels share the same Reset. When Reset is high, switch SW receives a logic 1 signal and SW is closed. The signal at the output of the second amplifier becomes VCOMP=VSTORE=VLOG-offset. VLOG-offset is stored in capacitor C1.

[0081] In auto-zero mode, that is, during the refresh interval, VHYS is set to VREF. When the signal Refresh is high, if neither the Up or Down signal is high, the switch SW receives a logic 0 signal and does not refresh. When the signal Refresh is high, if the Up or Down signal is high, the switch SW receives a logic 1 signal and SW is closed. The signal at the output of the second amplifier becomes VCOMP = VSTORE = VLOG-offset. The offset includes systematic offset (due to the finite gain of A1 and A2) and random offset (due to mismatch of components inside A1 and A2). The VLOG-offset is stored in capacitor C1. As Figure 2b As shown, the 1-bit storage block is set to logic 0.

[0082] like Figure 3 As shown, the signal Refresh becomes low. Accordingly, the switch SW is disconnected. The first amplifier A1 and the second amplifier A2 now operate as comparators. The VCOMP at the output of the second amplifier depends on VSTORE, VLOG and VHYS. VSTORE is the signal stored in the capacitor C1 during the refresh period. VLOG is related to the light intensity change at the photodiode D1.

[0083] In ф1 mode, i.e. during the first interval, VHYS is Figure 3 The timing diagram shown is set to VREF_PLUS, and the signal ф1 is set to a high state. The difference between VREF and VREF_PLUS is the hysteresis. According to the signal ф1, the switch SW1 is closed. VCOMP indicates whether the signal increase of VLOG is higher or lower than VSTORE+(VREF_PLUS-VREF) / A1. For example, if the signal increase is higher than (VREF_PLUS-VREF) / A1, VCOMP becomes logic "1", otherwise VCOMP becomes logic "0". The result is stored in a 1-bit storage block connected to the switch SW1, that is, if the signal increase of VLOG is higher than (VREF_PLUS-VREF) / A1, logic "1" is stored; if the signal increase of VLOG is lower than (VREF_PLUS-VREF) / A1, logic "0" is stored.

[0084] In ф2 mode, i.e. during the first interval, VHYS is Figure 3 The timing diagram shown is set to VREF_MINUS, and the signal ф2 is set to a high state. The difference between VREF and VREF_MINUS is hysteresis. According to the signal ф2, the switch SW2 is closed. VCOMP indicates whether the signal decrease of VLOG is higher or lower than VSTORE+(VREF-VREF_MINUS) / A1. For example, if the signal decrease of VLOG is higher than VSTORE+(VREF-VREF_MINUS) / A1, VCOMP becomes logic "0", otherwise VCOMP becomes logic "1". The result is inverted and stored in a 1-bit storage block connected to the switch SW2, that is, if the signal decrease of VLOG is higher than VSTORE+(VREF-VREF_MINUS) / A1, logic "1" is stored; if the signal increase of VLOG is lower than VSTORE+(VREF-VREF_MINUS) / A1, logic "0" is stored.

[0085] To read out the pixels, Figure 3 As shown in FIG. 1 , the signal line RowSel is set to a high state. Figure 2bAs shown, the signal line RowSel forms one input of the logic gates G1 and G2, and each output of the 1-bit storage block forms another input of the corresponding logic gates G1 and G2. According to the data in the 1-bit storage block, the signal line Stronger and the signal line Weaker are pulled up to the source voltage VDD or have a high impedance (i.e., have a floating output). By applying a current between the signal line Stronger and the ground potential and between the signal line Weaker and the ground potential, respectively, a logic "1" or a logic "0" can be read from the pixel. Since the signal line Stronger and the signal line Weaker are respectively at high impedance (instead of generating a logic "0"), a single signal line is sufficient to read the Stronger signal and the Weaker signal of the pixels arranged in columns and rows, respectively.

[0086] During pixel reading, if one of the Up and Down signals (or both, which is undesirable and should be very rare) is high, a high state is generated on the signal line Refresh as described above to close the switch SW controlled by the signal line Refresh. Therefore, the VCOMP=VSTORE=VLOG-offset generated by the current light intensity at the photodiode D1 is stored on the capacitor C1 for the next detection of the change in light intensity at the photodiode D1.

[0087] Figure 4 is a schematic block diagram of a plurality of pixels of an image sensor according to some embodiments of the present invention. The pixels are arranged in an array of N columns and M rows. The pixels of a particular row share a single line RowSel <m>, where m represents the row number, between 0 and M-1. Pixels in the same column share a single line c_st associated with the Stronger signal <n>and the single line c_wk associated with the Weaker signal <n>, where n is the column number, between 0 and N-1. Figure 4 As shown, the line c_st<..> related to the Stronger signal is connected to the readout circuit block O_st, and the line c_wk<..> related to the Weaker signal is connected to the readout circuit block O_wk. Figure 6 The readout circuit blocks O_st, O_wk are further explained.

[0088] Figure 5 is a schematic block diagram of four pixels arranged at specific positions of an image sensor according to some embodiments of the present invention. Figure 4 As shown, a specific arrangement of pixels is arranged at positions m, n. Figure 5 The arrangement of four pixels at positions m and n is shown. Figure 2b The signal line Stronger and signal line Weaker of the pixel described for a single pixel are connected to the column line c_st respectively<n,n+1> and column line c_wk<n,n+1> As above combined Figure 2b For a single pixel, the signal line RowSel<m,m+1> Connected to the corresponding inputs of the logic gates arranged in the pixel. If a specific signal line RowSel is selected <m>, then depending on the illumination variation of the corresponding pixel, the column line c_wk<..> is pulled up to the source voltage VDD or is in high impedance (floating).

[0089] Figure 6 is a schematic block diagram of a readout circuit for a pixel of an image sensor according to some embodiments of the present invention. Figure 6 The readout circuit O_wk is shown <n>, i.e., a specific one of the N readout circuits of the readout circuit block O_wk. <n>Connected to current source I, which is in turn connected to ground potential. <n>It is also connected to the buffer Buffer, which provides the output signal. <n>is pulled up to the source voltage VDD, the output signal is in a high state, for example, "1". <n>In high impedance (floating), c_wk <n>is pulled to the ground potential, and the output signal is in a low state, for example, “0”. The readout circuit O_st of the readout circuit block has its own structure.

[0090] As described above, the pixel according to the present invention has several advantages.

[0091] The first advantage relates to the offset. Figure 1 , the offset residual or input referred offset in the signal path is VOS = (VOS_Amp) / (1+A)+Vch, where VOS is the total input referred offset, VOS_Amp is the input referred offset of the amplifier, A is the amplifier gain, and Vch is the charge injection error caused when the switch SW changes state. Figure 1 As shown, parasitic capacitance Cpar is included between the input of the amplifier and ground potential. Taking into account the gain, the parasitic capacitance Cpar is designed to be minimized because CAC and Cpar form a capacitive voltage divider, which has the effect of greater Cpar resulting in greater VA attenuation. Figure 1 As shown, ΔVA=Vch=QCH / Cpar, where QCH is the charge injected when the switch SW changes its state. Therefore, Vch can be very large.

[0092] According to the present invention, the input-referred offset is reduced in two ways, providing much better performance than the prior art. First, a high-gain amplifier stage A1 or a two-stage amplifier with a gain is provided, with a higher total gain A=A1 or A=A1×A2. Thus, the total input-referred offset is reduced by the high gain of the amplifier A1 or the gain enhancement of the second stage A2. As a result, the present invention is insensitive to both the gain and the offset of the amplifier. Second, Figure 1 The capacitor C1 shown disposed between the sensitive node VA and the ground potential, substrate potential or other common potential can be designed as a large, high-density capacitor (e.g., MOS capacitor, poly-poly capacitor) to reduce the offset caused by charge injection QCH and expand the dynamic range.

[0093] The second advantage relates to area. Figure 1 The alternating current (AC) coupling topology requires small parasitics (which cause signal attenuation) and high voltage independence (which reduces the linearity of the signal path) for both CAC and C1. Therefore, metal-metal capacitors are selected to implement CAC and C1.

[0094] According to the present invention, the capacitor is connected to the ground potential or substrate potential or other common potential, and since the bottom plate capacitor is shorted to the ground potential, substrate potential or other common potential, a high density capacitor (e.g., MOS capacitor, polycrystalline-polycrystalline capacitor) can be used. Compared with metal-metal capacitors, high density capacitors such as MOS capacitors, polycrystalline-polycrystalline capacitors have higher density and can significantly reduce the area required for the pixel.

[0095] For example, according to the prior art Figure 1 The image sensor needs to have a maximum of 3fF / um 2 Metal capacitors with a capacitance density of about 6 fF / um can be used according to the present invention, where the capacitor requires about 25% of the total pixel area. 2 -7 fF / um 2 The high-density capacitor with a capacitance density of 1.5% reduces the pixel size by about 12.5%.

[0096] The third advantage relates to drift. Figure 1 , when the switch SW is open, the voltage VA drifts over time due to leakage (eg, leakage of the switch SW and leakage at the input of the amplifier A).

[0097] According to the present invention, VSTORE also drifts for similar reasons. However, when the same area is used, as Figure 2b The capacitor C1 shown is Figure 1 The capacitor CAC shown is for example two or three times larger. According to the invention, the drift rate is thus less severe. This allows a lower refresh rate, which has the advantage that slower changes in light intensity at the pixel can be detected.

[0098] The fourth advantage relates to the comparator arrangement. According to the prior art, reference Figure 1 , two comparators are required ( Figure 1 The comparators are labeled ON and OFF in the figure). Each comparator requires a certain area and power. The comparators work in parallel to distinguish whether there is a change in light intensity (ON = 1 / OFF = 0 or ON = 0 / OFF = 1), or whether there is no change in light intensity (ON = 0 and OFF = 0). The mismatch of the comparators, or the difference in VH and VL (see Figure 1 ) must be large enough to mask the mismatch. The input reference (referenced to A1 output) difference of VH and VL is (VH-VL)×C1 / CAC. Due to technology and area limitations, the ratio of C1 to CAC is not large. If the A1 output changes less than (VH-VL)×C1 / CAC, the change is not detected. A large difference between VH and VL results in reduced detection sensitivity.

[0099] According to the present invention, only one comparator is needed. Therefore, a smaller area is required. In addition, the comparator generates Up and Down signals using a small signal VHYS set to VREF, VREF_PLUS or VREF_MINUS (see Figure 2b , Figure 3 ). In auto-zero mode, VHYS = VREF. In ф1 mode, VHYS = VREF_PLUS = VREF + ΔV. ΔV is used as hysteresis. When the increase in VLOG is greater than ΔV / A1, the comparator outputs logic "1", so the signal Up is 1. Otherwise, the signal Up is 0. In ф2 mode, VHYS = VREF_MINUS = VREF-ΔV. ΔV is used as hysteresis. When the decrease in VLOG is greater than ΔV / A1, the comparator outputs logic "0" and is inverted by the inverter, so the signal Down is 1. Otherwise, the signal Down is 0. Therefore, two phases are required in the signal to generate the Up and Down signals, resulting in one cycle (see Figure 3 ) requires more time. For most applications, the difference is in the microsecond range and is therefore not critical. However, there is no mismatch between the two comparators and ΔV can be small enough to be due solely to noise.

[0100] Finally, it should be noted that the term "comprising" does not exclude other elements or steps, and "a" or "an" does not exclude a plurality. Elements described in connection with different embodiments may also be combined. It should also be noted that reference signs in the claims should not be construed as limiting the scope of the claims.< / n> < / n> < / n> < / n> < / n> < / n> < / m> < / n> < / n> < / m>

Claims

1. An image sensor comprising an arrangement of pixels, each pixel comprising an acquisition circuit (1), the acquisition circuit (1) comprising: A sensor circuit (11) configured to generate a sensor signal (VLOG) based on a light signal of a photosensor illuminating the pixel; a storage circuit (12) configured to store a storage signal (VSTORE) proportional to the sensor signal (VLOG) during a storage interval; as well as A comparator circuit (13) configured to generate a comparator signal (VCOMP) based on the sensor signal (VLOG) and the storage signal (VSTORE) after a storage interval; wherein the storage circuit (12) comprises at least one amplifier, the comparator circuit (13) comprises the same at least one amplifier, the sensor signal (VLOG) is connected to an input of the at least one amplifier, another input of the at least one amplifier is connected to ground via a capacitor (C1), and the storage signal (VSTORE) is connected to ground via the capacitor (C1); and wherein the comparator signal (VCOMP) is additionally generated after the storage interval according to the first offset signal (VREF_PLUS) during a first interval (ф1) and according to the second offset signal (VREF_MINUS) during a second interval (ф2); and The first offset signal (VREF_PLUS) and the second offset signal (VREF_MINUS) are respectively voltage offsets relative to a reference signal (VREF).

2. The image sensor according to claim 1, wherein: The output of the at least one amplifier provides a store signal (VSTORE) during a store interval.

3. The image sensor according to claim 1, wherein: The storage circuit (12) includes a first amplifier (A1) and a second amplifier (A2), wherein the first amplifier (A1) is connected to a sensor signal (VLOG) and a storage signal (VSTORE), wherein the second amplifier (A2) is connected to an output of the first amplifier (A1) and a hysteresis signal (VHYS) having a predetermined signal level during a storage interval, wherein a switch (SW) connects the output of the second amplifier (A2) to the storage signal (VSTORE) during the storage interval, and wherein the switch (SW) disconnects the output of the second amplifier (A2) from the storage signal (VSTORE) after the storage interval.

4. The image sensor according to claim 2, wherein: The storage circuit (12) includes a first amplifier (A1) and a second amplifier (A2), wherein the first amplifier (A1) is connected to a sensor signal (VLOG) and a storage signal (VSTORE), wherein the second amplifier (A2) is connected to an output of the first amplifier (A1) and a hysteresis signal (VHYS) having a predetermined signal level during a storage interval, wherein a switch (SW) connects the output of the second amplifier (A2) to the storage signal (VSTORE) during the storage interval, and wherein the switch (SW) disconnects the output of the second amplifier (A2) from the storage signal (VSTORE) after the storage interval.

5. The image sensor according to claim 1, wherein: The comparator circuit (13) comprises a first amplifier (A1) and a second amplifier (A2), wherein the first amplifier is connected to a sensor signal (VLOG) and a storage signal (VSTORE), wherein the second amplifier is connected to an output of the first amplifier (A1) and a hysteresis signal (VHYS), the hysteresis signal (VHYS) having a predetermined first offset signal (VREF_PLUS) during a first interval (ф1) and a predetermined second offset signal (VREF_MINUS) during a second interval (ф2) after the storage interval, and wherein the output of the second amplifier (A2) is connected to a comparator signal (VCOMP).

6. The image sensor according to claim 2, wherein: The comparator circuit (13) comprises a first amplifier (A1) and a second amplifier (A2), wherein the first amplifier is connected to a sensor signal (VLOG) and a storage signal (VSTORE), wherein the second amplifier is connected to an output of the first amplifier (A1) and a hysteresis signal (VHYS), the hysteresis signal (VHYS) having a predetermined first offset signal (VREF_PLUS) during a first interval (ф1) and a predetermined second offset signal (VREF_MINUS) during a second interval (ф2) after the storage interval, and wherein the output of the second amplifier (A2) is connected to a comparator signal (VCOMP).

7. The image sensor according to claim 3, wherein: The comparator circuit (13) comprises an identical first amplifier (A1) and a second amplifier (A2), wherein the first amplifier is connected to a sensor signal (VLOG) and a storage signal (VSTORE), wherein the second amplifier is connected to the output of the first amplifier (A1) and a hysteresis signal (VHYS), the hysteresis signal (VHYS) having a predetermined first offset signal (VREF_PLUS) during a first interval (ф1) and a predetermined second offset signal (VREF_MINUS) during a second interval (ф2) after the storage interval, and wherein the output of the second amplifier (A2) is connected to the comparator signal (VCOMP).

8. The image sensor according to claim 4, wherein: The comparator circuit (13) comprises an identical first amplifier (A1) and a second amplifier (A2), wherein the first amplifier is connected to a sensor signal (VLOG) and a storage signal (VSTORE), wherein the second amplifier is connected to the output of the first amplifier (A1) and a hysteresis signal (VHYS), the hysteresis signal (VHYS) having a predetermined first offset signal (VREF_PLUS) during a first interval (ф1) and a predetermined second offset signal (VREF_MINUS) during a second interval (ф2) after the storage interval, and wherein the output of the second amplifier (A2) is connected to the comparator signal (VCOMP).

9. The image sensor according to any one of claims 1 to 8, wherein: The acquisition circuit (1) also includes a first 1-bit storage block connectable to the comparator signal (VCOMP) during a first interval (ф1) and a second 1-bit storage block connectable to the comparator signal (VCOMP) during a second interval (ф2).

10. The image sensor according to claim 9, wherein: The acquisition circuit (1) also includes a first signal line (Stronger) and a second signal line (Weaker), the first signal line (Stronger) and the second signal line (Weaker) are respectively associated with the first 1-bit storage block and the second 1-bit storage block, and are connected to the source voltage (VDD) or floating according to the bit stored in the corresponding 1-bit storage block and according to the state of the row line (RowSel).

11. The image sensor according to any one of claims 1 to 8, wherein: The acquisition circuit (1) further includes a signal line (Refresh) for refreshing the storage signal (VSTORE).

12. The image sensor according to claim 9, wherein: The acquisition circuit (1) further includes a signal line (Refresh) for refreshing the storage signal (VSTORE).

13. The image sensor according to claim 10, wherein: The acquisition circuit (1) further includes a signal line (Refresh) for refreshing the storage signal (VSTORE).

14. The image sensor according to any one of claims 1 to 8, wherein: The acquisition circuit (1) also includes a logic gate for refreshing the storage signal (VSTORE) according to the processing of the comparator signal (VCOMP).

15. The image sensor according to claim 9, wherein: The acquisition circuit (1) also includes a logic gate for refreshing the storage signal (VSTORE) according to the processing of the comparator signal (VCOMP).

16. The image sensor according to claim 10, wherein: The acquisition circuit (1) also includes a logic gate for refreshing the storage signal (VSTORE) according to the processing of the comparator signal (VCOMP).

17. The image sensor according to any one of claims 1 to 8, wherein: The acquisition circuit (1) further comprises a readout circuit (APS) for reading out a diode signal (VPD) related to the sensor signal (VLOG).

18. The image sensor according to any one of claims 1 to 8, wherein: Image sensors are metal oxide semiconductors.

19. The image sensor according to any one of claims 1 to 8, wherein: The capacitor (C1) is a high density capacitor including a MOS capacitor or a polycrystalline capacitor, and wherein the capacitor (C1) has a bottom plate shorted to a ground potential, a substrate potential or other common potential.

20. A method of operating an image sensor, the image sensor being an image sensor according to any one of claims 1 to 19, the image sensor comprising an arrangement of pixels, each pixel comprising an acquisition circuit (1), the method comprising: Using a sensor circuit (11) to generate a sensor signal (VLOG) based on the light signal of the photosensor illuminating the pixel; During a storage interval, storing a storage signal (VSTORE) proportional to the sensor signal (VLOG) in a storage circuit (12); and A comparator circuit (13) is used to compare the sensor signal (VLOG) and the storage signal (VSTORE), and after a storage interval, a comparator signal (VCOMP) is generated based on the sensor signal (VLOG) and the storage signal (VSTORE), The storage circuit (12) comprises at least one amplifier, the comparator circuit (13) comprises the same at least one amplifier, the sensor signal (VLOG) is connected to an input of the at least one amplifier, another input of the at least one amplifier is connected to ground via a capacitor (C1), the storage signal (VSTORE) is connected to ground via the capacitor (C1), and the method further comprises: generating the comparator signal (VCOMP) additionally during a first interval (ф1) as a function of the first offset signal (VREF_PLUS) and during a second interval (ф2) as a function of the second offset signal (VREF_MINUS) after the storage interval, The first offset signal (VREF_PLUS) and the second offset signal (VREF_MINUS) are respectively voltage offsets relative to a reference signal (VREF).

21. The method according to claim 20, wherein: Storing the store signal (VSTORE) includes providing the store signal (VSTORE) at the output of the at least one amplifier during a storage interval.

22. The method according to claim 20, wherein: The storage circuit (12) comprises a first amplifier (A1) and a second amplifier (A2), wherein the first amplifier (A1) is connected to the sensor signal (VLOG) and the storage signal (VSTORE), Wherein, the method further comprises: providing a hysteresis signal (VHYS) having a predetermined signal level during a storage interval, and connecting a second amplifier (A2) to the output of the first amplifier (A1) and the hysteresis signal (VHYS), and During a storage interval, the output of the second amplifier (A2) is connected to a storage signal (VSTORE) via a switch (SW), and After the storage interval, the switch (SW) is controlled to disconnect the output of the second amplifier (A2) from the storage signal (VSTORE).

23. The method according to claim 21, wherein: The storage circuit (12) comprises a first amplifier (A1) and a second amplifier (A2), wherein the first amplifier (A1) is connected to the sensor signal (VLOG) and the storage signal (VSTORE), Wherein, the method further comprises: providing a hysteresis signal (VHYS) having a predetermined signal level during a storage interval, and connecting a second amplifier (A2) to the output of the first amplifier (A1) and the hysteresis signal (VHYS), and During a storage interval, the output of the second amplifier (A2) is connected to a storage signal (VSTORE) via a switch (SW), and After the storage interval, the switch (SW) is controlled to disconnect the output of the second amplifier (A2) from the storage signal (VSTORE).

24. The method according to claim 20, wherein: The comparator circuit (13) comprises a first amplifier (A1) and a second amplifier (A2), Wherein, the method further comprises: connecting the first amplifier to the sensor signal (VLOG) and the storage signal (VSTORE), and providing a hysteresis signal (VHYS) and connecting the second amplifier to the output terminal of the first amplifier (A1) and the hysteresis signal (VHYS), the hysteresis signal (VHYS) having a predetermined first offset signal (VREF_PLUS) during a first interval (ф1) after the storage interval and having a predetermined second offset signal (VREF_MINUS) during a second interval (ф2), and The output of the second amplifier (A2) is connected to the comparator signal (VCOMP).

25. The method according to claim 21, wherein: The comparator circuit (13) comprises a first amplifier (A1) and a second amplifier (A2), Wherein, the method further comprises: connecting the first amplifier to the sensor signal (VLOG) and the storage signal (VSTORE), and providing a hysteresis signal (VHYS) and connecting the second amplifier to the output terminal of the first amplifier (A1) and the hysteresis signal (VHYS), the hysteresis signal (VHYS) having a predetermined first offset signal (VREF_PLUS) during a first interval (ф1) after the storage interval and having a predetermined second offset signal (VREF_MINUS) during a second interval (ф2), and The output of the second amplifier (A2) is connected to the comparator signal (VCOMP).

26. The method of claim 22, wherein: The comparator circuit (13) comprises a first amplifier (A1) and a second amplifier (A2) which are identical, Wherein, the method further comprises: connecting the first amplifier to the sensor signal (VLOG) and the storage signal (VSTORE), and providing a hysteresis signal (VHYS) and connecting the second amplifier to the output terminal of the first amplifier (A1) and the hysteresis signal (VHYS), the hysteresis signal (VHYS) having a predetermined first offset signal (VREF_PLUS) during a first interval (ф1) after the storage interval and having a predetermined second offset signal (VREF_MINUS) during a second interval (ф2), and The output of the second amplifier (A2) is connected to the comparator signal (VCOMP).

27. The method according to claim 23, wherein: The comparator circuit (13) comprises a first amplifier (A1) and a second amplifier (A2) which are identical, Wherein, the method further comprises: connecting the first amplifier to the sensor signal (VLOG) and the storage signal (VSTORE), and providing a hysteresis signal (VHYS) and connecting the second amplifier to the output terminal of the first amplifier (A1) and the hysteresis signal (VHYS), the hysteresis signal (VHYS) having a predetermined first offset signal (VREF_PLUS) during a first interval (ф1) after the storage interval and having a predetermined second offset signal (VREF_MINUS) during a second interval (ф2), and The output of the second amplifier (A2) is connected to the comparator signal (VCOMP).

28. The method according to any one of claims 20 to 27, further comprising: A first 1-bit storage block of the acquisition circuit (1) is connected to the comparator signal (VCOMP) during a first interval (ф1), and a second 1-bit storage block of the acquisition circuit (1) is connected to the comparator signal (VCOMP) during a second interval (ф2).

29. The method according to claim 28, further comprising: A first signal line (Stronger) of an acquisition circuit (1) and a second signal line (Weaker) of an acquisition circuit (1) are associated with a first 1-bit storage block and a second 1-bit storage block, respectively, and the first signal line and the second signal line are connected to a source voltage (VDD) or floated according to the bits stored in the corresponding 1-bit storage blocks and according to the state of a row line (RowSel).

30. The method according to any one of claims 20 to 27, further comprising: The storage signal (VSTORE) is refreshed using the signal line (Refresh) of the acquisition circuit (1).

31. The method according to any one of claims 20 to 27, further comprising: The storage signal (VSTORE) is refreshed according to the processing of the comparator signal (VCOMP) through the logic gate.

32. The method according to any one of claims 20 to 27, wherein: The acquisition circuit (1) further comprises a readout circuit (APS), The method further comprises: reading out a diode signal (VPD) related to the sensor signal (VLOG) via a readout circuit (APS).

Images