A method and a circuit for measuring the setup time of a timing unit

Abstract

The present application provides a method and a circuit for measuring the setup time of a timing unit. The measurement method is applicable to a circuit for measuring the setup time of a timing unit, and the measurement method includes: respectively determining a first period value, a second period value, and a third period value of a clock signal, where the first period value is a critical period for the timing unit under test to correctly receive the clock signal in a first test path, the second period value is a critical period for a delay detection module to correctly receive the clock signal in a second test path, and the third period value is a critical period for the delay detection module to correctly receive the clock signal in a third test path; determining the setup time of the timing unit according to the first period value, the second period value, and the third period value.

Description

Technical Field

[0001] This application relates to the technical field of measurement of digital integrated circuits, for example, to a method and a circuit for measuring the setup time of a timing unit. Background Art

[0002] The setup time of a timing unit is one of the important factors affecting the stable transmission of signal data. When designing a timing unit library, the accurate measurement of the setup time of the timing unit directly affects the performance, production, and manufacturing of the chip. In the prior art, the clock phase fine adjustment method or using multiple buffers as the minimum measurement scale is usually adopted to equivalently measure the setup time. However, these methods have many deficiencies. For example, limited by the small adjustable range of the clock phase and the delay of the buffers, there are differences in the measured clock path and data path, and this difference is more obvious under different test voltages, resulting in a very large measurement error of the setup time of the timing unit. Summary of the Invention

[0003] In view of this, embodiments of this application provide a method and a circuit for measuring the setup time of a timing unit to improve the measurement accuracy of the setup time of the timing unit and meet the performance requirements of the chip.

[0004] Embodiments of this application provide a circuit for measuring the setup time of a timing unit. The measurement circuit includes a clock signal generation module, a first selection module, a second selection module, a delay detection module, a data signal transmission module, a clock signal transmission module, a timing unit to be measured, and a control module;

[0005] Wherein, the clock signal generation module is electrically connected to the first selection module, the delay detection module, and the control module respectively; the delay detection module is electrically connected to the first selection module, the second selection module, and the control module respectively; the first selection module is electrically connected to the control module, the data signal transmission module, and the clock signal transmission module respectively; the second selection module is electrically connected to the control module, the data signal transmission module, and the clock signal transmission module respectively; the data signal transmission module is electrically connected to the timing unit to be measured and the control module respectively, the clock signal transmission module is electrically connected to the timing unit to be measured and the control module respectively, and the timing unit to be measured is electrically connected to the control module;

[0006] The control module is used to control the first selection module and the second selection module to form a first test path, a second test path, and a third test path, so as to determine the setup time of the timing unit based on the first test path, the second test path, and the third test path. Wherein, the first test path is composed of the clock signal generation module, the data signal transmission module, the clock signal transmission module, the timing unit under test, and the control module; the second test path is composed of the clock signal generation module, the delay detection module, the data signal transmission module, and the control module; the third test path is composed of the clock signal generation module, the delay detection module, the clock signal transmission module, and the control module.

[0007] An embodiment of the present application further provides a method for measuring the setup time of a timing unit. This measurement method is applicable to the timing unit setup time measurement circuit described in the embodiment of the present application. The measurement circuit includes a clock signal generation module, a first selection module, a second selection module, a delay detection module, a data signal transmission module, a clock signal transmission module, a timing unit under test, and a control module. The control module controls the first selection module and the second selection module to form a first test path, a second test path, and a third test path. The first test path is composed of the clock signal generation module, the data signal transmission module, the clock signal transmission module, the timing unit under test, and the control module; the second test path is composed of the clock signal generation module, the delay detection module, the data signal transmission module, and the control module; the third test path is composed of the clock signal generation module, the delay detection module, the clock signal transmission module, and the control module;

[0008] The method includes:

[0009] Determine the first cycle value, the second cycle value, and the third cycle value of the clock signal respectively. Wherein, the first cycle value is the critical cycle when the timing unit under test correctly receives the clock signal in the first test path; the second cycle value is the critical cycle when the delay detection module correctly receives the clock signal in the second test path; the third cycle value is the critical cycle when the delay detection module correctly receives the clock signal in the third test path;

[0010] Determine the setup time of the timing unit according to the first cycle value, the second cycle value, and the third cycle value.

[0011] More descriptions about the above embodiments and other aspects of the present application and their implementation manners are provided in the accompanying drawings, the specific implementation manners, and the claims. Description of the Drawings

[0012] Figure 1 It is a schematic diagram of the setup time of a timing unit in the prior art;

[0013] Figure 2 It is a schematic structural diagram of a measurement circuit for the setup time of a timing unit provided by an embodiment of the present application;

[0014] Figure 3 It is a schematic structural diagram of another measurement circuit for the setup time of a timing unit provided by an embodiment of the present application;

[0015] Figure 4 It is a flowchart of a method for measuring the setup time of a timing unit provided by an embodiment of the present application;

[0016] Figure 5 It is a flowchart of a method for determining the period value of a clock signal provided by an embodiment of the present application;

[0017] Figure 6 It is a flowchart of a method for determining N critical period test values provided by an embodiment of the present application;

[0018] Figure 7 It is a flowchart of a method for determining the estimated range of the critical period of a clock signal provided by an embodiment of the present application. Detailed implementation manners

[0019] Embodiments of the present application will be described below in conjunction with the accompanying drawings. Without conflict, the embodiments in the present application and the features in the embodiments can be combined arbitrarily with each other.

[0020] Figure 1 It is a schematic diagram of the setup time of a timing unit in the prior art. Refer to Figure 1 , the setup time (tsu: setup time) of a timing unit (such as a flip-flop) refers to the time during which the data signal needs to remain stable before the rising edge of the clock signal of the timing unit arrives. If the setup time tsu is not sufficient, the data will not be stably latched into the flip-flop at this clock rising edge, and the setup time tsu refers to this minimum stable time.

[0021] In the prior art, the setup time of a timing unit can be obtained by simulation using a spice tool during the design of the cell library, but this is only a theoretical calculation value. If the theoretical calculation value is larger than the actual value in the chip, it will add unnecessary difficulties to the backend timing convergence. If the theoretical calculation value is smaller, it may cause timing problems after the chip is produced, and the chip cannot reach the actual operating frequency. Therefore, it is very important to maintain the consistency between the theoretical and actual values of the setup time after the design of the timing cell library is completed. To ensure the consistency between the actual value and the theoretical value of the setup time, it is usually necessary to measure and verify the setup time.

[0022] In an existing technical solution, a method for measuring the setup time based on fine adjustment of the clock phase is proposed. For example, through fine adjustment of the clock phase, two clocks with phase deviation after precise adjustment are respectively used as the clock and data and sent to the timing unit under test for identifying setup violation (setup time timing violation), so as to judge the setup time of the timing unit. However, the measurement accuracy itself is limited by the minimum step of the adjustable clock phase. Moreover, the clock has differences on different transmission paths, and under different voltages, the manifestations of such differences are different, resulting in a very large setup time error.

[0023] In another existing technical solution, it is proposed to use a buffer with a small delay as the minimum measurement scale, and at the same time construct buffers with different quantity differences for the clock and data paths of the timing unit, so as to judge how many minimum measurement scale buffers the setup time is equivalent to. The accuracy of this method is also limited by the delay of the buffer used as the minimum measurement scale. Similarly, there are differences in the measured clock and data paths, and under different voltages, the manifestations of such differences will increase significantly, resulting in a very large measurement result error.

[0024] In view of this, the present application proposes a measurement circuit and a measurement method for the setup time of a timing unit. First, the control module controls the first selection module and the second selection module to form a first test path, a second test path, and a third test path. Then, the critical period (denoted as the first period value) when the timing unit under test correctly receives the clock signal in the first test path, the critical period (denoted as the second period value) when the delay detection module correctly receives the clock signal in the second test path, and the critical period (denoted as the third period value) when the delay detection module correctly receives the clock signal in the third test path are respectively determined. Finally, the setup time of the timing unit is determined according to the first period value, the second period value, and the third period value. It can be seen that the determination of the setup time of the timing unit is only related to the first period value, the second period value, and the third period value, and is not limited by the clock phase adjustment range, the buffer delay, and the large difference in different test voltages resulting in a large measurement error, thereby improving the measurement accuracy.

[0025] In one implementation Figure 2 is a schematic structural diagram of a measurement circuit for the setup time of a timing unit provided by an embodiment of the present application. Refer to Figure 2 , the test circuit includes a clock signal generation module 110, a first selection module 120, a second selection module 130, a delay detection module 140, a data signal transmission module 150, a clock signal transmission module 160, a timing unit under test 170, and a control module 180;

[0026] Among them, the clock signal generation module 110 is electrically connected to the first selection module 120, the delay detection module 140, and the control module 180 respectively; the delay detection module 140 is electrically connected to the first selection module 120, the second selection module 130, and the control module 180 respectively; the first selection module 120 is electrically connected to the control module 180, the data signal transmission module 150, and the clock signal transmission module 160 respectively; the second selection module 130 is electrically connected to the control module 180, the data signal transmission module 150, and the clock signal transmission module 160 respectively; the data signal transmission module 150 is electrically connected to the timing unit under test 170 and the control module 180 respectively, the clock signal transmission module 160 is electrically connected to the timing unit under test 170 and the control module 180 respectively, and the timing unit under test 170 is electrically connected to the control module 180;

[0027] The control module 180 is used to control the first selection module 120 and the second selection module 130 to form a first test path, a second test path, and a third test path, so as to determine the setup time of the timing unit based on the first test path, the second test path, and the third test path. Among them, the first test path is composed of the clock signal generation module 110, the data signal transmission module 150, the clock signal transmission module 160, the timing unit under test 170, and the control module 180; the second test path is composed of the clock signal generation module 110, the delay detection module 140, the data signal transmission module 150, and the control module 180; the third test path is composed of the clock signal generation module 110, the delay detection module 140, the clock signal transmission module 160, and the control module 180.

[0028] In an embodiment, the first selection module 120 is used to control one of the clock signal generation module 110 and the delay detection module 140 to be connected to the data signal transmission module 150 and the clock signal transmission module 160 respectively. The second selection module 130 is used to control one of the data signal transmission module 150 and the clock signal transmission module 160 to be connected to the delay detection module 140. For example, when the control module 180 controls the first selection module 120 to control the signal generation module 110 to be connected to the data signal transmission module 150 and the clock signal transmission module 160 respectively, the test circuit enters the critical point test mode for the setup time of the timing unit under test, that is, a first test path composed of the clock signal generation module 110, the data signal transmission module 150, the clock signal transmission module 160, the timing unit under test 170, and the control module 180 is formed.

[0029] When the control module 180 controls the first selection module 120 to connect the delay detection module 140 to the data signal transmission module 150 and the clock signal transmission module 160 respectively, and controls the second selection module 130 to connect one of the data signal transmission module 150 and the clock signal transmission module 160 to the delay detection module 140, the test circuit enters the delay comparison mode of the clock signal transmission path and the data signal transmission path. Among them, the data signal transmission path is the second test path composed of the clock signal generation module 110, the delay detection module 140, the data signal transmission module 150 and the control module 180, and the clock signal transmission path is the third test path composed of the clock signal generation module 110, the delay detection module 140, the clock signal transmission module 160 and the control module 180.

[0030] In one embodiment, Figure 3 is a schematic structural diagram of another measurement circuit for the setup time of a timing unit provided in the embodiment of the present application. Refer to Figure 3 , the clock signal generation module 110 includes a clock frequency modulation unit 111 and a clock pulse control unit 112. The clock frequency modulation unit 111 is electrically connected to the clock pulse control unit 112. The clock pulse control unit 112 is electrically connected to the delay detection module 140 and the first input terminal A1 of the first selection module 120 respectively. The control module 180 is electrically connected to the clock frequency modulation unit 111 and the clock pulse control unit 112 respectively.

[0031] In an embodiment, the clock frequency modulation unit 111 can be a PLL (Phase Locked Loop), used as a clock source, with high clock frequency accuracy and stability, small jitter, and fine-tunable frequency. The clock pulse control unit 112 can be an OCC circuit (on-chip-clock, clock generation circuit), used to output clock pulse signals.

[0032] In one embodiment, refer to Figure 3 , the delay detection module 140 includes a first transmission register 141 and a reception register 142. Among them, the first input terminal of the first transmission register 141 is electrically connected to the clock signal generation module 110, an external data signal data1 is input to the second input terminal of the first transmission register 141, and the output terminal of the first transmission register 141 is electrically connected to the second input terminal A2 of the first selection module 120; the first input terminal of the reception register 142 is electrically connected to the clock signal generation module 110, the second input terminal of the reception register 142 is electrically connected to the output terminal of the second selection module 130, and the output terminal of the reception register 142 is electrically connected to the control module 180.

[0033] In an embodiment, the first transmission register 141 is used as the starting point for testing data signal transmission in the second test path and the third test path of the circuit, and the receiving register 142 is used as the ending point for testing data signal transmission in the second test path and the third test path of the circuit. For example, in the second test path, the control module 180 controls the second input terminal A2 of the first selection module 120 to be turned on, that is, the output terminals of the first transmission register 141 of the delay detection module are respectively connected to the data signal transmission module 150 and the clock signal transmission module 160. At the same time, the control module 180 also controls the second input terminal B2 of the second selection module 130 to be connected to the receiving register 142 of the delay detection module 140, thus forming a second test path composed of the clock signal generation module 110, the first transmission register 141, the data signal transmission module 150, the receiving register 142, and the control module 180. When testing in the second test path, the clock signal output by the clock signal generation module 110 is input to the first input terminal of the first transmission register 141, and the external data signal data1 is input to the second input terminal of the first transmission register 141. The external data signal data1 is output by the first transmission register 141, passes through the data signal transmission module 150, and finally is delivered to the receiving register 142. In the third test path, the control module 180 controls the second input terminal A2 of the first selection module 120 to be turned on, that is, the output terminals of the first transmission register 141 of the delay detection module are respectively connected to the data signal transmission module 150 and the clock signal transmission module 160. At the same time, the control module 180 also controls the first input terminal B1 of the second selection module 130 to be connected to the receiving register 142 of the delay detection module 140, thus forming a third test path composed of the clock signal generation module 110, the first transmission register 141, the clock signal transmission module 160, the receiving register 142, and the control module 180. When testing in the third test path, the clock signal output by the clock signal generation module 110 is input to the first input terminal of the first transmission register 141, and the external data signal data1 is input to the second input terminal of the first transmission register 141. The external data signal data1 is output by the first transmission register 141, passes through the clock signal transmission module 160, and finally is delivered to the receiving register 142.

[0034] In one embodiment, referring to Figure 3 , the data signal transmission module 150 includes a second transmission register 151. The first input terminal of the second transmission register 151 is electrically connected to the output terminal of the first selection module. The second input terminal of the second transmission register 151 inputs the external data signal data1. The output terminal of the second transmission register 151 is respectively electrically connected to the second input terminal of the second selection module 130 and the second input terminal of the timing unit under test 170.

[0035] In an embodiment, an external data signal data1 is input to the second input terminal of the second transmission register 151 to provide a data signal for the first test path test. For example, in the first test path, the control module 180 controls the first input terminal A1 of the first selection module 120 to be turned on, that is, the output terminals of the signal generation module 110 are respectively connected to the data signal transmission module 150 and the clock signal transmission module 160, forming a first test path composed of the clock signal generation module 110, the data signal transmission module 150, the clock signal transmission module 160, the timing unit 170 under test, and the control module 180. When testing in the first test path, a clock signal output by the clock signal generation module 110 is input to the first input terminal of the second transmission register 151, and an external data signal data1 is input to the second input terminal of the second transmission register 151. The external data signal data1 is output by the second transmission register 151 and then delivered to the timing unit 170 under test.

[0036] In an embodiment, refer to Figure 3 , the reset terminals of the second transmission register 151, the first transmission register 141, the reception register 142, and the timing unit 170 under test are all electrically connected to the control module 180. The reset and clear functions of the second transmission register 151, the first transmission register 141, the reception register 142, and the timing unit 170 under test can be controlled through the control module 180.

[0037] In one embodiment, refer to Figure 3 , the data signal transmission module 150 further includes a first buffer module b1. The input terminal of the first buffer module b1 is electrically connected to the output terminal of the second transmission register 151. The output terminal of the first buffer module b1 is respectively electrically connected to the second input terminal of the second selection module 130 and the second input terminal of the timing unit 170 under test; the clock signal transmission module 160 includes a second buffer module b2. The input terminal of the second buffer module b2 is electrically connected to the output terminal of the first selection module 120. The output terminal of the second buffer module b2 is respectively electrically connected to the first input terminal B1 of the second selection module 130 and the first input terminal of the timing unit 170 under test.

[0038] In an embodiment, the second transmission register 151 and the first buffer module b1 form a data signal transmission path, and the first buffer module b1 is used to adjust the delay time of the data transmission module 150. The second buffer module b2 forms a clock signal transmission path, and the second buffer module b2 is used to adjust the delay time of the clock signal transmission module 160. It should be noted that the number of the first buffer modules b1 in the data signal transmission path may include multiple, and the number of the second buffer modules b2 in the clock signal transmission path may also include multiple. The specific number can be set according to actual test requirements, and the specific number is not specifically limited here.

[0039] In one embodiment, when the control module 180 controls the first input terminal A1 of the first selection module 120 to be closed and the second input terminal A2 to be open, and the first input terminal B1 and the second input terminal B2 of the second selection module 130 to be both open, a first test path is formed; when the control module 180 controls the first input terminal A1 of the first selection module 120 to be open and the second input terminal A2 to be closed, and the first input terminal B1 of the second selection module 130 to be open and the second input terminal B2 to be closed, a second test path is formed; when the control module 180 controls the first input terminal A1 of the first selection module 120 to be open and the second input terminal A2 to be closed, and the first input terminal B1 of the second selection module 130 to be closed and the second input terminal B2 to be open, a third test path is formed.

[0040] In an embodiment, when the control module 180 controls the first input terminal A1 of the first selection module 120 to be closed and the second input terminal A2 to be open, and the first input terminal B1 and the second input terminal B2 of the second selection module 130 to be both open, that is, to disconnect the delay detection module from the data signal transmission module 150 and the clock signal transmission module 160, and connect the output terminals of the signal generation module 110 to the data signal transmission module 150 and the clock signal transmission module 160 respectively, a first test path composed of the clock signal generation module 110, the data signal transmission module 150 (including the data signal transmission path composed of the second transmission register 151 and the first buffer module b1), the clock signal transmission module 160 (including the clock signal transmission path formed by the second buffer module b2), the timing unit 170 to be measured, and the control module 180 is formed. In the first test path, the data signal transmission path has a fixed delay, and the delay value is denoted as T_data, and the clock signal transmission path also has a fixed delay, and the delay value is denoted as T_clk. When testing under the first test path, the first input terminal of the second transmission register 151 inputs the clock signal output by the clock signal generation module 110, and the second input terminal of the second transmission register 151 inputs the external data signal data1. The frequency of the clock signal can be adjusted by the clock signal generation module 110. Generally, when the frequency of the clock signal is relatively slow, the external data signal data1 can be captured by the timing unit 170 to be measured after being output by the second transmission register 151. However, when the frequency of the clock signal reaches a certain threshold, a setup violation will occur, and the timing unit 170 to be measured will not be able to capture the data signal sent by the second transmission register 151. At this time, the critical period of the clock signal when the setup violation occurs is denoted as Period_su, and this critical period satisfies the following conditions:

[0041] T data -T clk = Period_su - Tsu

[0042] Among them, Tsu is the setup time of the timing unit to be measured.

[0043] When the control module 180 controls the first input terminal A1 of the first selection module 120 to be disconnected and the second input terminal A2 to be closed, and the first input terminal B1 of the second selection module 130 to be disconnected and the second input terminal B2 to be closed, that is, the first transmission register 141 is connected to the data signal transmission module 150 (including the data signal transmission path composed of the second transmission register 151 and the first buffer module b1), and the data signal transmission module 150 is connected to the receiving register 142, forming a second test path composed of the clock signal generation module 110, the first transmission register 141, the second transmission register 151, the first buffer module b1, the receiving register 142, and the control module 180. When testing under the second test path, the clock signal output by the clock signal generation module 110 is input to the first input terminal of the first transmission register 141, and the external data signal data1 is input to the second input terminal of the first transmission register 141. The frequency of the clock signal can be adjusted through the clock signal generation module 110. Generally, when the frequency of the clock signal is relatively slow, the external data signal data1 can be captured by the receiving register 142 after being output by the first transmission register 141 through the second transmission register 151 and the first buffer module b1. When the frequency of the clock signal is relatively fast, the transmission rate of the data signal can be increased. However, when the frequency of the clock signal is too fast, the receiving register 142 will not be able to receive the data signal sent by the first transmission register 141 normally. Then when the frequency of the clock signal reaches a certain threshold, the period of the clock signal when the receiving register 142 can just receive the data signal is the critical period, and this critical period is denoted as Period_data.

[0044] When the control module 180 controls the first input terminal A1 of the first selection module 120 to be disconnected and the second input terminal A2 to be closed, and the first input terminal B1 of the second selection module 130 to be closed and the second input terminal B2 to be disconnected, that is, the first transmission register 141 is connected to the clock signal transmission module 160 (including the data signal transmission path formed by the second buffer module b2), and the clock signal transmission module 160 is connected to the reception register 142, a third test path composed of the clock signal generation module 110, the first transmission register 141, the second buffer module b2, the reception register 142, and the control module 180 is formed. When testing under the third test path, the clock signal output by the clock signal generation module 110 is input to the first input terminal of the first transmission register 141, and the external data signal data1 is input to the second input terminal of the first transmission register 141. The frequency of the clock signal can be adjusted through the clock signal generation module 110. Generally, when the frequency of the clock signal is relatively slow, the external data signal data1 can be captured by the reception register 142 after being output by the first transmission register 141 through the second buffer module b2. When the frequency of the clock signal is relatively fast, the transmission rate of the data signal can be increased. However, when the frequency of the clock signal is too fast, the reception register 142 will not be able to receive the data signal sent by the first transmission register 141 normally. Then, when the frequency of the clock signal reaches a certain threshold, the period of the clock signal when the reception register 142 can just receive the data signal is the critical period, and this critical period is denoted as Period_clk. Then, the critical period Period_data under the second test path and Period_clk under the third test path satisfy the following condition:

[0045] T data -T clk = Period_data - Period_clk

[0046] Combining with the condition satisfied by the critical period Period_su of the clock signal when a setup violation occurs under the first test path, it can be obtained that:

[0047] T su = Period_su - (Period_data - Period - clk)

[0048] It can be seen from this that the setup time T of the timing unit suThe critical period of the clock signal when a violation occurs only with the timing unit under test in the first test path is denoted as Period_su, the critical period Period_data of the clock signal when the delay detection module in the second test path can just normally receive the data signal, and the critical period Period_clk of the clock signal when the delay detection module in the third test path can just normally receive the data signal. It is related to these and has nothing to do with the differences between the data signal transmission path and the clock signal transmission path, the delay of the buffer, and the test voltage. It can avoid the problem of large measurement result errors caused by problems such as the differences between the data signal transmission path and the clock signal transmission path, the large differences in the delay of the buffer, and different test voltages in the prior art, thereby improving the measurement accuracy of the setup time of the timing unit under test.

[0049] In one implementation, Figure 4 is a flowchart of a method for measuring the setup time of a timing unit provided by an embodiment of the present application. The method for measuring the setup time of the timing unit of the present application is applicable to the measurement circuit for the setup time of the timing unit described in any embodiment of the present application. The measurement circuit includes a clock signal generation module, a first selection module, a second selection module, a delay detection module, a data signal transmission module, a clock signal transmission module, a timing unit under test, and a control module. The control module controls the first selection module and the second selection module to form a first test path, a second test path, and a third test path. The first test path consists of the clock signal generation module, the data signal transmission module, the clock signal transmission module, the timing unit under test, and the control module. The second test path consists of the clock signal generation module, the delay detection module, the data signal transmission module, and the control module. The third test path consists of the clock signal generation module, the delay detection module, the clock signal transmission module, and the control module;

[0050] Refer to Figure 4 , the measurement method includes the following steps:

[0051] S210. Determine the first period value, the second period value, and the third period value of the clock signal respectively. Among them, the first period value is the critical period when the timing unit under test correctly receives the clock signal in the first test path, the second period value is the critical period when the delay detection module correctly receives the clock signal in the second test path, and the third period value is the critical period when the delay detection module correctly receives the clock signal in the third test path;

[0052] S220. Determine the setup time of the timing unit according to the first period value, the second period value, and the third period value.

[0053] In one embodiment, the setup time of the timing unit = the first period value - (the second period value - the third period value).

[0054] In an embodiment, the control module 180 can control the period or frequency of the clock signal output by the clock signal generation module 110 to adjust the clock signal frequency under the first test path, the second test path, and the third test path.

[0055] In an embodiment, refer to Figure 4 , and the following are measured respectively: Under the first test path, when a violation occurs in the timing unit under test, when the timing unit under test can just capture the data signal sent by the second sending register 151 of the data signal transmission module 150, the period value of the clock signal, that is, the first period value Period_su; Under the second test path, when the receiving register 142 can just capture the data signal output by the data signal transmission module 150 sent by the first sending register 141 of the delay detection module 140, the period value of the clock signal, that is, the second period value Period_data; Under the third test path, when the receiving register 142 can just capture the data signal output by the clock signal transmission module 160 sent by the first sending register 141 of the delay detection module 140, the period value of the clock signal, that is, the third period value Period_clk. Among them, the first period value, the second period value, the third period value, and the setup time of the timing unit under test satisfy the following relationship:

[0056] T su = Period_su - (Period_data - Period_clk)

[0057] Therefore, the setup time T of the timing unit under test can be determined su .

[0058] In an implementation manner, Figure 5 is a flowchart of a method for determining the period value of a clock signal provided by an embodiment of the present application. According to Figure 5 the method described above, the period value of the clock signal can be determined, where the period value is any one of the first period value, the second period value, and the third period value. The method for determining the period value of the clock signal includes the following steps:

[0059] S310. Determine N critical period test values;

[0060] S320. Determine the period value of the clock signal according to the N critical period test values.

[0061] In an embodiment, the process of determining the first cycle value includes: when testing the timing unit under test for violations in the first test path, when the timing unit under test can just capture the data signal sent by the second transmission register 151 of the data signal transmission module 150, the cycle value of the clock signal is obtained to get a critical cycle test value Period_su_trigger_1. Repeat the above test N - 1 times to obtain a total of N critical cycle test values of the first cycle value. Take the average of the N critical cycle test values of the first cycle value to obtain the first cycle value. The expression is as follows:

[0062]

[0063] Among them, Period_su_trigger_i is the critical cycle test value of the first cycle value measured in the i-th test experiment, and Period_su_avg is the average of the critical cycle test values of the first cycle value in N test experiments.

[0064] In an embodiment, the process of determining the second cycle value includes: when testing the receiving register 142 in the second test path and it can just capture the data signal output by the data signal transmission module 150 and sent by the first transmission register 141 of the delay detection module 140, the cycle value of the clock signal is obtained to get a critical cycle test value Period_data_trigger_1. Repeat the above test N - 1 times to obtain a total of N critical cycle test values of the second cycle value. Take the average of the N critical cycle test values of the second cycle value to obtain the second cycle value. The expression is as follows:

[0065]

[0066] Among them, Period_data_trigger_i is the critical cycle test value of the second cycle value measured in the i-th test experiment, and Period_data_avg is the average of the critical cycle test values of the second cycle value in N test experiments.

[0067] In an embodiment, the process of determining the third cycle value includes: when testing the receiving register 142 in the third test path and it can just capture the data signal output by the clock signal transmission module 160 and sent by the first transmission register 141 of the delay detection module 140, the cycle value of the clock signal is obtained to get a critical cycle test value Period_clk_trigger_1. Repeat the above test N - 1 times to obtain a total of N critical cycle test values of the third cycle value. Take the average of the N critical cycle test values of the third cycle value to obtain the third cycle value. The expression is as follows:

[0068]

[0069] Among them, Period_clk_trigger_i is the critical period test value of the third period value measured in the i-th test experiment, and Period_clk_avg is the average value of the critical period test values of the third period values in N test experiments.

[0070] In one implementation, Figure 6 is a flowchart of a method for determining N critical period test values provided by an embodiment of the present application. Refer to Figure 6 , the method for determining N critical period test values includes the following steps:

[0071] S410, S1: Determine the critical period estimation range of the clock signal;

[0072] S420, S2: Determine the first step size;

[0073] S430, S3: Starting from the right interval value of the critical period estimation range, sequentially test towards the left interval value of the critical period estimation range according to the first step size until the timing unit to be tested or the delay detection module correctly receives the clock signal, and record the period of the clock signal at the current moment as the first critical period test value;

[0074] S440: Repeat steps S1 to S3 for N - 1 times, then the second critical period test value, the third critical period test value,..., the Nth critical period test value are obtained respectively.

[0075] In an embodiment, taking the determination of N critical period test values of a first period value as an example, the process of determining N critical period test values of the first period value includes: Under a first test path, a clock signal generating module emits a clock signal at a certain clock frequency, adjusts the frequency of the clock signal, tests the violation conditions of a to-be-tested timing unit at different clock frequencies, records the frequency or period of the clock signal when the to-be-tested timing unit has a violation, and finds the approximate range of the critical period of the clock signal when the to-be-tested timing unit has a violation, that is, the critical period estimation range F, denoted as <Period_gross-step_p, Period_gross+step_p>. Then, a first step size step1 is determined, and the control module 180 is used to change the period of the clock signal output by the clock signal generating module 110, and the violation conditions of the to-be-tested timing unit at each different clock period are tested. Among them, the change in the period of the clock signal can be: starting from the right interval value Period_gross+step_p of the critical period estimation range F, successively testing towards the left interval value Period_gross-step_p of the critical period estimation range F according to the first step size step1 until the to-be-tested timing unit correctly receives the clock signal, and recording the period of the clock signal at the current moment as the first critical period test value. Then, the above process is repeated N-1 times, and the second critical period test value, the third critical period test value,..., the Nth critical period test value are obtained respectively. Similarly, N critical period test values of a second period value and N critical period test values of a third period value can be determined according to the above method.

[0076] In one implementation, Figure 7 is a flowchart of a method for determining the critical period estimation range of a clock signal provided by an embodiment of the present application. Refer to Figure 7 , the method for determining the critical period estimation range of a clock signal includes the following steps:

[0077] S510. Obtain the expected value of the critical period of the clock signal;

[0078] S520. Determine the period step size, where the period step size includes multiple preset time windows;

[0079] S530. Perform tests in ascending order according to the period step size until, for the first time, the test value of the critical period of the clock signal is inconsistent with the expected value of the critical period. Take the difference between the test value when the test value of the critical period of the clock signal is inconsistent with the expected value of the critical period for the first time and the period step size as the left interval value of the critical period estimation range, and take the sum of the test value when the test value of the critical period of the clock signal is inconsistent with the expected value of the critical period for the first time and the period step size as the right interval value of the critical period estimation range.

[0080] In an embodiment, by way of example, taking the determination process of the critical period estimation range of the clock signal with the first period value as an example, the process of determining the critical period estimation range of the clock signal is as follows: First, obtain the expected value of the critical period of the clock signal through theoretical calculation. For example, it can be obtained by simulation using a spice tool. Then determine a period step size step2, where the period step size step2 is variable and includes a plurality of preset time windows with different periods. For example, the period step size step2 includes a plurality of time durations of different sizes such as T1, T2, T3... Tn. Finally, the control module 180 changes the period of the clock signal output by the clock signal generation module 110, and tests the critical period of the clock signal when a violation occurs in the timing unit under test corresponding to the clock signal period in the first test path. Among them, the change of the period of the clock signal can be: change the period of the clock signal in ascending order of each preset time window of the period step size step2 and perform tests respectively until the test value of the critical period of the clock signal is inconsistent with the expected value of the critical period for the first time. Take the difference between the test value when the test value of the critical period of the clock signal is inconsistent with the expected value of the critical period for the first time and the period step size as the left interval value of the critical period estimation range, and take the sum of the test value when the test value of the critical period of the clock signal is inconsistent with the expected value of the critical period for the first time and the period step size as the right interval value of the critical period estimation range. Similarly, the critical period estimation range of the clock signal with the second period value and the critical period estimation range of the clock signal with the third period value can be determined according to the above method.

[0081] In one embodiment, the first step size is determined according to the duration of the clock signal jitter.

[0082] Generally, the clock signal generated by the clock source generally has a jitter phenomenon. Due to the different qualities of the clock sources, there will be a large difference in the magnitude of the jitter, and the jitter will affect the determination of the first period value, the second period value, and the third period value of the clock signal. In order to eliminate or minimize the influence of the clock jitter on the measurement result accuracy, the first step size is determined according to the duration of the clock signal jitter. Let the first step size be step1, and let the duration of the clock signal jitter be T_jitter. Then the first step size can be determined according to the following formula:

[0083] step1 = T_jitter / M

[0084] where M is an integer. The larger the value of M, the smaller the step size, the higher the fine-tuning accuracy, and the better the effect of reducing the influence of jitter.

[0085] As described above, these are only exemplary embodiments of the present application and are not intended to limit the protection scope of the present application. Generally speaking, various embodiments of the present application can be implemented in hardware or dedicated circuits, software, logic, or any combination thereof. For example, some aspects can be implemented in hardware, while other aspects can be implemented in firmware or software that can be executed by a controller, microprocessor, or other computing device, although the present application is not limited thereto.

[0086] Through exemplary and non-limiting examples, a detailed description of the exemplary embodiments of the present application has been provided above. However, considering the accompanying drawings and the claims, various modifications and adjustments to the above embodiments will be obvious to those skilled in the art without departing from the scope of the present invention. Therefore, the proper scope of the present invention will be determined according to the claims.

Claims

1. A method for measuring the setup time of a timing unit, characterized in that, the measurement method is applicable to a measurement circuit for the setup time of a timing unit. The measurement circuit includes a clock signal generation module, a first selection module, a second selection module, a delay detection module, a data signal transmission module, a clock signal transmission module, a timing unit under test, and a control module. The control module controls the first selection module and the second selection module to form a first test path, a second test path, and a third test path. The first test path is composed of the clock signal generation module, the data signal transmission module, the clock signal transmission module, the timing unit under test, and the control module. The second test path is composed of the clock signal generation module, the delay detection module, the data signal transmission module, and the control module. The third test path is composed of the clock signal generation module, the delay detection module, the clock signal transmission module, and the control module; the method includes: respectively determining a first period value, a second period value, and a third period value of a clock signal, wherein the first period value is the critical period for the timing unit under test to correctly receive the clock signal under the first test path, the second period value is the critical period for the delay detection module to correctly receive the clock signal under the second test path, and the third period value is the critical period for the delay detection module to correctly receive the clock signal under the third test path; determining the setup time of the timing unit according to the first period value, the second period value, and the third period value.

2. The method for measuring the setup time of a timing unit according to claim 1, characterized in that, the setup time of the timing unit is equal to the sum of the first period value and the third period minus the second period value.

3. The method for measuring the setup time of a timing unit according to claim 1, characterized in that, the determination of the period value of the clock signal, where the period value is any one of the first period value, the second period value, and the third period value, includes: determining N critical period test values; determining the period value of the clock signal according to the N critical period test values.

4. The method for measuring the setup time of a timing unit according to claim 3, characterized in that, the determination of the N critical period test values includes: S1: determining the estimated range of the critical period of the clock signal; S2: determining the first step size; S3: starting from the right interval value of the estimated range of the critical period, sequentially testing according to the first step size towards the left interval value of the estimated range of the critical period until the timing unit under test or the delay detection module correctly receives the clock signal, and recording the period of the clock signal at the current moment as the first critical period test value; repeating steps S1 to S3 for N - 1 times to obtain the second critical period test value, the third critical period test value,..., the Nth critical period test value respectively.

5. The method for measuring the setup time of a timing unit according to claim 4, characterized in that, Determining the critical period estimation range of the clock signal includes: Obtaining the expected value of the critical period of the clock signal; Determining the period step size, where the period step size includes multiple preset time windows; Performing tests in ascending order according to the period step size until, for the first time, the test value of the critical period of the clock signal is inconsistent with the expected value of the critical period. At this time, the difference between the test value when the test value of the critical period of the clock signal is inconsistent with the expected value of the critical period for the first time and the period step size is used as the left interval value of the critical period estimation range, and the sum of the test value when the test value of the critical period of the clock signal is inconsistent with the expected value of the critical period for the first time and the period step size is used as the right interval value of the critical period estimation range.

6. The method for measuring the setup time of a timing unit according to claim 4, wherein, the first step size is determined according to the duration of the jitter of the clock signal.

7. A circuit for measuring the setup time of a timing unit, wherein, it includes a clock signal generation module, a first selection module, a second selection module, a delay detection module, a data signal transmission module, a clock signal transmission module, a timing unit under test, and a control module; wherein, the clock signal generation module is electrically connected to the first selection module, the delay detection module, and the control module respectively; the delay detection module is electrically connected to the first selection module, the second selection module, and the control module respectively; the first selection module is electrically connected to the control module, the data signal transmission module, and the clock signal transmission module respectively; the second selection module is electrically connected to the control module, the data signal transmission module, and the clock signal transmission module respectively; the data signal transmission module is electrically connected to the timing unit under test and the control module respectively, the clock signal transmission module is electrically connected to the timing unit under test and the control module respectively, and the timing unit under test is electrically connected to the control module; the control module is used to control the first selection module and the second selection module to form a first test path, a second test path, and a third test path, so as to determine the setup time of the timing unit based on the first test path, the second test path, and the third test path. Among them, the first test path is composed of the clock signal generation module, the data signal transmission module, the clock signal transmission module, the timing unit under test, and the control module, the second test path is composed of the clock signal generation module, the delay detection module, the data signal transmission module, and the control module, and the third test path is composed of the clock signal generation module, the delay detection module, the clock signal transmission module, and the control module.

8. The circuit for measuring the setup time of a timing unit according to claim 7, wherein, The clock signal generation module includes a clock frequency modulation unit and a clock pulse control unit. The clock frequency modulation unit is electrically connected to the clock pulse control unit. The clock pulse control unit is respectively electrically connected to the delay detection module and the first input end of the first selection module. The control module is respectively electrically connected to the clock frequency modulation unit and the clock pulse control unit.

9. The measurement circuit for establishing the time of the timing unit according to claim 7, wherein, the delay detection module includes a first transmission register and a reception register. Among them, the first input end of the first transmission register is electrically connected to the clock signal generation module. The second input end of the first transmission register inputs an external data signal. The output end of the first transmission register is electrically connected to the second input end of the first selection module; the first input end of the reception register is electrically connected to the clock signal generation module. The second input end of the reception register is electrically connected to the output end of the second selection module. The output end of the reception register is electrically connected to the control module.

10. The measurement circuit for establishing the time of the timing unit according to claim 9, wherein, the data signal transmission module includes a second transmission register. The first input end of the second transmission register is electrically connected to the output end of the first selection module. The second input end of the second transmission register inputs an external data signal. The output end of the second transmission register is respectively electrically connected to the second input end of the second selection module and the second input end of the timing unit to be measured.

11. The measurement circuit for establishing the time of the timing unit according to claim 10, wherein, the data signal transmission module further includes a first buffer module. The input end of the first buffer module is electrically connected to the output end of the second transmission register. The output end of the first buffer module is respectively electrically connected to the second input end of the second selection module and the second input end of the timing unit to be measured; the clock signal transmission module includes a second buffer module. The input end of the second buffer module is electrically connected to the output end of the first selection module. The output end of the second buffer module is respectively electrically connected to the first input end of the second selection module and the first input end of the timing unit to be measured.

12. The measurement circuit for establishing the time of the timing unit according to claim 11, wherein, when the control module controls the first input end of the first selection module to be closed and the second input end to be disconnected, and the first input end and the second input end of the second selection module are both disconnected, the first test path is formed; when the control module controls the first input end of the first selection module to be disconnected and the second input end to be closed, and the first input end and the second input end of the second selection module are both closed, the second test path is formed; when the control module controls the first input end of the first selection module to be disconnected and the second input end to be closed, and the first input end of the second selection module to be closed and the second input end to be disconnected, the third test path is formed.

Images