Semiconductor device and semiconductor memory device

Abstract

The present application discloses a semiconductor device and a semiconductor memory device. A semiconductor device may include a sudden power detection circuit and an operation circuit. The sudden power detection circuit may generate a power-off control signal in a sudden power-off state. The operation circuit may discharge a specific node based on the power-off control signal.

Description

Technical Field

[0001] Example embodiments relate to a semiconductor device and a semiconductor memory device, and in particular, to a semiconductor device and a semiconductor memory device that operate using an internal power supply voltage generated based on an external power supply voltage. Background Art

[0002] Generally, semiconductor devices use internal power supply voltages generated based on external power supply voltages to perform circuit operations. Likewise, volatile memory devices and nonvolatile memory devices (ie, semiconductor memory devices) also use internal power supply voltages generated based on external power supply voltages to perform circuit operations.

[0003] The advantage of a volatile memory device is that the data processing speed is high (which is the speed at which external data is stored therein or internal data is output to an external device). In addition, a volatile memory device has a disadvantage that an external power supply voltage continues to be supplied thereto while processing data. In contrast, a nonvolatile memory device has a disadvantage that its data processing speed is low. In addition, a nonvolatile memory device has an advantage that it retains data already stored therein even if an external power supply voltage is not supplied.

[0004] In this case, the nonvolatile memory device performs a programming operation to store data in the memory cell, and performs a read operation to output the data stored in the memory cell. In addition, the nonvolatile memory device performs an erase operation before the programming operation to erase the data stored in the memory cell. As described above, the nonvolatile memory device retains the data already stored therein even if the external power supply voltage is not supplied. However, if the external power supply is not smoothly supplied during the programming operation, the read operation, or the erase operation, the data stored in the memory cell may be damaged.

[0005] More specifically, in a nonvolatile memory device, a high voltage may be applied to a word line, a bit line, or a source line during a programming operation, a read operation, or an erase operation. Therefore, if an external power supply voltage is not smoothly supplied during a programming operation, a read operation, or an erase operation, the voltage level of the high voltage applied to the corresponding line may be involuntarily reduced. In this case, the distribution of data stored in the memory cells connected to the corresponding line is affected by the involuntarily reduced voltage level. The change in the data distribution of the memory cells means that the reliability of the data stored in the memory cells cannot be guaranteed.

[0006] Hereinafter, for convenience of description, a state in which the external power voltage is not smoothly supplied (ie, a state in which the voltage level of the external power voltage is reduced to a preset voltage level or lower) is referred to as a “sudden power-off state”. Summary of the invention

[0007] In an embodiment, a semiconductor device may include: a sudden power detection circuit configured to generate a power-off control signal having a voltage level corresponding to a voltage level of an external power supply voltage in a sudden power-off state; and an operating circuit configured to discharge a specific node during an enable period of the power-off control signal.

[0008] In an embodiment, a semiconductor device may include: a voltage detection circuit configured to enable a power-off control signal by detecting a voltage level of an external power supply voltage; an internal voltage generating circuit configured to receive the external power supply voltage, generate an internal power supply voltage by comparing the external power supply voltage with a preset reference voltage, and drive the internal power supply voltage as the external power supply voltage during an enabling period of the power-off control signal; and a control signal generating circuit configured to generate a control signal having a voltage level corresponding to the voltage level of the internal power supply voltage and configured to control circuit operation of the voltage detection circuit.

[0009] In an embodiment, a semiconductor memory device may include: a sudden power detection circuit configured to generate a power-off control signal having a voltage level corresponding to a voltage level of an external power supply voltage in a sudden power-off state; a memory cell array configured to store data, and the memory cell array includes memory cells connected between a bit line and a source line and having a gate connected to a word line; and a discharge drive circuit configured to discharge at least one of the bit line, the source line, and the word line during an enable period of the power-off control signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 is a block diagram showing a configuration of a semiconductor device according to an embodiment.

[0011] Figure 2 is a block diagram showing a configuration of a semiconductor device according to an embodiment.

[0012] Figure 3 It is shown Figure 2 FIG. 1 is a diagram of the configuration of the voltage detection circuit.

[0013] Figure 4 It is shown Figure 2 FIG. 1 is a diagram of the configuration of an internal voltage generating circuit.

[0014] Figure 5 is a block diagram showing a configuration of a semiconductor memory device according to an embodiment.

[0015] Figure 6 It shows that according to Figure 5A block diagram of a semiconductor memory device according to another embodiment of the semiconductor memory device. DETAILED DESCRIPTION

[0016] The description of the present disclosure is only an implementation method of the structure and / or function description. The scope of rights of the present disclosure should not be interpreted as being limited to the implementation methods described in the specification. That is, the scope of rights of the present disclosure should be understood to include equivalents that can realize the technical spirit, because the implementation methods can be modified in various ways and can have various forms. In addition, the purpose or effect proposed in the present disclosure does not mean that a specific implementation method should include all purposes or effects or only include these effects. Therefore, the scope of rights of the present disclosure should not be understood to be limited by it.

[0017] The meanings of the terms described in the present application should be understood as follows.

[0018] Terms such as "first" and "second" are used to distinguish one element from another element, and the scope of rights of the present disclosure should not be limited by these terms. For example, a first element may be named a second element. Likewise, a second element may be named a first element.

[0019] Unless the context clearly indicates otherwise, singular expressions should be understood to include plural expressions. Terms such as "including" or "having" should be understood to indicate the presence of set characteristics, quantities, steps, operations, elements, parts or combinations thereof, but not to exclude the possibility of the presence or addition of one or more other characteristics, quantities, steps, operations, elements, parts or combinations thereof.

[0020] In each step, symbols (e.g., a, b, and c) are used for convenience of description, and these symbols do not describe the order of the steps. Unless the context clearly describes a specific order, the steps may be performed in an order different from the order described in the context. That is, the steps may be performed according to the described order, may be performed substantially simultaneously with the described order, or may be performed in the reverse order of the described order.

[0021] Unless otherwise defined, all terms (including technical or scientific terms) used herein have the same meaning as those generally understood by those skilled in the art. Unless clearly defined in this application, terms defined in commonly used dictionaries should be interpreted as having the same meaning as in the context of the relevant technology, and should not be interpreted as having an ideal or overly formal meaning.

[0022] Before describing, the semiconductor device and the semiconductor memory device according to the embodiment can discharge a specific node in a sudden power-off state. In addition, the semiconductor memory device according to the embodiment can discharge at least one of a word line, a source line, and a bit line in a sudden power-off state.

[0023] Various embodiments are directed to providing a semiconductor device capable of stably generating a power-off control signal (ie, a detection signal) in a sudden power-off state.

[0024] In addition, various embodiments are directed to providing a semiconductor device capable of ensuring a smooth discharge operation of a circuit attempting to perform a circuit operation in a sudden power-off state.

[0025] In addition, various embodiments are directed to providing a semiconductor memory device capable of ensuring a stable discharge operation for each line configuring a memory cell array in a sudden power-off state.

[0026] The objects of the present disclosure are not limited to the above objects, and other objects not described above may be clearly understood by those skilled in the art to which the present disclosure belongs from the following description.

[0027] Figure 1 is a block diagram showing a configuration of a semiconductor device according to an embodiment.

[0028] Reference Figure 1 , the semiconductor device may include a sudden power detection circuit 10 and an operation circuit 20 .

[0029] First, in the sudden power-off state, the sudden power detection circuit 10 may be an element that generates a power-off control signal DTVCC having a voltage level corresponding to the voltage level of the external power supply voltage VCCE. In this case, the power-off control signal DTVCC may be a signal enabled at a logic level "high" in the sudden power-off state. In addition, during the enabling period, the power-off control signal DTVCC may have a voltage level corresponding to the voltage level of the external power supply voltage VCCE.

[0030] For reference, as described above, the sudden power-off state may mean a state in which the external power voltage is not smoothly supplied, that is, a state in which the voltage level of the external power voltage is reduced to a preset voltage level or lower.

[0031] The operation circuit 20 may be an element that discharges a specific node during an enable period of the power-down control signal DTVCC. The operation circuit 20 may correspond to a circuit that belongs to various circuits included in a semiconductor device and performs a discharge operation on a specific node based on the power-down control signal DTVCC.

[0032] The semiconductor device can generate a power-off control signal DTVCC based on the external power supply voltage VCCE in a sudden power-off state. Therefore, the power-off control signal DTVCC can have a voltage level corresponding to the voltage level of the external power supply voltage VCCE regardless of the internal power supply voltage. As a result, in a sudden power-off state, the operation circuit 20 supplied with the power-off control signal DTVCC can ensure smooth operation.

[0033] Figure 2 is a block diagram showing a configuration of a semiconductor device according to an embodiment.

[0034] Reference Figure 2 , the semiconductor device may include a voltage detection circuit 100, an internal voltage generation circuit 200, and a control signal generation circuit 300. In addition, the semiconductor device may include a reference voltage generation circuit 400 and an operation circuit 500.

[0035] First, the voltage detection circuit 100 may be an element that enables the power-off control signal DTVCC by detecting the voltage level of the external power supply voltage VCCE. The voltage detection circuit 100 may receive a first reference voltage VREF1 and may generate the power-off control signal DTVCC by comparing the first reference voltage VREF1 with the external power supply voltage VCCE. Therefore, when the external power supply voltage VCCE is lower than the first reference voltage VREF1, that is, in a sudden power-off state, the voltage detection circuit 100 may enable the power-off control signal DTVCC.

[0036] In this case, the control signal CTR input to the voltage detection circuit 100 may control whether to enable the detection operation of the voltage detection circuit 100. In addition, the control signal CTR may control the initialization operation of the voltage detection circuit 100 based on the circuit configuration of the voltage detection circuit 100. Figure 3 The detailed operation of the control signal CTR is described in more detail.

[0037] The internal voltage generating circuit 200 may be an element that receives the external power supply voltage VCCE and generates the internal power supply voltage VCCI in a normal operating state. In this case, the normal operating state means a circuit operating state in a section that is not in a sudden power-off state. In other words, the internal voltage generating circuit 200 may receive the second reference voltage VREF2 (i.e., a preset voltage) in a normal operating state, and may generate the internal power supply voltage VCCI by comparing the second reference voltage VREF2 with the external power supply voltage VCCE.

[0038] In addition, the internal voltage generating circuit 200 may be an element that drives the internal power supply voltage VCCI as the external power supply voltage VCCE during the enabling period of the power-down control signal DTVCC. In this case, the control signal CTR input to the internal voltage generating circuit 200 may control whether the voltage generating operation of the internal voltage generating circuit 200 is enabled. In addition, the control signal CTR may control the initialization operation of the internal voltage generating circuit 200 based on the circuit configuration of the internal voltage generating circuit 200. Figure 4 The detailed operation of the control signal CTR is described in more detail.

[0039] The control signal generating circuit 300 may be an element that controls the circuit operation of the voltage detecting circuit 100 by generating a control signal CTR whose voltage level corresponds to the voltage level of the internal power supply voltage VCCI. In this case, the control signal CTR may be a signal that controls an enabling operation or an initializing operation of the voltage detecting circuit 100. An example in which the control signal CTR controls the enabling operation of the voltage detecting circuit 100 and the internal voltage generating circuit 200 is described below.

[0040] The control signal CTR of the logic level "high" generated by the control signal generating circuit 300 may have a voltage level corresponding to the voltage level of the internal power supply voltage VCCI generated by the internal voltage generating circuit 200. The control signal CTR of the logic level "low" may have a voltage level corresponding to the voltage level of the ground power supply voltage VSS. In other words, as described above, in the sudden power-off state, the internal voltage generating circuit 200 may drive the internal power supply voltage VCCI as the external power supply voltage VCCE based on the power-off control signal DTVCC. In addition, the internal power supply voltage VCCI driven as the external power supply voltage VCCE may be applied to the control signal generating circuit 300. Therefore, the control signal CTR of the logic level "high" generated by the control signal generating circuit 300 may have the voltage level of the external power supply voltage VCCE.

[0041] The semiconductor device can use the power-off control signal DTVCC enabled in the sudden power-off state to drive the internal power supply voltage VCCI generated by the internal voltage generating circuit 200 as the external power supply voltage VCCE. In other words, in the sudden power-off state, the internal power supply voltage VCCI can be driven as the external power supply voltage VCCE. Therefore, the control signal CTR generated by the control signal generating circuit 300 can have a voltage level corresponding to the voltage level of the external power supply voltage VCCE. Therefore, the voltage detection circuit 100 enabled based on the control signal CTR can stably generate the desired power-off control signal DTVCC in the sudden power-off state.

[0042] The reference voltage generating circuit 400 may be an element that enables a voltage generating operation based on a control signal CTR and generates a first reference voltage VREF1 and a second reference voltage VERF2. The reference voltage generating circuit 400 may be implemented as a bandgap reference circuit. The first reference voltage VREF1 generated by the reference voltage generating circuit 400 may be provided to the voltage detection circuit 100. The second reference voltage VREF2 generated by the reference voltage generating circuit 400 may be provided to the internal voltage generating circuit 200. In this case, the control signal CTR may be a signal that controls an enabling operation or an initialization operation of the reference voltage generating circuit 400.

[0043] The operation circuit 500 may be an element that discharges a specific node during an enable period of the power-down control signal DTVCC. The operation circuit 500 may correspond to a circuit that belongs to various circuits included in a semiconductor device and performs a discharge operation on a specific node based on the power-down control signal DTVCC. Figure 5 The detailed configuration and operation of the circuit that performs the discharge operation are described in more detail.

[0044] Figure 3 It is shown Figure 2 FIG. 1 is a diagram of a configuration of a voltage detection circuit 100 .

[0045] Reference Figure 3 , the voltage detection circuit 100 may include a distribution circuit 110 , a comparison circuit 120 , and enabling circuits 130_1 and 130_2 .

[0046] First, the distribution circuit 110 may be an element that generates a distribution voltage VD by dividing the voltage level of the external power supply voltage VCCE. More specifically, the distribution circuit 110 may include a first resistor R1 and a second resistor R2 connected in series between a power level to which the external power supply voltage VCCE is applied and a ground level to which the ground power supply voltage VSS is applied. Therefore, the distribution voltage VD generated by the distribution circuit 110 may be output from a common node to which the first resistor R1 and the second resistor R2 are connected.

[0047] The comparison circuit 120 may be an element that generates a power-off control signal DTVCC by comparing the distribution voltage VD output by the distribution circuit 110 with the first reference voltage VREF1. More specifically, the comparison circuit 120 may receive the first reference voltage VREF1 through one input stage, may receive the distribution voltage VD through another input stage, and may generate the power-off control signal DTVCC by an operation of comparing the first reference voltage VREF1 with the distribution voltage VD. Therefore, the comparison circuit 120 may generate the power-off control signal DTVCC that is enabled when the voltage level of the distribution voltage VD is lower than the voltage level of the first reference voltage VREF1.

[0048] The enabling circuits 130_1 and 130_2 may be based on Figure 2The control signal generating circuit 300 of the embodiment of the present invention controls the elements of the enable operation of the comparison circuit 120 by the control signal CTR output by the control signal generating circuit 300. More specifically, the enable circuits 130_1 and 130_2 may include a first PMOS transistor PM1 whose source and drain are connected between the comparison circuit 120 and the power supply stage to which the external power supply voltage VCCE is applied, and the enable circuits 130_1 and 130_2 may respectively include a first NMOS transistor NM1 whose source and drain are connected between the comparison circuit 120 and the ground stage to which the ground power supply voltage VSS is applied. In this case, the first PMOS transistor PM1 may receive a negative control signal / CTR having a logic level opposite to that of the control signal CTR through its gate, and may perform an on / off operation. In addition, the first NMOS transistor NM1 may receive the control signal CTR through its gate and perform an on / off operation. Therefore, when the first PMOS transistor PM1 and the first NMOS transistor NM1 are turned on based on the negative control signal / CTR and the control signal CTR, respectively, the comparison circuit 120 may be enabled to perform an operation of comparing the distribution voltage VD with the first reference voltage VREF1 .

[0049] Through the above configuration, the voltage detection circuit 100 may generate the distribution voltage VD corresponding to the external power voltage VCCE, and may generate the power-down control signal DTVCC through a comparison operation enabled by the control signal CTR.

[0050] As described above, the control signal CTR generated by the semiconductor device may have a voltage level corresponding to the voltage level of the internal power supply voltage VCCI driven as the external power supply voltage VCCE in the sudden power-off state. Therefore, since the comparison circuit 120 is smoothly enabled in the sudden power-off state, the voltage detection circuit 100 can generate a stable power-off control signal DTVCC.

[0051] Figure 4 It is shown Figure 2 FIG. 2 is a diagram of a configuration of an internal voltage generating circuit 200 .

[0052] Reference Figure 4 , the internal voltage generating circuit 200 may include a comparison circuit 210, a driving circuit 220, a feedback circuit 230, a control circuit 240, and enabling circuits 250_1 and 250_2.

[0053] First, the comparison circuit 210 may be an element that generates a control voltage VC by comparing a feedback voltage VF corresponding to the internal power supply voltage VCCI with a second reference voltage VREF2 (i.e., a preset reference voltage). More specifically, the comparison circuit 210 may receive the second reference voltage VREF2 through one input stage, may receive the feedback voltage VF through another input stage, and may generate the control voltage VC through a comparison operation. Therefore, when the voltage level of the feedback voltage VF is lower than the voltage level of the second reference voltage VREF2, the comparison circuit 210 may reduce the voltage level of the control voltage VC.

[0054] The driving circuit 220 may be an element that drives the internal power supply voltage VCCI as the external power supply voltage VCCE based on the control voltage VC. More specifically, the driving circuit 220 may include a second PMOS transistor PM2, the source and drain of which are connected between a power supply stage to which the external power supply voltage VCCE is applied and an output stage to which the internal power supply voltage VCCI is output, and a gate of the second PMOS transistor PM2 is input with the control voltage VC. In this case, the on / off operation of the second PMOS transistor PM2 may be controlled based on the control voltage VC. Therefore, when the second PMOS transistor PM2 is turned on, the internal power supply voltage VCCI may be driven to the external power supply voltage VCCE.

[0055] The feedback circuit 230 may be an element that generates a feedback voltage VF by dividing the internal power supply voltage VCCI. More specifically, the feedback circuit 230 may include a third PMOS transistor PM3 and a fourth PMOS transistor PM4 that are connected in series between an output stage that outputs the internal power supply voltage VCCI and a ground stage to which a ground power supply voltage VSS is applied. The third PMOS transistor PM3 and the fourth PMOS transistor PM4 may be connected in a diode type. Therefore, the third PMOS transistor PM3 and the fourth PMOS transistor PM4 may output the feedback voltage VF by dividing the internal power supply voltage VCCI. In this case, the feedback voltage VF may be output from a common node to which the third PMOS transistor PM3 and the fourth PMOS transistor PM4 are connected and may be fed back to another input stage of the comparison circuit 210.

[0056] The control circuit 240 may be an element that controls the control voltage VC based on the power-off control signal DTVCC. More specifically, the control circuit 240 may include a second NMOS transistor NM2, the source and drain of which are connected between a ground level to which the ground power supply voltage VSS is applied and a node to which the control voltage VC is transmitted, and the gate of the second NMOS transistor NM2 is input with the power-off control signal DTVCC. In this case, the on / off operation of the second NMOS transistor NM2 may be controlled based on the power-off control signal DTVCC. Therefore, when the power-off control signal DTVCC is enabled with a logic level "high" in a sudden power-off state, for example, the second NMOS transistor NM2 may be turned on to drive the control voltage VC as the ground power supply voltage VSS. When the control voltage VC is driven to the ground power supply voltage VSS, the second PMOS transistor PM2 of the drive circuit 220 may be turned on, and therefore, the internal power supply voltage VCCI may be driven to the external power supply voltage VCCE.

[0057] The enabling circuits 250_1 and 250_2 may be based on Figure 2 The control signal generating circuit 300 outputs the control signal CTR to control the enable operation of the comparison circuit 210. More specifically, the enable circuits 250_1 and 250_2 may include a fifth PMOS transistor PM5 whose source and drain are connected between the power supply stage to which the external power supply voltage VCCE is applied and the comparison circuit 210, and the enable circuits 250_1 and 250_2 may respectively include a third NMOS transistor NM3 whose source and drain are connected between the comparison circuit 210 and the ground stage to which the ground power supply voltage VSS is applied. In this case, the fifth PMOS transistor PM5 may receive the negative control signal / CTR through its gate and may perform an on / off operation. In addition, the third NMOS transistor NM3 may receive the control signal CTR through its gate and may perform an on / off operation. Therefore, when the fifth PMOS transistor PM5 and the third NMOS transistor NM3 are turned on based on the negative control signal / CTR and the control signal CTR, respectively, the comparison circuit 210 may be enabled to perform an operation of comparing the feedback voltage VF with the second reference voltage VREF2.

[0058] By the above configuration, the internal voltage generating circuit 200 can generate the internal power voltage VCCI in the normal operation state. In addition, the internal voltage generating circuit 200 can drive the internal power voltage VCCI as the external power voltage VCCE during the enable period of the power-down control signal DTVCC in the sudden power-down state.

[0059] The semiconductor device can ensure the use of the internal power supply voltage VCCI by generating the internal power supply voltage VCCI driven as the external power supply voltage VCCE in a sudden power-off state. Figure 2 The control signal generating circuit 300 can generate a control signal CTR corresponding to the external power supply voltage VCCE in a sudden power-off state. Therefore, the control signal generating circuit 300 can be guaranteed to operate stably in a sudden power-off state. Figure 2 The voltage detection circuit 100, the internal voltage generation circuit 200, and the reference voltage generation circuit 400 to which the control signal CTR is inputted operate stably.

[0060] Figure 5 is a block diagram showing a configuration of a semiconductor memory device according to an embodiment.

[0061] Reference Figure 5 , a semiconductor memory device may include a sudden power detection circuit 1000 , a memory cell array 2000 , and discharge driving circuits 3010 , 3020 , and 3030 .

[0062] First, the sudden power detection circuit 1000 may be an element that generates a power-off control signal DTVCC having a voltage level corresponding to the voltage level of the external power supply voltage VCCE in a sudden power-off state. The sudden power detection circuit 1000 may include a voltage detection circuit 100A, an internal voltage generation circuit 200A, and a control signal generation circuit 300A. In this case, the voltage detection circuit 100A, the internal voltage generation circuit 200A, and the control signal generation circuit 300A may be respectively connected to Figure 2 The voltage detection circuit 100, the internal voltage generating circuit 200 and the control signal generating circuit 300 correspond to each other, and therefore, the detailed configuration and operation of each element will be omitted.

[0063] The memory cell array 2000 may be an element for storing data. The memory cell array 2000 may include a plurality of memory cells C0, C1, ..., and Cn, which are connected between a bit line BL and a source line CSL and whose gates are respectively connected to a plurality of word lines WL0, WL1, ..., and Wn (where n is a natural number). The memory cell array 2000 may include a plurality of memory cell strings ST, each of which includes a plurality of memory cells C0, C1, ..., and Cn. Figure 5 1 and 2 , one memory cell string ST is representatively shown in FIG. The memory cell string ST may perform a program operation, a read operation, or an erase operation based on the level of a voltage applied to a bit line BL, a source line CSL, and a plurality of word lines WL0, WL1, ..., and Wn. Since the program operation, the read operation, and the erase operation of the memory cell string ST are well-known techniques, the description of the detailed configuration and operation thereof is omitted.

[0064] For reference, the memory cell string ST may include a drain selection transistor DST having one end connected to the bit line BL and turned on / off based on the drain selection signal DSL, and a source selection transistor SST having one end connected to the source line CSL and turned on / off based on the source selection signal SSL. In addition, the memory cell string ST may include a plurality of memory cells C0, C1, ... and Cn connected in series between the drain selection transistor DST and the source selection transistor SST. In addition, the gates of the plurality of memory cells C0, C1, ... and Cn may be respectively connected to a plurality of word lines WL0, WL1, ... and Wn. Below, for the convenience of description, the word line WLn among the plurality of word lines WL0, WL1, ... and Wn is representatively described.

[0065] The discharge driving circuits 3010, 3020, and 3030 may be elements that discharge at least one of the bit line BL, the source line CSL, and the word line WLn during the enable period of the power-off control signal DTVCC. The discharge driving circuits 3010, 3020, and 3030 may include a first discharge driving circuit 3010 that discharges the bit line BL based on the power-off control signal DTVCC, a second discharge driving circuit 3020 that discharges the source line CSL based on the power-off control signal DTVCC, and a third discharge driving circuit 3030 that discharges the word line WLn based on the power-off control signal DTVCC.

[0066] More specifically, the first discharge driving circuit 3010 may include a fourth NMOS transistor NM4, a source and a drain of the fourth NMOS transistor NM4 are connected between a ground level to which the ground power supply voltage VSS is applied and the bit line BL, and a gate of the fourth NMOS transistor NM4 is input with a power-off control signal DTVCC. In this case, the fourth NMOS transistor NM4 may perform a turn-on / off operation based on the power-off control signal DTVCC. Therefore, when the fourth NMOS transistor NM4 is turned on based on the power-off control signal DTVCC, the bit line BL may be discharged to the ground power supply voltage VSS.

[0067] The second discharge driving circuit 3020 may include a fifth NMOS transistor NM5 turned on based on the power-off control signal DTVCC. The third discharge driving circuit 3030 may include a sixth NMOS transistor NM6 turned on based on the power-off control signal DTVCC. Similar to the first discharge driving circuit 3010, the second discharge driving circuit 3020 and the third discharge driving circuit 3030 may discharge the source line SL and the word line WLn to the ground power supply voltage VSS, respectively, based on the power-off control signal DTVCC.

[0068] The semiconductor memory device can generate a power-off control signal DTVCC having a voltage level corresponding to the voltage level of the external power supply voltage VCCE in the sudden power-off state. Therefore, in the sudden power-off state, the discharge operation of the bit line BL, the source line SL, and the word line WLn connected to the memory cell string ST can be stably guaranteed by the first discharge driving circuit 3010, the second discharge driving circuit 3020, and the third discharge driving circuit 3030.

[0069] Figure 6 It shows that according to Figure 5 A block diagram of a semiconductor memory device according to another embodiment of the semiconductor memory device.

[0070] Reference Figure 5 and Figure 6 ,Apart from Figure 5 In addition to the sudden power detection circuit 1000, the memory cell array 2000, and the first discharge driving circuit 3010, the second discharge driving circuit 3020, and the third discharge driving circuit 3030 shown in the figure, the semiconductor memory device may further include Figure 6 The selection control circuit 4000.

[0071] The selection control circuit 4000 may be an element that provides a power-off control signal DTVCC to at least one of the first discharge driving circuit 3010, the second discharge driving circuit 3020, and the third discharge driving circuit 3030 based on the operation information INF_OP of the memory cell array 2000 during normal operation. In this case, the first power-off control signal DTVCC1 may be a signal provided to the first discharge driving circuit 3010. The second power-off control signal DTVCC2 may be a signal provided to the second discharge driving circuit 3020. The third power-off control signal DTVCC3 may be a signal provided to the third discharge driving circuit 3030.

[0072] The operation information INF_OP may mean information corresponding to the operation state of the memory cell array 2000 during normal operation before the sudden power-off state occurs. That is, the memory cell array 2000 may perform any one of a program operation, a read operation, and an erase operation before the sudden power-off state occurs. In this case, the operation information INF_OP may include information about the operation of the memory cell array 2000.

[0073] For example, assuming that the memory cell array 2000 performs a programming operation or a reading operation before the sudden power-off state occurs, the operation information INF_OP may include information corresponding to the programming operation or the reading operation. In this case, the selection control circuit 4000 may, for example, selectively control the discharge operation of the word line WLn based on the operation information INF_OP. That is, the selection control circuit 4000 may output the power-off control signal DTVCC as the third power-off control signal DTVCC3 based on the operation information INF_OP. Therefore, the third power-off control signal DTVCC3 may be selectively sent to the third discharge driving circuit 3030. That is, the discharge operation may be performed on the word line WLn in priority to the source line SL and the bit line BL.

[0074] The semiconductor memory device may selectively discharge at least one of a word line, a source line, and a bit line based on a program operation, a read operation, and an erase operation performed during a normal operation in a sudden power-off state.

[0075] The embodiments of the present disclosure have an effect that it can smoothly control a circuit supplied with a power-off control signal by generating a stable power-off control signal in a sudden power-off state.

[0076] The embodiments of the present disclosure have an effect that it can increase the reliability of data stored in a memory cell by ensuring a stable discharge operation in a sudden power-off state.

[0077] Effects of the present disclosure are not limited to the above-described effects, and other effects not described above may be clearly understood by those skilled in the art to which the present disclosure pertains from the above description.

[0078] Although various embodiments have been described for illustrative purposes, it will be apparent to those skilled in the art that various changes and modifications can be made without departing from the spirit and scope of the disclosure as defined in the following claims.

[0079] CROSS-REFERENCE TO RELATED APPLICATIONS

[0080] This application claims priority to Korean Patent Application No. 10-2020-0064039, filed on May 28, 2020, which is hereby incorporated by reference in its entirety.

Claims

1. A semiconductor device, comprising: a voltage detection circuit configured to enable a power-off control signal by detecting a voltage level of an external power supply voltage; an internal voltage generating circuit configured to receive the external power supply voltage, generate an internal power supply voltage by comparing the external power supply voltage with a preset reference voltage, and drive the internal power supply voltage as the external power supply voltage during an enable period of the power-off control signal; as well as A control signal generating circuit is configured to generate a control signal having a voltage level corresponding to the voltage level of the internal power supply voltage and configured to control a circuit operation of the voltage detecting circuit.

2. The semiconductor device according to claim 1, further comprising a reference voltage generating circuit configured to generate the reference voltage, in, Whether to enable the voltage generating operation of the reference voltage generating circuit is based on the control signal.

3. The semiconductor device according to claim 1, wherein The voltage detection circuit comprises: a distribution circuit configured to generate a distribution voltage by dividing the voltage level of the external power supply voltage; a comparison circuit configured to generate the power-off control signal by comparing the distribution voltage with the reference voltage; and An enabling circuit is configured to control an enabling operation of the comparison circuit based on the control signal.

4. The semiconductor device according to claim 1, wherein The internal voltage generating circuit comprises: a comparison circuit configured to generate a control voltage by comparing a feedback voltage corresponding to the internal power supply voltage with the reference voltage; a driving circuit configured to drive the internal power supply voltage as the external power supply voltage based on the control voltage; a feedback circuit configured to generate the feedback voltage by dividing the internal power supply voltage; a control circuit configured to control the control voltage based on the power-off control signal; and An enabling circuit is configured to control an enabling operation of the comparison circuit based on the control signal. 5 . The semiconductor device according to claim 1 , further comprising an operation circuit configured to discharge at least one node within the semiconductor device during the enable period of the power-down control signal.

6. A semiconductor memory device, the semiconductor memory device comprising: a sudden power detection circuit configured to generate a power-off control signal having a voltage level corresponding to a voltage level of an external power supply voltage in a sudden power-off state; a memory cell array configured to store data and including memory cells connected between bit lines and source lines and having gates coupled to word lines; as well as A discharge driving circuit is configured to selectively discharge at least one of the bit line, the source line, and the word line during an enable period of the power-off control signal.

7. The semiconductor memory device according to claim 6, wherein: The sudden power detection circuit comprises: a voltage detection circuit configured to enable the power-off control signal by detecting the voltage level of the external power supply voltage; an internal voltage generating circuit configured to receive the external power supply voltage, generate an internal power supply voltage by comparing the external power supply voltage with a preset reference voltage, and drive the internal power supply voltage as the external power supply voltage during the enabling period of the power-off control signal; and A control signal generating circuit is configured to generate a control signal having a voltage level corresponding to the voltage level of the internal power supply voltage and configured to control a circuit operation of the voltage detecting circuit.

8. The semiconductor memory device according to claim 7, wherein: The voltage detection circuit comprises: a distribution circuit configured to generate a distribution voltage by dividing the voltage level of the external power supply voltage; a comparison circuit configured to generate the power-off control signal by comparing the distribution voltage with the reference voltage; and An enabling circuit is configured to control an enabling operation of the comparison circuit based on the control signal.

9. The semiconductor memory device according to claim 7, wherein: The internal voltage generating circuit comprises: a comparison circuit configured to generate a control voltage by comparing a feedback voltage corresponding to the external power supply voltage with the reference voltage; a driving circuit configured to drive the internal power supply voltage as the external power supply voltage based on the control voltage; a feedback circuit configured to generate the feedback voltage by dividing the internal power supply voltage; a control circuit configured to control the control voltage based on the power-off control signal; and An enabling circuit is configured to control an enabling operation of the comparison circuit based on the control signal.

10. The semiconductor memory device according to claim 6, wherein: The discharge driving circuit comprises: a first discharge driving circuit configured to discharge the bit line based on the selectively input power-off control signal; a second discharge driving circuit configured to discharge the source line based on the selectively input power-off control signal; and A third discharge driving circuit is configured to discharge the word line based on the selectively input power-off control signal.

11. The semiconductor memory device according to claim 10, further comprising a selection control circuit configured to provide the power-off control signal to at least one of the first discharge driving circuit, the second discharge driving circuit, and the third discharge driving circuit based on operation information of the memory cell array during normal operation before the sudden power-off state occurs.

12. The semiconductor memory device according to claim 11, wherein The operation information includes information on at least one of a program operation, a read operation, and an erase operation.

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