A magnetoresistive memory unit, a write control method and a storage and calculation module

Abstract

The present invention discloses a magnetoresistive memory unit, a write control method and a storage and calculation module, wherein the magnetoresistive memory unit comprises: a first magnetic tunnel junction, a second magnetic tunnel junction and a metal layer; the first magnetic tunnel junction and the second magnetic tunnel junction are both arranged on the metal layer; the metal layer is configured to pass a write current, the easy axis of the first magnetic tunnel junction is at a first angle with the direction of the write current in the plane where the metal layer is located, the easy axis of the second magnetic tunnel junction is at a second angle with the direction of the write current along the plane where the metal layer is located, and the first angle and the second angle are opposite to the deflection direction of the write current; the first magnetic tunnel junction and the second magnetic tunnel junction are configured to pass a read current. The magnetoresistive memory unit of the present invention can realize fully electrically controlled ultrafast magnetization reversal without external magnetic field assistance, which is conducive to large-scale integration, and can realize reading through a self-reference mechanism when reading information, thereby improving the reading margin, thereby enhancing the reading reliability and reducing the reading delay.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a magnetoresistive memory unit, a write control method and a storage and calculation module. Background Art

[0002] Convolutional Neural Networks (CNN) are widely used in many fields such as image recognition, speech recognition, and natural language processing, showing excellent performance. However, due to its huge demand for storage and computing resources, the hardware implementation of large-scale convolutional neural networks is limited. Binary Neural Networks (BNN) reduce storage resource overhead by binarizing the synaptic weights and neuron input and output of convolutional neural networks; dot products are used instead of high-precision multiplication operations to simplify computing tasks and reduce the burden of computing resources. At the same time, they show comparable accuracy to convolutional neural networks on various large-scale data sets. Therefore, binary neural networks have received more and more attention and provide a solution for the hardware implementation of deep neural networks. Hardware neural networks based on traditional von Neumann architecture are difficult to integrate and apply on a large scale due to storage wall and power consumption wall problems. In recent years, the development of in-memory computing (IMC) platforms based on new non-volatile memories has brought hardware neural networks into a new development period. Among various new non-volatile memories, SOT-MRAM (Spin-Orbit Torque Magnetic Random Access Memory) is expected to become the next generation of general-purpose memory due to its advantages such as high read and write speed, unlimited erase and write times, high data retention time, low write power consumption and compatibility with CMOS (Complementary Metal Oxide Semiconductor) process. It has been widely used in the research of in-memory computing platforms and hardware neural networks.

[0003] However, the current SOT-MRAM is not conducive to large-scale integration due to its three-terminal structure and the need for an external magnetic field to assist in achieving deterministic magnetization switching. In addition, its small tunnel magnetoresistance (TMR) limits its read performance, resulting in a higher read error rate. Summary of the invention

[0004] The embodiments of the present application provide a magnetoresistive memory unit, a write control method and a storage and computing module, wherein the magnetoresistive memory unit can realize fully electrically controlled ultrafast magnetization reversal without the assistance of an external magnetic field, which is conducive to large-scale integration, and can realize reading through a self-reference mechanism when reading information, thereby improving the reading margin, thereby enhancing the reading reliability and reducing the reading delay.

[0005] In the first aspect, the present application provides the following technical solutions through an embodiment of the present application:

[0006] A magnetoresistive memory unit comprises: a first magnetic tunnel junction, a second magnetic tunnel junction and a metal layer; the first magnetic tunnel junction and the second magnetic tunnel junction are both arranged on the metal layer; the metal layer is configured to pass a write current, the easy axis of the first magnetic tunnel junction forms a first angle with the direction of the write current in the plane where the metal layer is located, the easy axis of the second magnetic tunnel junction forms a second angle with the direction of the write current along the plane where the metal layer is located, and the first angle and the second angle have opposite deflection directions relative to the direction of the write current; the first magnetic tunnel junction and the second magnetic tunnel junction are configured to pass a read current.

[0007] Optionally, cross-sections of the first magnetic tunnel junction and the second magnetic tunnel junction are both elliptical.

[0008] Optionally, the first angle and the second angle are equal in size.

[0009] Optionally, the first angle and the second angle range from 30° to 60°.

[0010] Optionally, the first angle and the second angle are both 45°.

[0011] Optionally, the first magnetic tunnel junction and the second magnetic tunnel junction both include: a synthetic antiferromagnetic layer, a ferromagnetic reference layer, a barrier layer and a ferromagnetic free layer; the ferromagnetic free layer is arranged on the metal layer, the barrier layer is arranged on the side of the ferromagnetic free layer away from the metal layer, the ferromagnetic reference layer is arranged on the side of the barrier layer away from the metal layer, and the synthetic antiferromagnetic layer is arranged on the side of the ferromagnetic reference layer away from the metal layer; the magnetization directions of the ferromagnetic reference layers in the first magnetic tunnel junction and the second magnetic tunnel junction are the same.

[0012] Optionally, it also includes: a first transistor, a second transistor and a third transistor; the first transistor is connected to the side of the first magnetic tunnel junction away from the metal layer, the second transistor is connected to the side of the second magnetic tunnel junction away from the metal layer, and the third transistor is connected to the first end of the metal layer in the lateral direction.

[0013] In the second aspect, based on the same inventive concept, the present application provides the following technical solution through an embodiment of the present application:

[0014] A write control method for a magnetoresistive memory unit is applied to any magnetoresistive memory unit described in the first aspect above, and the write control method comprises:

[0015] A write current is passed through the metal layer along a first direction so that the magnetoresistive memory unit is in a first storage state; the first storage state is: the first magnetic tunnel junction is in a high resistance state, and the second magnetic tunnel junction is in a low resistance state; or, a write current is passed through the metal layer along a second direction so that the magnetoresistive memory unit is in a second storage state; the second storage state is: the first magnetic tunnel junction is in a low resistance state, and the second magnetic tunnel junction is in a high resistance state; wherein the first direction is opposite to the second direction.

[0016] In the third aspect, based on the same inventive concept, the present application provides the following technical solution through an embodiment of the present application:

[0017] A storage and computing module of a BNN chip comprises a synaptic array composed of any of the magnetoresistive memory units described in the first aspect above, wherein the synaptic array is used to store synaptic weights.

[0018] Optionally, in the synapse array, each column of the magnetoresistive memory unit stores a synaptic weight of a neuron;

[0019] The storage and calculation module is used to determine that the output of the target neuron is 1 when the sum of multiple synaptic weights of the corresponding column of the target neuron is positive; the target neuron is any neuron, and each of the magnetoresistive memory units corresponds to a synaptic weight; the storage and calculation module is also used to determine that the output of the target neuron is 0 when the sum of multiple synaptic weights of the target neuron is negative; wherein, for each of the magnetoresistive memory units: the storage and calculation module is also used to record the synaptic weight corresponding to the magnetoresistive memory unit as 1 when the read current of the first magnetic tunnel junction is greater than the read current of the second magnetic tunnel junction; and when the read current of the first magnetic tunnel junction is less than the read current of the second magnetic tunnel junction, record the synaptic weight corresponding to the magnetoresistive memory unit as -1.

[0020] One or more technical solutions provided in the embodiments of the present application have at least the following technical effects or advantages:

[0021] 1. The magnetoresistive memory unit of the embodiment of the present invention can realize fully electrically controlled ultrafast magnetization switching without external magnetic field assistance, because the first magnetic tunnel junction and the second magnetic tunnel junction are arranged on the metal layer and are deflected at the first angle and the second angle oppositely, respectively, which is conducive to large-scale integration.

[0022] 2. The magnetoresistive memory unit of the embodiment of the present invention realizes that the configuration of the first magnetic tunnel junction and the second magnetic tunnel junction is always opposite after inversion, forming a complementary structure to store one bit. When reading information, the reading can be realized through a self-reference mechanism, thereby improving the reading margin, thereby enhancing the reading reliability and reducing the reading delay. In addition, no external magnetic field is required to achieve flipping during operation.

[0023] 3. The magnetoresistive memory unit of the embodiment of the present invention can realize a 1R1W (one read and one write) dual-port storage array based on 3T2SOT MTJ (3 transistors, 2 spin-orbit moment magnetic tunnel junctions), which can read and write in blocks at the same time, greatly improving the read and write efficiency and increasing the parallelism of the storage unit.

[0024] 4. The storage and computing module of the BNN chip of the embodiment of the present invention is optimized at the algorithm level. When reading the synaptic array, the entire column can be read, and the synaptic weights can be added at the same time, which greatly improves the parallelism of the BNN. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0026] Figure 1 A schematic diagram showing the structure of a magnetoresistive memory unit in an embodiment of the present invention is shown;

[0027] Figure 2 Shows Figure 1 Schematic diagram of the deflection angle of the magnetic tunnel junction of the magnetoresistive memory unit;

[0028] Figure 3 Shows Figure 1 Schematic diagram of magnetization reversal of magnetic tunnel junction of magnetoresistive memory cell driven by current in +x direction;

[0029] Figure 4 Shows Figure 1 Schematic diagram of magnetization reversal of a magnetoresistive memory cell when driven by a current in the -x direction;

[0030] Figure 5 Shows Figure 1 Schematic diagram of magnetization reversal of magnetic tunnel junction of magnetoresistive memory unit under continuous bipolar pulses;

[0031] Figure 6 shows the control through 3 transistors Figure 1 Schematic diagram of the principle of reading and writing a magnetoresistive memory unit;

[0032] Figure 7 A schematic diagram of the structure of a synaptic array of a storage and computing module of a BNN chip provided in one embodiment of the present invention is shown.

[0033] Icon: 11-first magnetic tunnel junction; 12-second magnetic tunnel junction; 101-synthetic antiferromagnetic layer; 102-ferromagnetic reference layer; 103-barrier layer; 104-ferromagnetic free layer; 21-metal layer; 31-current path; 401-first transistor; 402-second transistor; 403-third transistor; 511-write driver; 512-column decoder; 611-sensitive amplifier; 711-row decoder; 811-source line driver; 812-source line decoder. DETAILED DESCRIPTION

[0034] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the present disclosure. In addition, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessary confusion of the concepts of the present disclosure.

[0035] Various structural schematic diagrams according to embodiments of the present disclosure are shown in the accompanying drawings. These figures are not drawn to scale, and some details are magnified and some details may be omitted for the purpose of clear expression. The shapes of various regions and layers shown in the figures and the relative sizes and positional relationships therebetween are only exemplary, and may deviate in practice due to manufacturing tolerances or technical limitations, and those skilled in the art may further design regions / layers with different shapes, sizes, and relative positions according to actual needs.

[0036] In the context of the present disclosure, when a layer / element is referred to as being "on" another layer / element, the layer / element may be directly on the other layer / element or an intervening layer / element may exist therebetween. In addition, if a layer / element is "on" another layer / element in one orientation, the layer / element may be "below" the other layer / element when the orientation is reversed.

[0037] See also Figure 1 A magnetoresistive memory cell provided in one embodiment of the present invention includes: a first magnetic tunnel junction 11 (Magnetic Tunnel Junction, MTJ), a second magnetic tunnel junction 12 and a metal layer 21.

[0038] The first magnetic tunnel junction 11 and the second magnetic tunnel junction 12 are both disposed on the metal layer 21. The metal layer 21 is configured to pass a write current.

[0039] For example, in Figure 1In the magnetoresistive memory cell shown, the write current can be along the positive direction of the x-axis or along the negative direction of the x-axis. The write current is the current that passes when writing information to the magnetoresistive memory cell.

[0040] The first magnetic tunnel junction 11 and the second magnetic tunnel junction 12 have the same structure, and the easy axis of the first magnetic tunnel junction 11 forms a first angle with the direction of the write current along the plane where the metal layer 21 is located, and the easy axis of the second magnetic tunnel junction 12 forms a second angle with the direction of the write current along the plane where the metal layer 21 is located, and the first angle and the second angle are opposite in deflection direction relative to the direction of the write current; the first magnetic tunnel junction 11 and the second magnetic tunnel junction 12 are configured to pass a read current. The read current is the current passed when reading the information stored in the magnetoresistive memory cell.

[0041] Since the first magnetic tunnel junction 11 and the second magnetic tunnel junction 12 are arranged on the metal layer 21, they are in an antisymmetric state; at this time, when a write current passes through the metal layer 21, the magnetization directions of the first magnetic tunnel junction 11 and the second magnetic tunnel junction 12 are always opposite, so that the configurations of the two magnetic tunnel junctions are always opposite and complementary. In this way, after passing write currents in different directions, the first magnetic tunnel junction 11 and the second magnetic tunnel junction 12 can be made to exhibit a high resistance state or a low resistance state respectively. When a read current passes through the first magnetic tunnel junction 11 and the second magnetic tunnel junction 12, different information can be obtained by comparing the read currents of the two magnetic tunnel junctions. In the entire read and write process, the write current can realize a sub-nanosecond level of fully electrically controlled ultrafast magnetization reversal without the need for an external magnetic field.

[0042] In a possible implementation, the cross-sections of the first magnetic tunnel junction 11 and the second magnetic tunnel junction 12 are both elliptical. It should be noted that the elliptical shape in this embodiment can be a strict elliptical shape at best; however, due to limitations such as process, the elliptical shape can also refer to a substantially elliptical shape. The first magnetic tunnel junction 11 and the second magnetic tunnel junction 12 can be an elliptical cylinder as a whole.

[0043] In a possible implementation, the first angle and the second angle should be equal to ensure that the first magnetic tunnel junction 11 and the second magnetic tunnel junction 12 have the same magnetization reversal effect, making information reading and writing more stable and reliable. Figure 2 As shown, the first angle size The size of the second angle The first angle and the second angle can be determined to be in the range of 30° to 60°, which can ensure a suitable threshold current and realize magnetization reversal without external field assistance. Experiments on the magnetoresistive memory unit in this embodiment show that: Figure 3 and Figure 4 The response graph of the current-driven magnetization reversal micromagnetic simulation results is shown, where the ordinate is the normalized value of the x component of the magnetization intensity (mx). Figure 3 and Figure 4 It can be seen that a better magnetization reversal effect can be achieved when the first angle and the second angle are in the range of 30° to 60°. For example, the first angle and the second angle can be 35°, 45°, 55°, etc. Figure 3 When the current is in the +x direction, the first magnetic tunnel junction 11 flips but the second magnetic tunnel junction 12 does not flip; Figure 4 When the current flows in the −x direction, the first magnetic tunnel junction 11 does not flip, but the second magnetic tunnel junction 12 flips.

[0044] Please continue reading Figure 5 ,exist Figure 5 The figure shows the reversal of the first magnetic tunnel junction 11 and the second magnetic tunnel junction 12 under the action of continuous bipolar pulses. Under the action of the first pulse, the magnetization directions of the first magnetic tunnel junction 11 and the second magnetic tunnel junction 12 change from parallel to antiparallel, that is, the initialization is completed. After the subsequent pulses, the magnetization directions of the first magnetic tunnel junction 11 and the second magnetic tunnel junction 12 are always opposite, and the corresponding storage states are opposite, and the reversal responds quickly, with high reliability, realizing the fully electrically controlled ultrafast magnetization reversal without the assistance of an external magnetic field.

[0045] For the first magnetic tunnel junction 11 , the second magnetic tunnel junction 12 and the metal layer 21 , the present embodiment has the following implementation methods.

[0046] The first magnetic tunnel junction 11 and the second magnetic tunnel junction 12 may both include: a synthetic antiferromagnetic layer 101, a ferromagnetic reference layer 102, a barrier layer 103 and a ferromagnetic free layer 104. The ferromagnetic free layer 104 is disposed on the metal layer 21, the barrier layer 103 is disposed on a side of the ferromagnetic free layer 104 away from the metal layer 21, the ferromagnetic reference layer 102 is disposed on a side of the barrier layer 103 away from the metal layer 21, and the synthetic antiferromagnetic layer 101 is disposed on a side of the ferromagnetic reference layer 102 away from the metal layer 21; the ferromagnetic reference layer 102 in the first magnetic tunnel junction 11 and the second magnetic tunnel junction 12 have the same magnetization direction.

[0047] The synthetic antiferromagnetic layer 101 is a stacked multi-layer structure and can be realized by using existing composition methods.

[0048] The ferromagnetic reference layer 102 can be one of cobalt iron boron (CoFeB), Permalloy (CoNi), cobalt (Co), cobalt platinum alloy (CoPt) or a combination thereof; other existing implementations can also be used. The magnetization directions of the ferromagnetic reference layers 102 of the first magnetic tunnel junction 11 and the second magnetic tunnel junction 12 are the same.

[0049] The barrier layer 103 and the ferromagnetic free layer 104 may be made of in-plane anisotropic ferromagnetic materials, such as cobalt iron boron (CoFeB), permalloy (CoNi), cobalt (Co), cobalt platinum alloy (CoPt), etc., or a combination thereof. The ferromagnetic free layer 104 may be flipped under the action of a write current.

[0050] The metal layer 21 may be made of a heavy metal material, for example, any one or more of platinum (Pt), tantalum (Ta) and tungsten (W) may be used.

[0051] In a possible implementation, the magnetoresistive memory unit further includes: a first transistor 401, a second transistor 402, and a third transistor 403. The first transistor 401 is connected to the side of the first magnetic tunnel junction 11 away from the metal layer 21, the second transistor 402 is connected to the side of the second magnetic tunnel junction 12 away from the metal layer 21, and the third transistor 403 is connected to the first lateral end of the metal layer 21, and the second lateral end of the metal layer 21 is used as an input end or an output end. Therefore, in this implementation, only three transistors can be used to realize the read and write control of the magnetoresistive memory unit, and a unit circuit of a 3T2SOT MTJ (3 transistors, 2 spin-orbit moment magnetic tunnel junctions) device can be realized, such as Figure 6 As shown. The input terminals of the first transistor 401 and the second transistor 402 are also connected to the first bit line and the second bit line, i.e., the first bit line BL and the second bit line / BL, respectively, and the word line is used to provide a read current. The control terminals of the first transistor 401 and the second transistor 402 can be connected to the read control word line, i.e., the read control word line RWL. The read control word line is used to provide a signal to control the first transistor 401 and the second transistor 402 to be turned on or off. The input terminal of the third transistor 403 can be connected to any word line, and the control terminal of the third transistor 403 is connected to the write control word line, i.e., the write control word line WWL. The write control word line is used to provide a signal to control the third transistor 403 to be turned on or off. The second end of the metal layer 21 can be realized as an input or output terminal by connecting a source line, i.e., the source line SL; the source line SL can be grounded or pulled high according to the required current polarity.

[0052] The types of the first transistor 401, the second transistor 402 and the third transistor 403 are not limited. Through the first transistor 401, the second transistor 402 and the third transistor 403, the circuit of the read operation and the circuit of the write operation of the magnetoresistive memory unit can be independently regulated. Based on this characteristic, a 1R1W (one read and one write) dual-port memory unit can be realized, which can greatly improve the read and write efficiency and increase the parallelism of the memory unit. Figure 1 shown.

[0053] In a specific implementation process, when a write operation is performed on a magnetoresistive memory cell, the process may be as follows:

[0054] A write current along a first direction is passed through the metal layer 21 to make the magnetoresistive memory cell present in a first storage state; the first storage state is: the first magnetic tunnel junction 11 is in a high resistance state, and the second magnetic tunnel junction 12 is in a low resistance state.

[0055] For example, when the ferromagnetic reference layer 102 of the first magnetic tunnel junction 11 and the second magnetic tunnel junction 12 are both in the +x direction, and the first direction is the +x direction, the magnetization direction of the first magnetic tunnel junction 11 is in the -x direction, and the magnetization direction of the second magnetic tunnel junction 12 is in the +x direction. Figure 3 At this time, in the first magnetic tunnel junction 11, the magnetization directions of the ferromagnetic free layer 104 and the ferromagnetic reference layer 102 are antiparallel, and the first magnetic tunnel junction 11 is in a high resistance state; in the second magnetic tunnel junction 12, the magnetization directions of the ferromagnetic free layer 104 and the ferromagnetic reference layer 102 are parallel, and the second magnetic tunnel junction 12 is in a low resistance state.

[0056] Alternatively, a write current is passed through the metal layer 21 along a second direction to make the magnetoresistive memory unit present a second storage state; the second storage state is: the first magnetic tunnel junction 11 is in a low resistance state, and the second magnetic tunnel junction 12 is in a high resistance state; wherein the first direction and the second direction are opposite.

[0057] For example, when the ferromagnetic reference layer 102 of the first magnetic tunnel junction 11 and the second magnetic tunnel junction 12 are both in the +x direction, and the first direction is the -x direction, the magnetization direction of the first magnetic tunnel junction 11 is in the +x direction, and the magnetization direction of the second magnetic tunnel junction 12 is in the -x direction. Figure 4 At this time, in the first magnetic tunnel junction 11, the magnetization directions of the ferromagnetic free layer 104 and the ferromagnetic reference layer 102 are parallel, and the first magnetic tunnel junction 11 is in a low resistance state; in the second magnetic tunnel junction 12, the magnetization directions of the ferromagnetic free layer 104 and the ferromagnetic reference layer 102 are antiparallel, and the second magnetic tunnel junction 12 is in a high resistance state.

[0058] For easier understanding, please continue to refer to the following example of writing information:

[0059] When writing, the level of the write control word line can be pulled high, and the level of the read control word line can be pulled low, so that the first transistor 401 and the second transistor 402 are turned off, and the third transistor 403 is turned on. Then, the source line is connected to a low level, and a current path flowing through the metal layer 21 is formed between the third transistor 403 and the source line. The metal layer 21 converts the current along the x-axis into a spin current polarized along the y-axis through the spin Hall effect or the Rashaba effect. The spin current is injected into the ferromagnetic free layer 104 along the z-axis to generate a spin-orbit moment to flip the magnetization of the ferromagnetic free layer 104, thereby realizing information writing; the writing process can be completed in only one step, with high writing efficiency and fast speed.

[0060] Correspondingly, please continue to refer to the following example of reading information:

[0061] When performing a read operation on a magnetoresistive memory cell, the level of the write control word line can be controlled to be pulled low, and the level of the read control word line can be pulled high, so that the first transistor 401 and the second transistor 402 are turned on, and the third transistor 403 is turned off; at the same time, the source line is connected to a low level. Thus, a current path flowing through the first magnetic tunnel junction 11 is formed between the first bit line and the source line, and a current path flowing through the second magnetic tunnel junction 12 is formed between the second bit line and the source line. The currents on the first bit line and the second bit line can be sent to a current-type sense amplifier to compare and read out the storage state of the storage cell. When determining the storage state of a magnetoresistive memory cell, an algorithm definition can be performed. For example, it can be defined that I BL >I / BL The corresponding synaptic weight is "1", I BL / BL When the corresponding synaptic weight is "-1", other definitions may be made in other embodiments, for example, BL >I / BL The corresponding synaptic weight is "-1", I BL / BL The corresponding synaptic weight is "1" and there is no restriction.

[0062] exist Figure 1 The current paths 31 for reading and writing information are shown in FIG.

[0063] It can be seen from the above examples that the magnetoresistive memory unit of this embodiment always realizes the opposite configuration after inversion through the first magnetic tunnel junction 11 and the second magnetic tunnel junction 12, forming a complementary structure to store one bit. When reading information, reading can be achieved through a self-reference mechanism. Therefore, the magnetoresistive memory unit of this embodiment can improve the read margin, thereby enhancing the read reliability and reducing the read delay. In addition, it does not require an external magnetic field to achieve flipping during operation, which is conducive to large-scale integration.

[0064] See also Figure 7 ​​In another embodiment of the present invention, a storage and calculation module of a BNN chip is also provided, the storage and calculation module includes a synaptic array composed of any magnetoresistive memory unit in the aforementioned embodiment, and the synaptic array is used to store synaptic weights. In the synaptic array, each column of magnetoresistive memory units stores the synaptic weight of a neuron. The first transistor 401 and the third transistor 403 of each column of magnetoresistive memory units are connected to the first bit line, and the second transistor 402 is connected to the second bit line; it should be noted that in other embodiments, the third transistor 403 can also be connected to the second bit line and controlled by the signal of the second bit line. The control ends of the first transistor 401 and the second transistor 402 of each row of magnetoresistive memory units are connected to the read control word line, and the control end of the third transistor 403 is connected to the write control word line; each row has its own read control word line and write control word line. The magnetoresistive memory units of each column are connected to the same source line. When working, the column decoder 512, the row decoder 711 and the source line decoder 812 select the unit for read / write operation, and the row decoder 711 can activate multiple word lines simultaneously according to the input. During the read operation, the total current on the first bit line BL and the second bit line / BL of each column is sent to the sense amplifier 611 for comparison to determine the output value. During the write operation, the write driver 511 and the source line driver 811 provide write current pulses.

[0065] It should be noted that the above-mentioned drivers and decoders in this embodiment can be implemented with reference to existing implementation schemes, and will not be described in detail in this embodiment.

[0066] The storage and calculation module is used to determine that the output of the target neuron is 1 when the sum of multiple synaptic weights of the corresponding column of the target neuron is positive; the target neuron is any neuron, and each magnetoresistive memory unit corresponds to a synaptic weight; the storage and calculation module is also used to determine that the output of the target neuron is 0 when the sum of multiple synaptic weights of the target neuron is negative. Among them, for each magnetoresistive memory unit: the storage and calculation module is also used to record the synaptic weight corresponding to the magnetoresistive memory unit as 1 when the read current of the first magnetic tunnel junction 11 is greater than the read current of the second magnetic tunnel junction 12; and when the read current of the first magnetic tunnel junction 11 is less than the read current of the second magnetic tunnel junction 12, the synaptic weight corresponding to the magnetoresistive memory unit is -1.

[0067] Due to R AP >>R P (R AP represents the resistance when the magnetization directions of the ferromagnetic reference layer 102 and the ferromagnetic free layer 104 are antiparallel and the magnetic tunnel junction is in a high resistance state; R P= ( ) indicates that the magnetization directions of the ferromagnetic reference layer 102 and the ferromagnetic free layer 104 are parallel, and the resistance of the magnetic tunnel junction is in a low resistance state. The read current on the first bit line or the second bit line is mainly generated by the read current of the magnetoresistive memory cell in the low resistance state. Therefore, the current I BL The current I / BL The difference corresponds to the difference in the number of low-resistance magnetoresistive memory cells in the two columns of word lines; that is, it corresponds to the sum of the synaptic weights corresponding to the magnetoresistive memory cells on one column. The current I BL The current I / BL The output is sent to the current-type sense amplifier 611 for comparison. It is defined that when the sum of the synaptic weights is positive, the sense amplifier output is "1", and vice versa, when the sum of the synaptic weights is negative, the sense amplifier output is "0". Therefore, the output of the sense amplifier can be directly regarded as the output of the binary neuron.

[0068] The storage and computing module of the BNN chip optimized by the above algorithm can read the synaptic array in its entirety and simultaneously realize the addition of synaptic weights, which greatly improves the parallelism of the BNN chip.

[0069] In addition, the features and beneficial effects of the storage and computing module of the BNN chip in this embodiment that have not been fully introduced can be referred to the description in the aforementioned embodiment of the magnetoresistive memory unit and will not be repeated in this embodiment.

[0070] Although the preferred embodiments of the present invention have been described, those skilled in the art may make other changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.

[0071] Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.

Claims

1. A magnetoresistive memory cell, characterized in that: include: a first magnetic tunnel junction, a second magnetic tunnel junction, and a metal layer; The first magnetic tunnel junction and the second magnetic tunnel junction are both arranged on the metal layer; The metal layer is configured to pass a write current, an easy axis of the first magnetic tunnel junction forms a first angle with a direction of the write current in a plane where the metal layer is located, an easy axis of the second magnetic tunnel junction forms a second angle with the direction of the write current along the plane where the metal layer is located, and the first angle and the second angle have opposite deflection directions relative to the direction of the write current; the first magnetic tunnel junction and the second magnetic tunnel junction are configured to pass a read current; The first angle and the second angle range from 30° to 60°.

2. The magnetoresistive memory cell according to claim 1, wherein: The cross sections of the first magnetic tunnel junction and the second magnetic tunnel junction are both elliptical.

3. The magnetoresistive memory cell according to claim 1, wherein: The first angle and the second angle are equal in magnitude.

4. The magnetoresistive memory cell according to claim 3, wherein: The first angle and the second angle are both 45°.

5. The magnetoresistive memory cell according to claim 1, wherein: The first magnetic tunnel junction and the second magnetic tunnel junction both include: a synthetic antiferromagnetic layer, a ferromagnetic reference layer, a barrier layer and a ferromagnetic free layer; the ferromagnetic free layer is arranged on the metal layer, the barrier layer is arranged on the side of the ferromagnetic free layer away from the metal layer, the ferromagnetic reference layer is arranged on the side of the barrier layer away from the metal layer, and the synthetic antiferromagnetic layer is arranged on the side of the ferromagnetic reference layer away from the metal layer; the magnetization directions of the ferromagnetic reference layers in the first magnetic tunnel junction and the second magnetic tunnel junction are the same.

6. The magnetoresistive memory cell according to claim 1, wherein: Also includes: A first transistor, a second transistor and a third transistor; the first transistor is connected to a side of the first magnetic tunnel junction away from the metal layer, the second transistor is connected to a side of the second magnetic tunnel junction away from the metal layer, and the third transistor is connected to a first end of the metal layer in a lateral direction.

7. A write control method for a magnetoresistive memory cell, characterized in that: Applied to the magnetoresistive memory cell according to any one of claims 1 to 6, the write control method comprises: Passing a write current along a first direction through the metal layer so that the magnetoresistive memory unit is in a first storage state; the first storage state is: the first magnetic tunnel junction is in a high resistance state, and the second magnetic tunnel junction is in a low resistance state; Alternatively, a write current is passed through the metal layer along a second direction so that the magnetoresistive memory unit is in a second storage state; the second storage state is: the first magnetic tunnel junction is in a low resistance state, and the second magnetic tunnel junction is in a high resistance state; wherein the first direction is opposite to the second direction.

8. A storage and computing module of a BNN chip, characterized in that: The invention comprises a synapse array composed of the magnetoresistive memory unit according to any one of claims 1 to 6, wherein the synapse array is used for storing synapse weights.

9. The storage and computing module of the BNN chip according to claim 8, characterized in that: In the synapse array, each column of the magnetoresistive memory unit stores the synaptic weight of a neuron; The storage and calculation module is used to determine that the output of the target neuron is 1 when the sum of multiple synaptic weights of the column corresponding to the target neuron is positive; the target neuron is any neuron, and each of the magnetoresistive memory units corresponds to one synaptic weight; The storage and calculation module is further used to determine that the output of the target neuron is 0 when the sum of multiple synaptic weights of the target neuron is negative; Among them, for each of the magnetoresistive memory units: the storage and calculation module is also used to record the synaptic weight corresponding to the magnetoresistive memory unit as 1 when the read current of the first magnetic tunnel junction is greater than the read current of the second magnetic tunnel junction; and when the read current of the first magnetic tunnel junction is less than the read current of the second magnetic tunnel junction, record the synaptic weight corresponding to the magnetoresistive memory unit as -1.

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