Tiered read reference calibration

Abstract

The present invention is entitled "Hierarchical Read Reference Calibration." The present invention discloses calibrating a read reference voltage. In one aspect, a control die calibrates a read reference voltage used to read a non-volatile memory cell. The control die is bonded to a memory die containing the memory cells. In one aspect, a hierarchical approach to calibrating the read reference voltage is employed. For example, first, the control die may attempt to determine a new value for the read reference voltage. If the new read reference voltage is satisfactory, the control die may use the new read reference voltage. The control die may use one or more different techniques to determine the new read reference voltage. If the new read reference voltage determined by the control die is not satisfactory, a memory controller in communication with the control die may calibrate the read reference voltage. By having the control die determine the new read reference voltage, the memory controller is significantly relieved of the burden of such tasks.

Description

Background Art

[0001] Strong growth in demand for portable consumer electronic devices is driving the need for high-capacity storage devices. Non-volatile semiconductor memory devices, such as flash memory cards, have become widely used to meet the growing demand for digital information storage and exchange. Their portability, versatility, and rugged design, along with their high reliability and large capacity, make these memory devices ideal for use in a variety of electronic devices, including, for example, digital cameras, digital music players, video game consoles, PDAs, and cellular phones.

[0002] Non-volatile semiconductor memory devices contain non-volatile memory cells that can be programmed to store data. Typically, memory cells are programmed into multiple data states. Using a greater number of data states allows each memory cell to store more bits. For example, four data states can be used to store two bits per memory cell, eight data states can be used to store three bits per memory cell, 16 data states can be used to store four bits per memory cell, and so on. To read data back from a non-volatile memory cell, a read reference voltage is typically used to determine what data state the memory cell is currently in.

[0003] For a variety of reasons, it may be advantageous to modify the read reference voltage over time in order to more accurately sense the data state to which the memory cell is intended to be programmed. One reason for such modification is that the condition of the memory cell may change between the time the memory cell is programmed and the time the memory cell is read back. For example, for a memory cell that stores its data state based on the charge stored in the memory cell, there may be a loss of charge over time. This charge loss is often referred to as a data retention problem. Memory cells may also suffer from program disturb, which refers to the condition of a memory cell (e.g., the amount of charge) changing due to other memory cells being programmed. Some memory cells may suffer from read disturb, which refers to the condition of a memory cell (e.g., the amount of charge) changing due to being read from. Another consideration is that there may be a significant temperature difference between the time the memory cell is programmed and the time the memory cell is read. Some memory cells are sensitive to such temperature changes. For example, some memory cells include transistors whose threshold voltage indicates the data state. The threshold voltage of a transistor is typically temperature dependent. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Figure 1A is a block diagram of one embodiment of a memory system connected to a host.

[0005] Figure 1B is a block diagram of one embodiment of a front-end processor circuit.

[0006] Figure 2is a block diagram of one embodiment of a back-end processor circuit.

[0007] Figure 3A is a functional block diagram of the integrated memory component.

[0008] Figure 3B is a block diagram of one embodiment of read / write circuitry and ECC for an integrated memory component.

[0009] Figure 3C An example of a sparse parity check matrix H is depicted.

[0010] Figure 3D Depicts the corresponding Figure 3C Sparse bipartite graph of sparse parity check matrix.

[0011] Figure 4 is a block diagram depicting one embodiment of a sensing block.

[0012] Figure 5A is a block diagram of one embodiment of an integrated memory component.

[0013] Figure 5B is a block diagram of one embodiment of an integrated memory component in which a control die controls two memory dies.

[0014] Figure 6A and Figure 6B It is a top view of a semiconductor wafer.

[0015] Figure 7 An exemplary pattern of bond pads on a planar surface of a semiconductor die is depicted.

[0016] Figure 8A Depicted is a side view of one embodiment of an integrated memory component stacked on a substrate.

[0017] Figure 8B Depicted is a side view of one embodiment of an integrated memory component stacked on a substrate.

[0018] Figure 9 is a perspective view of a portion of one exemplary embodiment of a monolithic three dimensional memory array that may include a memory structure.

[0019] Figure 10A is a schematic diagram of one embodiment of an integrated memory component.

[0020] Figure 10B is a schematic diagram of one embodiment of an integrated memory component in which one control die controls two memory dies.

[0021] Figure 11is a flow chart describing one embodiment of a process for programming NAND strings of memory cells organized into an array.

[0022] Figure 12A Exemplary threshold voltage distributions are shown for a memory array when each memory cell stores three bits of data.

[0023] Figure 12B Depicted are the threshold voltage distributions when each memory cell stores four bits of data.

[0024] Figure 13 is a flow chart of one embodiment of a process of operating a non-volatile memory including an integrated memory component.

[0025] Figure 14 is a flow chart of one embodiment of a process of operating a non-volatile memory including an integrated memory component.

[0026] Figure 15 is a flow chart of one embodiment of a process of operating a non-volatile memory including an integrated memory component.

[0027] Figure 16 is a flow chart of one embodiment of a process for determining a dynamic read reference voltage for a memory cell in an integrated memory component.

[0028] Figure 17 is a flow chart of one embodiment of a first stage of a bit error rate estimation scan to determine a new read reference voltage.

[0029] Figure 18 It is used to determine the new reference voltage. Figure 17 Flowchart of one embodiment of the second stage of the bit error rate estimation scan. DETAILED DESCRIPTION

[0030] The present technology will now be described with reference to the accompanying drawings, which, in an embodiment, relate to calibrating a read reference voltage for reading a non-volatile memory cell in a memory system. In one embodiment, the memory system includes an integrated memory component having a control die and a memory die. In some embodiments, the control die and the memory die are bonded together using, for example, bonding pads. The memory die may include non-volatile memory cells. The control die may control various operations on the memory die, such as reading, writing, and erasing. The control die may apply a read reference voltage to the memory cell in order to read data stored in the memory cell. In one embodiment, the control die calibrates the read reference voltage for reading the non-volatile memory cell. In one embodiment, data and / or control signals are transmitted through the bonding pads.

[0031] In one embodiment, a memory system includes a memory controller that communicates with an integrated memory component. Some embodiments include a hierarchical approach for calibrating a read reference voltage. For example, first, a control die may attempt to determine a new value for the read reference voltage. If the new read reference voltage is satisfactory, the control die may use the new read reference voltage. The control die may use one or more different techniques to determine the new read reference voltage. If the new read reference voltage determined by the control die is not satisfactory, the memory controller may calibrate the read reference voltage. Whether the read reference voltage is satisfactory may be based on an error metric for the codeword. Examples of error metrics include, but are not limited to, a codeword's companion weight and a codeword's bit error rate.

[0032] By having the control die determine the new read reference voltage (in many cases), the memory controller is greatly relieved of the burden of such tasks. In addition, the communication channel between the control die and the memory controller is not burdened with transmitting large amounts of data from the memory controller to determine the new read reference voltage. In some embodiments, the technology used by the memory controller may consume more time and / or power than the technology used by the control die. In other words, the technology used by the control die may consume less time and / or power than the technology used by the memory controller. In some embodiments, the memory controller has more processing power than the control die and is therefore more suitable for implementing more complex technologies to perform a more comprehensive search for the new read reference voltage. The layered approach allows, for example, the use of simpler technologies on the control die and the use of more complex technologies on the memory controller.

[0033] In some embodiments, the control die and the memory die are bonded together using a number of bonding pads that allow communication between the control die and the memory die. In one embodiment, the control die is able to access data from the memory die via the bonding pads. In one embodiment, each data bit and each parity bit of a codeword is read via a different bonding pad. This effectively provides an interface that is much wider than the data bus between the integrated memory component and the memory controller. Therefore, the transfer of codewords from the memory die to the control die is very efficient. The net effect is that determining a new read reference voltage on the control die can use communication bandwidth more efficiently than determining a new read reference voltage on the memory controller.

[0034] In some embodiments, the control die and memory die are fabricated on different semiconductor wafers, allowing different semiconductor manufacturing processes to be used on the different wafers. For example, the semiconductor manufacturing process may involve high-temperature annealing. Such high-temperature annealing may be required to properly form some circuit elements, but this may damage other circuit elements. Due to the limitations of semiconductor manufacturing processes, forming complex circuits such as decoders on the memory die can be challenging. In addition, the manufacturing process used to form memory cells on the memory die may impose constraints on the size of the transistors formed on the memory die. In some embodiments, the control circuit on the control die has transistors that are different (e.g., smaller) than the memory cell transistors on the memory die. The different (e.g., smaller) sizes of the transistors on the control die can improve the performance of the control circuit on the control die. For example, smaller transistors can use less power than larger transistors. In addition, using smaller transistors allows one embodiment of the control die to have more transistors on the control die for the control circuit. As a result, the control die can be better suited to perform operations such as determining a new read reference level than the memory die.

[0035] It should be understood that the present invention can be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that this disclosure will be thorough and complete, and the present invention will be fully conveyed to those skilled in the art. In fact, the present invention is intended to cover alternatives, modifications, and equivalents of these embodiments, which are all included within the scope and spirit of the present invention as defined by the appended claims. In addition, in the following specific embodiments of the present invention, many specific details are provided to provide a thorough understanding of the present invention. However, it will be apparent to those skilled in the art that the present invention can be implemented without such specific details.

[0036] As used herein, the terms "top" and "bottom," "upper" and "lower," and "vertical" and "horizontal," and variations thereof, such as may be used herein by way of example and for illustrative purposes only, are not intended to limit the description of the technology, as the referenced items may be interchanged in position and orientation. Additionally, as used herein, the terms "substantially" and / or "approximately" mean that a specified dimension or parameter may vary within acceptable manufacturing tolerances for a given application.

[0037] Figures 1A to 3B One example of a memory system that can be used to implement the techniques disclosed herein is described.

[0038] Figure 1A1 is a block diagram of one embodiment of a memory system 100 connected to a host 120. Memory system 100 can implement the techniques disclosed herein. Many different types of memory systems can be used with the techniques disclosed herein. One exemplary memory system is a solid-state drive ("SSD"); however, other types of memory systems can also be used. Memory system 100 includes a memory controller 102, integrated memory components 104 for storing data, and local memory (e.g., DRAM / ReRAM) 106. Memory controller 102 includes a front-end processor circuit (FEP) 110 and one or more back-end processor circuits (BEP) 112. In one embodiment, the FEP 110 circuit is implemented on an ASIC. In one embodiment, each BEP circuit 112 is implemented on a separate ASIC. The ASICs for each of the BEP circuits 112 and the FEP circuits 110 are implemented on the same semiconductor, allowing memory controller 102 to be manufactured as a system-on-chip ("SoC"). Each FEP 110 and BEP 112 includes its own processor. In one embodiment, FEP 110 and BEP 112 operate in a master-slave configuration, with FEP 110 serving as the master and each BEP 112 serving as a slave. For example, FEP circuitry 110 implements a flash translation layer, which performs memory management (e.g., garbage collection, wear leveling, etc.), logical-to-physical address translation, communication with the host, DRAM (local volatile memory) management, and overall operation of the SSD (or other non-volatile storage system). BEP circuitry 112 manages memory operations within the integrated memory component / die based on requests from FEP circuitry 110. In some embodiments, the integrated memory component is referred to as a memory package. For example, BEP circuitry 112 may perform read, erase, and program processes. Additionally, BEP circuitry 112 may perform buffer management, set specific voltage levels required by FEP circuitry 110, perform error correction (ECC), control the switch-mode interface to the memory package, and more. In one embodiment, each BEP circuitry 112 is responsible for its own set of memory packages. Memory controller 102 is an example of a control circuit. The term "device" may be used herein to refer to any of the integrated memory component 104, the memory system 100, the memory controller 102, or a combination of the memory system 100 and the host 120, but is not limited thereto.

[0039] In one embodiment, there are multiple integrated memory components 104. In one embodiment, each integrated memory component 104 includes one or more memory dies and one or more control dies. Each memory die includes one or more memory structures. The control die controls operations on the memory die. For example, the control die can control read, write, and erase operations on the memory die. In one embodiment, the memory controller 102 communicates with the control die to instruct the control die to perform read, write, or erase operations on one or more non-volatile memory dies or one or more memory structures. In one embodiment, each memory die in the integrated memory component 104 utilizes NAND flash memory (including two-dimensional NAND flash memory and / or three-dimensional NAND flash memory). In other embodiments, the integrated memory component 104 may include other types of memory; for example, the memory package may include PCM memory.

[0040] Memory controller 102 communicates with host 120 via interface 130, which implements NVM Express (NVMe) over PCI Express (PCIe). To operate with memory system 100, host 120 includes a host processor 122, host memory 124, and PCIe interface 126 that communicate over bus 128. Host memory 124 is the host's physical memory and can be DRAM, SRAM, non-volatile memory, or another type of storage device. Host 120 is external to and separate from memory system 100. In one embodiment, memory system 100 is embedded in host 120.

[0041] Figure 1B is a block diagram of one embodiment of the FEP circuit 110 . Figure 1BA PCIe interface 150 is shown, communicating with a host 120, along with a host processor 152 in communication with the PCIe interface. Host processor 152 can be any type of processor known in the art and suitable for implementation. Host processor 152 communicates with a network-on-chip (NOC) 154. A NOC is a communication subsystem on an integrated circuit, typically between cores in a SoC. A NOC can span synchronous and asynchronous clock domains, or utilize unclocked asynchronous logic. NOC technology applies network theory and methods to on-chip communication, offering significant improvements over conventional bus and crossbar interconnects. Compared to other designs, NOCs improve the scalability of SoCs and the power efficiency of complex SoCs. The wires and links in a NOC are shared by many signals. Because all links in a NOC can operate simultaneously on different data packets, a high degree of parallelism is achieved. Therefore, as the complexity of integrated subsystems continues to increase, NOCs offer enhanced performance (such as throughput) and scalability compared to previous communication architectures (e.g., dedicated point-to-point signal lines, shared buses, or segmented buses with bridges). Connected to and in communication with the NOC 154 are a memory processor 156, SRAM 160, and a DRAM controller 162. The DRAM controller 162 is used to operate and communicate with DRAM (e.g., DRAM 106). The SRAM 160 is local RAM memory used by the memory processor 156. The memory processor 156 is used to run the FEP circuitry and perform various memory operations. Also in communication with the NOC are two PCIe interfaces 164 and 166. Figure 1B In the embodiment of FIG, memory controller 102 includes two BEP circuits 112; therefore, there are two PCIe interfaces 164 / 166. Each PCIe interface communicates with one of the BEP circuits 112. In other embodiments, there may be more or fewer than two BEP circuits 112; therefore, there may be more than two PCIe interfaces.

[0042] Figure 2 is a block diagram of one embodiment of the BEP circuit 112 . Figure 2 A method for communicating with the FEP circuit 110 (e.g., Figure 1B2 and 3. The PCIe interface 200 communicates with one of the PCIe interfaces 164 and 166 of the processor. The PCIe interface 200 communicates with two NOCs 202 and 204. In one embodiment, the two NOCs can be combined into a large NOC. Each NOC (202 / 204) is connected to the SRAM (230 / 260), buffer (232 / 262), processor (220 / 250) and data path controller (222 / 252) via an XOR engine (224 / 254), an ECC engine (226 / 256) and a read reference voltage calibration engine (225 / 255). The ECC engine 226 / 256 is used to perform error correction, as known in the art. In this article, the ECC engine 226 / 256 may be referred to as a controller ECC engine. The XOR engine 224 / 254 is used to perform XOR on data so that data can be combined and stored in a recoverable manner when there is a programming error. The read reference voltage calibration engine (225 / 255) is used to determine a new read reference voltage. The read reference voltage calibration engine (225 / 255) can use the ECC engine (226 / 256) to calibrate the read reference voltage.

[0043] The data path controller 222 is connected to the memory interface 228 for communicating with the integrated memory assembly via four channels. Therefore, the top NOC 202 is associated with the memory interface 228 for the four channels for communicating with the integrated memory assembly, and the bottom NOC 204 is associated with the memory interface 258 for the four additional channels for communicating with the integrated memory assembly. In one embodiment, each memory interface 228 / 258 includes four switch mode interfaces (TM interfaces), four buffers, and four schedulers. There is a scheduler, buffer, and TM interface for each of the channels. The processor can be any standard processor known in the art. The data path controller 222 / 252 can be a processor, FPGA, microprocessor, or other type of controller. The XOR engine 224 / 254, ECC engine 226 / 256, and read reference voltage calibration engine (225 / 255) are dedicated hardware circuits referred to as hardware accelerators. In other embodiments, the XOR engine 224 / 254, ECC engine 226 / 256, and read reference voltage calibration engine (225 / 255) can be implemented in software. The scheduler, buffer and TM interface are hardware circuits. In other embodiments, the memory interface (circuitry for communicating with the memory die) can be a Figure 2 In addition, there is a different structure than the one depicted. Figure 1B and Figure 2 Controllers of different configurations may also be used with the techniques described herein.

[0044] Figure 3Ais a functional block diagram of one embodiment of an integrated memory component 104. In one embodiment, the integrated memory component 104 includes two types of semiconductor dies (or, more simply, "dies"). Memory die 302 includes memory structure 326. Memory structure 326 may include non-volatile memory cells. Control die 304 includes control circuitry 310. As described in detail below, in some embodiments, memory die 302 and control die 304 are bonded together. Typically, there are multiple control dies 304 and multiple memory dies 302 in the integrated memory component 104.

[0045] Control circuitry 310 performs memory operations (e.g., write, read, erase, etc.) on memory structure 326. Control circuitry 310 includes a state machine 312, an on-chip address decoder 314, power control circuitry 316, a memory area 318, read / write circuitry 328, and an ECC engine 330. In another embodiment, a portion of read / write circuitry 328 is located on control die 304, and a portion of read / write circuitry 328 is located on memory die 302. For example, read / write circuitry 328 may include sense amplifiers. In one embodiment, the sense amplifiers are located on control die 304. In one embodiment, the sense amplifiers are located on memory die 302.

[0046] As used herein, the terms "memory die," "memory semiconductor die," and the like refer to semiconductor dies that contain nonvolatile memory cells for storage. As used herein, the terms "control die," "control semiconductor die," and the like refer to semiconductor dies that contain control circuitry for performing memory operations on the nonvolatile memory cells on the memory die. Typically, many semiconductor dies are formed from a single semiconductor (e.g., silicon) wafer.

[0047] The on-chip address decoder 314 compares the address used by the host 120 or the memory controller 102 with the row decoder and column decoder ( Figure 3A The power control circuit 316 provides an address interface between the hardware addresses used by the memory (not explicitly shown). The power control circuit 316 controls the power and voltage provided to the word lines, bit lines, and select lines during memory operations. In one embodiment, the power control circuit 316 includes voltage circuits. The power control circuit 316 may include a charge pump for generating voltages. In one embodiment, the power control circuit 316 executes under the control of the state machine 312.

[0048] In some embodiments, the read / write circuitry 328 includes a sense block (which may include a sense amplifier (SA)). In some embodiments, the sense amplifier includes a bit line driver. In one embodiment, the read / write circuitry 328 executes under the control of the state machine 312. In some embodiments, each memory structure 326 is capable of being read and written to a memory structure via a row decoder ( Figure 3A not shown) by word lines and via column decoders ( Figure 3A The CMOS (not shown) is addressed by bit lines.

[0049] The error correction code (ECC) engine 330 is configured to decode error correction codewords. Herein, the ECC engine 330 may be referred to as an on-die ECC engine. In one embodiment, the on-die ECC engine 330 is configured to encode data bits from the memory controller 102 into codewords comprising data bits and parity bits. The control circuit stores the codewords in the memory structure 326. In one embodiment, the on-die ECC engine 330 is configured to decode the codewords read back from the memory structure 326. In some embodiments, if the on-die ECC engine 330 successfully decodes the codeword, the control die 304 only sends the data bits back to the memory controller 102. In some embodiments, if the on-die ECC engine 330 does not successfully decode the codeword, the controller ECC engine 226 / 256 may be used to decode the codeword. In some embodiments, the on-die ECC engine 330 is configured to calculate a new read reference voltage for reading memory cells in the memory structure 326.

[0050] Any subset of the components in the control circuit 310 may be considered one or more control circuits. The state machine 312, on-die ECC engine 330, read / write circuits 328, and / or memory controller 102 (or equivalent functional circuitry) are Figure 3A A combination of all or a subset of the other circuits depicted in the drawings may be considered one or more control circuits. The one or more control circuits may include only hardware or a combination of hardware and software (including firmware). For example, a controller programmed by firmware is an example of a control circuit. The one or more control circuits may include a processor, a PGA (programmable gate array), an FPGA (field programmable gate array), an ASIC (application-specific integrated circuit), an integrated circuit, or other types of circuits.

[0051] Paths 352 are pathways between one or more components in control circuitry 310 and memory structures on memory die 302. A portion of each pathway resides in memory die 302, and a portion of each pathway resides in control die 304. The term "path" may be used for the portion of pathway 352 that is entirely within one of the dies. Thus, memory die 302 can be said to have a first plurality of pathways and control die 304 can be said to have a second plurality of pathways. In one embodiment, control die 304 and memory die 302 are configured to transmit signals through pathway pairs of the first plurality of pathways and the second plurality of pathways. In some embodiments, memory die 302 and control die 304 are bonded to one another or otherwise attached to one another to facilitate transmission of signals through the pathway pairs.

[0052] Paths can be used to provide or receive signals (e.g., voltage, current). Paths include conductive paths. Paths may include, but are not limited to, one or more of bonding pads, metal interconnects, vias, transistors, conductive materials, and other materials that can transmit or carry electrical signals. In one embodiment, pathways 352 allow control circuitry 310 to provide voltages to word lines, select lines, and bit lines on memory die 302. Paths 352 can be used to receive signals from, for example, bit lines. In one embodiment, there are approximately 100,000 pathways 352. However, there may be more or less than 100,000 pathways. Having such a large number of pathways 352 allows very large amounts of data or other signals to be transmitted in parallel.

[0053] In one embodiment, the integrated memory component 104 includes a set of input and / or output (I / O) pins connected to a communication channel (also referred to herein as a data bus 332). For generality, the communication channel is depicted as being connected to the integrated memory component 104. The communication channel can be connected to either or both of the memory die 302 and / or the control die 304. In one embodiment, the communication channel directly connects the memory controller 102 to the control die 304. In one embodiment, the communication channel directly connects the memory controller 102 to the memory die 302. If the communication channel directly connects the memory controller to the memory die 302, then a path 352 can be used to allow communication between the memory controller 102 and the control circuit 310.

[0054] In one embodiment, memory structure 326 includes a three-dimensional memory array of non-volatile memory cells, wherein multiple memory levels are formed over a single substrate, such as a wafer. The memory structure can include any type of non-volatile memory monolithically formed in one or more physical layers of an array of memory cells, having active regions disposed over a silicon (or other type) substrate. In one example, the non-volatile memory cells include vertical NAND strings having charge-trapping material.

[0055] In another embodiment, the memory structure 326 includes a two-dimensional memory array of non-volatile memory cells. In one example, the non-volatile memory cells are NAND flash memory cells that utilize floating gates. Other types of memory cells (e.g., NOR-type flash memory) may also be used.

[0056] The exact type of memory array architecture or memory cells included in the memory structure 326 is not limited to the examples described above. Many different types of memory array architectures or memory technologies can be used to form the memory structure 326. No specific non-volatile memory technology is required to implement the claimed novel embodiments presented herein. Other examples of suitable technologies for the memory cells of the memory structure 326 include phase change memory (e.g., PCM), etc. Examples of suitable technologies for the memory cell architecture of the memory structure 326 include two-dimensional arrays, three-dimensional arrays, cross-point arrays, stacked two-dimensional arrays, vertical bit line arrays, etc.

[0057] Those skilled in the art will recognize that the technology described herein is not limited to a single particular memory structure, but encompasses many related memory structures within the spirit and scope of the technology as described herein and understood by those skilled in the art.

[0058] Although Figure 3A One control die 304 and one memory die 302 are depicted in the integrated memory component 104 , but there may be more than one control die 304 and more than one memory die 302 in the integrated memory component 104 .

[0059] Figure 3B FIG2 is a block diagram of one embodiment of the read / write circuit 328 and the ECC engine 330 of the control die 304. The read / write circuit 328 has a sense amplifier 350 and a latch 360. The latch 360 may include a data latch 360a and a parity latch 360b. In one embodiment, the data latch 360a stores the data bits of the codeword, and the parity latch stores the parity bits of the codeword. Specific latches for the data bits and the parity bits are not required. Figure 3B Four sets of data latches 360(1), 360(2), 360(3), 360(4) are depicted. Each set can be used to store a different page of codewords. In an embodiment where each memory cell stores four bits, four pages are stored in a set of memory cells. These four pages can be referred to as the lower page (LP), the lower middle page (LMP), the upper middle page (UMP), and the upper page (UP). In another embodiment, the sense amplifiers 350 are located on the memory die 302, but the latches 360 remain on the control die 304.

[0060] The on-die ECC engine 330 is capable of encoding the data bits received from the memory controller 102. In one embodiment, the on-die ECC engine 330 forms codewords, each codeword comprising data bits and parity bits. In one embodiment, the memory controller 102 provides the codewords to the control die 304. The control circuit 310 stores the codewords in non-volatile memory cells in the memory structure 326. Based on a request to read data from the memory controller 102, the control circuit 310 reads the codewords from the memory structure 326. The on-die ECC engine 330 is also capable of decoding and error correcting the codewords read from the memory structure 326. In some embodiments, the on-die ECC engine 330 calculates parity bits for each stored data unit (e.g., page). Parity bits (also known as error correction codes) can be stored together with the data unit (e.g., page). The combination of a data unit and its associated parity bits is called a codeword. In one embodiment, the parity bits are stored away from the data unit (e.g., page).

[0061] In one embodiment, upon successful decoding of a codeword, the control die 304 sends only the data bits, but not the parity bits, to the memory controller 102. Thus, bandwidth is conserved on the communication lines between the memory controller 102 and the integrated memory component 104. Additionally, significant power savings can be achieved. For example, the interface between the control die and the controller can be a high-speed interface.

[0062] The on-die ECC engine 330 includes companion calculation logic 370, an encoder 380, a decoder 390, and a read reference voltage calibration 385. The encoder 380 is configured to encode data using an ECC scheme, such as a Reed Solomon encoder, a Bose-Chaudhuri-Hocquenghem (BCH) encoder, a low-density parity check (LDPC) encoder, a turbo code encoder, an encoder configured to encode one or more other ECC encoding schemes, or any combination thereof. The encoder 380 may form a codeword comprising data bits 382 and parity bits 384. The data bits may be provided by the memory controller 102.

[0063] In one embodiment, data bits 382 are stored in data latches 360a, and parity bits 384 are stored in parity latches 360b. Based on the bits in latches 360, sense amplifiers 350 can control the bit line voltages in memory structure 326 when the nonvolatile memory cells are being programmed. In this way, a codeword can be programmed into the nonvolatile memory cells in memory structure 326. It should be understood that other voltages can also be applied to memory structure 326, such as a programming voltage applied to memory cells selected for programming.

[0064] Decoder 390 is configured to decode codewords stored in memory die 302. In one embodiment, sense amplifier 350 senses the bit lines in memory structure 326 to read the codeword. Sense amplifier 350 can store the read codeword in latch 360. Decoder 390 is capable of detecting and correcting errors in the codeword. In one embodiment, decoder 390 is a relatively low-power decoder compared to the decoder on memory controller 102. In one embodiment, the decoder on memory controller 102 is capable of correcting more bit errors in the codeword than can typically be corrected by decoder 390. Thus, decoder 390 can provide a trade-off between power consumption and error correction capability. For example, decoder 390 can be very efficient in terms of power consumption, but at the expense of potentially being unable to correct a large number of errors in the codeword.

[0065] In one embodiment, decoder 390 implements a hard bit decoder. In one embodiment, decoder 390 implements a soft bit decoder. Decoder 390 can implement both a hard bit decoder and a soft bit decoder. For example, control die 304 can first attempt to decode the codeword using a hard bit decoder. If that fails, control die 304 can then attempt to decode using a soft bit decoder.

[0066] In some embodiments, decoder 390 is based on a sparse bipartite graph having bit (or variable) nodes and check nodes. Decoder 390 can pass messages between the bit nodes and the check nodes. In some embodiments, the message passing between the bit nodes and the check nodes is achieved by performing message passing computations. The message passing computations can be based on belief propagation.

[0067] The syndrome calculation logic 370 can determine the syndrome weight of the codeword. The syndrome weight refers to the number of parity check equations that are not satisfied. Figure 3C and Figure 3D The parity check equation is discussed in more detail. The initial companion weight of a codeword may be associated with the bit error rate (BER) of the codeword. Therefore, the control die 304 can estimate the BER of the codeword based on the initial companion weight. In one embodiment, the companion logic is implemented in hardware. The companion weight can be determined when the codeword is not fully decoded. Therefore, the initial companion weight can be calculated in less time and less power than decoding the codeword. In some embodiments, the control die 304 makes management decisions based on the estimated BER. For example, the control die 304 can determine what technology should be used to decode the codeword, what read reference voltage should be used to read the memory cell, etc. based on the estimated BER.

[0068] Read reference voltage calibration 385 is configured to determine a new read reference voltage for reading memory cells in memory structure 326. Read reference voltage calibration 385 may use one or more different techniques to determine the new read reference voltage. In one embodiment, read reference voltage calibration 385 analyzes the threshold voltage distribution of the data stored in the memory cells in memory structure 326. For example, read reference voltage calibration 385 may perform a valley search to find the lowest point in the valley between two adjacent threshold voltage distributions. In another example, read reference voltage calibration 385 may determine whether the number of memory cells having a threshold voltage below a certain read reference voltage is greater or less than an expected value. Read reference voltage calibration 385 may then determine a new read reference voltage based on the analysis of the threshold voltage distribution.

[0069] In one embodiment, read reference voltage calibration 385 may use decoder 390 to help determine a new read reference voltage. In one embodiment, read reference voltage calibration 385 determines the new read reference voltage based on an error metric associated with data stored in a group of memory cells in memory structure 326. The error metric may be, for example, an accompanying weight of a codeword or an estimated bit error rate of a codeword.

[0070] Note that the technique of analyzing the threshold voltage distribution can avoid the use of decoder 390 and can therefore be faster and simpler than the technique of using decoder 390. However, analyzing the threshold voltage distribution to determine the new read reference voltage may not be as accurate as analyzing the error metric of the codeword. For example, if there is a significant temperature difference between programming the group of memory cells and reading the group of memory cells, the valley search may be somewhat inaccurate.

[0071] Some embodiments include a hierarchical approach for determining a new read reference voltage. For example, first, the control die 304 may attempt to determine a new read reference voltage using read reference voltage calibration 385. If the new read reference voltage is satisfactory, the control die 304 may use the new read reference voltage to read data from the memory structure 326. The control die 304 may use one or more different techniques to determine the new read reference voltage. In one embodiment, the control die 304 first uses a technique that analyzes threshold voltage distributions. If this first technique is unsuccessful, the control die 304 may use a technique that analyzes error metrics for codewords stored in the memory structure 326. If the new read reference voltage determined by the control die 304 is not satisfactory, the memory controller 102 may determine a new read reference voltage.

[0072] By having the control die 304 determine the new read level (in many cases), the memory controller 102 is largely relieved of the burden of such tasks. In some embodiments, the techniques used by the memory controller may consume more time and / or power than the techniques used by the control die. In some embodiments, the memory controller has more processing power than the control die and, therefore, may be better suited to perform a more comprehensive search for a new read reference voltage.

[0073] As described above, in some embodiments, the on-die ECC engine 330 uses a sparse parity-check matrix. Figure 3C An example of a sparse parity check matrix H (which can also be represented as a sparse bipartite graph) is depicted. The matrix includes M rows and K+M columns, which correspond to the K information bits and M parity check bits in each codeword of length N=K+M. In addition, the parity check bits are defined such that M parity check equations are satisfied, where each row of the matrix represents a parity check equation.

[0074] Figure 3D Depicts the corresponding Figure 3C A sparse bipartite graph 392 of a sparse parity check matrix of a code can be defined by a sparse bipartite graph G = (V, C, E) having a set V of N (in this example, N = 13) bit nodes 394, a set C of M (in this example, M = 10) check nodes 396, and a set E (in this example, E = 38) of edges 398 connecting the bit nodes 394 to the check nodes 396. The bit nodes correspond to codeword bits, and the check nodes correspond to the parity check constraints on the bits. The bit nodes 394 are connected to the check nodes 396 in which they participate by edges 398.

[0075] During decoding, one embodiment of decoder 390 attempts to satisfy parity checks. In this example, there are ten parity checks, as shown by check nodes cn1 through cn10. The first parity check at cn1 determines whether in represents an exclusive OR (XOR) logical operation. This check is satisfied if there is an even number of "1"s in the bit corresponding to the variable nodes v2, v4, v11, and v13. This check is represented by the fact that arrows from the variable nodes v2, v4, v11, and v13 are connected to the check node cn1 in the bipartite graph. The second parity check at cn2 determines whether The third parity check at cn3 determines whether The fourth parity check at cn4 determines whether The fifth parity check at cn5 determines whether The sixth parity check at cn6 determines whether The seventh parity check at cn7 determines whether The eighth parity check at cn8 determines whether The ninth parity check at cn9 determines whether And the tenth parity check at cn10 determines whether

[0076] In one embodiment, decoder 390 uses an iterative probabilistic decoding process involving iterative message passing decoding algorithms. These algorithms operate by exchanging messages between bit nodes and check nodes on the edges of the underlying bipartite graph representing the code.

[0077] Initial estimates of the codeword bits (based on what is read from the memory structure 326) can be provided to the decoder 390. These initial estimates can be refined and improved by imposing parity constraints that the bits should satisfy to be considered a valid codeword. This can be accomplished by exchanging information between bit nodes representing codeword bits and check nodes representing parity constraints on the codeword bits using messages passed along the edges of the graph.

[0078] Figure 4 is a block diagram depicting one embodiment of a sense block 450. The sense block is part of the read / write circuits 328. A single sense block 450 is divided into one or more core portions called sense circuits or sense amplifiers 350(1) to 350(4) and a common portion called management circuitry 480. In one embodiment, there will be a separate sense circuit for each bit line / NAND string and one common management circuit 480 for a group of multiple (e.g., four or eight) sense circuits. Each of the sense circuits in the group communicates with an associated management circuit via a data bus 454. Thus, there are one or more management circuits in communication with the sense circuits of a group of storage elements (memory cells).

[0079] As an example, sense amplifier 350(1) includes sensing circuitry 460 that performs sensing by determining whether the conduction current in a connected bit line is above or below a predetermined threshold level. Sensing can occur during a read or verify operation. The sensing circuitry also supplies the bit line voltage during application of a programming voltage in a programming operation.

[0080] The sensing circuit 460 may include a Vbl selector 462, a sense node 464, a comparison circuit 466, and a trip latch 468. During application of a programming voltage, the Vbl selector 462 may pass a program enable voltage (e.g., V_pgm_enable) or a program inhibit voltage (e.g., Vbl_inh) to a bit line connected to a memory cell. As used herein, a "program enable voltage" is defined as a voltage applied to a memory cell that enables programming of the memory cell, while a programming voltage (e.g., Vpgm) is also applied to the memory cell. In some embodiments, the program enable voltage is applied to a bit line coupled to a memory cell, while a programming voltage (e.g., Vpgm) is applied to the control gate of the memory cell. As used herein, a "program inhibit voltage" is defined as a voltage applied to a bit line coupled to a memory cell to inhibit programming of the memory cell, while a programming voltage (e.g., Vpgm) is also applied to the memory cell (e.g., applied to the control gate of the memory cell). Note that a boost voltage (e.g., Vpass) may be applied to unselected word lines along with the program inhibit voltage applied to the bit line.

[0081] A program inhibit voltage is applied to bit lines coupled to memory cells that are not to be programmed and / or to bit lines having memory cells that have reached their respective target threshold voltages through execution of the programming process. These bit lines may be referred to as "unselected bit lines." A program inhibit voltage is not applied to bit lines having memory cells to be programmed ("selected bit lines"). In one embodiment, when a program inhibit voltage is applied to an unselected bit line, the bit line is cut off from the NAND channel. Thus, in one embodiment, the program inhibit voltage is not passed to the NAND channel. A boost voltage is applied to unselected word lines to raise the potential of the NAND channel, which inhibits programming of memory cells that receive the program voltage at their control gates.

[0082] By setting the control gate voltage of the transistor high enough (e.g., higher than the Vbl passed from the Vbl selector), transistor 470 (e.g., nMOS) can be configured to pass the Vbl from Vbl selector 462 to the pass gate. For example, selector 472 can pass the power supply voltage Vdd (e.g., 3V to 4V) to the control gate of transistor 470.

[0083] The sense amplifier 350(1) is configured to control the timing of when voltage is applied to the bit line. During sensing operations such as read and verify operations, transistor 470 sets the bit line voltage based on the voltage passed by selector 472. The bit line voltage is roughly equal to the control gate voltage of the transistor minus its Vt (e.g., 3V). For example, if Vbl+Vt is passed by selector 472, the bit line voltage will be Vbl. This assumes that the source line is at 0V. Transistor 470 clamps the bit line voltage based on the control gate voltage and acts as a source follower rather than passing the gate. Vbl selector 462 can pass a relatively high voltage such as Vdd that is higher than the control gate voltage on transistor 470 to provide a source follower mode. During sensing, transistor 470 thus charges the bit line.

[0084] In one approach, the selector 472 of each sense amplifier can be controlled separately from the selectors of the other sense amplifiers to pass either Vbl or Vdd. The Vbl selector 462 of each sense amplifier can also be controlled separately from the Vbl selectors of the other sense amplifiers.

[0085] During sensing, the sense node 464 is charged to an initial voltage, such as Vsense_init=3V. The sense node is then connected to the bit line via transistor 470, and the amount of decay of the sense node is used to determine whether the memory cell is in a conductive state or a non-conductive state. In one embodiment, the current flowing in the bot line discharges the sense node (e.g., a sense capacitor). The length of time the sense node is allowed to decay may be referred to herein as the "accumulation time." A comparison circuit 466 is used to compare the sense node voltage with a trip voltage during sensing. If the sense node voltage decays below the trip voltage Vtrip, the memory cell is in a conductive state and its Vt is equal to or lower than the voltage of the verification signal. If the sense node voltage does not decay below Vtrip, the memory cell is in a non-conductive state and its Vt is higher than the voltage of the verification signal. The sense amplifier 350(1) includes a trip latch 468 that is set by the comparison circuit 466 based on whether the memory cell is in a conductive state or a non-conductive state. The data in the trip latch can be a bit read by the processor 482.

[0086] The management circuit 480 includes a processor 482, four exemplary sets of data latches 484, 485, 486, 487, and an I / O interface 488 coupled between the sets of data latches and the data bus 332 (the data bus may be connected to the memory controller 102). A set of data latches may be provided for each sense amplifier, for example including separate latches LDL, LMDL, UMDL, and UDL. In some cases, fewer or additional data latches may be used. The LDL stores bits for the lower page data, the LMDL stores bits for the middle lower page data, the UMDL stores bits for the middle upper page data, and the UDL stores bits for the upper page data. This is in a memory device with sixteen levels or four bits per memory cell. In one embodiment, there are eight levels or three bits per memory cell.

[0087] Processor 482 performs calculations such as determining the data stored in the sensed memory cells and storing the determined data in the set of data latches. Each set of data latches 484 to 487 is used to store data bits determined by processor 482 during a read operation and to store data bits imported from data bus 332 during a program operation, which represents write data to be programmed into the memory. I / O interface 488 provides an interface between data latches 484 to 487 and data bus 332.

[0088] Processor 482 may also be used to determine what voltage to apply to the bit line based on the state of the latch.

[0089] During reads, the system's operation is under the control of a state machine 312, which controls the application of different control gate voltages to the addressed memory cells. As it steps through the various predefined control gate voltages corresponding to the various memory states supported by the memory, the sense circuit can trip at one of these voltages, and the corresponding output will be provided from the sense circuit to the processor 482 via data bus 454. At this point, the processor 482 determines the resulting memory state by considering the trip event of the sense circuit and information about the control gate voltage applied via input line 490 from the state machine. It then calculates the binary encoding of the memory state and stores the resulting data bits in data latches 484 to 487.

[0090] Some specific implementations may include multiple processors 482. In one embodiment, each processor 482 will include an output line (not shown) so that each of the output lines is wired ORed together. In some embodiments, the output lines are inverted before being connected to the wired OR line. This configuration makes it possible to quickly determine when the programming process is complete during the program verification test because the state machine receiving the wired OR can determine when all programmed bits have reached the desired level. For example, when each bit reaches its desired level, the logic zero of that bit will be sent to the wired OR line (or data one is inverted). When all bits output data 0 (or data one is inverted), the state machine knows to terminate the programming process. Because each processor communicates with four sense amplifiers, the state machine needs to read the wired OR line four times, or logic is added to the processor 482 to accumulate the results of the associated bit lines so that the state machine only needs to read the wired OR line once. Similarly, by correctly selecting the logic levels, the global state machine can detect when the first bit changes its state and change the algorithm accordingly.

[0091] During a program or verify operation of a memory cell, the data to be programmed (write data) is stored from data bus 332 in the set of data latches 484 through 487, in the LDL, LMDL, UMDL and UDL latches in a four-bit per memory cell implementation.

[0092] Under the control of the state machine, the programming operation applies a set of programming voltage pulses to the control gates of the addressed memory cells. The amplitude of each voltage pulse can be gradually increased by one step from the previous programming pulse during the process, a process known as incremental step pulse programming. Each programming voltage is followed by a verification operation to determine whether the memory cell has been programmed to the desired memory state. In some cases, the processor 482 monitors the readback memory state relative to the desired memory state. When the two are consistent, the processor 482 sets the bit line to program inhibit mode, such as by updating its latch. This inhibits further programming of the memory cell coupled to the bit line, even if additional programming pulses are applied to its control gate.

[0093] Each set of data latches 484 to 487 can be implemented as a stack of data latches for each sense amplifier. In one embodiment, each sense amplifier 350 has three data latches. In some implementations, the data latches are implemented as shift registers so that parallel data stored therein is converted to serial data for the data bus 332, and vice versa. All data latches corresponding to a read / write block of memory cells can be connected together to form a block shift register, so that a block of data can be input or output via serial transmission. Specifically, the group of read / write circuit modules is arranged so that its data latch groups shift data into or out of the data bus in sequence, just as if they were part of a shift register for the entire read / write block.

[0094] The data latch identifies when the associated memory cell reaches certain milestones of the programming operation. For example, the latch can identify that the Vt of the memory cell is lower than a specific verification voltage. The data latch indicates whether the memory cell is currently storing one or more bits from a page of data. For example, the LDL latch can be used to store the lower page data. When the lower page bit is stored in the associated memory cell, the LDL latch is flipped (e.g., from 0 to 1). When the lower page bit, the upper page bit, or the upper page bit is stored in the associated memory cell, respectively, the LMDL, UMDL, or UDL latch is flipped. This occurs when the associated memory cell completes programming.

[0095] Figure 5A is a block diagram of one embodiment of the integrated memory component 104. Figure 5A Depicts Figure 1A or Figure 3A Further details of one embodiment of the integrated memory component 104 are provided. The memory die 302 includes a plane 520 of memory cells. The memory die 302 may have additional planes. The planes are divided into M blocks. In one example, each plane has about 1040 blocks. However, a different number of blocks may be used. In one embodiment, a block comprising memory cells is a unit of erase. That is, all memory cells of a block are erased together. In other embodiments, memory cells may be grouped into blocks for other reasons, such as to organize the memory structure 326 to enable signaling and selection circuits. A representative bit line (BL) is depicted for each plane. There may be thousands or tens of thousands of such bit lines per plane. As described more fully below, each block may be divided into a number of word lines. In one embodiment, a block represents a group of connected memory cells because the memory cells of the block share a common set of undisconnected word lines and undisconnected bit lines. Figure 5A In the structure of , block 0 and block M-1 of plane 520 are located at the edge of the memory structure (or referred to as being located in the edge region / portion of the memory structure).

[0096] In one embodiment, control die 304 includes several sense amplifiers (SAs) 350. In this example, each sense amplifier 350 is connected to a bit line. In one embodiment, the sense amplifier includes a bit line driver. Thus, the sense amplifier can provide a voltage to the bit line connected thereto. The sense amplifier is configured to sense the condition of the bit line. In one embodiment, the sense amplifier is configured to sense the current flowing in the bit line. In one embodiment, the sense amplifier is configured to sense the voltage on the bit line.

[0097] The control die 304 includes several word line drivers 560(1) to 560(n). The word line drivers 560 are configured to provide voltage to the word lines. In this example, there are "n" word lines per memory cell block. In one embodiment, one of the blocks in the plane 520 is selected for a memory array operation at a time. In one embodiment, if the memory operation is programming or reading, one word line within the selected block is selected for the memory operation. In one embodiment, if the memory operation is erasing, all word lines within the selected block are selected for erasing. The word line drivers 560 provide voltage to the word lines in the first selected block (e.g., block 2) in the memory die 302. The control die 304 may also include a charge pump, a voltage generator, etc., which may be used to provide voltage to the word line drivers 560 and / or the bit line drivers.

[0098] The memory die 302 has several bonding pads 570a, 570b on the first major surface 582 of the memory die 302. There can be "n" bonding pads 570a to receive voltages from corresponding "n" word line drivers 560(1) through 560(n). There can be one bonding pad 570b for each bit line associated with the plane 520. The reference numeral 570 will be used to generally refer to the bonding pads on the major surface 582.

[0099] In some embodiments, each data bit and each parity bit of a codeword is transmitted via a different pair of bonding pads 570b, 574b. The bits of the codeword can be transmitted in parallel via the bonding pad pairs 570b, 574b. This provides very efficient data transmission, for example, between the memory controller 102 and the integrated memory component 104. For example, the data bus between the memory controller 102 and the integrated memory component 104 can provide, for example, 8, 16, or possibly 32 bits to be transmitted in parallel. However, the data bus between the memory controller 102 and the integrated memory component 104 is not limited to these examples.

[0100] The control die 304 has a number of bonding pads 574a, 574b on the first major surface 584 of the control die 304. There can be "n" bonding pads 574a to deliver voltages from the corresponding "n" word line drivers 560(1) to 560(n) to the memory die 302a. There can be one bonding pad 574b for each bit line associated with the plane 520. The reference numeral 574 will be used to generally refer to the bonding pads on the major surface 582. Note that there can be bonding pad pairs 570a / 574a and bonding pad pairs 570b / 574b. In some embodiments, the bonding pads 570 and / or 574 are flip chip bonding pads.

[0101] In one embodiment, the pattern of the bonding pads 570 matches the pattern of the bonding pads 574. In one embodiment, the bonding pads 570 are bonded (e.g., flip chip bonded) to the bonding pads 574. Thus, the bonding pads 570, 574 electrically and physically couple the memory die 302 to the control die 304. In addition, the bonding pads 570, 574 allow for internal signal transmission between the memory die 302 and the control die 304. Thus, the memory die 302 and the control die 304 are bonded together. Although Figure 5A One control die 304 is depicted bonded to one memory die 302 , but in one embodiment, one control die 304 is bonded to two memory dies 302 .

[0102] As used herein, "internal signaling" refers to signaling between the control die 304 and the memory die 302. Internal signaling allows circuitry on the control die 304 to control memory operations in the memory die 302. Therefore, the bond pads 570, 574 can be used for memory operation signaling. As used herein, "memory operation signaling" refers to any signal related to memory operations in the memory die 302. Memory operation signaling can include, but is not limited to, providing voltage, providing current, receiving voltage, receiving current, sensing voltage, and / or sensing current.

[0103] The bonding pads 570, 574 can be formed of, for example, copper, aluminum, and alloys thereof. There can be a liner between the bonding pads 570, 574 and the main surface (582, 584). The liner can be formed of, for example, a titanium / titanium nitride stack. The bonding pads 570, 574 and the liner can be applied by vapor deposition and / or electroplating techniques. The bonding pad and liner together can have a thickness of 720 nm, but in other embodiments, the thickness can be greater or less.

[0104] Metal interconnects and / or vias may be used to electrically connect various components in the die to bonding pads 570, 574. Several conductive paths are described that may be implemented using metal interconnects and / or vias. For example, sense amplifier 350 may be electrically connected to bonding pad 574b via via 512. There may be thousands of such sense amplifiers, vias, and bonding pads. Note that the BL does not necessarily connect directly to bonding pad 570b. The word line driver 560 may be electrically connected to bonding pad 574a via via 502. Note that via 502 may include a separate conductive path for each word line driver 560(1) to 560(n). Likewise, there may be a separate bonding pad 574a for each word line driver 560(1) to 560(n). The word lines in block 2 of the memory die 302 may be electrically connected to bonding pad 570a via via 504. In Figure 5A, for the corresponding "n" word lines in a block, there are "n" vias 504. For each via 504, there may be a separate pair of bond pads 570a, 574a. Figure 10A Further details of one embodiment of an integrated memory component 104 with metal interconnects and / or vias are depicted.

[0105] Figure 5B Another embodiment of the integrated memory component 104 is depicted in which one control die 304 can be used to control two memory dies 302a, 302b. Figure 5A As described above, the control die 304 has a number of bonding pads 574(a), 574(b) on the first major surface 584. The control die 304 has a number of bonding pads 576(a), 576(b) on the second major surface 588. There can be "n" bonding pads 576(a) to deliver voltages from corresponding "n" word line drivers 560(1) to 560(n) to the memory die 302b. The word line drivers 560 can be electrically connected to the bonding pads 576a through the vias 506. There can be one bonding pad 576b for each bit line associated with the plane 530 on the memory die 302b. The reference numeral 576 will be used to generally refer to the bonding pads on the major surface 588.

[0106] The second memory die 302b has a number of bonding pads 572(a), 572(b) on the first major surface 586 of the second memory die 302b. There can be "n" bonding pads 572(a) to receive voltages from corresponding "n" word line drivers 560(1) to 560(n). The word lines in plane 530 can be electrically connected to bonding pads 572a via vias 508. There can be one bonding pad 572(b) for each bit line associated with plane 530. Reference numeral 572 will be used to generally refer to the bonding pads on major surface 586. Note that there can be bonding pad pairs 572(a) / 576(a) and bonding pad pairs 572(b) / 576(b). In some embodiments, bonding pads 572 and / or 576 are flip chip bonding pads.

[0107] In one embodiment, the "n" word line drivers 560(1) through 560(n) are shared between the two memory dies 302a, 302b. For example, a single word line driver can be used to provide voltage to a word line in memory die 302a and a word line in memory die 302b. However, it is not required that the word line drivers 560 be shared between the memory dies 302a, 302b.

[0108] Figure 6AFIG. 6 is a top view of a semiconductor wafer 635a from which a plurality of control dies 304 may be formed. Wafer 635a has many copies of integrated circuits 603. In one embodiment, each of the integrated circuits 603 includes a control circuit 310 (see FIG. 6 ). Figure 3A ). In some embodiments, wafer 635a is diced into semiconductor dies, each of which contains one of the copies of integrated circuit 603. Thus, many control semiconductor dies (control dies 304) can be formed from wafer 635a. Note also that even before wafer 635a is diced, each region where integrated circuit 603 resides can be referred to as a control semiconductor die, as the term "control semiconductor die" is used herein.

[0109] Figure 6B FIG. 6 is a top view of a semiconductor wafer 635b from which a plurality of memory dies 302 may be formed. Wafer 635b has many copies of integrated circuits 605. In one embodiment, each of the integrated circuits 605 includes a memory structure 326 (see FIG. 6 ). Figure 3A ). In some embodiments, wafer 635b is diced into semiconductor dies, each of which contains one of the copies of integrated circuit 605. Thus, many memory semiconductor dies (memory dies 302) can be formed from wafer 635b. Note also that even before wafer 635b is diced, each region where integrated circuit 605 is located can be referred to as a memory semiconductor die, as the term "memory semiconductor die" is used herein.

[0110] The semiconductor wafer 635 can start from an ingot of single crystal silicon grown by CZ, FZ or other processes. The semiconductor wafer 635 can be cut and polished on the main surface to provide a smooth surface. The integrated circuits 603, 605 can be formed on and / or in the main surface. Cutting the wafer 635 into semiconductor dies can be performed before or after bonding. In one embodiment, the two wafers 635, 635b are bonded together. After the two wafers are bonded together, cutting is performed. Thus, many integrated memory components 104 can be formed from the two wafers 635. In another embodiment, the two wafers 635a, 635b are cut into semiconductor dies (control die 304, memory die 302). Each of the semiconductor dies is then bonded together to form an integrated memory component 104. Regardless of whether cutting occurs before or after bonding, it can be said that the integrated memory component 104 includes a control semiconductor die and a memory semiconductor die bonded together.

[0111] Cutting the wafer 635 into semiconductor dies can be performed before or after bonding. In one embodiment, the two wafers 635, 635b are bonded together. After the two wafers are bonded together, cutting is performed. Thus, many integrated memory components 104 can be formed from the two wafers 635. In another embodiment, the two wafers 635a, 635b are cut into semiconductor dies (control die 304, memory die 302). Each of the semiconductor dies is then bonded together to form an integrated memory component 104. Regardless of whether cutting occurs before or after bonding, it can be said that the integrated memory component 104 includes a control semiconductor die and a memory semiconductor die bonded together.

[0112] As briefly discussed above, the control die 304 and the memory die 302 can be bonded together. Bond pads on each die can be used to bond the two dies together. Recall that FIG5 depicts an example of a bonding pad 570 on the memory die 302 and a bonding pad 574 on the control die 304. Figure 7 An exemplary pattern of bonding pads on the planar surface of a semiconductor die is depicted. The semiconductor die may be a memory die 302 or a control die 304. The bonding pads may be any of the bonding pads 570 or 574 that are suitable for the semiconductor die. Figure 7 More bonding pads are depicted. As an example, 100,000 or more interconnects may be required between two semiconductor dies. To support such a large number of electrical interconnects, the bonding pads can have a small area and pitch. In some embodiments, the bonding pads are flip-chip bonding pads.

[0113] The semiconductor dies (memory die 302, control die 304) in the integrated memory assembly 104 can be bonded to each other by initially aligning the bond pads 570, 574 on the respective dies with each other. Thereafter, the bond pads can be bonded together using any of a variety of bonding techniques, depending in part on the bond pad size and bond pad spacing (i.e., bond pad pitch). The size and pitch of the bond pads, in turn, can be determined by the number of electrical interconnects required between the first semiconductor die (memory die 302) and the second semiconductor die (control die 304).

[0114] In some embodiments, in a so-called Cu-Cu bonding process, the bonding pads are bonded directly to each other without solder or other additional materials. In the Cu-Cu bonding process, the bonding pads are controlled to be highly flat and are formed in a highly controlled environment that is substantially free of environmental particles that might otherwise deposit on the bonding pads and prevent tight bonding. Under such properly controlled conditions, the bonding pads are aligned and pressed against each other to form a mutual bond based on surface tension. This bond can be formed at room temperature, although heat can also be applied. In embodiments using Cu-Cu bonding, the bonding pads can be approximately 5 μm square and spaced apart from each other at a spacing of 5 μm to 5 μm. Although the process is referred to herein as Cu-Cu bonding, the term may also apply to situations where the bonding pads are formed of materials other than copper.

[0115] When the area of ​​the bonding pad is small, it may be difficult to bond the semiconductor dies together. By providing a film layer on the surface of the semiconductor die including the bonding pad, the size and spacing of the bonding pad can be further reduced. The film layer is disposed around the bonding pad. When the dies are put together, the bonding pads can be bonded to each other, and the film layers on the individual dies can be bonded to each other. This bonding technology can be referred to as hybrid bonding. In an embodiment using hybrid bonding, the bonding pads can be approximately 5 μm square and spaced apart from each other at a spacing of 1 μm to 5 μm. Bonding technology can be used to provide bonding pads with smaller size and spacing.

[0116] Some embodiments may include a film on the surface of the die (memory die 302, control die 304). If such a film is not initially provided, the space between the die can be filled at the bottom with epoxy or other resin or polymer. The bottom fill material can be applied as a liquid and then hardened into a solid layer. This bottom fill step protects the electrical connections between the die (memory die 302, control die 304) and further secures the die together. Various materials can be used as the bottom fill material, but in an embodiment, the bottom fill material can be Hysol epoxy resin from Henkel Corporation, which has offices in California, USA.

[0117] As described herein, there can be more than one control die 304 and more than one memory die 302 in the integrated memory component 104. In some embodiments, the integrated memory component 104 includes a stack of multiple control dies 304 and multiple memory dies 302. Figure 8AA side view of one embodiment of an integrated memory component 104 stacked on a substrate 802 is depicted. The integrated memory component 104 has three control die 304 and three memory die 302. Each control die 304 is bonded to one of the memory die 302. Some of the bonding pads 570, 574 are depicted. There may be more bonding pads. The space between the bonded die (memory die 302, control die 304) is filled with a solid layer 848, which can be formed of an epoxy or other resin or polymer. The solid layer 848 protects the electrical connections between the die (memory die 302, control die 304) and further secures the die together. Various materials can be used as the solid layer 848, but in an embodiment, the solid layer can be a Hysol epoxy resin from Henkel Corporation, which has offices in California, USA.

[0118] The integrated memory components 104 may be stacked, for example, in a stepped offset fashion, such that the bonding pads 804 at each level are uncovered and accessible from above. Wire bonds 806 connected to the bonding pads 804 connect the control die 304 to the substrate 802. Several such wire bonds may be formed across the width of each control die 304 (i.e., formed to the width of the die). Figure 8A page).

[0119] Memory die through silicon vias (TSVs) 812 may be used to route signals through the control die 304. Control die through silicon vias (TSVs) 814 may be used to route signals through the memory die 302. TSVs 812, 814 may be formed before, during, or after the formation of the integrated circuits in the semiconductor die (memory die 302, control die 304). The TSVs may be formed by etching holes through the wafer. These holes may then be lined with a barrier to prevent metal diffusion. The barrier layer may in turn be lined with a seed layer, and the seed layer may be plated with an electrical conductor such as copper, although other suitable materials such as aluminum, tin, nickel, gold, doped polysilicon, and alloys or combinations thereof may be used.

[0120] Solder balls 808 may optionally be attached to contact pads 810 on the lower surface of substrate 802. Solder balls 808 may be used to electrically and mechanically couple integrated memory assembly 104 to a host device, such as a printed circuit board. Solder balls 808 may be omitted if integrated memory assembly 104 is to be used as an LGA package. Solder balls 808 may form part of the interface between integrated memory assembly 104 and memory controller 102.

[0121] Figure 8BA side view of one embodiment of an integrated memory assembly 104 stacked on a substrate 802 is depicted. The integrated memory assembly 104 has three control dies 304 and three memory dies 302. In this example, each control die 304 is bonded to at least one memory die 302. Optionally, a control die 304 can be bonded to two memory dies 302. For example, two of the control dies 304 are bonded to a memory die 302 above the control die 304 and a memory die 302 below the control die 304.

[0122] Some of the bonding pads 570, 574 are depicted. There may be more bonding pads. The space between the die that are bonded together (memory die 302, control die 304) is filled with a solid layer 848, which may be formed of epoxy or other resins or polymers. Figure 8A Compared to the example in Figure 8B There is no stair-step offset for the integrated memory component 104 in FIG. Memory die through silicon vias (TSVs) 812 may be used to route signals through the memory die 302 . Control die through silicon vias (TSVs) 814 may be used to route signals through the control die 304 .

[0123] Solder balls 808 may optionally be attached to contact pads 810 on the lower surface of substrate 802. Solder balls 808 may be used to electrically and mechanically couple integrated memory assembly 104 to a host device, such as a printed circuit board. Solder balls 808 may be omitted if integrated memory assembly 104 is to be used as an LGA package.

[0124] Figure 9 is a perspective view of a portion of an exemplary embodiment of a monolithic three-dimensional memory array including a memory structure 326 that includes a plurality of nonvolatile memory cells. For example, Figure 9 A portion of a block comprising a memory is shown. The depicted structure includes a set of bit lines BL located above a stack of alternating dielectric and conductive layers, with vertical columns of material extending through the dielectric and conductive layers. For illustrative purposes, one of the dielectric layers is labeled D and one of the conductive layers (also referred to as a wordline layer) is labeled W. The number of alternating dielectric and conductive layers can vary based on specific implementation requirements. One set of embodiments includes 108 to 304 alternating dielectric and conductive layers. An example embodiment includes 96 data wordline layers, 8 select layers, 6 dummy wordline layers, and 110 dielectric layers. More or fewer than 108 to 304 layers may also be used. In one embodiment, the alternating dielectric and conductive layers are divided into four "fingers" or sub-blocks by local interconnects LI. Figure 9Two fingers and two local interconnects LI are shown. The source line layer SL is located below the alternating dielectric and word line layers. Vertical columns of material (also called memory holes) are formed in the stack of alternating dielectric and conductive layers. For example, one of the vertical columns / memory holes is labeled MH. Note that in Figure 9 In the diagram, the dielectric layers are depicted in perspective so that a reader can see the memory holes located in the stack of alternating dielectric and conductive layers. In one embodiment, a NAND string is formed by filling vertical columns / memory holes with a material including a charge-trapping material to create vertical columns of memory cells. Each memory cell can store one or more bits of data.

[0125] Figure 10A is a schematic diagram of one embodiment of the integrated memory component 104. Figure 10A In the depicted embodiment, the memory die 302 is bonded to the control die 304. This bond configuration is similar to Figure 5A Note that although gaps are depicted between adjacent pairs of dies, such gaps may be filled with epoxy or other resins or polymers. Figure 10A Additional details of one embodiment of passageway 352 are shown.

[0126] The memory die includes a memory structure 326. The memory structure 326 is adjacent to the substrate 1072 of the memory die 302. In some embodiments, the substrate 1072 is formed from a portion of a silicon wafer. In this example, the memory structure 326 includes a three-dimensional memory array. The memory structure 326 has Figure 9 There are many word line layers (WL) separated by dielectric layers. The dielectric layers are represented by the gaps between the word line layers. Thus, the word line layers and dielectric layers form a stack. There can be more than Figure 10A More wordline layers are depicted. Figure 9 As in the example of FIG. 1 , there are several columns extending through the stack. In each stack, a column 1002 is designated by reference numeral 1002. The columns contain memory cells. For example, each column can contain a NAND string. Adjacent stacks have a number of bit lines (BLs).

[0127] The word line driver 560 concurrently provides voltage to the word line 1042 in the memory die 302. The path from the word line driver 560 to the word line 1042 includes a conductive path 1032, a bonding pad 574a, a bonding pad 570a, and a conductive path 1034. In some embodiments, the conductive paths 1032, 1034 are referred to as a path pair. The conductive paths 1032, 1034 can each include one or more through-holes (which can extend vertically relative to the main surface of the die) and one or more metal interconnects (which can extend horizontally relative to the main surface of the die). The conductive paths 1032, 1034 can include transistors or other circuit elements. In one embodiment, the transistor can actually be used to open or close the path. Other word line drivers ( Figure 10A (not shown) provides voltage to other word lines. Therefore, in addition to the bonding pads 574a, 570a, there are further bonding pads 574a, 570a. As is known in the art, the bonding pads can be formed of, for example, copper, aluminum, and alloys thereof.

[0128] Sense amplifier 350 communicates with the bit lines in memory die 302. The path from sense amplifier 350 to the bit line includes conductive path 1052, bonding pad 574b, bonding pad 570b, and conductive path 1054. In some embodiments, conductive paths 1052, 1054 are referred to as a path pair. Conductive paths 1052, 1054 may include one or more through-holes (which may extend vertically relative to the main surface of the die) and one or more metal interconnects (which may extend horizontally relative to the main surface of the die). The metal interconnects may be formed of various conductive metals, including, for example, copper and copper alloys known in the art, and the through-holes may be lined with and / or filled with various conductive metals, including, for example, tungsten, copper, and copper alloys known in the art. Conductive paths 1052, 1054 may include transistors or other circuit elements. In one embodiment, the transistors may actually be used to open or close the paths.

[0129] The control die 304 has a substrate 1076, which may be formed from a silicon wafer. The sense amplifier 350, word line driver 560, and other circuits 1020 may be formed on and / or in the substrate 1076. The circuits 1020 may include some or all of the control circuits 310 (see FIG. Figure 3A In some embodiments, the sense amplifier 350, word line driver 560, and / or other circuitry 1020 comprises CMOS circuitry.

[0130] There are external signal paths that allow circuitry on the control die 304 to communicate with entities external to the integrated memory component 104, such as the memory controller 102. Thus, the circuitry 1020 on the control die 304 can communicate with, for example, the memory controller 102 (see Figure 3AOptionally, circuitry on control die 304 can communicate with, for example, host 120. External pathways include through-via 1058 in control die 304, bonding pad 574c, bonding pad 570c, through-silicon via (TSV) 1060, and external pad 1078. TSV 1060 extends through substrate 1072.

[0131] The TSVs 1060 can be formed before, during, or after the formation of the integrated circuits in the semiconductor die (memory die 302, control die 304). The TSVs can be formed by etching holes through the wafer. For example, holes can be etched through the substrate 1072. Holes can also be etched through the material of the adjacent wafer. These holes can then be lined with a barrier to prevent metal diffusion. The barrier layer can in turn be lined with a seed layer, and the seed layer can be plated with an electrical conductor such as copper, although other suitable materials such as aluminum, tin, nickel, gold, doped polysilicon, and alloys or combinations thereof can be used.

[0132] right Figure 10A Many modifications of the depicted embodiment are possible. One modification is to have the sense amplifier 350 located on the memory die 302 .

[0133] Figure 10B is a schematic diagram of one embodiment of the integrated memory component 104. This joint configuration is similar to Figure 5B The depicted embodiment. Figure 10B The configuration in Figure 10A The configuration in FIG adds an additional memory die. Therefore, similar reference numerals are used for Figure 10B Memory die 302a in, such as for Figure 10A Like the memory die 302 in FIG. Figure 10B In the depicted embodiment, a first memory die 302a is bonded to a control die 304, and the control die 304 is bonded to a second memory die 302b. Note that although gaps are depicted between adjacent pairs of dies, such gaps may be filled with epoxy or other resins or polymers.

[0134] Each memory die 302a, 302b includes a memory structure 326. Memory structure 326a is adjacent to substrate 1072 of memory die 302a. Memory structure 326b is adjacent to substrate 1074 of memory die 302b. In some embodiments, substrates 1072, 1074 are formed from a portion of a silicon wafer. In this example, memory structures 326 each include a three-dimensional memory array.

[0135] The word line driver 560 concurrently provides voltage to the first word line 1042 in the memory die 302a and the second word line 1044 in the memory die 302b. The path from the word line driver 560 to the second word line 1044 includes the conductive path 1032, the through silicon via (TSV) 1068, the bonding pad 576a, the bonding pad 572a and the conductive path 1036. Figure 10B (not shown) provides voltage to other word lines.

[0136] Sense amplifier 350a communicates with a bit line in memory die 302a. The path from sense amplifier 350a to the bit line includes conductive path 1052, bond pad 574b, bond pad 570b, and conductive path 1054. Sense amplifier 350b communicates with a bit line in memory die 302b. The path from sense amplifier 350b to the bit line includes conductive path 1054, TSV 1056, bond pad 576b, bond pad 572b, and conductive path 1048.

[0137] right Figure 10B Many modifications of the depicted embodiment are possible. One modification is to have the sense amplifier 350a located on the first memory die 302a and the sense amplifier 350b located on the second memory die 302b.

[0138] Figure 11 is a flow chart describing one embodiment of a process 1100 for programming a NAND string of memory cells organized into an array. In one exemplary embodiment, the integrated memory component 104 is executed using the control circuit 310 discussed above. Figure 11 For example, Figure 11 The process 1100 may be executed at the direction of the state machine 312. In one embodiment, the process 1100 is used to program a codeword into the memory structure 326.

[0139] In many implementations, the amplitude of the programming pulses increases by a predetermined step size with each successive pulse. Figure 11 In step 1102, the programming voltage (Vpgm) is initialized to a starting amplitude (eg, approximately 12V to 16V, or another suitable level), and the program counter PC maintained by the state machine 312 is initialized to 1.

[0140] In one embodiment, a group of memory cells selected for programming (referred to herein as selected memory cells) are programmed simultaneously and are all connected to the same word line (the selected word line). There may be other memory cells that are not selected for programming (unselected memory cells) that are also connected to the selected word line. That is, the selected word line will also be connected to the memory cells that should be prohibited from programming. In addition, when the memory cells reach their intended target data state, they will be prohibited from further programming. These NAND strings (e.g., unselected NAND strings) have their channels boosted to prohibit programming, and these strings include memory cells that are connected to the selected word line to be prohibited from programming. When the channel has an increased voltage, the voltage difference between the channel and the word line is not enough to cause programming. To assist with the boosting, in step 1104, the memory system precharges the channels of the NAND strings that include the memory cells connected to the selected word line that will be prohibited from programming.

[0141] In step 1106, the NAND strings including memory cells connected to the selected word line to be inhibited from programming have their channels boosted to inhibit programming. Such NAND strings are referred to herein as "unselected NAND strings." In one embodiment, the unselected word lines receive one or more boost voltages (e.g., approximately 7 to 11 volts) to implement the boosting scheme. A program inhibit voltage is applied to the bit lines coupled to the unselected NAND strings.

[0142] In step 1108, a program pulse of the program signal Vpgm is applied to the selected word line (the word line selected for programming). In one embodiment, if the memory cells on the NAND string should be programmed, the corresponding bit lines are biased at a program enable voltage. Such NAND strings are referred to herein as "selected NAND strings."

[0143] In step 1108, programming pulses are concurrently applied to all memory cells connected to the selected word line so that all memory cells connected to the selected word line are programmed in parallel (unless they are program inhibited). That is, they are programmed at the same time or during overlapping times (both of which are considered simultaneous). In this way, all memory cells connected to the selected word line will have their threshold voltages changed at the same time unless they are program inhibited.

[0144] In step 1110, memory cells that have reached their target state are locked out from further programming. Step 1110 may include performing verification at one or more verify reference levels. In one embodiment, the verification process is performed by testing whether the threshold voltage of the memory cells selected for programming has reached an appropriate verify reference voltage.

[0145] In step 1110, after the memory cell has been verified (passed a Vt test) that the memory cell has reached its target state, the memory cell may be locked out.

[0146] If, in step 1112, it is determined that all memory cells have reached their target threshold voltage (PASS), then the programming process is complete and successful because all selected memory cells have been programmed and verified to their target states. In step 1114, a "PASS" status is reported. Otherwise, if, in step 1112, it is determined that not all memory cells have reached their target threshold voltage (Fail), then the programming process will continue to step 1116.

[0147] In step 1116, the memory system counts the number of memory cells that have not yet reached their corresponding target threshold voltage distribution. That is, the system counts the number of memory cells that have not yet reached their target state. This counting can be performed by the state machine, the memory controller 102, or other logic components. In one embodiment, each sense block in the sense block will store the status (pass / fail) of its corresponding cell. In one embodiment, there is a total count that reflects the total number of memory cells currently being programmed that have failed the last verify step. In another embodiment, a separate count is maintained for each data state.

[0148] In step 1118, a determination is made as to whether the count from step 1116 is less than or equal to a predetermined limit. In one embodiment, the predetermined limit is the number of bits that can be corrected by an error correction code (ECC) during a read of the page of memory cells. If the number of failed cells is less than or equal to the predetermined limit, the programming process may be stopped and a "pass" status reported in step 1114. In this case, enough memory cells were correctly programmed so that the remaining few memory cells that were not fully programmed can be corrected using ECC during the read process. In some embodiments, the predetermined limit used in step 1118 is lower than the number of bits that can be corrected by an error correction code (ECC) during the read process to allow for future / additional errors. When programming fewer than all of the memory cells of a page, or comparing counts for only one data state (or fewer than all states), the predetermined limit may be a fraction (proportional or non-proportional) of the number of bits that can be corrected by ECC during a read of the page of memory cells. In some embodiments, this limit is not predetermined. Instead, it changes based on the number of errors that have been counted for the page, the number of program-erase cycles performed, or other criteria.

[0149] If the number of failed memory cells is not less than a predetermined limit, the programming process continues at step 1120 and the program counter PC is checked against the programming limit value (PL). Examples of programming limit values ​​include 6, 12, 16, 19, and 30; however, other values ​​may be used. If the program counter PC is not less than the programming limit value PL, the programming process is deemed to have failed and a "failed" status is reported in step 1124. If the program counter PC is less than the programming limit value PL, the process continues at step 1122, during which the program counter PC is incremented by 1 and the programming voltage Vpgm is stepped to the next amplitude. For example, the next pulse will have an amplitude that is one step larger (e.g., a step of 0.1 volts to 1.0 volts) than the previous pulse. After step 1122, the process loops back to step 1104 and another programming pulse is applied to the selected word line so that the program is executed. Figure 11 Another iteration of the programming process (steps 1104 to 1122).

[0150] At the end of a successful programming process, the threshold voltage of the memory cell should be within one or more distributions of threshold voltages for programmed memory cells or within a distribution of threshold voltages for erased memory cells, as appropriate. Figure 12A An exemplary threshold voltage distribution for a memory array is shown when each memory cell stores three bits of data. However, other embodiments may use other data capacities per memory cell (e.g., such as one, two, four, or five bits of data per memory cell). Figure 12A Eight threshold voltage distributions are shown, corresponding to eight data states. The first threshold voltage distribution (data state) Er represents an erased memory cell. The other seven threshold voltage distributions (data states) A ​​to G represent programmed memory cells and are therefore also referred to as programmed states. Each threshold voltage distribution (data state) corresponds to a predetermined value for a set of data bits. The specific relationship between the data programmed into the memory cell and the threshold voltage level of the cell depends on the data encoding scheme adopted by the cell. In one embodiment, the data values ​​are assigned to the threshold voltage ranges using Gray code allocation so that if the threshold voltage of the memory is erroneously shifted to its adjacent physical state, only one bit will be affected.

[0151] Figure 12A Seven read reference voltages, VrA, VrB, VrC, VrD, VrE, VrF, and VrG, are shown for reading data from memory cells. By testing (e.g., performing a sensing operation) whether the threshold voltage of a given memory cell is above or below the seven read reference voltages, the system can determine the data state (i.e., A, B, C, D, ...) that the memory cell is in.

[0152] Figure 12A Also shown are seven verify reference voltages, VvA, VvB, VvC, VvD, VvE, VvF, and VvG. In some embodiments, when programming memory cells to data state A, the system tests whether these memory cells have a threshold voltage greater than or equal to VvA. When programming memory cells to data state B, the system tests whether these memory cells have a threshold voltage greater than or equal to VvB. When programming memory cells to data state C, the system determines whether these memory cells have a threshold voltage greater than or equal to VvC. When programming memory cells to data state D, the system tests whether these memory cells have a threshold voltage greater than or equal to VvD. When programming memory cells to data state E, the system tests whether these memory cells have a threshold voltage greater than or equal to VvE. When programming memory cells to data state F, the system tests whether these memory cells have a threshold voltage greater than or equal to VvF. When programming memory cells to data state G, the system tests whether these memory cells have a threshold voltage greater than or equal to VvG. Figure 12A Also shown is Vev, which is the voltage level used to test whether the memory cell has been properly erased.

[0153] In one embodiment, referred to as full sequence programming, memory cells can be programmed directly from erased data state Er to any of programmed data states A through G. For example, a group of memory cells to be programmed can first be erased so that all memory cells in the group are in erased data state Er. The programming process can then be used to program the memory cells directly to data states A, B, C, D, E, F, and / or G. For example, while some memory cells are being programmed from data state ER to data state A, other memory cells are being programmed from data state Er to data state B and / or from data state Er to data state C, and so on. Figure 12A The arrows represent full sequence programming. In some embodiments, data states A through G may overlap, where the control die 304 and / or memory controller 102 rely on error correction to identify the correct data being stored.

[0154] In addition to full sequence programming, the techniques described herein can also be used with other types of programming, including but not limited to multi-level programming / multi-phase programming. In one embodiment of multi-level programming / multi-phase programming, in the first phase, all memory cells that are to end up with any of data states D to G are programmed to an intermediate state no higher than D. In the first phase, memory cells that are to end up with any of data states Er to C do not receive programming. In the second phase, memory cells that are to end up with any of data states B or C are programmed to a state no higher than B; memory cells that end up with data states F or G are programmed to a state no higher than F. In the third phase, the memory cells are programmed to their final states. In one embodiment, the first page is programmed in the first phase, the second page is programmed in the second phase, and the third page is programmed in the third phase. Herein, once a page has been programmed into a group of memory cells, the memory cells can be read back to retrieve the page. Therefore, the intermediate states associated with multi-phase programming are considered to be programmed states herein.

[0155] Generally speaking, during verify operations and read operations, the selected word line is connected to a voltage (an example of a reference signal) whose level is determined for each read operation (e.g., see Figure 12A Read comparison levels VrA, VrB, VrC, VrD, VrE, VrF, and VrG) or verification operations (e.g., see Figure 12A The verification target levels (VvA, VvB, VvC, VvD, VvE, VvF, and VvG) of the memory cells are specified in order to determine whether the threshold voltage of the associated memory cells has reached this level. After the word line voltage is applied, the conduction current of the memory cell is measured to determine whether the memory cell is turned on (conducting current) in response to the voltage applied to the word line. If the conduction current is measured to be greater than a certain value, it is assumed that the memory cell is turned on and the voltage applied to the word line is greater than the threshold voltage of the memory cell. If the conduction current is not measured to be greater than the certain value, it is assumed that the memory cell is not turned on and the voltage applied to the word line is not greater than the threshold voltage of the memory cell. During the read or verify process, unselected memory cells are provided with one or more read pass voltages (also called bypass voltages) at their control gates so that these memory cells will operate as pass gates (e.g., conduct current regardless of whether these memory cells are being programmed or erased).

[0156] There are many ways to measure the conduction current of a memory cell during a read or verify operation. In one example, the conduction current of a memory cell is measured as the rate at which the memory cell discharges or charges a dedicated capacitor in a sense amplifier. In another example, the conduction current of a selected memory cell allows (or does not allow) the NAND string containing the memory cell to discharge the corresponding bit line. The voltage on the bit line is measured after a certain period of time to see if it has discharged. It should be noted that the techniques described herein can be used with different methods known in the art for verification / reading. Other read and verify techniques known in the art can also be used.

[0157] Figure 12B Depicted are the threshold voltage distributions when each memory cell stores four bits of data. Figure 12B The figure depicts that there may be some overlap between data states S0 to S15. Overlap can occur due to factors such as memory cells losing charge (and therefore the threshold voltage dropping). Program disturb can unintentionally increase the threshold voltage of a memory cell. Similarly, read disturb can unintentionally increase the threshold voltage of a memory cell. Over time, the position of the threshold voltage distribution can change. Such changes can increase the bit error rate, thereby increasing decoding time or even making decoding impossible. Changing the read reference voltage can help mitigate such effects.

[0158] As mentioned above, Figure 12B An example is depicted in which each memory cell stores four bits. Thus, four pages can be stored in a group of memory cells. The group of memory cells can be connected to the same word line. These pages can be referred to as the lower page, the middle lower page, the middle upper page, and the upper page. In one embodiment, to read the lower page, four different read reference voltages are used to sense the memory cells. For example, the memory cells can be sensed at Vr1, Vr4, Vr6, and Vr11. In some embodiments, the read reference voltage used to read the page is adjusted from time to time. In some embodiments, a hierarchical approach is employed in which the control die 304 uses one or more techniques to find a new read reference voltage. If the control die does not successfully find a satisfactory read reference voltage, the memory controller 102 can search for a new read reference voltage.

[0159] Figure 13FIG1 is a flow chart of one embodiment of a process 1300 for operating a nonvolatile memory including an integrated memory component 104. The process 1300 can be used to determine a new read reference voltage for reading memory cells on the memory die 302. The process 1300 can be performed in response to a variety of triggers, such as, but not limited to, a UECC error, a BER above a threshold, a decode time above a threshold, and the like. A UECC error means that the decoder was unable to successfully decode a codeword. This can be applied to a decoder on the control die 304 or a decoder in the memory controller 102.

[0160] Process 1300 employs a hierarchical approach to determining a new read reference voltage, wherein the control die 304 first attempts to determine the new read reference voltage, and then the memory controller 102 attempts to determine the new read reference voltage. The control die 304 and the memory controller 102 may use different techniques to determine the new read reference voltage. In one embodiment, the technique used by the memory controller 102 may consume more time and / or power than the technique used by the control die 304.

[0161] Step 1302 includes calibrating a read reference voltage by circuitry 310 on control die 304. For purposes of discussion, control die 304 uses a first technique. Control die 304 may use more than one technique to calibrate a read reference voltage.

[0162] In one embodiment, the control die 304 uses a technique for analyzing the threshold voltage distribution. In one embodiment, the control die 304 performs a scan for the valley between two threshold voltage distributions. The new read reference voltage may be located at the valley. A valley is a location between two adjacent threshold voltage distributions that have the smallest number of memory cells. For example, Figure 12B The valley between data state S3 and data state S4 is shown. In one embodiment, a new read reference voltage is established at the valley.

[0163] In one embodiment, valley scanning includes reading various levels close to the current read reference voltage. Figure 12B For example, a valley scan can read continuously at [Vr4-3Δ, Vr4-2Δ, Vr4-Δ, Vr4, Vr4+Δ, Vr4+2Δ, Vr4+3Δ]. For each new read, the number of memory cells whose state "flips" can be counted. In other words, the count consists of the number of memory cells that transitioned from non-conducting (i.e., having a threshold voltage higher than the read reference voltage) to conducting (i.e., having a threshold voltage lower than the read reference voltage). In one embodiment, the valley is selected based on the location with the fewest such transitions. For example, the new read reference voltage can be selected as the read reference voltage with the fewest such transitions. Other techniques can be used to perform the valley scan.

[0164] In one embodiment, the control die 304 compares the number of memory cells in the threshold voltage distribution to the expected number of memory cells that will be in the threshold voltage distribution. In one embodiment, the approximate number of memory cells in each of the data states is known. For example, due to data scrambling (or other factors), the number of memory cells in each data state may be approximately the same. Figure 12B , in one embodiment, approximately one eighth of the memory cells should be below VrA, two eighths of the memory cells should be below VrB, three eighths of the memory cells should be below VrC, etc. In one embodiment, for each read reference voltage (e.g., VrA, VrB, VrC, etc.), the control die 304 reads at various candidate reference voltages close to that reference level and selects the candidate with the result closest to the above ratios.

[0165] In one embodiment, the control die 304 uses a technique to analyze error metrics relative to data stored in the non-volatile memory cells. The error metric can be, for example, a companion weight or a bit error rate (BER). The control die 304 can analyze the error metrics for codewords read from a group of non-volatile memory cells. In one embodiment, the control die 304 performs a bit error rate estimation scan (BES) to determine new read reference voltages. Briefly, the BES can include sensing memory cells using different sets of read reference voltages and then determining an error metric, such as a BER, for each set of read reference voltages.

[0166] For example, relative to Figure 12B In the example in FIG, there are seven candidate read reference voltages for each of the four read reference voltages used to sense the lower page. This means that there are a total of 7^4 possible combinations of read reference voltages for reading the lower page. However, the control die 304 can only explore a very limited number of these combinations, saving time and power. In addition, the circuitry required to perform the calculations can be simplified. In one embodiment, multiple candidate reference levels are used for one read reference voltage, while the other read reference voltages are fixed. This technique greatly reduces the number of sensing operations. For example, relative to Figure 12BIn the example in , if only one of the possible read reference voltages is used for three of the read reference voltages, this results in only seven possible combinations. For example, one combination may be [Vr1-5Δ, Vr4, Vr6, Vr11], another combination may be [Vr1-2Δ, Vr4, Vr6, Vr11], another combination may be [Vr1-Δ, Vr4, Vr6, Vr11], and so on. If only the reference voltage Vr1 is allowed to vary, this limits the possible combinations to seven. However, the control die 304 can form a similar group of other read reference voltages (Vr4, Vr6, Vr11) for reading the lower page. The control die can also calibrate the read reference voltages for reading at the other three pages (e.g., middle lower page, middle upper page, upper page). Combined Figure 17 More details of one embodiment of the first stage of the BES are shown and described.

[0167] Step 1304 is to determine whether the control die 304 successfully calibrated the read reference voltage. In one embodiment, the error metric should be below a target threshold to indicate success.

[0168] In step 1306, if the control die 304 successfully calibrates the read reference voltage, the control die 304 stores the new (or calibrated) read reference voltage. Note that the memory controller 102 does not need to be involved until this point. Therefore, data does not need to be transferred from the control die 304 to the memory controller 102 until this point.

[0169] If the control die 304 does not successfully calibrate the read reference voltage, steps 1308 through 1314 are performed. Step 1308 includes the control die 304 requesting the memory controller 102 to calibrate the read reference voltage. Step 1310 includes the memory controller 102 calibrating the read reference voltage. The memory controller 102 may use a second technique that is different from the technique used by the control die 304. In one embodiment, the memory controller 102 uses a technique that analyzes error metrics relative to data stored in the non-volatile memory cells. For example, the memory controller 102 may use one type of BES. However, the memory controller 102 may perform a more detailed or comprehensive BES than that performed by the control die 304. For example, with respect to Figure 12B In the example in FIG, there are seven candidate read reference voltages for each of the four read reference voltages for the lower page. This means that there are a total of 7^4 possible combinations of read reference voltages for reading the lower page. The exhaustive BES does not necessarily have to explore all of these 7^4 possible combinations, but may explore more combinations than the control die 304 explores. In one embodiment, the memory controller 102 explores the reference voltage group for reading the page, where more than one read reference voltage allows for multiple candidates. In combination Figure 18 More details of one embodiment of the second stage of the BES are shown and described.

[0170] Step 1312 includes the memory controller 102 sending the new read reference voltage to the control die 304. Step 1314 includes the control die 304 storing the new read reference voltage.

[0171] Figure 14 FIG1 is a flow chart of one embodiment of a process 1400 for operating a nonvolatile memory including an integrated memory component 104. The process 1400 may be used to determine a new read reference voltage for reading memory cells on the memory die 302. The process 1400 may be performed in response to a variety of triggers, such as, but not limited to, a UECC error, a BER above a threshold, a decode time above a threshold, etc. The process 1400 employs a hierarchical approach to determine a new read reference voltage at the control die 304.

[0172] Process 1400 involves determining a new read reference voltage using different techniques on control die 304. In process 1400, one of these techniques is based on analyzing threshold voltage distributions, and another technique involves analyzing error metrics.

[0173] Step 1402 includes analyzing the threshold voltage distribution of the data stored in the non-volatile memory cells on the memory die 302 in order to search for a first set of dynamic read reference voltages. Analyzing the threshold voltage distribution can be performed without any decoding of the codeword. In some embodiments, analyzing the threshold voltage distribution can utilize existing hardware for sensing memory cells. For example, reference Figure 5A In one embodiment, the control die 304 has a sense amplifier 350 and other logic that allows the control die 304 to analyze the threshold voltage distribution. Thus, analyzing the threshold voltage distribution to determine the new read reference voltage can be performed with minimal additional logic added to the integrated memory component 104. An example of analyzing the threshold voltage distribution to determine the new read reference voltage has been discussed above in conjunction with step 1302. In one embodiment, the control die 304 performs a scan for the valley between the two threshold voltage distributions. In one embodiment, the control die 304 compares the number of memory cells having a threshold voltage below the selected read reference voltage to the ratio of the expected number of memory cells that will have a threshold voltage below the selected read reference voltage.

[0174] Step 1404 may include the control die 304 reading the codeword stored in a group of memory cells using the new read reference voltage.Step 1406 may include the control die 304 attempting to decode the codeword.

[0175] Step 1408 includes determining whether the new read reference voltage is satisfactory. In other words, determining whether the new read reference voltage is successful. Whether the new read reference voltage is satisfactory may be determined based on an error metric of a codeword (e.g., data) read using the new read reference voltage. In one embodiment, if the error metric (of the data or codeword) is within a threshold, then the new read reference voltage is satisfactory. If the error metric exceeds the threshold, then the new read reference voltage is unsatisfactory. For example, success may be determined based on whether the codeword's companion weight is below a threshold, whether the codeword's estimated BER is below a threshold, or other factors. In one embodiment, if the companion weight is below a predetermined value, then the companion weight is within the threshold. In one embodiment, if the companion weight is below a predetermined value, then the BER is within the threshold.

[0176] If the new read reference voltage is satisfactory, the control die 304 passes the decoded data to the memory controller 102 in step 1410. The control die 304 may also store the first dynamic read level for future use.

[0177] If the new read reference voltage is not satisfactory, steps 1412 through 1416 are performed.Step 1412 includes the control die 304 analyzing error metrics of data stored in non-volatile memory cells on the memory die 302 to search for a second dynamic read level.

[0178] Step 1414 includes determining whether the second dynamic read level is satisfactory. If the second dynamic read level is satisfactory (yes at step 1414), the control die 304 uses the second dynamic read level to read the data in the memory cells on the memory die 302. The control die 304 may decode the data and send the decoded data to the memory controller 102. The control die 304 may also store the second dynamic read level for future use.

[0179] If the second dynamic read level is not satisfactory (step 1414 is no), then process 1500 may be performed. Process 1500 is shown in FIG. Figure 15 middle.

[0180] Figure 15 is a flow chart of one embodiment of a process 1500 for operating a nonvolatile memory including an integrated memory component 104. Process 1500 can be used to determine a new read reference voltage for reading memory cells on memory die 302. Process 1500 can be performed in response to process 1400 failing to determine a satisfactory dynamic read level.

[0181] Step 1502 includes the memory controller 102 determining error metrics for data stored in non-volatile memory cells on the memory die 302 in order to search for dynamic read levels. In one embodiment, the memory controller 102 performs the second phase of the BES process. Figure 18 Details of one embodiment of the second phase of the BES process are shown and described.

[0182] Step 1504 includes the memory controller 102 sending the third dynamic read level to the control die 304. The control die 304 may store the third dynamic read level for future use.

[0183] Step 1506 includes controlling the die to use the third set of dynamic read levels to read data in the non-volatile memory cells on the memory die 302. Step 1506 may also include controlling the die 304 to decode the data.

[0184] Step 1508 includes controlling the die 304 to pass the data to the memory controller 102 .

[0185] In one embodiment, a hierarchical method for determining dynamic read levels includes performing a valley scan, performing a first phase of a BES scan, and then optionally performing a second phase of a BES scan to determine the dynamic read level. Figure 16 FIG1 is a flow chart of one embodiment of a process 1600 for determining dynamic read levels of memory cells in the integrated memory component 104. The process 1600 may be used to determine a new read reference voltage for reading memory cells on the memory die 302. The process 1600 may be performed in response to a variety of triggers, such as, but not limited to, a UECC error, a BER above a threshold, a decode time above a threshold, etc. The process 1600 employs a hierarchical approach to determining a new read reference voltage at the control die 304.

[0186] Step 1602 includes performing a valley scan of the threshold voltage distribution of the data stored in the nonvolatile memory cells on the memory die 302 to search for a first set of dynamic read reference voltages. Performing the valley scan can be performed without any decoding of the codeword. In some embodiments, performing the valley scan can utilize existing hardware for sensing memory cells. Thus, performing the valley scan to determine the new read reference voltage can be performed with minimal additional logic added to the integrated memory component 104.

[0187] Step 1604 includes determining whether the valley scan was successful. If the valley scan was successful, then in step 1606, the first set of dynamic read levels can be stored on the control die 304. If the valley scan was unsuccessful, then control passes to step 1608.

[0188] Step 1608 includes the control die 304 performing a first phase of a BES scan to determine a second set of dynamic read levels. If the first phase of the BES scan is successful (yes at step 1610), then in step 1612, the second set of dynamic read levels may be stored on the control die 304. If the first phase of the BES scan is unsuccessful (no at step 1610), then control passes to step 1614. Step 1614 includes the memory controller 102 performing a second phase of a BES scan to determine a third set of dynamic read levels. Step 1616 includes the control die 304 storing the third set of dynamic read levels.

[0189] Many variations of process 1600 are possible. In some embodiments, additional layers may be added. In some embodiments, not all layers are performed. For example, one of the techniques in steps 1602, 1606, or 1614 may be skipped. In some embodiments, a technique at one layer may be replaced with another technique. For example, the valley scan in step 1602 may be replaced with another technique, such as comparing the ratio of the number of memory cells in each threshold voltage distribution.

[0190] Some embodiments analyze error metrics to determine a new read reference voltage. A technique for analyzing error metrics is referred to herein as BES. In some embodiments, BES has a first phase and a second phase. In some embodiments, the first phase may also be referred to as a greedy phase. In some embodiments, the second phase may be referred to as an exhaustive or comprehensive phase. Figure 17 is a flow chart of one embodiment of the first stage of a BES to determine a new read reference voltage. Figure 18 is a flow chart of one embodiment of the second stage of the BES to determine a new read reference voltage.

[0191] Now refer to Figure 17 , the first stage of BES can be executed on the control die 304. Figure 12B Example threshold distribution in to facilitate discussion Figure 17 1700 in . Process 1700 can be used for the read reference voltages used to sense one page. Process 1700 can be used to update Vrl, Vr4, Vr6, and Vrl 1, which, in one embodiment, are used to sense the next page. Process 1700 can be repeated for other pages.

[0192] Step 1702 includes selecting a read reference voltage to be updated. Figure 12B , you can choose to read the reference voltage Vr1.

[0193] Step 1704 includes forming read reference voltage groups, each of which includes multiple candidate voltages for the selected read reference voltage, while the other read reference voltages are fixed. For example, the multiple groups may include the following: [Vr1-3Δ, Vr4, Vr6, Vr11], [Vr1-2Δ, Vr4, Vr6, Vr11], [Vr1-Δ, Vr4, Vr6, Vr11], [Vr1, Vr4, Vr6, Vr11], [Vr1+Δ, Vr4, Vr6, Vr11], [Vr1+2Δ, Vr4, Vr6, Vr11], and [Vr1+3Δ, Vr4, Vr6, Vr11]. Thus, seven groups may be formed in this example. More or fewer than seven groups may be formed in step 1704. Note that, unlike Figure 12B Seven groups is a relatively small number of groups compared to the 7^4 possible read reference voltage groups in the example of FIG.

[0194] Step 1706 includes reading a codeword from the non-volatile memory cells on the memory die 302 using the read reference voltage group. In this example, seven codewords can be read (one for each group in step 1704). The following describes how one codeword can be read. The memory cells can be sensed continuously at each of the following reference voltages [Vr1-3Δ, Vr4, Vr6, Vr11]. As each reference voltage is applied to the selected memory cell, the selected memory cell may or may not conduct current. A latch can be used to store an indication of whether the selected memory cell conducts current for that reference voltage. In one embodiment, a single bit is generated for the selected memory cell based on the results of sensing at all reference voltages in the group. Thus, a codeword is formed by sensing a group of memory cells.

[0195] Step 1708 includes determining an ECC metric for each codeword read in step 1706. In one embodiment, the ECC metric is a companion weight. This may be an initial companion weight. In one embodiment, the initial companion weight is determined by performing a decoding iteration in an iterative message passing decoder. In one embodiment, the ECC metric is an estimated BER. In one embodiment, the BER is estimated based on the initial companion weight. Therefore, it should be noted that the codeword does not need to be fully decoded to determine the ECC metric.

[0196] Step 1710 includes determining a new value for the selected read voltage based on the ECC metric for the codeword. For example, the set of read reference voltages that produces the codeword with the best ECC metric can be selected. The best ECC metric refers to the best performance. For accompanying weights, lower weights are better. In other words, having fewer unsatisfied check nodes is better. For BER, the lowest BER is best. If there is a tie, any suitable tie-breaking procedure can be used, such as selecting the value closest to the current read reference voltage. Note that step 1710 determines a new read reference voltage only for one of the read reference voltages selected in step 1704.

[0197] Step 1712 includes determining whether another read reference voltage should be analyzed. Assuming the process is not complete, the process repeats steps 1702 to 1710 for another one of the read reference voltages used to sense the page. For example, see Figure 12B , these groups may include the following: [Vr1*, Vr4-3Δ, Vr6, Vr11], [Vr1*, Vr4-2Δ, Vr6, Vr11], [Vr1*, Vr4-Δ, Vr6, Vr11], [Vr1*, Vr4, Vr6, Vr11], [Vr1*, Vr4+Δ, Vr6, Vr11], [Vr1*, Vr4+2Δ, Vr6, Vr11], and [Vr1*, Vr4+3Δ, Vr6, Vr11]. In this example, Vr1* is the new value of Vr1.

[0198] In one embodiment, steps 1702 through 1710 are repeated for each of the read reference voltages used to sense the page. However, process 1700 need not repeat steps 1702 through 1710 for each of the read reference voltages used to sense the page. In other words, one or more of the read reference voltages may optionally remain unchanged without attempting to find a new value. In one embodiment, steps 1702 through 1710 are performed more than once for at least one of the read reference voltages. For example, steps 1702 through 1710 may be performed until the ECC metric in step 1708 is sufficiently low.

[0199] After the process is complete, a new read reference voltage is determined (yes at step 1712), and a determination is made at step 1714 as to whether the process was successful. In one embodiment, if the ECC metric at step 1708 does not reach the target level within a certain number of iterations, process 1700 ends in a failed state. In other words, process 1700 concludes that the new read reference voltage is unsatisfactory. In one embodiment, if process 1700 concludes that the new read reference voltage is unsatisfactory, process 1800 is executed.

[0200] If the process successfully finds a new read reference voltage (yes at step 1714 ), then at step 1716 , the control die 304 stores the new read reference voltage.

[0201] Now refer to Figure 18 , the second stage of BES can be executed on the memory controller 102. Figure 12B Example threshold distribution in to facilitate discussion Figure 18 1800. Process 1800 can be used for the read reference voltages used to sense one page. Process 1800 can be used to update Vrl, Vr4, Vr6, and Vrl 1, which, in one embodiment, are used to sense the next page. Process 1800 can be repeated for other pages.

[0202] Step 1802 includes forming read reference voltage groups, each read reference voltage group containing a plurality of candidate voltages for each read reference voltage of a sensing page. Figure 12B , there are 7^4 possible read reference voltage groups. Note that process 1800 does not require sensing of each of these 7^4 possible groups.

[0203] Step 1804 includes sensing nonvolatile memory cells on memory die 302 using at least one of the sets of read reference voltages.

[0204] Step 1806 includes generating a codeword based on the sensing of step 1804 .

[0205] Step 1808 includes determining an ECC metric for each codeword. In one embodiment, the ECC metric is a companion weight. This may be an initial companion weight. In one embodiment, the initial companion weight is determined by performing a decoding iteration in an iterative message passing decoder. In one embodiment, the ECC metric is an estimated BER. In one embodiment, the BER is estimated based on the initial companion weight. Therefore, it should be noted that the codeword does not need to be fully decoded to determine the ECC metric.

[0206] Step 1810 includes determining a new value for the read reference voltage based on the codeword's ECC metric. For example, the read reference voltage set that produces the codeword with the best ECC metric can be selected. The best ECC metric refers to the best performance. With respect to the adjoint weight, lower weights are better. In other words, having fewer unsatisfied check nodes is better. With respect to BER, the lowest BER is best. If there is a tie, any suitable tie-breaking procedure can be used, such as selecting the value closest to the current read reference voltage.

[0207] Step 1812 includes determining whether the search for a new read reference voltage is complete. In one embodiment, step 1812 is based on whether the companion weight of the codeword in step 1806 is below a threshold. If the companion weight is not below the threshold, the process can repeat steps 1804 to 1810 for other read reference voltage groups. When it is determined (in step 1812) that sufficient accuracy has been achieved for the read reference voltage, the new read reference voltage is stored in step 1814.

[0208] A first embodiment includes a device comprising a first semiconductor die comprising a non-volatile memory cell and a first plurality of pathways. The device also includes a second semiconductor die comprising one or more control circuits and a second plurality of pathways. The one or more control circuits are configured to transmit signals through pathway pairs of the first plurality of pathways and the second plurality of pathways. The one or more control circuits are further configured to read data in the non-volatile memory cell using a read reference voltage. The one or more control circuits are configured to receive data in parallel from the first semiconductor die through the second plurality of pathways. The one or more control circuits are configured to calibrate the read reference voltage used to read the non-volatile memory cell. The one or more control circuits are configured to read the data in the non-volatile memory cell using the calibrated read reference voltage.

[0209] In a second embodiment, furthering the first embodiment, the apparatus further comprises a memory controller that communicates with one or more control circuits on the second semiconductor die via a communication channel external to the second semiconductor die. The memory controller comprises a control circuit configured to calibrate the read reference voltage in response to the read reference voltage calibrated by the one or more control circuits on the second semiconductor die being unsatisfactory.

[0210] In a third embodiment, to further the first or second embodiments, the one or more control circuits on the control die are further configured to determine an error metric for a codeword stored in the nonvolatile memory cell. The one or more control circuits on the control die are further configured to calibrate a read reference voltage based on the error metric.

[0211] In a fourth embodiment, to further any of the first to third embodiments, one or more control circuits on the control die are further configured to form read reference voltage groups, each read reference voltage group containing multiple candidate voltages for a selected read reference voltage, while the other read reference voltages are fixed. The one or more control circuits on the control die are further configured to read codewords from a group of non-volatile memory cells on the memory die using the read reference voltage groups. The one or more control circuits on the control die are further configured to determine an error metric for each of the codewords. The one or more control circuits on the control die are further configured to calibrate the selected read reference voltage based on the error metric for the codeword.

[0212] In a fifth embodiment, to further any of the first to fourth embodiments, the apparatus further comprises a memory controller that communicates with one or more control circuits on the second semiconductor die via a communication channel external to the second semiconductor die. The memory controller comprises a control circuit configured to determine an error metric for each of a plurality of groups of read reference voltages, wherein each group comprises a plurality of candidate read reference voltages for each of a plurality of read reference voltages for reading a codeword. The control circuit of the memory controller is configured to calibrate the read reference voltages based on the error metric.

[0213] In a sixth embodiment, to further any of the first to fifth embodiments, the second semiconductor die includes logic configured to calibrate a read reference voltage based on an analysis of a threshold voltage distribution of data stored in a group of nonvolatile memory cells. The second semiconductor die is configured to calibrate the read reference voltage based on an analysis of an error metric of a codeword stored in the group of nonvolatile memory cell voltages in response to the read reference voltage calibrated based on the analysis of the threshold voltage distribution being unsatisfactory.

[0214] In a seventh embodiment, to advance any one of the first to sixth embodiments, one or more control circuits on the second semiconductor die are further configured to reuse data used to calibrate the read reference voltage of the group based on analysis of the threshold voltage distribution to calibrate the read reference voltage based on analysis of the error metric.

[0215] In an eighth embodiment, to advance any of the sixth to seventh embodiments, one or more control circuits on the second semiconductor die are configured to perform a scan of a valley between two of the threshold voltage distributions to calibrate a read reference voltage based on an analysis of the threshold voltage distribution of data stored in the group of nonvolatile memory cells.

[0216] In a ninth embodiment, to further any of the first to eighth embodiments, one or more control circuits on the second semiconductor die are configured to compare a ratio of a number of memory cells having a threshold voltage lower than a selected read reference voltage to an expected number of memory cells that will have a threshold voltage lower than the selected read reference voltage to calibrate the selected read reference voltage based on an analysis of a threshold voltage distribution of data stored in the group of nonvolatile memory cells.

[0217] In a tenth embodiment, in furtherance of any one of the first to ninth embodiments, the first semiconductor die includes a first plurality of bonding pads. Additionally, the second semiconductor die includes a second plurality of bonding pads. Each via pair includes a bonding pad from the first plurality of bonding pads and a bonding pad from the second plurality of bonding pads.

[0218] One embodiment includes a method for calibrating a read reference voltage. The method includes analyzing, by one or more control circuits on a control die of an integrated memory assembly including a memory die and a control die, a threshold voltage distribution of data stored in non-volatile memory cells on the memory die to search for a first dynamic read level. The method includes transferring a codeword read from the non-volatile memory cells using the first dynamic read level to the control die, including transferring the codeword from the memory die to the control die by bonding the memory die to bonding pads of the control die. The method includes analyzing, by one or more control circuits on the control die, an error metric of the data stored in the non-volatile memory cells on the memory die to search for a second dynamic read level in response to the first dynamic read level being unsatisfactory. The method includes transferring, from the control die to a memory controller, data read from the non-volatile memory cells using the second dynamic read level in response to the second dynamic read level being satisfactory.

[0219] One embodiment includes a nonvolatile memory system comprising a memory controller and an assembly having a memory semiconductor die bonded to a control semiconductor die to allow communication between the memory semiconductor die and the control semiconductor die. The assembly communicates with the memory controller. The memory semiconductor die includes a second nonvolatile memory cell. The control semiconductor die includes one or more control circuits configured to read data in the nonvolatile memory cell using a read reference voltage. The one or more control circuits are configured to calibrate a new read reference voltage for reading the nonvolatile memory cell. The one or more control circuits are configured to read data in the nonvolatile memory cell using the new read reference voltage. The one or more control circuits are configured to determine an error metric relative to data read using the new read reference voltage. The one or more control circuits are configured to pass data to the memory controller in response to the error metric being within a threshold. The memory controller is configured to calculate a new read reference voltage for reading the nonvolatile memory cell in response to the error metric exceeding the threshold.

[0220] The above specific embodiments of the present invention have been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise forms disclosed. Many modifications and variations are possible in light of the above teachings. The described embodiments have been selected to best illustrate the principles of the invention and its practical application, thereby enabling others skilled in the art to best utilize the invention in various embodiments with various modifications suitable for the specific use contemplated. The scope of the invention is intended to be defined by the appended claims.

Claims

1. A device comprising: a first semiconductor die comprising a nonvolatile memory cell and a first plurality of vias; and a second semiconductor die comprising one or more control circuits and a second plurality of vias, wherein the one or more control circuits are configured to route signals through via pairs of the first plurality of vias and the second plurality of vias, wherein the one or more control circuits are further configured to: reading data in the nonvolatile memory cells using a read reference voltage, wherein the one or more control circuits are configured to receive the data in parallel from the first semiconductor die through the second plurality of paths; calibrating a read reference voltage for reading the nonvolatile memory cell; as well as reading data in the nonvolatile memory cell using the calibrated read reference voltage; wherein the one or more control circuits on the second semiconductor die are further configured to: forming read reference voltage groups, each read reference voltage group including a plurality of candidate voltages of a selected read reference voltage, while other read reference voltages are fixed; reading a codeword from a set of said nonvolatile memory cells on said first semiconductor die using said set of said read reference voltages; determining an error metric for each of the codewords; as well as A selected read reference voltage is calibrated based on the error metric for the codeword.

2. The apparatus according to claim 1, further comprising: a memory controller that communicates with the one or more control circuits on the second semiconductor die via a communication channel external to the second semiconductor die, wherein the memory controller is configured to calibrate the read reference voltage in response to the read reference voltage calibrated by the one or more control circuits on the second semiconductor die being unsatisfactory.

3. The apparatus of claim 1 , wherein the one or more control circuits on the second semiconductor die are further configured to: determining an error metric for a codeword stored in the nonvolatile memory unit; and The read reference voltage is calibrated based on the error metric.

4. The apparatus according to claim 1, further comprising: a memory controller that communicates with the one or more control circuits on the second semiconductor die via a communication channel external to the second semiconductor die, wherein the memory controller includes control circuitry configured to: determining an error metric for each of a plurality of sets of read reference voltages, wherein each set includes a plurality of candidate read reference voltages for each of a plurality of read reference voltages for reading a codeword; as well as The read reference voltage is calibrated based on the error metric.

5. The apparatus according to claim 1, wherein: the second semiconductor die including logic configured to calibrate the read reference voltage based on an analysis of a threshold voltage distribution of data stored in a group of the nonvolatile memory cells; and The second semiconductor die is configured to calibrate the read reference voltage based on an analysis of an error metric of a codeword stored in the set of nonvolatile memory cell voltages in response to the read reference voltage calibrated based on the analysis of the threshold voltage distribution being unsatisfactory.

6. The apparatus of claim 5 , wherein the one or more control circuits on the second semiconductor die are further configured to: Data used to calibrate the set of read reference voltages is reused based on the analysis of the threshold voltage distribution to calibrate the read reference voltages based on the analysis of the error metric.

7. The apparatus of claim 5 , wherein the one or more control circuits on the second semiconductor die are configured to: Scanning a valley between two of the threshold voltage distributions is performed to calibrate the read reference voltage based on the analysis of the threshold voltage distributions of data stored in the nonvolatile memory cells of the group.

8. The apparatus of claim 5, wherein the one or more control circuits on the second semiconductor die are configured to: A ratio of a number of memory cells having a threshold voltage below a selected read reference voltage is compared to an expected number of memory cells that will have a threshold voltage below the selected read reference voltage to calibrate the selected read reference voltage based on the analysis of the threshold voltage distribution of data stored in the group of nonvolatile memory cells.

9. The apparatus according to claim 1, wherein: the first semiconductor die comprising a first plurality of bond pads; the second semiconductor die includes a second plurality of bond pads; and Each via pair includes a bonding pad from the first plurality of bonding pads and a bonding pad from the second plurality of bonding pads.

10. A method for calibrating a read reference voltage, the method comprising: analyzing, by one or more control circuits on a control die of an integrated memory assembly comprising a memory die and a control die, a threshold voltage distribution of data stored in nonvolatile memory cells on the memory die to search for a first dynamic read level; transferring a codeword read from the nonvolatile memory cell using the first dynamic read level to the control die, comprising transferring the codeword from the memory die to the control die by bonding the memory die to a bond pad of the control die; analyzing, by the one or more control circuits on the control die, error metrics of data stored in nonvolatile memory cells on the memory die to search for a second dynamic read level in response to the first dynamic read level being unsatisfactory; as well as transferring data read from the nonvolatile memory cells using the second dynamic read level from the control die to a memory controller in response to the second dynamic read level being satisfactory; in: Analyzing the threshold voltage distribution includes performing a valley scan of the threshold voltage distribution; Analyzing the error metrics at the control die includes the control die performing a greedy phase of a bit error rate (BER) estimation scan; and Analyzing the error metrics at the memory controller includes the memory controller performing a comprehensive phase of the BER estimation scan.

11. The method according to claim 10, further comprising: Error metrics at the memory controller are analyzed in response to the second dynamic read level being unsatisfactory to determine a third dynamic read level for reading the nonvolatile memory cells on the memory die.

12. A non-volatile storage system comprising: Memory controller; and An assembly comprising a memory semiconductor die bonded to a control semiconductor die to allow communication between the memory semiconductor die and the control semiconductor die, wherein the assembly communicates with the memory controller, wherein the memory semiconductor die includes non-volatile memory cells, wherein the control semiconductor die includes one or more control circuits, the one or more control circuits being configured to: reading data in the nonvolatile memory cell using a read reference voltage; calculating a new read reference voltage for reading the nonvolatile memory cell; reading data in the nonvolatile memory cell using the new read reference voltage; determining an error metric relative to the data read using the new read reference voltage; as well as communicating the data to the memory controller in response to the error metric being within a threshold; wherein the memory controller is configured to calculate a new read reference voltage for reading the nonvolatile memory cell in response to the error metric exceeding the threshold; wherein the one or more control circuits on the control semiconductor die are further configured to: determining an initial companion weight for a codeword stored in the nonvolatile memory unit; as well as The new read reference voltage is calculated based on the initial companion weight.

13. The non-volatile storage system of claim 12 , wherein the one or more control circuits on the control semiconductor die are further configured to: analyzing a threshold voltage distribution of data stored in the nonvolatile memory cell; and The new read reference voltage is calculated based on the threshold voltage distribution.

14. The non-volatile storage system according to claim 12, wherein: the one or more control circuits on the control semiconductor die being further configured to perform a greedy phase of a technique that uses estimated bit errors of a codeword stored in the nonvolatile memory cell in order to calculate the new read reference voltage; and The memory controller is further configured to perform a comprehensive phase of the technique that uses estimated bit errors of a codeword stored in the nonvolatile memory cells in order to calculate the new read reference voltage.

15. The non-volatile storage system according to claim 12, wherein: The one or more control circuits configured to calculate the new read reference voltage include an error correction code (ECC) engine configured to decode a codeword and circuitry that uses the ECC engine to determine the new read reference voltage.

16. The non-volatile storage system according to claim 15, wherein: The one or more control circuits are configured to calculate the new read reference voltage, including logic configured to analyze a threshold voltage distribution without decoding the codeword.

17. The non-volatile storage system according to claim 12, wherein: The one or more control circuits configured to calculate the new read reference voltage include a transistor having a first size; and The non-volatile memory cell includes a transistor having a second size that is larger than the first size.

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