Storage device, storage controller, and storage controller operation method

Abstract

The present application discloses a storage device, a storage controller, and an operating method of the storage controller. An electronic device is provided, more specifically, a storage device for alleviating a period of peak current due to current overlap. The storage device includes: a memory device, which includes multiple tube cores; and a storage controller, which controls the memory device. The memory device generates state information about the amount of current consumed by each of the multiple tube cores during a busy period in which all multiple tube cores are in a busy state, and wherein the storage controller determines based on the state information whether the peak current of multiple tube cores among the multiple tube cores is consumed in a common sub-period among multiple sub-periods spanning the busy period, and when it is determined that the peak current of multiple tube cores is consumed in the common sub-period, the storage controller controls the memory device to suspend the operation of the tube core among the multiple tube cores.

Description

Technical Field

[0001] Various embodiments of the present disclosure relate generally to electronic devices, and more particularly, to a storage device and an operating method of the storage device. Background Art

[0002] A storage device may store data under the control of a host device such as a computer, a smart phone, or a smart tablet. Examples of storage devices include devices for storing data on a disk such as a hard disk drive (HDD) and devices for storing data in a semiconductor memory, particularly a non-volatile memory such as a solid state drive (SSD) or a memory card.

[0003] The storage device may include a memory device for storing data and a storage controller for controlling the memory device to store data. The memory device may be classified as a volatile memory device or a non-volatile memory device. Examples of non-volatile memory devices include read-only memory (ROM) devices, programmable ROM (PROM) devices, electrically programmable ROM (EPROM) devices, electrically erasable programmable ROM (EEPROM) devices, flash memory devices, phase change RAM (PRAM) devices, magnetic RAM (MRAM) devices, resistive RAM (RRAM) devices, and ferroelectric RAM (FRAM) devices. Summary of the invention

[0004] Various embodiments relate to a memory device for mitigating a period during which a peak current occurs due to overlapping currents and a method of operating the memory device.

[0005] According to an embodiment, a storage controller for controlling a memory device including a plurality of dies may include a state information determination component configured to determine whether peak currents of a plurality of dies among the plurality of dies appear in a common sub-period among a plurality of sub-periods spanning the busy period based on state information received from the memory device during a busy period in which all the plurality of dies are in a busy state, and to generate pause information based on determining that the peak currents of the plurality of dies appear in the common sub-period. The storage controller also includes a peak current controller configured to output a pause command for suspending operation of at least one die among the plurality of dies during the common sub-period based on the pause information.

[0006] According to an embodiment, a method for operating a storage controller for controlling a memory device including a plurality of dies includes the following steps: receiving status information from a memory device during a busy period in which all of the plurality of dies are in a busy state. The method also includes the following steps: determining, based on the status information, whether a peak current of a plurality of dies among the plurality of dies occurs in a common sub-period among a plurality of sub-periods spanning the busy period. The method also includes the following steps: generating, based on the determination, pause information for suspending operation of at least one die among the plurality of dies. The method also includes the following steps: outputting a pause command for suspending operation of the at least one die during the common sub-period based on the pause information.

[0007] According to an embodiment, a memory device includes: a memory device including a plurality of dies; and a memory controller that controls the memory device. The memory device generates state information about the amount of current consumed by each of the plurality of dies during a busy period in which all of the plurality of dies are in a busy state. The memory controller determines whether a peak current of a plurality of dies among the plurality of dies is consumed in a common sub-period among a plurality of sub-periods spanning the busy period based on the state information, and when it is determined that a peak current of a plurality of dies is consumed in the common sub-period, the memory controller controls the memory device to suspend operation of a die among the plurality of dies. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a block diagram showing a storage device.

[0009] Figure 2 It is shown Figure 1 A diagram showing the structure of a memory device.

[0010] Figure 3 It is shown Figure 2 A diagram of an embodiment of a memory cell array is shown.

[0011] Figure 4 It is shown that the Figure 1 A diagram of multiple dies in a memory device is shown.

[0012] Figure 5 is a graph showing the amount of current consumed by each of the two dies and the total amount of current obtained by adding the amounts of current consumed by the two dies.

[0013] Figure 6 is a diagram showing the operation of two dies during a period where peak current overlap occurs.

[0014] Figure 7 is a diagram illustrating the operation of two dies during a period in which peak current overlap occurs, according to an embodiment.

[0015] Figure 8 It is shown Figure 5 The total current shown is Figure 7 A diagram showing a comparison between the total current amounts.

[0016] Fig. 9 It is shown Figure 1 FIG. 5 is a diagram showing a configuration of a storage controller and a process of outputting a pause command.

[0017] Fig.10 is a diagram showing a method of subdividing overlapping busy periods.

[0018] Fig.11A and Fig. 11B is a table showing status information output from the memory device.

[0019] Fig.12 is a table showing a method of determining whether periods in which peak currents occur overlap based on status information.

[0020] Fig.13 is a diagram illustrating the operation of a memory controller according to an embodiment.

[0021] Fig.14 is a diagram illustrating the operation of a memory controller according to an embodiment.

[0022] Fig.15 It is shown Figure 1 A diagram of another embodiment of a storage controller is shown.

[0023] Fig.16 is a block diagram illustrating a memory card system to which a memory device is applied according to an embodiment.

[0024] Fig.17 is a block diagram illustrating an example of a solid state drive (SSD) system to which a storage device is applied according to an embodiment.

[0025] Fig.18 is a block diagram illustrating a user system to which a storage device is applied according to an embodiment. DETAILED DESCRIPTION

[0026] Below, only the specific structure or functional description of an example of an implementation of the concept disclosed in this specification is shown to describe an example of an implementation according to the concept, and the example of an implementation according to the concept can be implemented in various forms, but the description is not limited to the example of the implementation described in this specification.

[0027] Hereinafter, embodiments of the present disclosure are described with reference to the accompanying drawings so that those skilled in the art can implement the technical spirit of the present disclosure.

[0028] Figure 1 is a block diagram showing the storage device 50 .

[0029] Reference Figure 1 , the storage device 50 may include a memory device 100 and a storage controller 200 .

[0030] The storage device 50 may store data in response to the control of the host 300. Examples of the host include a cellular phone, a smart phone, an MP3 player, a laptop computer, a desktop computer, a game console, a TV, a tablet PC, or an in-vehicle infotainment system.

[0031] The storage device 50 may be configured as one of various types of storage devices according to a host interface corresponding to a communication method with the host 300. For example, the storage device 50 may be configured as one of various types of storage devices, such as a solid state drive (SSD); a multimedia card (MMC) in the form of eMMC, RS-MMC, or micro-MMC; a secure digital (SD) card; a mini-SD card; a micro-SD card; a universal serial bus (USB) storage device; a universal flash memory (UFS) device; a personal computer memory card international association (PCMCIA) card type storage device; a peripheral component interconnect (PCI) card type storage device; a high-speed PCI (PCI-E) card type storage device; a compact flash (CF) card; a smart media card; or a memory stick.

[0032] The memory device 50 may be manufactured into one of various types of packages. For example, the memory device 50 may be manufactured into a package on package (POP), a system on package (SIP), a system on chip (SOC), a multi-chip package (MCP), a chip on board (COB), a wafer-level manufacturing package (WFP), or a wafer-level stacked package (WSP).

[0033] The memory device 100 may store data. The memory device 100 may operate in response to the control of the memory controller 200. The memory device 100 may include a memory cell array including a plurality of memory cells storing data. The memory cell array may include a plurality of memory blocks. Each memory block may include a plurality of memory cells, and the plurality of memory cells may form a plurality of pages. According to an embodiment, a page may be a unit for storing data in the memory device 100 or reading data stored in the memory device 100. A memory block may be a unit for erasing data.

[0034] According to an embodiment, the memory device 100 may be a double data rate synchronous dynamic random access memory (DDR SDRAM) device, a low power double data rate 4 (LPDDR4) SDRAM device, a graphic double data rate (GDDR) SDRAM device, a low power DDR (LPDDR) device, a Rambus dynamic random access memory (RDRAM) device, a NAND flash memory device, a vertical NAND flash memory device, a NOR flash memory device, a resistive random access memory (RRAM) device, a phase change memory (PRAM) device, a magnetoresistive random access memory (MRAM) device, a ferroelectric random access memory (FRAM) device, or a spin transfer torque random access memory (STT-RAM) device. For convenience of explanation, it is assumed in the context of the following description that the memory device 100 is a NAND flash memory device.

[0035] The memory device 100 may have a two-dimensional or three-dimensional array structure. Hereinafter, the three-dimensional array structure is described as an embodiment. However, the embodiment is not limited to the three-dimensional array structure. The embodiments of the present disclosure can be applied not only to a flash memory device in which a charge storage layer includes a conductive floating gate (FG), but also to a charge trap flash memory (CTF) memory device in which a charge storage layer includes an insulating layer.

[0036] According to an embodiment, the memory device 100 may be operated by a single-level cell (SLC) method in which one memory cell stores one bit of data. Alternatively, the memory device 100 may be operated by a method in which one memory cell stores at least two bits of data. For example, the memory device 100 may be operated by a multi-level cell (MLC) method in which one memory cell stores two bits of data, a triple-level cell (TLC) method in which one memory cell stores three bits of data, or a quad-level cell (QLC) method in which one memory cell stores four bits of data.

[0037] The memory device 100 may receive a command and an address from the memory controller 200 and access an area selected by an address in the memory cell array. That is, the memory device 100 may perform an operation corresponding to the command on the area selected by the address. For example, the memory device 100 may perform a write operation (or a programming operation), a read operation, or an erase operation according to the received command. For example, when a programming command is received, the memory device 100 may program data into the area selected by the address. When a read command is received, the memory device 100 may read data from the area selected by the address. When an erase command is received, the memory device 100 may erase data stored in the area selected by the address.

[0038] According to an embodiment, the memory controller 200 may include a state information determination component 210. The state information determination component 210 may determine states of a plurality of dies included in the memory device 100, and also determine whether to suspend an operation performed on one of the plurality of dies.

[0039] For example, the state information determination component 210 may receive a ready / busy signal R / B from a plurality of dies. A ready signal may indicate that the die is in a ready state where the die is on standby and not performing an operation. A busy signal may indicate that the die is in a busy state where the die is performing an operation.

[0040] According to an embodiment, when all signals received from the plurality of dies are busy signals, the state information determining component 210 may output a state read command to each of the plurality of dies. The memory device 100 may output state information in response to the state read command received from the state information determining component 210. The state information may include information indicating current consumed by each of the plurality of dies.

[0041] For example, the memory device 100 may subdivide a period during which each of the plurality of dies is in a busy state into sub-periods of a predetermined length, and may set and output bits indicating a current consumption amount corresponding to the sub-period as the status information.

[0042] According to an embodiment, the state information determination component 210 may determine the sub-period in which the peak current overlaps based on the state information received from the memory device 100. The state information determination component 210 may select one of the plurality of dies during the sub-period in which the peak current overlaps, and may generate pause information including information about the selected die and the time at which the operation of the selected die is suspended. The time interval at which the operation of the selected die is suspended may be the same as the sub-period in which the peak current overlaps. In addition, the pause information may be transmitted to the peak current controller 220.

[0043] According to an embodiment, the memory controller 200 may include a peak current controller 220. The peak current controller 220 may determine to output a suspend command based on the suspend information received from the state information determining component 210.

[0044] For example, when the suspend information includes information indicating that the operation on a predetermined die should be suspended, the peak current controller 220 may output a suspend command to the predetermined die to suspend the operation.

[0045] The memory controller 200 may control general operations of the memory device 50 .

[0046] The memory controller 200 may execute firmware when a power supply voltage is applied to the memory device 50. When the memory device 100 is a flash memory device, the memory controller 200 may execute firmware such as a flash translation layer (FTL) for controlling communication between the host 300 and the memory device 100.

[0047] According to an embodiment, the storage controller 200 may receive data and a logical block address (LBA) from the host 300, and include firmware (not shown) that converts the LBA into a physical block address (PBA) indicating an address of a memory cell in which data included in the memory device 100 is to be stored. In addition, the storage controller 200 may store a logical-physical address mapping table configuring a mapping relationship between the LBA and the PBA in a buffer memory.

[0048] The storage controller 200 may control the memory device 100 to perform a program operation, a read operation, an erase operation, etc. in response to a request from the host 300. For example, when the storage controller 200 receives a program request from the host 300, the storage controller 200 may convert the program request into a program command and may provide the program command, the PBA, and the data to the memory device 100. When the storage controller 200 receives a read request and an LBA from the host 300, the storage controller 200 may convert the read request into a read command, select a PBA corresponding to the LBA, and then may provide the read command and the PBA to the memory device 100. When the storage controller 200 receives an erase request and an LBA from the host 300, the storage controller 200 may convert the erase request into an erase command, select a PBA corresponding to the LBA, and then may provide the erase command and the PBA to the memory device 100.

[0049] According to an embodiment, the memory controller 200 may generate and transmit a program command, address, and data to the memory device 100 without a request from the host 300. For example, the memory controller 200 may provide the command, address, and data to the memory device 100 to perform background operations such as a program operation for wear leveling and a program operation for garbage collection.

[0050] According to an embodiment, the storage device 50 may further include a buffer memory (not shown). The storage controller 200 may control data exchange between the host 300 and the buffer memory (not shown). Alternatively, the storage controller 200 may temporarily store system data for controlling the memory device 100 in the buffer memory. For example, the storage controller 200 may temporarily store data input from the host 300, and thereafter transmit the data temporarily stored in the buffer memory to the memory device 100.

[0051] According to various embodiments, the buffer memory may be used as an operation memory or a cache memory of the memory controller 200. The buffer memory may store codes or commands executed by the memory controller 200. Alternatively, the buffer memory may store data processed by the memory controller 200.

[0052] Depending on the implementation, the buffer memory may include a dynamic random access memory (DRAM) or a static random access memory (SRAM) such as a double data rate synchronous random access memory (DDR SDRAM), a low power double data rate 4 (LPDDR4) SDRAM, a graphics double data rate (GDDR) SDRAM, a low power DDR (LPDDR), or a Rambus dynamic random access memory (RDRAM).

[0053] According to various embodiments, a buffer memory may be coupled to the storage device 50 outside the storage device 50. A volatile memory device of the storage device 50 coupled to the storage device 50 outside the storage device 50 may be used as a buffer memory.

[0054] According to an embodiment, the memory controller 200 may control a plurality of memory devices. The memory controller 200 may control the memory devices according to an interleaving scheme to improve operation performance.

[0055] The host 300 may communicate with the storage device 50 using at least one of various communication methods such as a universal serial bus (USB), a serial AT attachment (SATA), a serial attached SCSI (SAS), a high-speed inter-chip (HSIC), a small computer system interface (SCSI), a peripheral component interconnect (PCI), PCI express (PCIe), non-volatile memory express (NVMe), universal flash memory (UFS), secure digital (SD), a multimedia card (MMC), an embedded MMC (eMMC), a dual in-line memory module (DIMM), a registered DIMM (RDIMM) and / or a load reduced DIMM (LRDIMM).

[0056] Figure 2 It is shown Figure 1 FIG. 1 is a diagram showing the structure of a memory device 100 .

[0057] Reference Figure 2 , the memory device 100 may include a memory cell array 110 , a peripheral circuit 120 , and a control logic 130 .

[0058] The memory cell array 110 may include a plurality of memory blocks BLK1 to BLKz. The plurality of memory blocks BLK1 to BLKz may be coupled to a row decoder 121 through a row line RL. The plurality of memory blocks BLK1 to BLKz may be coupled to a page buffer group 123 through bit lines BL1 to BLn. Each of the plurality of memory blocks BLK1 to BLKz may include a plurality of memory cells. According to an embodiment, the plurality of memory cells may be nonvolatile memory cells. Memory cells coupled to the same word line may be defined as one page. Therefore, each memory block may include a plurality of pages.

[0059] The row line RL may include at least one source select line, a plurality of word lines, and at least one drain select line.

[0060] Each memory cell included in the memory cell array 110 may include a single level cell (SLC) storing one-bit data, a multi level cell (MLC) storing two-bit data, a triple level cell (TLC) storing three-bit data, or a quad level cell (QLC) storing four-bit data.

[0061] The peripheral circuit 120 may be configured to perform a program operation, a read operation, or an erase operation on a selected region of the memory cell array 110 in response to the control of the control logic 130. The peripheral circuit 120 may drive the memory cell array 110. For example, the peripheral circuit 120 may apply various operating voltages to the row lines RL and the bit lines BL1 to BLn or discharge the applied voltages in response to the control of the control logic 130.

[0062] The peripheral circuit 120 may include a row decoder 121 , a voltage generator 122 , a page buffer group 123 , a column decoder 124 , an input / output circuit 125 , and a sensing circuit 126 .

[0063] The row decoder 121 may be coupled to the memory cell array 110 via a row line RL. The row line RL may include at least one source selection line, a plurality of word lines, and at least one drain selection line. According to an embodiment, the word line may include a normal word line and a dummy word line. According to an embodiment, the row line RL may also include a pipe selection line.

[0064] The row decoder 121 may decode the row address RADD received from the control logic 130. The row decoder 121 may select at least one memory block among the memory blocks BLK1 to BLKz according to the decoded address. In addition, the row decoder 121 may select at least one word line of the selected memory block according to the decoded address to apply the voltage generated by the voltage generator 122 to the at least one word line WL.

[0065] For example, during a program operation, the row decoder 121 may apply a program voltage to a selected word line and a program pass voltage having a voltage level lower than the program voltage to unselected word lines. During a program verification operation, the row decoder 121 may apply a verification voltage to a selected word line and a verification pass voltage having a voltage level higher than the verification voltage to unselected word lines. During a read operation, the row decoder 121 may apply a read voltage to a selected word line and a read pass voltage having a voltage level higher than the read voltage to unselected word lines.

[0066] According to an embodiment, an erase operation of the memory device 100 may be performed in units of memory blocks. During the erase operation, the row decoder 121 may select one of the memory blocks according to the decoded address. During the erase operation, the row decoder 121 may apply a ground voltage to a word line coupled to the selected memory block.

[0067] The voltage generator 122 may operate in response to the control of the control logic 130. The voltage generator 122 may generate a plurality of voltages using an external power supply voltage supplied to the memory device 100. More specifically, the voltage generator 122 may generate various operation voltages Vop applied to perform a program operation, a read operation, and an erase operation in response to the operation signal OPSIG. For example, the voltage generator 122 may generate a program voltage, a verification voltage, a pass voltage, a read voltage, and an erase voltage in response to the control of the control logic 130.

[0068] According to an embodiment, the voltage generator 122 may generate an internal power supply voltage by adjusting an external power supply voltage. The internal power supply voltage generated by the voltage generator 122 may be used as an operating voltage of the memory device 100.

[0069] According to an embodiment, the voltage generator 122 may generate a plurality of voltages using an external power supply voltage or an internal power supply voltage.

[0070] For example, the voltage generator 122 may include a plurality of pumping capacitors that receive an internal power supply voltage, and generate a plurality of voltages by selectively enabling the plurality of pumping capacitors in response to the control of the control logic 130 .

[0071] The generated plurality of voltages may be supplied to the memory cell array 110 through the row decoder 121 .

[0072] The page buffer group 123 may include first to n-th page buffers PB1 to PBn. The first to n-th page buffers PB1 to PBn may be connected to the memory cell array 110 through first to n-th bit lines BL1 to BLn, respectively. The first to n-th page buffers PB1 to PBn may operate in response to the control of the control logic 130. More specifically, the first to n-th page buffers PB1 to PBn may operate in response to the page buffer control signal PBSIGNALS. For example, the first to n-th page buffers PB1 to PBn may temporarily store data received through the first to n-th bit lines BL1 to BLn, or may sense the voltage or current of the bit lines BL1 to BLn during a read operation or a verification operation.

[0073] More specifically, during a program operation, when a program voltage is applied to a selected word line, the first to n-th page buffers PB1 to PBn may transmit data DATA received through the input / output circuit 125 to a selected memory cell through the first to n-th bit lines BL1 to BLn. Memory cells of a page selected according to the transmitted data DATA may be programmed. During a program verification operation, the first to n-th page buffers PB1 to PBn may read page data from a selected memory cell by sensing a voltage or current received through the first to n-th bit lines BL1 to BLn, respectively.

[0074] During a read operation, in response to control of the column decoder 124 , the first to nth page buffers PB1 to PBn may read data DATA from memory cells of a selected page through the first to nth bit lines BL1 to BLn and output the read data DATA to the input / output circuit 125 .

[0075] During an erase operation, the first to nth page buffers PB1 to PBn may float the first to nth bit lines BL1 to BLn or may apply an erase voltage.

[0076] The column decoder 124 may transfer data between the input / output circuit 125 and the page buffer group 123 in response to the column address CADD. For example, the column decoder 124 may exchange data with the first to nth page buffers PB1 to PBn through the data lines DL, or may exchange data with the input / output circuit 125 through the column lines CL.

[0077] The input / output circuit 125 can be used to Figure 1 The command CMD and the address ADDR received by the memory controller 200 shown and described are transferred to the control logic 130 , or data DATA may be exchanged with the column decoder 124 .

[0078] During a read operation or a verification operation, the sensing circuit 126 may generate a reference current in response to an enable bit VRYBIT signal and compare a sensing voltage VPB received from the page buffer group 123 with a reference voltage generated by the reference current to output a pass signal PASS or a fail signal FAIL.

[0079] The control logic 130 can control the peripheral circuit 120 by outputting an operation signal OPSIG, a row address RADD, a page buffer control signal PBSIGNALS, and an enable bit VRYBIT in response to a command CMD and an address ADDR. For example, the control logic 130 can control the read operation of the selected storage block in response to a sub-block read command and an address. In addition, the control logic 130 can control the erase operation of the selected sub-block included in the selected storage block in response to a sub-block erase command and an address. In addition, the control logic 130 can determine whether the verification operation passes or fails in response to a pass signal PASS or a fail signal FAIL. The control logic 130 can be implemented as hardware, software, or a combination of hardware and software. For example, the control logic 130 can be a control logic circuit operating according to an algorithm and / or a processor that executes a control logic code.

[0080] Figure 3 It is shown Figure 2 A diagram of an embodiment of a memory cell array 110 is shown.

[0081] Reference Figure 2 and Figure 3 , Figure 3 It is shown that the Figure 2 1 is a circuit diagram of one memory block BLKa among a plurality of memory blocks BLK1 to BLKz in the memory cell array 110 shown.

[0082] The first selection line, the word line, and the second selection line arranged in parallel to each other may be connected to the memory block BLKa. For example, the word line may be arranged in parallel to each other between the first selection line and the second selection line. The first selection line may be a source selection line SSL, and the second selection line may be a drain selection line DSL.

[0083] More specifically, the memory block BLKa may include a plurality of strings connected between the bit lines BL1 to BLn and the source line SL. The bit lines BL1 to BLn may be connected to the strings, respectively, and the source line SL may be connected to the strings in common. Since the strings may have the same configuration, the string ST connected to the first bit line BL1 is described as an example.

[0084] The string ST may include a source selection transistor SST, a plurality of memory cells F1 to F16, and a drain selection transistor DST connected in series between a source line SL and a first bit line BL1. Each string ST may include at least one source selection transistor SST, at least one drain selection transistor DST, and a plurality of memory cells F1 to F16 connected in series between a source line SL and a first bit line BL1. Figure 3 Memory cells F1 to F16 are shown as more memory cells.

[0085] The source of the source selection transistor SST may be connected to the source line SL, and the drain of the drain selection transistor DST may be connected to the first bit line BL1. The memory cells F1 to F16 may be connected in series between the source selection transistor SST and the drain selection transistor DST. The gates of the source selection transistors SST included in different strings ST may be connected to the source selection line SSL, the gates of the drain selection transistors DST may be connected to the drain selection line DSL, and the gates of the memory cells F1 to F16 may be connected to a plurality of word lines WL1 to WL16, respectively. A group of memory cells connected to the same word line among the memory cells included in different strings ST may be referred to as a physical page PPG. Therefore, the memory block BLKa may include as many physical pages PPG as the number of word lines WL1 to WL16.

[0086] A single memory cell can store one bit of data. Typically, this memory cell is called a single-level cell (SLC). One physical page (PPG) including an SLC can store data of one logical page (LPG). The data of one LPG can include as many data bits as the number of memory cells included in one PPG. Alternatively, a single memory cell can store two or more bits of data. Typically, this memory cell is called a multi-level cell (MLC). One PPG including an MLC can store data of two or more logical LPGs.

[0087] A single memory cell storing two or more bits of data may be referred to as a multi-level cell (MLC). However, recently, as the number of data bits stored in a single memory cell increases, a multi-level cell (MLC) may refer to a memory cell storing two bits of data, a memory cell storing three or more bits of data is referred to as a three-level cell (TLC), and a memory cell storing four or more bits of data is referred to as a quad-level cell (QLC). In addition to the above-mentioned memory cells, various types of memory cells storing multi-bit data have been developed, and this embodiment may be applied to a memory device 100 storing two or more bits of data.

[0088] According to another embodiment, the memory block may have a three-dimensional structure. Each memory block may include a plurality of memory cells stacked above a substrate. The plurality of memory cells may be arranged in the +X direction, the +Y direction, and the +Z direction.

[0089] Figure 4 It is shown that the Figure 1 A diagram of multiple dies in memory device 100 is shown.

[0090] Reference Figure 4 , the memory device 100 may include a first die DIE1 and a second die DIE2. The first die DIE1 and the second die DIE2 may be connected to the memory controller 200 through a first channel CH1 and a second channel CH2, respectively. Each of the first die DIE1 and the second die DIE2 may include a plurality of planes. Each of the plurality of planes may include a plurality of memory blocks. Each of the plurality of memory blocks may include a plurality of pages. Each of the plurality of pages may include a plurality of memory cells.

[0091] according to Figure 4 In the illustrated embodiment, the memory device 100 includes two dies, namely a first die DIE1 and a second die DIE2. However, according to another embodiment, the memory device 100 may include more than two dies.

[0092] Depending on the implementation, the multiple dies may perform operations independently of each other. In other words, the multiple dies may perform operations simultaneously or at different times.

[0093] The memory controller 200 may control operations performed on the first die DIE1 and the second die DIE2 independently of each other through the channels CH1 and CH2, respectively. For example, the memory controller 200 may control operations performed on the first die DIE1 through the first channel CH1 and operations performed on the second die DIE2 through the second channel CH2.

[0094] Therefore, the memory controller 200 may output commands CMD, addresses, and data through respective channels to perform operations on the first die DIE1 and the second die DIE2. Operations may be performed on the first die DIE1 and the second die DIE2 based on the commands CMD, addresses, and data received through the first channel CH1 and the second channel CH2. The operations performed on the first die DIE1 and the second die DIE2 may be programming (or writing) operations, reading operations, or erasing operations. Data of the first die DIE1 and the second die DIE2 may be transmitted to the memory controller 200 through the first channel CH1 and the second channel CH2, respectively.

[0095] When operations are performed on a plurality of dies in response to the control of the storage controller 200, the plurality of dies may consume current (power). The currents respectively consumed by the plurality of dies may vary according to the operations. For example, the current consumed during a programming operation, a read operation, or an erase operation may vary. In addition, the current consumed during a precharge operation, a discharge operation, or a pulse application operation included in a programming operation, a read operation, or an erase operation may vary.

[0096] According to an embodiment, when an operation in which all of the plurality of dies consume peak current is performed, the reliability of the memory device may be degraded. In other words, since the amount of current consumed by the memory device becomes maximum, it may be difficult to ensure the reliability of data stored in the memory device.

[0097] When it is predicted that multiple dies are to perform operations that all consume peak current, operations on dies other than one die are suspended until the operation on the one die is completed. However, this method may delay the completion of the operation and may be inefficient.

[0098] Therefore, according to an embodiment of the present disclosure, a method for operating a die may be provided. More specifically, according to the method for operating a die, when all signals received from a plurality of dies are busy signals, the busy time period is subdivided into sub-periods, and the operation of the die is suspended only during the sub-periods in which the peak current occurs.

[0099] Figure 5 is a graph showing the amount of current consumed by each of two dies and the total amount of current obtained by adding the amounts of current consumed by the dies.

[0100] Figure 5 Changes in the amount of current consumed by each die, the ready / busy signal R / B output from each die, and the total amount of current obtained by adding the amounts of current consumed by the first die DIE1 and the second die DIE2 are shown.

[0101] According to an embodiment, the first die DIE1 and the second die DIE2 may perform an operation only during the time period t11 to t17. In other words, each of the first current CURRENT1 indicating the amount of current consumed by the first die DIE1 and the second current CURRENT2 indicating the amount of current consumed by the second die DIE2 may have a non-zero value only during the time period t11 to t17, and may be "0" at times other than the time period t11 to t17.

[0102] In addition, the ready / busy signal R / B output from the first die DIE1 and the second die DIE2 may be in a high state at a time before t11 and a time after t17, and may be in a low state during a period t11 to t17. In other words, the first die DIE1 and the second die DIE2 may be in a ready state before time t11 and after time t17, and may be in a busy state only during a period t11 to t17.

[0103] As a result, during the time before t11 and during the time after t17, since the first die DIE1 and the second die DIE2 are in a standby state in which no operation is performed, the first total current CUR_SUM1 obtained by adding the current amounts consumed by the first die DIE1 and the second die DIE2 may be 0. However, the first total current CUR_SUM1 during the period t11 to t17 may take a value obtained by adding the current amounts consumed during the respective sub-periods within the period t11 to t17.

[0104] exist Figure 5 , it is assumed that each of the first die DIE1 and the second die DIE2 performs a program operation. Therefore, a precharge operation, a discharge operation, a program voltage applying operation, a verification voltage applying operation, a pass voltage applying operation, etc. may be performed during the period t11 to t17.

[0105] For example, a period t11 to t17 in which a program operation is performed may be subdivided into sub-periods t11 to t12, t12 to t13, t13 to t14, t14 to t15, t15 to t16, and t16 to t17 in which sub-operations of the program operation are performed. The amount of current consumed during each sub-period may vary depending on the sub-operation being performed in the sub-period. In other words, the first current CURRENT1 and the second current CURRENT2 may have various values ​​that vary from sub-period to sub-period according to the sub-operations performed by each die.

[0106] According to an embodiment, both the first die DIE1 and the second die DIE2 may consume a peak current during a sub-period t12 to t13 among the busy sub-periods in the period t11 to t17. In other words, during the sub-period t12 to t13, an operation consuming a peak current among sub-operations included in a programming operation may be simultaneously performed on the first die DIE1 and the second die DIE2, and a first total current CUR_SUM1 obtained by adding the current amounts consumed by the first die DIE1 and the second die DIE2 may have a maximum value.

[0107] When multiple dies consume peak current during the same busy period, the operation of one of the dies may be suspended until the entire busy period is over. However, when the operation of one of the dies is suspended until the busy period is over, the completion of the operation may be delayed and inefficient.

[0108] Figure 6 is a diagram showing the operation of two dies during a period when the peak currents of the dies overlap.

[0109] Figure 6 The ready / busy signals R / B output from the first die DIE1 and the second die DIE2 are shown.

[0110] Initially, it can be predicted that the first die DIE1 and the second die DIE2 are in a busy state during the period t21 to t22. In other words, during the period t21 to t22, the ready / busy signal R / B output from the first die DIE1 and the second die DIE2 may be in a low state, and at times outside the period t21 to t22, the ready / busy signal R / B output from the first die DIE1 and the second die DIE2 may be in a high state.

[0111] However, in the period t21 to t22, peak current may occur for both dies. In other words, the period in which the amount of current consumed by the first die DIE1 is at a peak may be the same period in which the amount of current consumed by the second die DIE2 is at a peak.

[0112] When the peak currents of multiple dies appear in the same time period, the operation of the dies except one die can be delayed DELAY until the busy state of the one die ends. Therefore, the peak currents now appear in different time periods.

[0113] In other words, refer to Figure 6 , when the peak current of each die appears in the same period t21 to t22, Figure 4 The memory device 100 shown may suspend the operation on the second die DIE2 during the entire period t21 to t22 when the first die DIE1 is in the busy state, may delay the operation to be performed on the second die DIE2 by DELAY, and may perform the delayed operation on the second die DIE2 during a later period t22 to t23. Figure 6 As shown, the ready / busy signal R / B output from the second die DIE2 may be in a high state outside the period t22 to t23 and in a low state during the period t22 to t23.

[0114] As a result, when the peak currents of the first die DIE1 and the second die DIE2 overlap each other in the same period, Figure 4 The illustrated memory device 100 may suspend operation of one die (i.e., according to Figure 6 In the embodiment shown, the second die DIE2 may be suspended until a later period of time. The operation of the second die DIE2 may be suspended until the busy state of the first die DIE1 ends.

[0115] When the operation of the second die DIE2 is suspended until the busy state of the first die DIE1 ends, a delay time of the operation performed on the second die DIE2 may increase, and the operation may be inefficient.

[0116] Therefore, the present disclosure teaches a method of delaying operation only during the sub-period when the peak current occurs.

[0117] Figure 7 is a diagram illustrating preventing peak currents of different dies from occurring during the same sub-period according to an embodiment.

[0118] Reference Figure 5 and Figure 7 , Figure 7 Show that Figure 5 The implementation of sub-period delay is shown when the peak currents of different dies initially occur during the same sub-period. In other words, Figure 7 The second current CURRENT2 consumed by the second die DIE2 and the ready / busy signal R / B outputted from the second die DIE2 correspond to the Figure 5 The amount of current and the signal when the operation performed by the second die DIE2 is delayed are shown.

[0119] According to an embodiment, in Figure 5 and Figure 7 In the embodiment, the first current CURRENT1 consumed by the first die DIE1 and the ready / busy signal R / B outputted from the first die DIE1 are the same. Figure 5 The sub-periods in which the peak currents appear in the first die DIE1 and the second die DIE2 overlap each other, so Figure 5 The second current CURRENT2 consumed by the second die DIE2 and the ready / busy signal R / B output from the second die DIE2 may be different from Figure 7 A second current CURRENT2 consumed by the second die DIE2 and a ready / busy signal R / B output from the second die DIE2 are shown.

[0120] According to an embodiment, a sub-period in which a peak current appears in the first die DIE1 may overlap with a sub-period in which a peak current appears in the second die DIE2. Since the periods in which the peak current appears overlap with each other, the operation of the second die DIE2 may be delayed between the first die DIE1 and the second die DIE2. Alternatively, according to another embodiment, the operation of the first die DIE1 may be delayed between the first die DIE1 and the second die DIE2.

[0121] Reference Figure 5 According to an embodiment, peak current occurs in both the first die DIE1 and the second die DIE2 during the sub-period t12 to t13, and the operation performed on the second die DIE2 may be suspended during the sub-period t12 to t13. In other words, the operation performed on the second die DIE2 may be delayed and performed later.

[0122] For example, the operation performed on the second die DIE2 may be suspended during the sub-period t12 to t13, and the ready / busy signal R / B output from the second die DIE2 may be in a high state. In other words, the ready / busy signal R / B indicating that the second die DIE2 is in a standby state may be output. Since the operation performed on the second die DIE2 is suspended, the second current CURRENT2 consumed by the second die DIE2 may be "0". The suspended operation may be delayed for as long as the time of the sub-period in which the peak current overlap occurs.

[0123] Reference Figure 7 , a sub-period during which the peak current appears in the first die DIE1 and the second die DIE2 is t12 to t13, and the operation performed on the second die DIE2 may be suspended during the sub-period t12 to t13 (at time t13 minus t12, tsus).

[0124] According to an embodiment, the operation delayed in sub-period t12 to t13 may be performed during period t13 to t14. In other words, the operation performed on the second die DIE2 may be suspended for as long as the sub-period in which the peak current overlap occurs, and the suspended operation may be resumed later.

[0125] Due to the sub-period delay introduced above, the sub-period in which the peak current appears in the first die DIE1 is no longer the same sub-period in which the peak current appears in the second die DIE2. In other words, the sub-period in which the peak current appears in the first die DIE1 is still t12 to t13, while the sub-period in which the peak current appears in the second die DIE2 has shifted to t13 to t14.

[0126] Therefore, since the operation performed on the second die DIE2 is delayed, the ready / busy signal R / B output from the second die DIE2 may be in a low state during the sub-period t13 to t28. In other words, the operation performed on the second die DIE2 may be delayed by the time tsus, and the ready / busy signal R / B in a low state may be output during the sub-period t17 to t28.

[0127] Thereafter, when the sub-periods in which the peak currents occur in the first die DIE1 and the second die DIE2 overlap each other again, the operation on one of the first die DIE1 and the second die DIE2 may be suspended again.

[0128] As a result, when sub-periods in which peak currents occur overlap with each other in a plurality of dies, an operation on at least one of the plurality of dies may be delayed by the time the sub-periods overlap with each other and then performed, so that the overlap of the sub-periods in which the peak currents occur may be mitigated. When the overlap of the sub-periods in which the peak currents occur is mitigated, the reliability of data stored in the storage device may be improved.

[0129] Figure 8 It is shown Figure 5 The total current and Figure 7 A diagram showing a comparison between the total current amounts.

[0130] Reference Figure 5 , Figure 7 and Figure 8 , Figure 8 Show Figure 5 The first total current CUR_SUM1 shown and the Figure 7 The second total current CUR_SUM2 is obtained by adding the first current CURRENT1 and the second current CURRENT2 shown in FIG. Figure 8 Shown as Figure 5 The first total current CUR_SUM1 is the total current consumed by the first die DIE1 and the second die DIE2 when the operation performed on the second die DIE2 is not delayed, and the total current consumed by the first die DIE1 and the second die DIE2 is the total current consumed by the first die DIE1 and the second die DIE2 when the operation performed on the second die DIE2 is not delayed. Figure 7 A second total current CUR_SUM2 is shown as the total amount of current consumed by the first die DIE1 and the second die DIE2 when the operation performed on the second die DIE2 is delayed.

[0131] Reference Figure 5 , the first total current CUR_SUM1 may refer to a total amount of current consumed by the first die DIE1 and the second die DIE2 when an operation on one of the first die DIE1 and the second die DIE2 is not delayed even when there is a period in which sub-periods in which peak currents occur in the first die DIE1 and the second die DIE2 overlap.

[0132] According to an embodiment, during period t12 to t13, since operation of one of the first and second dies DIE1 and DIE2 is not delayed, the first total current CUR_SUM1 may have a maximum value. In addition, the deviation of the value of the first total current CUR_SUM1 may be large according to the sub-period.

[0133] However, referring to Figure 7 The second total current CUR_SUM2 may refer to a total amount of current consumed by the first die DIE1 and the second die DIE2 when operation on the second die DIE2 is delayed due to overlap of a sub-period during which a peak current occurs in the first die DIE1 and a period during which a peak current occurs in the second die DIE2.

[0134] According to an embodiment, during the sub-period t13 to t14 instead of the sub-period t12 to t13, the second total current CUR_SUM2 may have a maximum value because the operation performed on the second die DIE2 is delayed. In addition, the deviation of the value of the second total current CUR_SUM2 may be small according to the period.

[0135] Fig. 9 It is shown Figure 1 FIG. 2 is a diagram showing a configuration of the storage controller 200 and a process of outputting a pause command.

[0136] Fig. 9 The illustrated memory controller 200 may include a state information determination component 210 and a peak current controller 220 .

[0137] According to an embodiment, the state information determining component 210 may receive a ready / busy signal R / B from each of the plurality of dies included in the memory device 100. The ready / busy signal R / B may indicate whether the die is in a busy state where the die performs an operation or a ready state where the die does not perform an operation.

[0138] According to an embodiment, when all ready / busy signals R / B received from the plurality of dies respectively indicate a busy state (i.e., a low state), the state information determination component 210 may output a state read command SR_CMD to the memory device 100. According to an embodiment, the state read command SR_CMD may be output to determine whether the amount of current consumed by each die and the period in which the peak current occurs overlap. In other words, the state read command SR_CMD may indicate that information on the amount of current consumed by the die should be output.

[0139] The memory device 100 may output status information STATUS_INF in response to the status read command SR_CMD. The status information STATUS_INF may include information on the amount of current consumed by each die when all of the plurality of dies are in a busy state.

[0140] For example, the period in which the busy state is maintained may be divided into a plurality of sub-periods, and information about the amount of current consumed by each die per sub-period may be included in the state information STATUS_INF. In other words, the memory device 100 may divide the busy period (i.e., the period in which the busy state is maintained) into a plurality of sub-periods, and may output information about the amount of current consumption per die corresponding to each of the plurality of sub-periods.

[0141] According to an embodiment, the period may be divided into a plurality of sub-periods according to a predetermined length or a predetermined operation. In other words, the period in which the busy state is maintained may be divided into sub-periods each having a predetermined length, or may be divided according to a busy sub-operation (e.g., a precharge operation, a discharge operation, or a voltage application operation).

[0142] According to an embodiment, the status information determining component 210 may receive the status information STATUS_INF. The status information determining component 210 may determine whether to suspend the operation of at least one die among the plurality of dies included in the memory device 100 and the time when the operation is suspended based on the status information STATUS_INF.

[0143] For example, when it is determined based on the status information STATUS_INF that the sub-periods in which the peak currents occur in the plurality of dies overlap with each other, the status information determination component 210 may determine to suspend the operation of at least one of the plurality of dies. In addition, the status information determination component 210 may determine to suspend the operation in the sub-period in which the peak currents overlap.

[0144] When the state information determination component 210 determines to suspend the operation of at least one die among the plurality of dies included in the memory device 100, the state information determination component 210 may generate the suspension information SUSPEND_INF. The suspension information SUSPEND_INF may include information about the die for which the operation is suspended and information about the sub-period during which the operation of the corresponding die is suspended. The state information determination component 210 may output the generated suspension information SUSPEND_INF to the peak current controller 220.

[0145] The peak current controller 220 may output the suspend command SUSPEND_CMD to the memory device 100 based on the suspend information SUSPEND_INF. In other words, the peak current controller 220 may control the corresponding die to suspend the operation to be performed on the corresponding die during the suspend sub-period included in the suspend information SUSPEND_INF (i.e., the sub-period in which the operation on the corresponding die is suspended).

[0146] According to an embodiment, the memory device 100 may receive the suspend command SUSPEND_CMD from the peak current controller 220 and suspend the operation of the corresponding die based on the suspend command SUSPEND_CMD.

[0147] After suspending the operation of the corresponding die in response to the suspend command SUSPEND_CMD, the peak current controller 220 may output a resume command to resume the suspended operation when the suspend sub-period ends.

[0148] Fig.10 is a diagram showing a method of subdividing overlapping busy periods.

[0149] Fig.10 Shown when from Fig. 9The plurality of sub-periods included in the status information STATUS_INF when all ready / busy signals R / B outputted by the plurality of dies included in the illustrated memory device 100 indicate a busy state.

[0150] exist Fig.10 In, assuming Fig. 9 The number of dies included in the memory device 100 shown is two. Fig.10 In, assuming Fig. 9 The memory device 100 shown comprises a first die DIE1 and a second die DIE2. According to another embodiment, Fig. 9 The illustrated memory device 100 may include more than two dies.

[0151] According to an embodiment, all ready / busy signals R / B output from the first die DIE1 and the second die DIE2 may indicate a busy state. In other words, the first die DIE1 and the second die DIE2 may be in a busy state at the same time.

[0152] Reference Fig.10 , during the period t21 to t26, both the first die DIE1 and the second die DIE2 may be in a busy state in which the first die DIE1 and the second die DIE2 perform operations.

[0153] Fig. 9 The state information determination component 210 shown may provide Fig. 9 The memory device 100 shown outputs a status read command SR_CMD, and Fig. 9 The illustrated memory device 100 may output status information STATUS_INF corresponding to the status read command SR_CMD to mitigate overlap of peak currents of the first die DIE1 and the second die DIE2. The status information STATUS_INF may divide a busy period into a plurality of sub-periods and may include information on the amount of current consumed during the plurality of sub-periods.

[0154] exist Fig.10 In the embodiment, the busy period of each of the first die DIE1 and the second die DIE2 may be divided into sub-periods A1 to A9. The busy period may be divided into sub-periods A1 to A9 according to the length of a predetermined sub-period or the length of a predetermined operation (eg, a precharge operation, a discharge operation, or a voltage application operation).

[0155] According to an embodiment, sub-period A1 may correspond to period t21 to t22, sub-period A3 may correspond to sub-period t22 to t23, sub-period A5 may correspond to sub-period t23 to t24, sub-period A7 may correspond to period t24 to t25, and sub-period A9 may correspond to period t25 to t26. Therefore, Fig. 9The illustrated memory device 100 may generate information on the amount of current consumed during each sub-period in response to a status read command SR_CMD and may output the generated information as status information STATUS_INF.

[0156] Reference Fig.11A and Fig. 11B describe Fig. 9 The method in which the memory device 100 outputs the status information STATUS_INF is shown.

[0157] Fig.11A and Fig. 11B 2 is a diagram showing status information STATUS_INF output from the memory device 100 .

[0158] Reference Fig.11A and Fig. 11B , Fig.11A The binary number BINARYNUMBER corresponding to the current consumption CURRENT is shown. Fig. 11B A method of outputting status information STATUS_INF is shown.

[0159] According to an embodiment, the current consumption amount CURRENT may have a value from 0 to 100 and may be a value belonging to Fig.11A The current consumption CURRENT can be expressed in milliamperes (mA), microamperes (μA), or nanoamperes (nA).

[0160] exist Fig.11A In the embodiment, the current consumption CURRENT may belong to a range among the predetermined ranges. According to an embodiment, when the current consumption CURRENT increases, the range may be subdivided into more ranges. In other words, in order to minimize the overlap of the period when the peak current occurs, when the current consumption CURRENT increases, the range may be subdivided into more ranges.

[0161] Reference Fig.11AIn the example shown, when the current consumption CURRENT falls within the range of 0 to 50 units, the binary number BINARY NUMBER corresponding to the current consumption CURRENT may be "00". When the current consumption CURRENT falls within the range of 51 to 75 units, the binary number BINARY NUMBER corresponding to the current consumption CURRENT may be "01". When the current consumption CURRENT falls within the range of 76 to 90 units, the binary number BINARY NUMBER corresponding to the current consumption CURRENT may be "10". When the current consumption CURRENT falls within the range of 91 to 100 units, the binary number BINARY NUMBER corresponding to the current consumption CURRENT may be "11".

[0162] According to another embodiment, when the range to which the current consumption CURRENT belongs is divided into five or more ranges, the binary number BINARY NUMBER for indicating the corresponding current consumption CURRENT may be one of "000", "001", "010", "011", "100", "101", "110", and "111". In other words, when the range to which the current consumption CURRENT belongs is divided into more ranges, the number of bits for indicating the corresponding current consumption CURRENT may increase.

[0163] Reference Fig. 11B The status information STATUS_INF is represented by eight bits and can be obtained by Fig. 9 The memory device 100 is shown coupled to Fig. 9 The input / output pins DQ1 to DQ8 of the memory controller 200 are shown to output Fig. 9 The memory controller 200 shown. In other words, eight bits indicating the status information STATUS_INF may be output through the input / output pins DQ1 to DQ8.

[0164] In addition, Fig. 9 During the busy periods of the plurality of dies included in the illustrated memory device 100, the busy period may be divided into sub-periods to output status information STATUS_INF per sub-period. In other words, when a bit indicating a current consumption amount CURRENT corresponding to one of the plurality of sub-periods is output through the input / output pins DQ1 to DQ8, a bit indicating a current consumption amount CURRENT corresponding to a sub-period after the one sub-period may be output.

[0165] According to an embodiment, when the amount of current consumed by the die belongs to the range of 0 to 50, the binary number BINARY NUMBER corresponding to the current consumption CURRENT may be "00". Therefore, Fig. 9 The illustrated memory device 100 may output “0” through the input / output pin DQ1 and output “0” through the input / output pin DQ2 .

[0166] According to an embodiment, when the amount of current consumed by the die is in the range of 51 to 75, the binary number BINARY NUMBER corresponding to the current consumption CURRENT may be "01", "0" may be output through the input / output pin DQ1, and "1" may be output through the input / output pin DQ2. When the amount of current consumed by the die is in the range of 76 to 90, the binary number BINARY NUMBER corresponding to the current consumption CURRENT may be "10", "1" may be output through the input / output pin DQ1, and "0" may be output through the input / output pin DQ2. When the amount of current consumed by the die is in the range of 91 to 100, the binary number BINARY NUMBER corresponding to the current consumption CURRENT may be "11", "1" may be output through the input / output pin DQ1, and "1" may be output through the input / output pin DQ2.

[0167] According to an embodiment, information indicating the ready / busy state of the die and / or information indicating whether an operation performed on the die passes or fails may be represented by the remaining bits except for the two bits indicating the amount of current consumed by the die among the eight bits of the indication status information STATUS_INF.

[0168] According to another embodiment, when the range to which the current consumption amount CURRENT belongs is divided into five or more ranges, the current consumption amount CURRENT may be represented by three or more bits among eight bits indicating the status information STATUS_INF.

[0169] Fig.12 2 is a diagram showing a method of determining whether sub-periods in which peak currents occur overlap based on the status information STATUS_INF. For example, whether the peak currents of each of DIE 1 and DIE 2 occur in the same sub-period.

[0170] Reference Fig.10 , Fig.11A , Fig. 11B and Fig.12 , Fig.12 The first column of the table shown may indicate Fig.10 The second column can indicate the sub-periods A1 to A9 shown in FIG. Fig.10 The third column may indicate the binary number corresponding to the current consumed by the first die DIE1 during the sub-periods A1 to A9 shown in FIG. Fig.10The binary number corresponding to the amount of current consumed by the second die DIE2 during the sub-periods A1 to A9 is shown.

[0171] According to an embodiment, during the sub-periods A1 to A9, the first die DIE1 and the second die DIE2 may be in a busy state. The busy state of the first die DIE1 and the second die DIE2 may be divided into sub-periods A1 to A9, and the amount of current consumed by the first die DIE1 and the second die DIE2 during each of the sub-periods A1 to A9 may be output as the status information STATUS_INF to Fig. 9 A storage controller 200 is shown.

[0172] Fig. 9 The storage controller 200 shown may be based on Fig. 9 The illustrated memory device 100 receives status information STATUS_INF to determine whether sub-periods in which peak currents occur overlap with each other.

[0173] For example, since the binary number corresponding to the amount of current consumed by the first die DIE1 during the sub-period A1 is "11", and the binary number corresponding to the amount of current consumed by the second die DIE2 during the sub-period A1 is "11", during the period A1, the sub-periods in which the peak currents appear in the first die DIE1 and the second die DIE2 may overlap. In other words, since the currents consumed by the respective dies are both in accordance with the indication Fig.11A The range of maximum current consumption shown corresponds to a binary number, so during the sub-period A1 , the peak current in the first die DIE1 and the peak current in the second die DIE2 may occur simultaneously.

[0174] therefore, Fig. 9 The storage controller 200 shown may provide Fig. 9 The memory device 100 is shown outputting an indication Fig. 9 The illustrated memory device 100 suspends the operation of one of the first die DIE1 and the second die DIE2 by a suspend command for a time corresponding to the sub-period A1.

[0175] When the pause command is output to Fig. 9 The memory device 100 shown in FIG. Fig. 9 The illustrated memory device 100 may suspend the operation on one of the first die DIE1 and the second die DIE2 for a time corresponding to the sub-period A1 in response to the suspend command.

[0176] Fig.13 is a diagram illustrating the operation of a memory controller according to an embodiment.

[0177] Reference Fig.13In step S1301, when the memory controller receives the busy signal from all the multiple dies, the memory controller may output a status read command to each die. The status read command may be output to determine the amount of current consumed by each die and whether the sub-periods in which the peak current occurs overlap. In other words, the status read command may instruct the die to output information about the amount of current consumed by the die.

[0178] In step S1303, the memory controller may receive status information corresponding to the status read command from the memory device. The status information may include information about the amount of current consumed by each die when all of the plurality of dies are in a busy state. In addition, the status information may divide a period of maintaining the busy state into a plurality of sub-periods, and may include information about the amount of current consumed by each die per sub-period.

[0179] In step S1305, the storage controller may generate pause information based on the state information. For example, when the current consumption corresponding to a predetermined sub-period among a plurality of sub-periods in both the first die and the second die has a maximum value, the storage controller may generate pause information. In other words, when the sub-periods in which the peak currents in the first die and the second die overlap, the storage controller may generate pause information. The pause information may include information about the die whose operation is suspended between the first die and the second die and information about the time when the operation is suspended. The time when the operation is suspended may correspond to the sub-period in which the peak currents of the first die and the second die overlap.

[0180] However, when the current consumption amount corresponding to a predetermined sub-period among the plurality of sub-periods is not a peak current in any one of the first die and the second die, the memory controller may not generate the suspend information.

[0181] In step S1307, the storage controller may output a pause command based on the pause information. In other words, since the pause information includes information about the die whose operation is suspended among the plurality of dies and information about the time when the operation is suspended, the storage controller may output a pause command to the memory device instructing the corresponding die to suspend the operation for a predetermined time based on the pause information.

[0182] Fig.14 is a diagram illustrating the operation of a memory controller according to an embodiment.

[0183] Reference Fig.14 In step S1401, the memory controller may add the current amounts consumed by the plurality of dies per sub-period based on the state information received from the memory device. The state information may include information about the current amounts consumed by the respective dies when all the plurality of dies are in a busy state. In addition, the state information may divide the period in which the busy state is maintained into a plurality of sub-periods, and may include information about the current amounts consumed by the respective dies per sub-period.

[0184] In step S1403, the memory controller may determine whether there is a sub-period in which the peak currents of different dies overlap among the plurality of sub-periods. In other words, the memory controller may add the currents consumed by the plurality of dies per sub-period, and may determine whether the sub-periods in which the peak currents appear in the respective dies overlap based on the result obtained by adding the current consumptions.

[0185] When there is no period in which sub-periods of peak current occur in multiple dies overlapping each other (S1403: No), the processing flow may proceed to step S1401 again, and the storage controller may add the amount of current consumed in each sub-period by receiving status information when all dies included in the memory device become busy.

[0186] However, when there is a period in which the sub-periods in which the peak currents appear in a plurality of dies overlap ( S1403 : Yes), the process flow may proceed to step S1405 .

[0187] In step S1405, the memory controller may output a pause command to at least one of the plurality of dies. In other words, a pause command indicating that the operation of the at least one die should be paused may be output to mitigate the overlap of the periods in which the peak currents appear in the plurality of dies in the same sub-period. The time during which the operation is paused may correspond to the sub-period in which the peak currents overlap.

[0188] In step S1407, the storage controller may output a resume command to resume the suspended operation of the die. In other words, since the suspended operation should be resumed for the die whose operation was suspended by the suspend command when the time for suspending the operation has passed, the storage controller may output a resume command to the memory device.

[0189] Fig.15 It is shown Figure 1 A diagram of another embodiment of a storage controller is shown.

[0190] The storage controller 1000 may be connected to a host and a memory device. In response to a request from the host, the storage controller 1000 may access the memory device. For example, the storage controller 1000 may control a read operation, a program operation, an erase operation, and a background operation of the memory device. The storage controller 1000 may provide an interface between the memory device and the host. The storage controller 1000 may run firmware for controlling the memory device.

[0191] Reference Fig.15 , the memory controller 1000 may include a processor 1010 , a memory buffer 1020 , an error correction code (ECC) block 1030 , a host interface 1040 , a buffer controller 1050 , a memory interface 1060 , and a bus 1070 .

[0192] The bus 1070 may provide a channel between the components of the memory controller 1000 .

[0193] The processor 1010 may control the overall operation of the memory controller 1000 and may perform logic operations. The processor 1010 may communicate with an external host through a host interface 1040 and communicate with a memory device through a memory interface 1060. In addition, the processor 1010 may communicate with a memory buffer 1020 through a buffer controller 1050. The processor 1010 may control the operation of the memory device using the memory buffer 1020 as an operating memory, a cache memory, or a buffer memory.

[0194] The processor 1010 may perform the function of a flash translation layer (FTL). The processor 1010 may convert a logical block address (LBA) provided by a host into a physical block address (PBA) through the FTL. The FTL may receive the LBA and convert the received LBA into a PBA using a mapping table. Depending on the mapping unit, there may be various address mapping methods for the FTL. Typical address mapping methods include a page mapping method, a block mapping method, and a hybrid mapping method.

[0195] The processor 1010 may randomize the data received from the host. For example, the processor 1010 may randomize the data received from the host using a randomization seed. The randomized data may be provided to the memory device as data to be stored and may be programmed in the memory cell array.

[0196] According to an embodiment, the processor 1010 may execute software or firmware to perform randomization operations and de-randomization operations.

[0197] According to an embodiment, the processor 1010 may be based on Fig. 9 The memory device 100 receives status information to determine Fig. 9 The amount of current consumed by each of the plurality of dies included in the memory device 100 shown. For example, the amount of current consumed by each of the plurality of dies included in the memory device 100 shown in FIG. Fig. 9 The status response command output when all the dies included in the memory device 100 are in the busy state is from Fig. 9 The illustrated memory device 100 outputs status information. The status information may divide a busy period of each die into a plurality of sub-periods having the same length, and may include information on an amount of current consumed by each die corresponding to each of the plurality of sub-periods.

[0198] The processor 1010 may determine whether the sub-periods in which the peak currents appear in the plurality of dies overlap based on the state information. In other words, the processor 1010 may determine whether Fig. 9All dies included in the memory device 100 shown consume the maximum current and whether the sub-periods in which the dies consume the maximum current overlap.

[0199] According to an embodiment, when the sub-periods in which the peak currents appear in the multiple dies overlap, the processor 1010 may output a pause command. The pause command may indicate that when the periods in which the peak currents appear in the multiple dies overlap, the operation of at least one of the multiple dies should be delayed by the sub-period in which the periods in which the peak currents appear in the multiple dies overlap.

[0200] Fig. 9 The illustrated memory device 100 may delay the operation on the corresponding die in response to the suspend command by as long as the sub-periods in which the sub-periods in which the peak currents occur in the plurality of dies overlap.

[0201] The memory buffer 1020 may be used as an operation memory, a cache memory, or a buffer memory of the processor 1010. The memory buffer 1020 may store codes and commands executed by the processor 1010. The memory buffer 1020 may store data processed by the processor 1010. The memory buffer 1020 may include a static RAM (SRAM) or a dynamic RAM (DRAM).

[0202] The ECC block 1030 may perform error correction. The ECC block 1030 may perform ECC encoding based on data to be written to the memory device through the memory interface 1060. The ECC-encoded data may be transmitted to the memory device through the memory interface 1060. The ECC block 1030 may perform ECC decoding based on data received from the memory device through the memory interface 1060. For example, the ECC block 1030 may be included as a component of the memory interface 1060 and disposed in the memory interface 1060.

[0203] The host interface 1040 may communicate with an external host under the control of the processor 1010. The host interface 1040 may perform communication using at least one of various communication methods such as a universal serial bus (USB), a serial AT attachment (SATA), a serial attached SCSI (SAS), a high-speed inter-chip (HSIC), a small computer system interface (SCSI), a peripheral component interconnect (PCI), PCI Express (PCIe), a high-speed non-volatile memory (NVMe), a universal flash memory (UFS), a secure digital (SD), a multimedia card (MMC), an embedded MMC (eMMC), a dual in-line memory module (DIMM), a registered DIMM (RDIMM), and / or a load reduction DIMM (LRDIMM).

[0204] The buffer controller 1050 may control the memory buffer 1020 under the control of the processor 1010 .

[0205] The memory interface 1060 may communicate with the memory device under the control of the processor 1010. The memory interface 1060 may communicate commands, addresses, and data with the memory device through a channel.

[0206] The memory controller 1000 does not necessarily include the memory buffer 1020 and the buffer controller 1050 in all embodiments. Either or both of these components may be provided separately, or either or both of their functions may be performed by one or more other components in the memory controller 1000.

[0207] For example, the processor 1010 may use code to control the operation of the storage controller 1000. The processor 1010 may load the code from a nonvolatile memory device (e.g., a read only memory (ROM)) provided in the storage controller 1000. In another example, the processor 1010 may load the code from the memory device through the memory interface 1060.

[0208] For example, the bus 1070 of the memory controller 1000 may be divided into a control bus and a data bus. The data bus may transmit data in the memory controller 1000, and the control bus may transmit control information such as commands and addresses in the memory controller 1000. The data bus and the control bus may be isolated from each other so as not to interfere with or affect each other. The data bus may be connected to the host interface 1040, the buffer controller 1050, the ECC block 1030, and the memory interface 1060. The control bus may be connected to the host interface 1040, the processor 1010, the buffer controller 1050, the memory buffer 1020, and the memory interface 1060.

[0209] Fig.16 is a block diagram illustrating a memory card system 2000 to which a memory device is applied according to an embodiment.

[0210] Reference Fig.16 , the memory card system 2000 may include a memory controller 2100 , a memory device 2200 , and a connector 2300 .

[0211] The storage controller 2100 may be connected to the memory device 2200. The storage controller 2100 may access the memory device 2200. For example, the storage controller 2100 may control the read operation, write operation, erase operation, and background operation of the memory device 2200. The storage controller 2100 may provide an interface between the memory device 2200 and the host. The storage controller 2100 may run firmware for controlling the memory device 2200. The memory device 2200 may be operated in accordance with the above reference Figure 1 Description Figure 1 The memory device 100 shown is configured in the same manner.

[0212] For example, the memory controller 2100 may include components such as a random access memory (RAM), a processing unit, a host interface, a memory interface, and an ECC block.

[0213] The storage controller 2100 may communicate with an external device through the connector 2300. The storage controller 2100 may communicate with an external device (e.g., a host) according to a predetermined communication protocol. For example, the storage controller 2100 may communicate with an external device (e.g., a host) through at least one of various communication protocols such as a universal serial bus (USB), a multimedia card (MMC), an embedded MMC (eMMC), a peripheral component interconnect (PCI), a high-speed PCI (PCIe), an advanced technology attachment (ATA), a serial ATA (SATA), a parallel ATA (PATA), a small computer system interface (SCSI), an enhanced small disk interface (ESDI), an integrated drive electronics (IDE), a firewire, a universal flash memory (UFS), Wi-Fi, Bluetooth, and / or a high-speed non-volatile memory (NVMe) protocol. For example, the connector 2300 may be defined by at least one of the various communication protocols described above.

[0214] For example, the memory device 2200 may be specifically implemented as one of various nonvolatile memory devices such as electrically erasable programmable ROM (EEPROM), NAND flash memory, NOR flash memory, phase change RAM (PRAM), resistive RAM (ReRAM), ferroelectric RAM (FRAM), and spin-transfer torque magnetic RAM (STT-MRAM).

[0215] The storage controller 2100 and the memory device 2200 may be integrated into a single semiconductor device to form a memory card. For example, the storage controller 2100 and the memory device 2200 may be integrated into a single semiconductor device and form a memory card such as a Personal Computer Memory Card International Association (PCMCIA), a Compact Flash (CF) card, a Smart Media Card (SM or SMC), a Memory Stick, a Multimedia Card (MMC, RS-MMC, MMCmicro or eMMC), a Secure Digital (SD) card (SD, miniSD, microSD or SDHC), and a Universal Flash Storage (UFS).

[0216] According to an embodiment, the memory controller 2100 may determine the amount of current consumed by each of the plurality of dies included in the memory device 2200 based on the status information received from the memory device 2200. For example, the status information may be output from the memory device 2200 in response to a status response command output when all dies included in the memory device 2200 are in a busy state. The status information may divide a busy period of each die into a plurality of sub-periods having the same length, and may include information on the amount of current consumed by each die corresponding to each of the plurality of sub-periods.

[0217] The memory controller 2100 can determine whether the sub-periods in which the peak current occurs in the plurality of dies overlap based on the state information. In other words, the memory controller 2100 can determine whether the maximum current is consumed in all dies included in the memory device 2200 and whether the sub-periods in which the dies consume the maximum current overlap.

[0218] According to an embodiment, when sub-periods of peak current occurring in a plurality of dies overlap, the memory controller 2100 may output a pause command The pause command may indicate that operation on at least one of the plurality of dies should be delayed by the sub-period of peak current overlap.

[0219] The memory device 2200 may delay the operation on the corresponding die by the sub-period in which the peak currents of the die overlap in response to the suspend command.

[0220] Fig.17 is a block diagram illustrating an example of a solid state drive (SSD) system 3000 to which a storage device is applied according to an embodiment.

[0221] Reference Fig.17 , the SSD system 3000 may include a host 3100 and an SSD 3200. The SSD 3200 may exchange a signal SIG with the host 3100 through a signal connector 3001, and may receive power PWR through a power connector 3002. The SSD 3200 may include an SSD controller 3210, a plurality of flash memories 3221 to 322n, an auxiliary power supply 3230, and a buffer memory 3240.

[0222] According to an embodiment, the SSD controller 3210 may perform the above-mentioned Figure 1 Description Figure 1 The functions of the storage controller 200 are as follows.

[0223] The SSD controller 3210 may control the plurality of flash memories 3221 to 322n in response to a signal SIG received from the host 3100. For example, the signal SIG may be a signal based on an interface of the host 3100 and the SSD 3200. For example, the signal SIG may be defined by at least one of various interfaces such as a universal serial bus (USB), a multimedia card (MMC), an embedded MMC (eMMC), a peripheral component interconnect (PCI), PCI Express (PCIe), an advanced technology attachment (ATA), a serial ATA (SATA), a parallel ATA (PATA), a small computer system interface (SCSI), an enhanced small disk interface (ESDI), an integrated drive electronics (IDE), a firewire, a universal flash memory (UFS), a Wi-Fi, a Bluetooth, and a non-volatile memory express (NVMe) interface.

[0224] According to an embodiment, the SSD controller 3210 may determine the amount of current consumed by each of the plurality of dies included in the plurality of flash memories 3221 to 322n based on the state information received from each of the plurality of flash memories 3221 to 322n. For example, the state information may be output from the plurality of flash memories 3221 to 322n in response to a state response command output when all dies included in the plurality of flash memories 3221 to 322n are in a busy state. The state information may divide the busy period of each die into a plurality of sub-periods having the same length, and may include information on the amount of current consumed by each die corresponding to each of the plurality of sub-periods.

[0225] The SSD controller 3210 may determine whether the sub-periods of the peak current of the die overlap based on the status information. In other words, the SSD controller 3210 may determine whether the maximum current is consumed in all the die included in the plurality of flash memories 3221 to 322n and whether the sub-periods in which the die consumes the maximum current overlap.

[0226] According to an embodiment, when the sub-periods of peak currents in multiple dies overlap, the SSD controller 3210 may output a pause command. The pause command may indicate that operation on at least one of the multiple dies should be delayed by the sub-periods of peak current overlap of the multiple dies.

[0227] The plurality of flash memories 3221 to 322n may delay operation on corresponding dies by a sub-period in which the peak currents overlap in response to the suspend command.

[0228] The auxiliary power supply 3230 may be coupled to the host 3100 through the power connector 3002. The auxiliary power supply 3230 may be charged with the power PWR supplied from the host 3100. When the power PWR is not smoothly supplied from the host 3100, the auxiliary power supply 3230 may supply power to the SSD 3200. For example, the auxiliary power supply 3230 may be provided inside or outside the SSD 3200. For example, the auxiliary power supply 3230 may be provided on a mainboard and may supply auxiliary power to the SSD 3200.

[0229] The buffer memory 3240 may be used as a buffer memory of the SSD 3200. For example, the buffer memory 3240 may temporarily store data received from the host 3100 or data received from the plurality of flash memories 3221 to 322n, or may temporarily store metadata (e.g., a mapping table) of the plurality of flash memories 3221 to 322n. The buffer memory 3240 may include a volatile memory such as DRAM, SDRAM, DDRSDRAM, LPDDR SDRAM, and GRAM, or a nonvolatile memory such as FRAM, ReRAM, STT-MRAM, and PRAM.

[0230] Fig.18 is a block diagram illustrating a user system 4000 to which a storage device is applied according to an embodiment.

[0231] Reference Fig.18 , the user system 4000 may include an application processor 4100 , a memory module 4200 , a network module 4300 , a storage module 4400 , and a user interface 4500 .

[0232] The application processor 4100 may run a component, an operating system (OS), or a user program included in the user system 4000. For example, the application processor 4100 may include a controller, an interface, a graphic engine, etc. for controlling the components included in the user system 4000. The application processor 4100 may be provided as a system chip (SoC).

[0233] The memory module 4200 may be used as a main memory, an operating memory, a buffer memory, or a cache memory of the user system 4000. The memory module 4200 may include a volatile random access memory such as DRAM, SDRAM, DDR SDRAM, DDR2 SDRAM, DDR3 SDRAM, LPDDR SDRAM, LPDDR2 SDRAM, and LPDDR3 SDRAM, or a nonvolatile random access memory such as PRAM, ReRAM, MRAM, and FRAM. For example, the application processor 4100 and the memory module 4200 may be packaged based on a stacked package (POP) to be provided as a single semiconductor package.

[0234] The network module 4300 may communicate with an external device. For example, the network module 4300 may support wireless communications such as code division multiple access (CDMA), global system for mobile communications (GSM), wideband CDMA (WCDMA), CDMA-2000, time division multiple access (TDMA), long term evolution (LTE), Wimax, WLAN, UWB, Bluetooth, or Wi-Fi. For example, the network module 4300 may be included in the application processor 4100.

[0235] The storage module 4400 may store data. For example, the storage module 4400 may store data received from the application processor 4100. Alternatively, the storage module 4400 may transmit the data stored in the storage module 4400 to the application processor 4100. For example, the storage module 4400 may be embodied as a non-volatile semiconductor memory device such as a phase change RAM (PRAM) device, a magnetic RAM (MRAM) device, a resistive RAM (RRAM) device, a NAND flash memory device, a NOR flash memory device, or a NAND flash memory device having a three-dimensional (3D) structure. For example, the storage module 4400 may be provided as a removable storage medium (i.e., a removable drive) such as a memory card or an external drive of the user system 4000.

[0236] For example, the storage module 4400 may include a plurality of non-volatile memory devices, each of which may be configured as described above with reference to Figure 2 and Figure 3 The storage module 4400 may be operated in the same manner as described above with reference to Figure 1 The storage device 50 operates in the same manner as described.

[0237] According to an embodiment, the application processor 4100 may determine the amount of current consumed by each of the plurality of dies included in the memory module 4400 based on the status information received from the memory module 4400. For example, the status information may be output from the memory module 4400 in response to a status response command output when all dies included in the memory module 4400 are in a busy state. The status information may divide a busy period of each die into a plurality of sub-periods having the same length and may include information on the amount of current consumed by each die corresponding to each of the plurality of sub-periods.

[0238] Application processor 4100 may determine whether sub-periods in which peak currents occur overlap based on the status information. In other words, application processor 4100 may determine whether all dies included in memory module 4400 consume the maximum current and whether sub-periods in which the dies consume the maximum current overlap.

[0239] According to an embodiment, when the sub-periods in which peak currents occur in multiple dies overlap, the application processor 4100 may output a pause command. The pause command may indicate that operation on at least one die among the multiple dies should be delayed by the amount by which the sub-periods in which peak currents occur in the multiple dies overlap.

[0240] The memory module 4400 may delay the operation on the corresponding die by a sub-period in which periods during which peak currents occur in the plurality of dies overlap in response to the suspend command.

[0241] The user interface 4500 may include an interface for inputting data or commands to the application processor 4100 or outputting data to an external device. For example, the user interface 4500 may include a user input interface such as a keyboard, a keypad, a button, a touch panel, a touch screen, a touch pad, a touch ball, a camera, a microphone, a gyro sensor, a vibration sensor, and a piezoelectric device. The user interface 4500 may also include a user output interface such as a liquid crystal display (LCD), an organic light emitting diode (OLED) display device, an active matrix OLED (AMOLED) display device, an LED, a speaker, and a monitor.

[0242] According to an embodiment of the present disclosure, when the busy periods of multiple dies overlap, the overlapping portion of the busy period can be subdivided into subperiods to determine the subperiods in which the peak currents of the multiple dies overlap. During the subperiod, the operation of one of the multiple dies can be suspended, so that the performance of the memory device can be improved.

[0243] CROSS-REFERENCE TO RELATED APPLICATIONS

[0244] This application claims the benefit of Korean Patent Application No. 10-2020-0063685, filed on May 27, 2020, in the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference.

Claims

1. A memory controller for controlling a memory device comprising a plurality of dies, the memory controller comprising: a state information determination component configured to determine, based on state information received from the memory device during a busy period in which all of the plurality of dies are in a busy state, whether peak currents of a plurality of dies among the plurality of dies occur in a common sub-period among a plurality of sub-periods spanning the busy period, and to generate suspend information based on determining that the peak currents of the plurality of dies occur in the common sub-period; as well as A peak current controller is configured to output a suspend command to suspend operation of at least one die among the plurality of dies during the common sub-period based on the suspend information.

2. The storage controller according to claim 1, wherein: When a ready / busy signal indicating that all of the plurality of dies are in the busy state is received from the memory device, the state information determination component outputs a state read command for obtaining information on an amount of current consumed by the plurality of dies.

3. The storage controller according to claim 2, wherein: The status information determining component receives the status information output from the memory device in response to the status read command.

4. The storage controller according to claim 1, wherein: The busy period is divided into the plurality of sub-periods that are predetermined, and the state information includes information on a current consumption amount of each of the plurality of dies corresponding to the plurality of sub-periods.

5. The storage controller according to claim 4, wherein: The busy period is divided into the plurality of sub-periods based on a time interval for performing a sub-operation on each of the plurality of dies.

6. The storage controller according to claim 4, wherein: The state information determining component adds the current amounts consumed by the plurality of dies for each of the plurality of sub-periods based on the state information, and determines whether the peak currents of the plurality of dies occur in the common sub-period based on the added current amounts.

7. The storage controller according to claim 6, wherein: The state information determining component determines that the peak currents of the plurality of dies occur in the common sub-period based on the added current amounts having a maximum value.

8. The storage controller according to claim 6, wherein: When the peak currents of the plurality of dies appear in the common sub-period, the state information determining component generates the pause information, and The suspension information includes information about the at least one die whose operation is suspended and a time interval during which the operation is suspended.

9. The storage controller according to claim 8, wherein: The time interval during which the operation is suspended corresponds to the common sub-period during which the peak currents of the plurality of dies occur.

10. The storage controller according to claim 8, wherein: The peak current controller outputs the suspend command instructing the at least one die determined based on the suspend information to suspend a specific operation for the time interval for suspending operation of the at least one die.

11. The storage controller according to claim 8, wherein: The peak current controller outputs a resume command for resuming the suspended operation of the at least one die after the operation of the at least one die is suspended for the time interval.

12. A method of operating a memory controller for controlling a memory device comprising a plurality of dies, the method comprising the steps of: receiving status information from the memory device during a busy period when all of the plurality of dies are in a busy state; determining, based on the state information, whether peak currents of a plurality of dies in the plurality of dies occur in a common sub-period in a plurality of sub-periods spanning the busy period; generating suspend information for suspending operation of at least one die among the plurality of dies based on determining that the peak currents of the plurality of dies occur in the common sub-period; as well as A suspend command to suspend operation of the at least one die during the common sub-period is output based on the suspend information.

13. The method according to claim 12, wherein: The step of receiving the status information comprises the following steps: receiving a ready / busy signal from the memory device indicating that all of the plurality of dies are in the busy state; and outputting a status read command for obtaining information about an amount of current consumed by the plurality of dies, Wherein, the status information is output from the memory device in response to the status read command.

14. The method according to claim 12, wherein: The busy period is divided into the plurality of sub-periods that are predetermined, and the state information includes information on a current consumption amount of each of the plurality of dies corresponding to the plurality of sub-periods.

15. The method according to claim 14, wherein: The busy period is divided into the plurality of sub-periods based on a time interval for performing a sub-operation on each of the plurality of dies.

16. The method according to claim 14, wherein: The step of determining whether the peak currents of the plurality of dies occur in the common sub-period comprises the following steps: summing the amount of current consumed by the plurality of dies for each of the plurality of sub-periods based on the state information; and In which sub-period the added peak current appears is determined based on the added current amount.

17. The method according to claim 16, wherein: The step of determining in which sub-period the added peak current appears includes the step of determining in which sub-period the added current amount has a maximum value.

18. The method according to claim 16, further comprising the steps of: generating the pause information when the peak currents of the plurality of dies appear in the common sub-period, The suspension information includes information about the at least one die whose operation is suspended and a time interval during which the operation is suspended.

19. The method according to claim 18, wherein: When generating the pause information, the pause information including information on the time interval during which the operation is paused is generated, and the time interval during which the operation is paused corresponds to the length of a common sub-period.

20. A storage device, comprising: A memory device comprising a plurality of dies; as well as a memory controller for controlling the memory device, wherein the memory device generates state information about the amount of current consumed by each of the plurality of dies during a busy period when all of the plurality of dies are in a busy state, and The storage controller determines, based on the status information, whether the peak current of multiple die among the multiple die are consumed in a common sub-period among multiple sub-periods spanning the busy period, and when it is determined that the peak current of multiple die are consumed in the common sub-period, the storage controller controls the memory device to suspend operation on the die among the multiple die.

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