Microelectronic package fabrication using an array of interconnected substrates

Abstract

Interconnect substrate arrays, microelectronic packages, and methods for fabricating microelectronic packages using interconnect substrate arrays comprising integrated electrostatic discharge (ESD) protection grids are provided. In an embodiment, the method includes obtaining an interconnect substrate array having an integrated ESD protection grid. The ESD protection grid further includes ESD grid lines at least partially formed in a single cleavage of the interconnect substrate array and electrically coupling die attachment regions of the substrate array to one or more peripheral machine ground contacts. Array-level manufacturing steps are performed to generate an interconnect package array using the interconnect substrate array, while the die attachment regions are electrically coupled to electrical ground via the ESD protection grid during at least one of the array-level manufacturing steps. Subsequently, the interconnect package array is cleaved to produce a plurality of cleaved microelectronic packages.

Description

Technical Field

[0001] Embodiments of this disclosure generally relate to microelectronics, and more specifically, to methods for fabricating microelectronic packages using an array of interconnect substrates comprising an integrated electrostatic discharge (ESD) protection grid, as well as such substrate strips and microelectronic packages.

[0002] abbreviation

[0003] The abbreviations that appear relatively infrequently in this article are defined upon first use, while the more frequent abbreviations are defined as follows:

[0004] BGA - Ball Grid Array;

[0005] ESD - Electrostatic Discharge;

[0006] IC - Integrated Circuit;

[0007] LGA - Pad Grid Array;

[0008] SMD - Surface Mount Devices; and

[0009] TSV - Through-substrate via. Background Technology

[0010] Microelectronic packages include a package body containing one or more semiconductor dies and any number of discrete SMD capacitors, SMD resistors, SMD inductors, or other microelectronic components. Wire bonding is commonly used to provide electrical interconnects between the ends of a given microelectronic package and the microelectronic components contained within the package, wherein the package ends take various forms depending on whether the microelectronic package is an LGA package, BGA package, leadframe-based package, or another package type. Microelectronic package manufacturing can be simplified by simultaneously producing multiple packages via high-volume fabrication of interconnect substrate arrays; that is, structures containing multiple substrates are interconnected by intervening in a single-slit street, which is subsequently removed during the single-slit process. In a common manufacturing method, a substrate panel is initially produced containing a relatively large number of interconnect substrates. The substrate panel is then divided into multiple substrate strips, each with a generally rectangular shape factor, which is well-suited for modification through different manufacturing equipment stages. A given substrate strip can contain from a few to hundreds of interconnect substrates arranged in a grid layout. The elongated rectangular shape factor of the substrate strip can be improved for linearity and indexing through different processing stages, such as die attachment, wire bonding, and strip molding. Following such strip-level or array-level processing, the resulting structure is sawed, stamped, or otherwise diced to produce multiple discrete package units. Additional processing steps, such as ball attachment in the case of BGA packaging, can be performed after strip dicing to complete the fabrication of discrete packages. Summary of the Invention

[0011] According to one aspect of the present invention, a method for manufacturing a microelectronic package is provided, comprising:

[0012] An interconnect substrate array is obtained, the interconnect substrate array comprising:

[0013] A packaging substrate, the packaging substrate including a die attachment area;

[0014] A single-cut channel, wherein the single-cut channel is interspersed with the packaging substrate;

[0015] Peripheral machine grounding contacts, the peripheral machine grounding contacts being adjacent to the edge region of the interconnect substrate array; and

[0016] An electrostatic discharge (ESD) protection grid, the ESD protection grid including ESD grid lines that electrically couple the die attachment area to the peripheral machine ground contact, the ESD grid lines being at least partially formed in the single cleavage of the interconnect substrate array;

[0017] Perform array-level manufacturing steps to generate an interconnect package array using the interconnect substrate array, while electrically coupling the die attachment area to electrical ground via the ESD protection grid during at least one of the array-level manufacturing steps; and

[0018] After performing the array-level manufacturing steps, the interconnect package array is diced to produce multiple diced microelectronic packages.

[0019] According to one or more embodiments, performing the array-level manufacturing step includes attaching an integrated circuit (IC) die to the die attachment area using a die bonding machine while maintaining contact between the peripheral machine ground contact and the grounding feature of the die bonding machine.

[0020] According to one or more embodiments, bonding includes bonding the IC die to the die attachment region using a conductive bonding material.

[0021] According to one or more embodiments, if the ESD protection grid is not present, the die attachment area will be electrically floating when the IC die is attached to the die attachment area using the die bonding machine.

[0022] According to one or more embodiments, performing the array-level manufacturing step includes using a wire bonding machine to form wire bonds that interconnect integrated circuit dies bonded to the die attachment region, while maintaining contact between the peripheral machine ground contacts and the ground features of the wire bonding machine.

[0023] According to one or more embodiments, performing the array-level manufacturing step includes performing at least one array-level manufacturing step using a first machine having a grounding clamp mechanism while maintaining contact between the peripheral machine grounding contact and the grounding clamp mechanism.

[0024] According to one or more embodiments, the ESD protection grid is primarily located in the single tangent in terms of volume.

[0025] According to one or more embodiments, performing the array-level manufacturing step includes:

[0026] Bond the integrated circuit (IC) die to the die attachment area;

[0027] After bonding the IC die to the die attachment region, wire bonding is formed to electrically interconnect the IC die with a substrate end disposed on the packaging substrate; and

[0028] After electrically interconnecting the IC die with the substrate, the interconnect substrate array, the IC die, and the wire bonding are overmolded to produce the interconnect package array.

[0029] According to one or more embodiments, single-cutter includes single-cuttering the interconnect package array to produce the plurality of single-cutter microelectronic packages, each of the plurality of single-cutter microelectronic packages comprising:

[0030] A packaging substrate having substrate sidewalls defined by the single-cut process;

[0031] as well as

[0032] One of the ESD grid lines is cut off, the cut off ESD grid line is contained in the package substrate and extends to the sidewall of the substrate.

[0033] According to one or more embodiments, the peripheral machine grounding contact includes a portion of an elongated metal feature that is first impacted by the molding material when the molding material is introduced through the molding gate during the overmolding of the interconnect substrate array, the IC die, and the wire bond.

[0034] According to one or more embodiments, the interconnect substrate array includes a substrate strip having a generally rectangular planar shape and comprising the package substrate arranged in at least one grid layout.

[0035] According to one or more embodiments, the peripheral machine grounding contact is formed as an elongated metal contact located near the elongated side edge of the substrate strip and extending substantially parallel to the elongated side edge.

[0036] According to one or more embodiments, performing the array-level manufacturing step includes bonding an integrated circuit (IC) die to the die attachment region using a conductive bonding layer; and

[0037] The IC die mentioned above includes:

[0038] On the rear side of the die, when the IC die is bonded to the die attachment area, the rear side of the die faces the die attachment area;

[0039] The front side of the die, which is opposite to the rear side of the die; and

[0040] The ESD grounding structure is formed on the front side of the die and is electrically coupled to the die attachment area through the rear side of the die and the conductive bonding layer when the IC die is bonded to the die attachment area.

[0041] According to one or more embodiments, the ESD grounding structure is further selected to have an annular geometry extending around the peripheral portion on the front side of the die.

[0042] According to a second aspect of the present invention, an interconnect substrate array is provided, comprising:

[0043] A packaging substrate, the packaging substrate including a die attachment area;

[0044] A single-cut channel, wherein the single-cut channel is interspersed and interconnected with the packaging substrate;

[0045] Peripheral machine grounding contact, the peripheral machine grounding contact being adjacent to the edge region of the interconnect substrate array;

[0046] Dielectric substrate array body; and

[0047] An electrostatic discharge (ESD) protection grid is formed in the dielectric substrate array body and includes ESD grid lines that electrically couple the die attachment area to the peripheral machine grounding contact, the ESD grid lines being at least partially formed in the single cleavage of the interconnect substrate array.

[0048] According to one or more embodiments, the interconnect substrate array includes a substrate strip having a generally rectangular planar shape;

[0049] The packaging substrate is arranged in at least a first grid layout; and

[0050] The peripheral machine grounding contact is formed as an elongated metal contact, which is located near the side edge of the substrate strip and extends generally parallel to the side edge.

[0051] According to one or more embodiments, the ESD protection grid is primarily located in the single tangent in terms of volume;

[0052] The packaging substrate has an average thickness; and

[0053] Each of the ESD grid lines has a thickness less than half the average thickness of the package substrate.

[0054] According to one or more embodiments, the packaging substrate includes a ground plane, and the die attachment area is electrically coupled to the ESD protection grid through the ground plane.

[0055] According to a third aspect of the present invention, a microelectronic package is provided, comprising:

[0056] A packaging substrate having a die attachment area and a single-cut sidewall;

[0057] An integrated circuit (IC) die, the IC die having a die rear side facing the die attachment area and a die front side opposite to the die rear side;

[0058] A conductive bonding layer, wherein the conductive bonding layer bonds the IC die to the die attachment region; and

[0059] A cut electrostatic discharge (ESD) protection grid line, the cut ESD protection grid line being electrically coupled to the die attachment area, the cut ESD protection grid line extending to and passing through one of the cut sidewalls of the package substrate.

[0060] According to one or more embodiments, an ESD grounding structure is further included, which is formed on the front side of the die, has an annular geometry, and extends around the peripheral portion of the front side of the die, the ESD grounding structure being electrically coupled to the die attachment region through the rear side of the die and the conductive bonding layer. Attached Figure Description

[0061] At least one example of the invention will be described below in conjunction with the accompanying drawings, in which the same reference numerals denote the same elements, and:

[0062] Figure 1 This is an isometric view of an LGA package manufactured using an interconnect substrate array including an integrated ESD protection grid, as shown in the example embodiment.

[0063] Figure 2 It is along the cross-section plane 2-2 (in Figure 1 (Cut out by the Chinese character) Figure 1 The example LGA package cross-sectional view is shown below;

[0064] Figure 3 It is included in Figure 1 and 2 The isometric view of the semiconductor die in the LGA package shown illustrates the ESD grounding structure (which also acts as a sealing ring) and other features that may be formed on the front side of the package die in the embodiment.

[0065] Figure 4 This is an example method for fabricating multiple microelectronic packages using an array of interconnect substrates containing an integrated ESD protection grid, such as... Figure 1 and 2 The example shown includes multiple instances of LGA wrappers;

[0066] Figure 5 This is a plan view of an interconnect substrate array (here, a substrate strip) with an integrated ESD protection grid, as depicted in an exemplary embodiment according to this disclosure; and

[0067] Figure 6-10 according to Figure 4 The example implementation of the packaging manufacturing method described herein illustrates, step by step, the manufacturing steps that can be used to manufacture multiple microelectronic packages while reducing the probability of ESD damage in array-level manufacturing.

[0068] For the sake of simplicity and clarity, descriptions and details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the exemplary and non-limiting embodiments of the invention described in the following detailed description. It should be further understood that, unless otherwise stated, features or elements appearing in the drawings are not necessarily drawn to scale. For example, the dimensions of certain elements or regions in the figures may be enlarged relative to other elements or regions to improve understanding of embodiments of the invention. Detailed Implementation

[0069] Embodiments of this disclosure are illustrated in the accompanying drawings, which are briefly described above. Various modifications to the exemplary embodiments will be apparent to those skilled in the art without departing from the scope of the invention as set forth in the appended claims.

[0070] definition

[0071] The following definitions apply throughout this document. Terms not explicitly defined herein or elsewhere in this document have their general meaning in the relevant technical field.

[0072] Rear side of the die - the side (outer main surface) of the die that is opposite to the front side of the die along an axis orthogonal to the front side of the die (defined below).

[0073] The front side of the die - the side of the die on which the bonding pad is located, either alone or in the majority, (outer main surface).

[0074] Metal – a material which is composed primarily of one or more metallic components by weight percentage.

[0075] Microelectronic packaging – a discrete unit comprising one or more microelectronic components, such as a semiconductor die carrying an integrated circuit, supported by a substrate and at least partially enclosed by a package body. When comprising multiple interconnected microelectronic components, such as one or more dies and passive SMD devices, microelectronic packaging can be more specifically referred to as “system-in-package” or “SiP”.

[0076] Overview

[0077] As mentioned above, microelectronic packages are typically manufactured simultaneously by processing interconnect substrate arrays, such as substrate strips cut from larger substrate panels. These substrate strips may undergo an initial die attachment process performed using a die bonding machine, which attaches one or more semiconductor dies (and possibly other microelectronic components) to each substrate included in the substrate strip. The die bonding machine may include features such as a clamping mechanism or indexer that engage the edges of the substrate strip to hold the strip against a support surface of the machine; this support surface may be, for example, the upper surface of a metal chuck. Following die attachment, a wire bonding machine with similar features can further process the substrate strip. Specifically, such a wire bonding machine can be used to form wire bonds that electrically interconnect the newly attached dies and any other microelectronic components attached to the substrate strip to the substrate ends (or end connections) of the interconnect substrates. Substrate end connections can be, for example, conductive features of the substrate that provide connections to externally accessible ends of the package; for example, in the case of an LGA package, substrate end connections can be bonding pads disposed on the front side or “die support surface” of the LGA substrate, which are electrically coupled to bonding pads or “pads” exposed along the rear or bottom side of the LGA substrate.

[0078] The manufacturing techniques described above enable the production of relatively large quantities of microelectronic packages in a relatively simplified and cost-effective manner. However, in some cases, a high percentage of undesirable microelectronic packages may fail quality tests after array-level processing. Such yield losses directly increase the production cost of each viable or marketable microelectronic package. Yield losses can occur when a microelectronic package fails performance parameter tests at some point after the die attachment and interconnect (e.g., wire bonding) processing steps described above. There can be a variety of reasons why a microelectronic package may fail quality test measurements; often, the specific failure mode or precision mechanism that leads to the scrapping and potential damage of a particular package remains unknown. While such yield losses are ideally driven to zero in any given microelectronic package manufacturing process, this is generally impractical under realistic conditions; and in current manufacturing practices, a certain amount of unavoidable yield loss is usually permissible. However, it has been found that such yield losses can be exacerbated when certain conditions increase the likelihood of device damage due to array-level manufacturing ESD events; these array-level manufacturing ESD events are those occurring during the processing of interconnect substrate arrays, such as during die attachment and wire bonding processes used to produce LGA, BGA, and similar microelectronic packages from substrate strips. Array processing ESD events can also have long-term negative impacts on package reliability, for example, by generating low-level potential defects that are unlikely to be detected during final electrical and functional testing. For example, it has been determined that ESD events can generate point defects in dielectric films, which, although small and extremely difficult to detect, can propagate over time with power and temperature cycling and eventually lead to device failure. Similarly, potential defects caused by array-level manufacturing ESD events may appear as tiny dislocations within the transistor gate oxide layer, which are typically undetectable but may eventually trigger device field failure modes over time.

[0079] When installed and utilized within specific systems or applications, the potential for ESD events to damage microelectronic components contained within finished microelectronic packages has long been recognized. However, effective solutions for providing ESD protection during array-level processing of interconnect substrate arrays, such as strip-level processing of substrate strips, are rare (if any). One reason may be the current lack of awareness in the industry of destructive ESD events that occur during array-level manufacturing. Depending on processing parameters and other factors, ESD events may be infrequent during array-level processing; and when they do occur, such ESD events may be minor enough in magnitude or duration to avoid damaging sensitive component areas contained within the microelectronic package, such as transistor gate dielectric layers. This infrequency or inadequacy of such array-level manufacturing ESD events may be due to intermittent, unintentional grounding of the conductive features of the substrate strip through contact with grounded metal features of die bonding machines, wire bonding machines, and similar processing equipment used to perform different array-level manufacturing processes. Furthermore, when many conventional semiconductor dies are attached, the potential for severe array-level manufacturing ESD events is minimized, for example, dies composed of bulk silicon (Si) wafers with common lattice orientations have relatively low resistivity due to their corresponding thickness; for example, a resistivity of 100 kiloohms (Ω) or less, as measured along a vertical axis extending from the front to the rear of the die body. Conversely, it has been determined that when semiconductor dies with electrically floating and / or high resistivity are attached to a substrate strip (or other interconnect substrate array), the chance of relatively severe array-level manufacturing ESD events damaging sensitive components and resulting in corresponding yield losses increases significantly.

[0080] Besides performing array-level processing within a cleanroom environment, one way to reduce the tendency for ESD events in array-level manufacturing is to use negative ion generators; that is, devices configured to introduce a forced ionized gas flow into the microelectronic workpiece during processing. However, the potential use of such negative ion generators during array-level processing is associated with various drawbacks. Negative ion generators are typically relatively expensive and bulky devices. The use of negative ion generators may interfere with achieving ideal high temperatures (e.g., ideal temperatures for forming intermetallic compounds during wire bonding) during array-level processing due to the inherent convective cooling effect of the forced gas flow impacting the substrate strip (or other interconnect substrate array). Even disregarding these limitations, negative ion generators may be ineffective in consistently preventing ESD events in array-level manufacturing. Given this, there is a persistent industry need for technological solutions to reduce the likelihood of severe manufacturing ESD events during array-level processing of substrate strips or other interconnect substrate arrays. Ideally, such solutions would be able to be integrated into a wide variety of different substrate strips (or other interconnect substrate arrays) with minimal additional cost and minimal need to modify existing substrate designs or layouts. It is also hoped that such solutions will be compatible with various types of manufacturing equipment used to perform die attachment, electrical interconnection (e.g., wire bonding), and other array-level processing steps.

[0081] To meet the aforementioned industry needs, interconnect substrate arrays, microelectronic packages, and methods for manufacturing microelectronic packages using interconnect substrate arrays comprising integrated ESD protection grids are disclosed below. In many cases, the interconnect substrate arrays described below take the form of substrate strips with a generally rectangular planar shape or shape factor, and are therefore primarily as described below. However, it should be emphasized that the teachings presented herein are equally applicable to any type of interconnect substrate array, regardless of its shape factor or structural composition, for processing said interconnect substrate array to produce multiple microelectronic packages susceptible to ESD damage during array-level processing. Advantageously, embodiments of the ESD protection grids described below can be integrated into existing substrate array designs with minimal additional cost while simultaneously providing compatibility with a variety of array-level processing devices, including die attachment and wire bonding machines. Furthermore, the integrated ESD protection grid described herein is highly effective in preventing or at least reducing the severity of ESD events in array-level manufacturing, including when high-resistivity dies are attached to designated die-bonding regions of a given interconnect substrate array; for example, IC dies manufactured using gallium nitride (GaN) structures, gallium arsenide (GaAs) structures, or certain silicon (Si) materials (including high-resistivity Si materials) well-suited for TSV integration, to name just a few. Significant cost savings can be achieved by reducing yield losses at high-volume manufacturing scales; for example, in some cases, testing has shown yield losses can be reduced by more than 3%. Additionally, by minimizing instances of microelectronic packages that are only slightly damaged by array-level ESD events and by leveraging margins in quality testing parameters, greater consistency in achieving ideal package performance levels and improving overall reliability can be achieved.

[0082] Embodiments integrating ESD protection grids include intersecting grid lines that electrically interconnect die attachment regions of an interconnect substrate array with peripheral ground structures or contacts located near one or more peripheral edges of the substrate array with the integrated ESD protection grid. For example, in the case of a substrate strip with extended side edges, the ESD protection grid may be connected to one or more extended peripheral ground contacts, such as extended strip-shaped metal regions extending generally parallel to the extended side edges of the strip. In cases where the substrate strip (or other interconnect substrate array) is encapsulated or overmolded, the peripheral ground contacts may be combined with or connected to molded gate metal features of the strip; that is, when the metallized regions of the strip are first injected or otherwise distributed onto the strip during strip-level processing, they contact the molding material. Such peripheral ground contacts electrically contact the grounding structure of a processing device (e.g., a grounding clamp mechanism or indexer) during array-level processing to provide a low-resistance path to ground from the die attachment regions of the interconnect substrate array to the electrical ground. When a given die is attached to a designated die attachment area using a conductive bonding material, such as a metal-containing epoxy resin, a low-resistance electrical path is also provided. This low-resistance electrical path originates from the back side of the die, passes through the die attachment area, through the integrated ESD protection grid, through the peripheral machine ground contact, and ultimately reaches the electrical ground (carrier ground) of the processing device. Therefore, the likelihood of a highly charged electrostatic field (e-field) accumulating near each IC die is reduced, correspondingly reducing the likelihood of severe array-level manufacturing ESD events that could potentially damage the IC die (or other microelectronic components bonded to the substrate array) in other ways during array-level processing. More broadly, such semiconductor dies and any other microelectronic components (e.g., SMDs) incorporated into a given microelectronic package are protected from ESD events occurring at any given location throughout the package undergoing array-level manufacturing.

[0083] The method described above integrates the ESD protection grid into the substrate strip or other interconnect substrate array, minimizing the likelihood and severity of array-level manufacturing ESD events. Specifically, this reduces yield losses that could otherwise occur due to such ESD events when high-resistivity IC dies are bonded to the substrate array, interconnected, and otherwise processed during array-level processing. Simultaneously, the integrated ESD protection grid is formed at least partially (if not primarily) in a single cleavage of the interconnect substrate array; for example, a majority of the ESD protection grid volume may be located within a single cleavage of a given substrate array. Therefore, the provision of the ESD protection grid occupies a small portion of the design-relevant area of ​​the package substrate forming the interconnect substrate array. By extension, performing die attachment, interconnection (e.g., wire bonding), and any additional array-level processing steps (e.g., substrate array overmolding) to convert the integrated substrate array into an interconnect package array that is easily cleaved, after which most (if not substantially all (again, in volume)) of the ESD protection grid can be removed during the cleaving of the interconnect substrate array into individual cells. However, small artifacts of the ESD protection grid can be retained in the completed microelectronic package, such as cut grid lines (also referred to below as "extended tabs") that previously connected the die attachment area directly or indirectly to the ESD protection grid and now terminate at the peripheral sidewall of the package substrate, as discussed further below.

[0084] In embodiments, a unique front-side ESD grounding structure in the front layer of a semiconductor die can also provide additional protection against array-level manufacturing ESD events, the semiconductor die being bonded to a die attachment region of an interconnect substrate array. Such a front-side ESD grounding structure can be formed on the front side of the die at a location adjacent to the outer edge of a given die; and additionally, the ESD grounding structure can be electrically coupled to the rear side of the die via one or more TSVs; as previously noted, the term "TSV" stands for "Through-Substrate Via," and more specifically, the term "Through-Silicon Via" is reserved for instances where the TSV is formed in a die at least partially composed of silicon. This provision of such an ESD grounding structure can be beneficial in further providing a low-resistivity grounding path extending from the front side of the die to the rear side of the die, and thus, through the die attachment region, through the integrated ESD protection grid, and to the chassis or machine ground of the processing equipment. In some cases, this can also reduce static charge buildup near the front side of the semiconductor die, thereby further reducing the die's susceptibility to array-level manufacturing ESD damage. If desired, a given ESD grounding structure can be used to provide additional functionality in the completed package. Such additional functionality may include forming a shielding structure to reduce RF interference or crosstalk in radio frequency (RF) applications, such as in the case of a power amplifier (PA) package containing an RF power die. In other cases, the ESD grounding structure may be implemented as a ring structure extending around the upper periphery of the front side of the semiconductor die to form a physical barrier against the ingress of moisture and other contaminants. When this functionality is provided, the ESD grounding structure may also be referred to hereinafter as a “ground sealing ring.” In another embodiment, the manufacturing methods described below can be performed without using such a front-side ESD grounding structure while processing a substrate strip (or other interconnect substrate array) containing an integrated ESD protection grid. The following will be combined with… Figure 1-10 Examples of microelectronic packages fabricated using interconnect substrate arrays that include integrated ESD protection grids are described. In embodiments, such packages effectively, but not necessarily, additionally include a ground sealing ring or other such front-side ESD grounding structures.

[0085] Example microelectronic package fabricated using an interconnect substrate array containing an integrated ESD protection grid

[0086] Figure 1 and 2These are isometric and cross-sectional views of an example microelectronic package 20 manufactured by processing an interconnect substrate array containing an integrated ESD protection grid. In this particular example, the microelectronic package 20 is in the form of an LGA package and will therefore be referred to hereinafter as "LGA package 20". However, it should be emphasized that the following description is equally applicable to other package types that can be manufactured using interconnect substrate arrays with integrated ESD protection grids, such as BGA packages. A non-exhaustive list of other package types that may be manufactured according to the teachings set forth herein includes BGA packages and flat no-leads packages or micro leadframe (MLF) packages, such as square flat no-leads (QFN) packages and dual-plane flat no-leads (DFN) packages. The following description is combined with... Figure 4-10 Example methods for manufacturing LGA package 20 and several similar or identical packages are discussed. However, first, LGA package 20 is described in more detail to provide a non-limiting context in which embodiments of this specification can be better understood.

[0087] Generally, the LGA package 20 shares many structural features with a typical LGA package. For example, the LGA package 20 includes a package substrate 22 (hereinafter referred to as "LGA substrate 22") having a front side or "die support surface" 24 and a relatively rear side 26. A molded package body 28 is formed over and bonded to the die support surface 24 of the LGA substrate 22. One or more microelectronic devices are bonded to the LGA substrate 22 and embedded within the molded package body 28. For example, from Figure 2 As can be seen in the cross-section, the semiconductor or integrated circuit die 30 (hereinafter referred to as "IC die 30") can be attached to the die support surface 24 of the LGA substrate 22 via a die bonding layer 32. Specifically, the IC die 30 can be bonded to a design area or region of the die support surface 24, referred to herein as "die attachment area 31". At least a portion of the die attachment area 31 is made of a conductive material and is electrically coupled to the IC die 30 via the die bonding layer 32 (specifically, as described below, electrically coupled to the die backside 36). To provide such electrical connection, the die bonding layer 32 is made of a conductive bonding material (e.g., metal-filled epoxy, solder, or sintering material). As a more specific example, in some embodiments, the die bonding layer 32 may be made of a die attachment material containing metal particles loaded with, for example, silver (Ag) or copper (Cu) particles. In other cases, and as a second example, the die bonding layer 32 may be composed of a sintered material consisting primarily of Ag, Cu, or a combination thereof by weight.

[0088] IC die 30 includes an upper main surface or front side 34 opposite to the lower main surface or "rear side" 36. The rear side 36 of IC die 30 is attached to the upper main surface or die support surface 24 of package substrate 22 via die bonding layer 28, as previously mentioned. Circuit system with multiple bonding pads 38 ( Figure 2 One of them can be seen in the image, and they are formed together on the front side 34 of the IC die 30. Additionally, in this embodiment, an ESD grounding structure 40 is formed on the front side 34 of the IC die 30, as further described below. Bonding pads 38 are electrically interconnected with selected conductive features 42, 44, 46, 48, 50, and 52 of the LGA substrate 22 via wire bonding 54. Specifically, as... Figure 2 As indicated on the right, for one such bonding pad 38, each bonding pad 38 can be electrically connected to a patterned pad or bonding pad 44 included in the upper patterned metal layers 42, 44 of the LGA substrate 22. The upper patterned metal layers 42, 44 can be electrically coupled to the lower patterned metal layers 46, 48 via any number of TSVs 50, 52 and via any number of intervening patterned metal layers. In the illustrated example, the lower patterned metal layers 46, 48 define a plurality of smaller ends or pads 46 exposed at the rear side 26, which can be arranged in one or more rows extending generally parallel to the edge region of the LGA substrate 22 (in Figure 1 (Best observed in the middle). Additionally, the lower metal layers 46, 48 can be patterned to define a relatively large center contact, which in an embodiment may serve as an additional end 48 of the LGA package 20 and may also serve as a heat sink or radiator. In the illustrated example, end 48 is the ground plane and ground terminal of the LGA package 20, and is therefore referred to hereinafter as "ground terminal 48". Various conductive features of the LGA substrate 22 are electrically isolated by a dielectric body 56, which may be formed as one or more layers of printed circuit board (PCB) resin, a dielectric polymer containing fillers, multilayer alumina, low-temperature co-fired ceramic, or other dielectric materials. In other embodiments, the LGA substrate 22 may contain more or fewer wiring layers or may have a different configuration, such as a coreless substrate configuration. Generally, the embodiments of this disclosure are applicable to any component or manufacturing process where ESD damage may occur and ESD damage is implemented using a substrate array or carrier with any suitable substrate construction and composition.

[0089] IC die 30 can be manufactured using any suitable die technology and can include different IC designs depending on the desired functionality of IC die 30. In one embodiment, IC die 30 can be fabricated using a bulk workpiece of silicon (Si) or another semiconductor material. In other embodiments, a layered die structure can be used to produce IC die 30. This is in Figure 2The IC die 30 is generally shown as comprising a die body 58, 60 on which a front-side layer 62 is formed. When the IC die 30 is produced, for example, using a single-cut bulk silicon (Si) wafer workpiece, the die body 58, 60 may be made of a single semiconductor material. Alternatively, the die body 58, 60 may be made of multiple layers of different materials, including at least one layer or body of semiconductor material. In a later aspect, in an embodiment of producing the IC die 30 using layered (e.g., GaN) die technology, the upper portion 58 of the die body 58, 60 may be substantially or primarily made of a first semiconductor material (e.g., GaN) by weight, while the lower portion 60 of the die body 58, 60 may be made of another material (or combination of materials) on which the first semiconductor (e.g., GaN) layer is formed, such as silicon carbide (SiC). In other cases, the IC die 30 can be fabricated using an alternative die technology that provides relatively high resistance, such as using a GaAs die structure or an IC die made of Si material with a high resistivity lattice orientation that is very suitable for TSV integration. The front layer 62 also includes an additional patterned metal layer defining the bonding pads 38 and interconnects, a dielectric layer for providing isolation between discrete features of the patterned metal layer, and an outer passivation layer that may at least partially define the front side 34 of the IC die 30. A back pad metal layer or multilayer system 64 can be provided opposite the front side 34 of the die to facilitate metallurgical bonding and low-resistance electrical contact with the die bonding layer 28. Such a configuration may be useful when, for example, the IC die 30 is in the form of a radio frequency (RF) power die containing one or more transistors, such as field-effect transistors (FETs), for RF signal or power amplification purposes. In other embodiments, the IC die 30 may include other circuit elements, including one or more bipolar transistors, and / or may lack such a back pad metal layer or multilayer system.

[0090] As mentioned above, in this embodiment, the ESD grounding structure 40 may also be formed on the front side 34 of the IC die 30. When provided, the ESD grounding structure 40 is electrically coupled to the rear side 36 of the die via, for example, one or more TSVs 66 formed through the die bodies 58, 60, as... Figure 2As indicated by bubble 68 in the details. Prior to encapsulating or overmolding the IC die 30, the ESD grounding structure 40 can be exposed from the outside of the front side 34 to further reduce static charge buildup along the front side 34 of the IC die 30 during LGA package fabrication. Additionally, in embodiments, the ESD grounding structure 40 can be utilized for additional purposes in post-packaging manufacturing. For example, in embodiments, the ESD grounding structure 40 can be sized and positioned to act as an EMI shield. In other cases, the ESD grounding structure 40 can be formed with an annular geometry extending around the periphery of the front side 34 and acting as a sealing ring; i.e., a physical barrier preventing contaminants from entering the front layer 62. By simply referring to… Figure 3 This can be understood more fully. Figure 3 An embodiment is depicted in which an ESD grounding structure 40 can be produced having an annular geometry extending around the periphery of the front side 34 of the die front side 34, as depicted, which may side the die bonding pad 38. The ESD grounding structure 40 can be constructed from a variety of different conductive materials, including: non-metallic materials such as polycrystalline silicon; and metallic materials such as gold, germanium gold, tungsten silicide, and aluminum copper tungsten, to name just a few.

[0091] The LGA package 20 further includes at least one cut segment 70 (hereinafter referred to as "tab extension 70") of the ESD protection grid lines, which extends to and penetrates or passes through the sidewall 72 of the LGA substrate 22, or more generally, the sidewall 72 of the LGA package 20, such as Figure 1 and 2 As shown. The extended tab 70 is an article or residue of a larger ESD protection grid integrated into the interconnect substrate array that produces the LGA package 20. In this regard, it is convenient to simultaneously manufacture the LGA package 20 and many similar LGA packages using such interconnect substrate arrays in the form of substrate strips, which contain an integrated ESD protection grid that provides enhanced ESD protection during array-level processing of the strip. In other embodiments, a large portion of the integrated ESD protection grid may remain within the completed LGA package 20; however, as described more fully below, when in a partially manufactured, interconnected state, the integrated ESD protection grid is advantageously located primarily within the single cleavage that separates the LGA package. Therefore, after the interconnect package array is cleaved to produce multiple cleaved LGA package units including the LGA package 20, the integrated LGA protection grid may be significantly damaged. The following is in conjunction with... Figure 4-10 Further descriptions of example methods for manufacturing LGA package 20 and several similar or identical packages are provided in this section, along with a more detailed discussion of example embodiments of ESD protection grids.

[0092] Example Packaging Fabrication Method Using an Interconnect Substrate Array Including an Integrated ESD Protection Grid

[0093] Now refer to Figure 4 An example packaging manufacturing method 74 is presented for fabricating multiple microelectronic packages using an interconnect substrate array with an integrated ESD protection grid. Based on the foregoing description, packaging manufacturing method 74 will be described as producing packages in conjunction with the above. Figure 1-3 The LGA package discussed has 20 similar or identical LGA packages, in Figure 4-10 CCTV needs to continue using the previously cited reference numerals. However, it should be emphasized that package manufacturing method 74 can be used in the manufacture of other LGA packages, and more broadly, in the manufacture of other package types that benefit from enhanced ESD protection during array-level processing. For example, the method described below may be readily applicable to the production of BGA packages, which can be similar to LGA packages through most of the processing stages that result in ball attachment or collision. It is worth noting that because the ESD protection grid described below is a passive structure integrated into the interconnect substrate array (e.g., substrate strip) itself, the ESD protection grid can be moved into or integrated into various interconnect substrate arrays and is easily deployed in most assembly processes. As mentioned above, variations of method 74 are also applicable to the manufacture of other microelectronic package types, including but not limited to BGA and MLF (e.g., QFN and DFN) packages.

[0094] In the illustrated example, the packaging manufacturing method 74 is divided into three processing stages or blocks 76, 78, and 80. To begin method 74 (stage 76), an interconnect substrate array comprising one or more integrated ESD protection grids is obtained by independent manufacturing, purchase from a supplier, or otherwise. Here, the integrated substrate array obtained during stage 76 is an elongated substrate strip 82 comprising a relatively large number of interconnect LGA substrates arranged in two grid layouts 84, separated by an intervention intermediate region or area 86. The substrate strip 82 extends along a longitudinal axis (indicated by dashed line 88) and includes two longitudinal (longitudinal) edges 90 extending generally parallel to the longitudinal axis 88. Peripheral machine ground contacts 92 are formed around the edge regions of the substrate strip 82. For example, as Figure 4As shown in the upper portion, the peripheral machine grounding contact 92 can be formed as an elongated strip or bar located near one of the elongated edges 90 of the substrate strip 82 and extending generally parallel to one of the elongated edges 90 (and by extension, generally parallel to the longitudinal axis 88 of the strip 82). This positioning of the peripheral machine grounding contact 92 facilitates electrical grounding through physical contact with the grounding features of one or more workpieces in a processing device, such as a clamping mechanism or indexing mechanism included in a die attachment machine and / or wire bonding machine. In embodiments where the substrate strip 82 is overmolded, the grounding contact 92 can also serve as a molding metal region located at the position of the strip 82 that first contacts the heated molding material when guided over the strip 82 during molding. In other words, the peripheral machine grounding contact 92 can be formed as part of the elongated metal feature, which, in an embodiment, is first impacted by the molding material when the molding material is introduced through the molding gate during the overmolding of the interconnect substrate array, IC die, and wire bond.

[0095] refer to Figure 5 A more detailed plan view of a region of substrate strip 82 is shown. Two ESD protection grids 94 are integrated into substrate strip 82, wherein each ESD protection grid 94 is interspersed with one of substrate grid layouts 84. Each ESD protection grid 94 includes a plurality of conductive traces or lines 96, 98 formed in the dielectric body (hereinafter referred to as "dielectric strip body 100") of substrate strip 82. In an embodiment, the traces or lines 96, 98 (hereinafter referred to as "ESD grid lines 96, 98") are formed as metallic (e.g., copper (Cu)) features, each having a thickness less than the average total thickness of substrate strip 82 (and possibly less than half the average thickness), such as along an axis orthogonal to the front side of substrate strip 82 (corresponding to...). Figure 5 The coordinates are measured at the Z-axis of the coordinate diagram 102. In embodiments where the ESD protection grid 94 is primarily located in a single kerf of the substrate strip 82 and the strip 82 is cut by sawing, this minimizes saw blade wear. In addition to the extended tabs 70, each of the ESD protection grids 94 includes a longitudinal ESD grid line 96 (extending parallel to the longitudinal axis 88 of the substrate strip 82 and corresponding to...) Figure 5 The coordinates 102 (X-axis) and the transverse ESD grid line 98 (extending perpendicular to the longitudinal axis 88 of the substrate strip 82 and corresponding to the Y-axis of the coordinates 102) are shown. As illustrated, the ESD grid lines 96 and 98 intersect to form a grid or lattice structure, wherein the grid lines 96 and 98 are adjacent to the periphery of the interconnect package (LGA) substrate 22. The ESD grid lines 96 and 98 may be primarily (if not substantially entirely) formed in a single cleavage of the substrate strip 82 and are therefore removed after the single cleavage of the strip 82, as described below. Figure 6-10 Further discussion.

[0096] In alternative implementations, the ESD protection grid 94 can have other structural layouts or arrangements, assuming that the ESD protection grid integrated into a given interconnect substrate array (here, substrate strip 82) electrically couples the die attachment area to additional peripheral machine ground contacts included in the substrate array. In this regard, and preferably in Figure 5 As seen in detailed bubble 104 in the upper portion, the die attachment regions 31 of the illustrated LGA substrate 22 can each be electrically connected to a peripheral machine ground contact 92 via a first grid line segment (i.e., an extension tab 70), followed by ESD grid lines 96, 98. Specifically, in the illustrated embodiment, the extension tab 70 extends from the metallization feature 71 to the end of a passive SMD, such as a chip cap, which can then be subsequently bonded to, for example, a location. The extension tab 70 extends from feature 71 to the illustrated grid line 98, and thus to a larger ESD protection grid 94, as shown in detailed bubble 104. Feature 71 is electrically coupled to the metallized die attachment region 31 via certain metal routing features of the substrate strip 82, which may include various vias, interconnects, and ground planes; for example, Figure 2 The ground plane 48 is shown. The extended tab 70 (and more broadly, the ESD protection grid 94) is also electrically coupled to the die attachment area 31, although in the example shown it is an indirect coupling.

[0097] In another embodiment, the extension tab 70 can be repositioned to different locations where the die attachment region 31 is electrically coupled to the larger ESD protection grid 94; for example, as shown by the dashed lines in detail bubble 104, in some embodiments, the extension tab 70 can (by design) be moved to location 73 where one of the die attachment regions 31 is directly connected to an adjacent grid line 98 and thus to the larger ESD protection grid 94. Furthermore, in yet another embodiment, extension tabs can be formed at each of the illustrated locations 70, 73 to further enhance ESD protection; it should be noted that in the embodiments, any feasible number of extension tabs can be formed to electrically couple the conductive features of each package substrate 22 to the larger ESD protection grid 94 without much additional cost and with little need to change the substrate layout, provided that the layout or arrangement of a given package substrate 22 can accommodate multiple instances of the extension tab 70 without violating design rules. Furthermore, integrating multiple extended tabs 70 at different locations within a given substrate 22 can enhance the ESD protection of the packaged die by ensuring that a low-impedance path to ground is provided to dissipate or reduce ESD energy, regardless of the specific location or "impact point" where an ESD event may occur. This can be particularly advantageous when used to manufacture larger SiP substrates, such as... Figure 5 The substrate 22 shown has a relatively large area on which such ESD events may occur.

[0098] Peripheral machine grounding contact 92 is advantageously located near one or more peripheral edges of substrate strip 82 to facilitate contact during array-level processing with the electrical grounding characteristics of one or more workpieces of the equipment used to process substrate strip 82 (and thus assemble microelectronic packages), such as in package manufacturing method 74. Figure 4 This is executed during processing phase 78. Figure 4 In the example, substrate strip 82 may undergo at least the following processing steps or stages during array-level processing: die attachment 106 performed using die attachment machine 108, wire bonding 110 performed using wire bonding machine 112, and overmolding 114 performed using suitable molding (e.g., injection or transfer molding) equipment (not shown) to produce one or more overmolded interconnect package arrays 116. Following array-level processing, interconnect package array 116 is diced during processing stage 80, and any additional processing steps may be performed to produce multiple diced packages 20 completing package manufacturing method 74. These processing steps are provided by way of example only; it should be noted that in alternative embodiments, other processing steps may be performed during array-level processing of the interconnect substrate array. For example, in embodiments, different interconnect technologies than wire bonding may be used to electrically interconnect microelectronic devices with package ends, such as using a three-dimensional printing process with conductive materials (e.g., ink containing metal particles) to form the necessary interconnects. Similarly, in other embodiments, overmolding may not be performed; and it is possible that different types of package housings may be bonded to each package substrate 22 to enclose the microelectronic components contained therein. Finally, although processing stage 106 is referred to herein as the “die attachment” processing stage, it should be understood that during stage 106, any number and type of microelectronic components (including discrete passive SMD components) other than one or more dies may also be bonded to each package substrate 22.

[0099] As previously indicated, the peripheral machine grounding contact 92 is advantageously configured to extend along the outer edge region of the substrate strip 82 to facilitate contact with the grounding features of one or more workpieces of the processing equipment utilized during array-level processing of the strip 82. For general-purpose workpieces of the processing equipment or machine 120 having an upper support surface 122, in Figure 5An example of such a grounding machine feature 118 is shown, wherein the upper support surface 122, such as the upper surface of a metal chuck, supports substrate strip 82 (and other such substrate strips) during array-level processing steps performed using machine 120. In embodiments, the grounding machine feature 118 takes the form of a clamping mechanism; the term “clamping mechanism” as broadly defined herein refers to any mechanical feature of an array-level manufacturing machine, such as a die bonding machine or a wire bonding machine, which engages the workpiece (here, the interconnect substrate array) against a support surface (e.g., support surface 122) during processing to clamp or hold the workpiece. The term “indexer” is also used herein to refer to a clamping mechanism further used to selectively push or move the workpiece (interconnect substrate array) relative to the machine support surface in a controlled manner. Figure 5 As indicated by symbol 124, such a gripper mechanism 118 may be at least partially constructed of a conductive material (e.g., a metal or alloy) electrically grounded and in contact with a given peripheral machine ground contact 92 to secure the substrate strip 82 prior to processing (e.g., die attachment or wire bonding). Specifically, the gripper mechanism 118 may be electrically coupled to the housing ground of the processing device 120, which in turn is electrically coupled to ground, to provide a return path for dissipating excess current from ESD events.

[0100] In this embodiment, the support surface 122 can also be electrically grounded, such as in... Figure 5This is further indicated by symbol 126. Therefore, in other embodiments, the peripheral machine ground contact 92 may be further exposed along the rear side (main surface, not shown) of the substrate strip 82 to ground with the support surface 122. It is worth noting that since the contact between the rear sides of the package substrates 22 is intermittent, conductive features on the rear side of the interconnect package substrates 22 may not reliably provide such rear-side grounding. It should be noted that in embodiments, the entire substrate strip 82 may not remain flat or flush against the support surface 122 because, for example, the strip 82 is pushed by a specific workpiece of the processing equipment. Alternatively, dielectric bonding mask features may be present on the rear side of the substrate strip 82, thereby preventing physical contact between any such conductive rear-side features and the support surface 122. In contrast, the peripheral machine grounding contact 92, with its exposed arrangement along the upper surface or front side of the substrate strip 82, provides a reliable interface for contacting the grounding feature of the processing device 120 by engaging with another grounding structural feature of the gripper mechanism 118 or device 120 (e.g., pins or plungers of a load spring), which, where appropriate, descends to contact the peripheral machine grounding contact 92 (or otherwise). However, it is also possible to provide peripheral machine grounding contacts along the rear side of the substrate strip 82 (specifically, if such contact features are raised) for contacting the grounding support surface 122 to enhance ESD dissipation in addition to or in lieu of the contact between the peripheral machine grounding contacts 92 exposed along the front side or upper surface of the strip 82, such as... Figure 5 As shown and further described below.

[0101] Next, refer to Figure 6-10 According to example packaging manufacturing method 74 ( Figure 4 The example implementation illustrates several manufacturing steps that, when properly performed, are used to fabricate multiple microelectronic packages while reducing the likelihood of ESD damage during array-level manufacturing. First, refer to... Figure 4 A limited area of ​​substrate strip 82 is shown, comprising a fully depicted package substrate 22' adjacent to the two partially depicted package substrates 22'; the apostrophe "`" indicates that the shown package substrate 22' is shown in its pre-single-cut form. Referring to the centrally depicted package substrate 22', Figure 6-10 The cross section shown roughly corresponds to Figure 2 The diagram shows a cross-section of the LGA package 20, with the same reference numerals used to indicate the structural features previously discussed. The package substrates 22' are interconnected in the form of substrate strips 82 at the current manufacturing moment and are connected (and thus interleaved with) by single-cut tracks 128; that is, areas of the substrate strips 82 are disposed of during subsequent single-cuts of the strips 82, as described below. Figure 10As described. Therefore, at this stage of manufacturing, the ESD grid line 96 remains intact and within the single slit 128, as shown. It can be further seen that the extension tab 70 extends to the single slit 128 to connect to the ESD grid line 96, and thus to the larger ESD protection grid 94. Figure 5 ESD grid lines 70, 96, and 98 can be formed during substrate manufacturing along with other conductive features of the package substrate 22' (e.g., using well-known metal plating and patterning processes), and specifically, can be formed as part of an upper patterned metal layer formed above the substrate panel, from which the substrate strip 82 breaks off. However, the specific manner in which the ESD grid lines 70, 96, and 98 are formed will also differ in different embodiments, depending on the ESD protection grid design and substrate type (it should also be noted that various types of substrates can be utilized in conjunction with embodiments of this disclosure).

[0102] refer to Figure 7 Subsequently, die attachment is performed to bond one or more dies 30 to their corresponding die attachment regions 31 via conductive bonding layer 32, and, where possible, other microelectronic components are attached to other regions (not shown) of each package substrate 22. As previously emphasized, ESD events may occur during the die attachment process, such as... Figure 7 The symbol 130 indicates this. In the absence of an ESD protection grid 94, including the extended tab 70 and ESD grid line 98 shown, no low-resistance electrical path to ground is provided when the conductive features of the substrate strip 82 (as is often seen in conventional array-level processing) do not contact the grounding area of ​​the processing equipment (here, the die bonding equipment is used to attach the IC die 30) and remain electrically floating. In this case, a large static electric field can accumulate along the corresponding front side 34 of the IC die 30; and when a sufficient difference is generated, discharge through the IC die 30 can cause potential ESD damage to sensitive areas of the die 30 (e.g., transistor gate dielectric) and / or other potential damage to other ESD-sensitive components mounted to the package substrate 22. In the case of transistor damage, such ESD damage can exacerbate gate-source leakage (IGSS) levels, threshold voltage mismatch (ΔVth), and other critical parameters that degrade die performance. In contrast, in the example shown, the ESD protection grid 94 completes a low-resistance electrical path to ground, as... Figure 7 The path 132 is indicated by the dashed line 132. This path 132 extends from the die attachment area 31, through the conductive features of the interconnect package substrate 22' (including the ground plane 48), generally through the extension tab 70 and the ESD protection grid 94, and through the peripheral machine ground contact 92. Figure 4 and 5 ), and by processing the grounding characteristics of the equipment (here, the die attachment machine 108) Figure 4Ultimately, the grounding characteristic contacts the peripheral machine grounding contact 92 of the contact substrate strip 82, leading to the electrical grounding system. By conducting along this path, static charge may be easily dissipated to reduce charge buildup along the corresponding front side 34 of the IC die 30; and thus, to prevent ESD events during die attachment or to reduce the severity of such ESD events when they should occur.

[0103] See further Figure 8 After die attachment, wire bonding is performed to form wire bonds 54 that electrically interconnect the newly attached die 30 to the end of the package substrate 22', and further form interconnections with various other microelectronic components bonded to the substrate 22' (if present). Similarly, as indicated by reference numeral 134, severe ESD events can occur during wire bonding without providing an ESD protection grid 94 that could potentially damage the die 30 and other sensitive components bonded to the package substrate 22'. However, due to the integration of the ESD protection grid 94 in this example, the low-resistance electrical path 132 described above is formed to extend from the die attachment region 31, through the ground plane 48, through the extension tab 70 and the remainder of the ESD protection grid 94, and finally to one or more peripheral machine ground contacts 92 positioned to contact the grounding features of the processing equipment; for example, in Figure 8 Regarding the manufacturing stage shown, for Figure 4 The grounding features of the wire bonding machine 112 are shown. Essentially, the ESD protection grid 94 then provides passive shielding against ESD damage to sensitive package components that may otherwise occur during array-level processing steps, including but not limited to die attachments. Figure 7 ) and / or wire bonding ( Figure 8 Additionally, when provided, the front-side ESD grounding structure 40 can further extend this low-resistance ground path to the corresponding front side 34 of the die 30 for additional ESD protection, which may be advantageous in some embodiments. In other embodiments, the die 30 may not have such an ESD grounding structure 40 (e.g., in cases where the corresponding rear side 36 of the IC die 30 already serves as a ground terminal, such as in the case of an RF power die containing, for example, a FET that acts as a power amplifier and has a ground source end), and enhanced ESD protection can be provided separately by integrating one or more ESD protection grids 94 into the substrate strip 82.

[0104] After wire bonding, the molded substrate tape can be encapsulated or overmolded to produce an overmolded interconnect package array 116, as previously described in step 114 of the example package manufacturing method 74. Figure 9The resulting structure is shown, where reference numeral 28' identifies the molded package body, which maintains interconnects in the form of a larger molded block 134 during this processing stage. A single cleavage is then performed to divide the interconnect package array 116 into discrete cells or LGA packages 20, as... Figure 10 As shown. For this purpose, any suitable single-cutting process can be used, including sawing or punching. Single-cutting removes the structure previously present within the single-cut track 128, thereby destroying most (if not substantially all) of the ESD protection grid 94 in terms of volume. However, as previously discussed and as... Figure 10 As shown, extension tabs 70 remain in the form of articles or residues within the newly cut LGA package 20, each tab 70 extending to the cut sidewall of the package substrate 22, or more generally, the cut sidewall of the LGA package 20; the term "cut sidewall" refers to the sidewall defined by the cut. Thus, any given LGA package 20 includes at least one extension tab 70 directly or indirectly electrically coupled to the die attachment region 31. Additional extension tabs 70 extend to the cut package sidewall and pass through it (specifically, through the portion of the sidewall defined by the edge of the package substrate). Therefore, unless additional steps are taken after the cut of the interconnect package array to cover the exposed ends of the tabs 70 in some way, the outer ends of the extension tabs 70 are visible from outside the package.

[0105] Summarize

[0106] Therefore, interconnect substrate arrays incorporating integrated ESD protection grids and methods have been provided for manufacturing microelectronic packages using such interconnect substrate arrays and microelectronic packages produced according to such methods. By integrating ESD protection grids into various interconnect substrate arrays, the likelihood and severity of array-level manufacturing ESD events can be advantageously minimized to improve the uniformity of package performance, reduce yield losses, and thus reduce package manufacturing costs. Overall package reliability can also be improved by reducing array-level manufacturing ESD events, which could otherwise introduce low-level latent defects that are at least difficult to detect, if not undetectable during final-stage testing. Notably, embodiments of the ESD protection grids described herein can be integrated into various interconnect substrate types and designs with minimal layout changes and minimal cost; for example, without the ESD protection grids described herein, embodiments of the package manufacturing processes described above can be advantageously used in conjunction with any substrate array or "carrier" that remains electrically floating continuously or intermittently during array-level processing. Furthermore, the ESD protection grids are compatible with a wide variety of workpieces in currently available processing equipment. Finally, in at least some cases, embodiments of the manufacturing method described above can provide additional enhanced ESD protection by integrating a front-side ESD grounding structure, which can be formed on the front side of a semiconductor die contained within a given microelectronic package. When present, such a front-side ESD grounding structure can further contribute to providing a low-resistance electrical path from the front side of the given die to the rear side of the die, ultimately through the ESD protection grid and to an electrically grounding contact provided by a mechanism or device for processing the microelectronic package and other packages during array-level processing.

[0107] In an embodiment, a method for manufacturing a microelectronic package includes independently manufacturing, purchasing, or otherwise obtaining an interconnect substrate array. The interconnect substrate array includes: a package substrate including a die attachment region; a single cleavage interspersed with the package substrate; a peripheral machine ground contact adjacent to an edge region of the interconnect substrate array; and an ESD protection grid including ESD grid lines electrically coupling the die attachment region to the peripheral machine ground contact. The ESD grid lines are at least partially formed in the single cleavage of the interconnect substrate array. The method further includes the steps or processes of: performing array-level manufacturing steps to generate an interconnect package array using the interconnect substrate array, while electrically coupling the die attachment region to electrical ground via the ESD protection grid during at least one array-level manufacturing step. After performing the array-level manufacturing steps, the interconnect package array is cleaved to produce a plurality of cleaved microelectronic packages. Additionally, in at least some embodiments, performing the array-level manufacturing steps may include attaching an IC die to a die attachment region using a die bonding machine while maintaining contact between the peripheral machine ground contacts and the grounding characteristics of the die bonding machine; for example, the IC die may be bonded to the die attachment region using a conductive bonding material. Alternatively, if no ESD protection grid is present, the die attachment region will be electrically floating when the IC die is attached to the die attachment region using a die bonding machine. In other words, if no ESD protection is present, the die attachment region will be electrically floating when the IC die is attached to the die attachment region using a die bonding machine.

[0108] Interconnect substrate arrays, such as substrate strips, with integrated ESD protection grids are also provided. In embodiments, the interconnect substrate array includes: a package substrate including a die attachment region; a single chute interspersed with the package substrate; at least one peripheral machine ground contact adjacent to an edge region of the interconnect substrate array; a dielectric substrate array body; and an ESD protection grid formed in the dielectric substrate array body. The ESD protection grid includes ESD grid lines electrically coupling the die attachment region to the peripheral machine ground contact. The ESD grid lines are at least partially formed in the single chute of the interconnect substrate array. Additionally, in at least some cases, the interconnect substrate array takes the form of a substrate strip with a generally rectangular planar shape, the package substrate is arranged in at least a first grid layout, and the peripheral machine ground contact is formed as an extended metal contact located near and extending generally parallel to the extended side edge of the substrate strip. In other cases, the ESD protection grid is primarily located in a single cleavage in terms of volume, and each ESD grid line has a thickness less than half the thickness of the package substrate. Alternatively, the package substrate may include a ground plane through which the die attachment area is electrically coupled to the ESD protection grid.

[0109] The foregoing also discloses a type of microelectronic package manufactured using an interconnect substrate array with an integrated ESD protection grid. In embodiments, the microelectronic package includes: a package substrate having a die attachment region and a single-cut sidewall; an IC die having a die rear side facing the die attachment region and a die front side opposite the die rear side; and a conductive bonding layer that bonds the IC die to the die attachment region. Cut-off ESD protection grid lines (e.g., the extended tabs 70 described above) are electrically coupled to the die attachment region. Additionally, the cut-off ESD protection grid lines extend to and pass through or penetrate one of the single-cut sidewalls of the package substrate. In at least some embodiments, the microelectronic package further includes an ESD grounding structure formed on the die front side, having an annular geometry and extending around a peripheral portion of the die front side. When provided, the ESD grounding structure is electrically coupled to the die attachment region via the die rear side and the conductive bonding layer.

[0110] Although at least one exemplary embodiment has been presented in the foregoing detailed descriptions, it should be understood that numerous variations exist. It should also be understood that the exemplary embodiments are merely examples and are not intended to limit the scope, applicability, or configuration of the invention in any way. More precisely, the foregoing detailed descriptions will provide those skilled in the art with a convenient guide for implementing exemplary embodiments of the invention, and it should be understood that various changes can be made to the function and arrangement of the elements described in the exemplary embodiments without departing from the scope of the invention as set forth in the appended claims. Numerical identifiers, such as “first,” “second,” “third,” etc., have been used above according to the order in which certain elements are introduced in the foregoing detailed descriptions. Such numerical identifiers may also be used in subsequent claims to indicate the order of introduction in the claims. Therefore, such numerical identifiers may vary between the detailed descriptions and subsequent claims to reflect differences in the order of element introduction.

Claims

1. A method for fabricating a microelectronic package, characterized by, include: An interconnect substrate array is obtained, the interconnect substrate array comprising: A packaging substrate, the packaging substrate including a die attachment area; A single-cut channel, wherein the single-cut channel is interspersed with the packaging substrate; Peripheral machine grounding contacts, the peripheral machine grounding contacts being adjacent to the edge region of the interconnect substrate array; and An electrostatic discharge (ESD) protection grid, the ESD protection grid including ESD grid lines that electrically couple the die attachment area to the peripheral machine ground contact, the ESD grid lines being at least partially formed in the single cleavage of the interconnect substrate array; Perform array-level manufacturing steps to generate an interconnect package array using the interconnect substrate array, while electrically coupling the die attachment area to electrical ground via the ESD protection grid during at least one of the array-level manufacturing steps; and After performing the array-level manufacturing steps, the interconnect package array is diced to produce multiple diced microelectronic packages.

2. The method of claim 1, wherein, Performing the array-level manufacturing steps includes attaching an integrated circuit (IC) die to the die attachment area using a die bonding machine while maintaining contact between the peripheral machine grounding contact and the grounding feature of the die bonding machine.

3. The method of claim 2, wherein, Bonding includes using a conductive bonding material to bond the IC die to the die attachment region.

4. The method of claim 2, wherein, If the ESD protection grid is not present, the die attachment area will be electrically floating when the IC die is attached to the die attachment area using the die bonding machine.

5. An array of interconnected substrates, characterized in that, include: A packaging substrate, the packaging substrate including a die attachment area; A single-cut channel, wherein the single-cut channel is interspersed and interconnected with the packaging substrate; Peripheral machine grounding contact, the peripheral machine grounding contact being adjacent to the edge region of the interconnect substrate array; Dielectric substrate array body; as well as An electrostatic discharge (ESD) protection grid is formed in the dielectric substrate array body and includes ESD grid lines that electrically couple the die attachment area to the peripheral machine grounding contact, the ESD grid lines being at least partially formed in the single cleavage of the interconnect substrate array.

6. The array of interconnection substrates of claim 5, wherein, The interconnect substrate array includes a substrate strip having a generally rectangular planar shape; The packaging substrate is arranged in at least a first grid layout; and The peripheral machine grounding contact is formed as an elongated metal contact, which is located near the side edge of the substrate strip and extends generally parallel to the side edge.

7. The interconnect substrate array according to claim 5, characterized in that, The ESD protection grid is mainly located in the single tangent in terms of volume; The packaging substrate has an average thickness; and Each of the ESD grid lines has a thickness less than half the average thickness of the package substrate.

8. The interconnect substrate array according to claim 5, characterized in that, The packaging substrate includes a ground plane, and the die attachment area is electrically coupled to the ESD protection grid through the ground plane.

9. A microelectronic package, characterized in that, include: A packaging substrate having a die attachment area and a single-cut sidewall; An integrated circuit (IC) die, the IC die having a rear side facing the die attachment area and a front side opposite to the rear side; A conductive bonding layer that bonds the IC die to the die attachment region; as well as A cut electrostatic discharge (ESD) protection grid line, the cut ESD protection grid line being electrically coupled to the die attachment region, the cut ESD protection grid line extending to and passing through one of the single-cut sidewalls of the package substrate. The microelectronic package further includes an ESD grounding structure formed on the front side of the die, having an annular geometry and extending around the peripheral portion of the front side of the die. The ESD grounding structure is electrically coupled to the die attachment area through the rear side of the die and the conductive bonding layer.

Images