Semiconductor structure and method for manufacturing the same

Abstract

The semiconductor structure includes a substrate, a conductive region, a first insulating layer, a second insulating layer, a gate structure, a low-k spacer, a gate contact, and a conductive region contact. The low-k spacer is formed between the sidewall of the gate structure and the first insulating layer. The gate contact is bonded to the top surface of the gate structure. Along the top surface of the second insulating layer, the adjacent distance between the sidewall of the gate contact and the conductive region contact is in the range of about 4 nm to about 7 nm. A method for manufacturing a semiconductor structure is also provided.

Description

Technical Field

[0001] The present invention relates to a semiconductor structure and a method for manufacturing the same. In particular, the disclosed semiconductor structure comprises a low-k spacer laterally contacting a sidewall of a gate structure, and an offset gate contact for bonding the gate structure and the low-k spacer. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced rapid development. Technological advances in materials and design in ICs have produced multiple generations of ICs. Each generation has smaller and more complex circuits than the previous generation. However, these advances have increased the complexity of IC processing and manufacturing.

[0003] Over the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased, while geometry size (i.e., the smallest component (or line) that can be produced using a manufacturing process) has decreased. This shrinking process generally provides benefits by increasing production efficiency and reducing associated costs.

[0004] However, as feature sizes continue to decrease, manufacturing processes continue to become more difficult to perform, and the critical dimension uniformity of components (or lines) continues to become more difficult to control. For example, the precision of photolithography operations may cause overlay offset defects. Therefore, it is challenging to form reliable semiconductor devices at increasingly smaller sizes. Summary of the invention

[0005] Some embodiments of the present application provide a semiconductor structure, including: a substrate having a first surface; a conductive region located in the substrate; a first insulating layer located above the first surface; a second insulating layer located above the first insulating layer; a gate structure located above the first surface of the substrate and surrounded by the first insulating layer; a low-k spacer located between the side wall of the gate structure and the first insulating layer; a gate contact bonded to the top surface of the gate structure; and a conductive region contact located above the conductive region and surrounded by the first insulating layer and the second insulating layer, the top surface of the conductive region contact being flush with the top surface of the second insulating layer; wherein, along the top surface of the second insulating layer, the adjacent distance between the side wall of the gate contact and the conductive region contact is in the range of 4nm to 7nm.

[0006] Other embodiments of the present application provide a semiconductor structure, including: a substrate having a first surface; a conductive region located in the substrate; a first insulating layer located above the first surface; a second insulating layer located above the first insulating layer; a gate structure located above the first surface of the substrate and surrounded by the first insulating layer; a low-k spacer located between the side wall of the gate structure and the first insulating layer; a gate contact bonded to the top surface of the gate structure and the top surface of the low-k spacer; and a conductive region contact located above the conductive region and surrounded by the first insulating layer and the second insulating layer.

[0007] Some other embodiments of the present application provide a method for manufacturing a semiconductor structure, comprising: forming an insulating stack above a substrate, the substrate having a conductive region and an isolation region at a first surface of the substrate, and having a conductive region contact and a gate structure above the conductive region and the isolation region, respectively, wherein the gate structure is laterally surrounded by a low-k spacer; forming a first groove passing through the isolation stack above the gate structure by aligning the first groove with a top surface of the gate structure and a top surface of the low-k spacer; forming a second groove passing through the isolation stack above the conductive region contact; forming a heavy covering layer above the isolation stack, the first groove and the second groove; and forming a first through-hole contact and a second through-hole contact in the first groove and the second groove, respectively. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] When read in conjunction with the accompanying drawings, various aspects of the present invention can be best understood from the following detailed description. It should be noted that, in accordance with standard industry practice, various structures are not drawn to scale. In fact, the size of each structure may be arbitrarily increased or decreased for clarity of discussion.

[0009] Figure 1A is a schematic diagram illustrating a top perspective view of a semiconductor structure according to some embodiments of the present invention.

[0010] Figure 1B According to some embodiments of the present invention, Figure 1A Cross-sectional view of the semiconductor structure along line AA'.

[0011] Figure 2 is a cross-sectional view of a semiconductor structure according to some embodiments of the present invention.

[0012] Figure 3 is a cross-sectional view of a semiconductor structure according to some embodiments of the present invention.

[0013] FIG. 4A to FIG. 4J is a cross-sectional view of a semiconductor device during an intermediate stage of manufacturing operations according to some embodiments of the present invention. DETAILED DESCRIPTION

[0014] The following disclosure provides a plurality of different embodiments or examples of different components for implementing the provided subject matter. In order to simplify the present invention, specific examples of elements and arrangements are described below. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first and second components are directly contacted and formed, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present invention may repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0015] Furthermore, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another (or additional) elements or components as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0016] As used herein, terms such as "first", "second" and "third" describe various elements, components, regions, layers and / or parts, which should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Terms such as "first", "second" and "third" do not imply an order or sequence when used in this article unless the context clearly indicates.

[0017] With the trend of shrinking semiconductor device geometries, it is difficult to further reduce the size of the gate itself and the vias above the source / drain region. Therefore, reducing the spacing between the gate and the source / drain region is one of the methods that helps in scaling down the process. However, in order to obtain better device performance, it is important to reduce the impact on the resistance of the interconnect, which may be related to mobility. For example, it becomes more difficult to control the parasitic capacitance of the metal gate to the source / drain due to the shrinking device geometry.

[0018] Meanwhile, in advanced technology nodes (especially below 20nm), the overlay offset problem arising from lithography operations becomes daunting due to the small spacing between components. Overlay offset may cause defects, dielectric breakdown, short circuits, or increased contact resistance. Therefore, the present invention provides a semiconductor structure that can reduce parasitic capacitance and expand the acceptability of the overlay offset budget of the gate contact, which can make the performance of the semiconductor device have better stability.

[0019] refer to Figure 1A and Figure 1B , Figure 1A is a schematic diagram illustrating a top perspective view of a semiconductor device, Figure 1B Is a semiconductor device along Figure 1A A cross-sectional view of the line AA' (along the main direction X) in FIG. Figure 1A Various layers such as etch stop layers and insulating layers are omitted to clearly illustrate the contacts. Figure 1B As shown, the semiconductor structure 100 includes a substrate 101. In some embodiments, the substrate 101 includes silicon, and optionally or additionally, the substrate 101 includes other materials such as germanium (Ge), silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs) and / or indium antimonide (InSb), or alloy semiconductors such as silicon germanium (SiGe), GaAsP, AlInAs, AlGaInAs, GaInP and / or GaInAsP; or combinations thereof. In some other embodiments, the substrate 101 includes one or more III-V group materials, one or more II-IV group materials, or combinations thereof. In some other embodiments, the substrate 101 is a semiconductor-on-insulator substrate, such as a silicon-on-insulator (SOI) substrate, a silicon-germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate. The substrate 101 may include various doping regions configured according to design requirements, such as a p-type doping region, an n-type doping region, or a combination thereof. The p-type doped region (e.g., p-type well) includes a p-type dopant, such as boron, indium, other p-type dopants, or a combination thereof. The n-type doped region (e.g., n-type well) includes an n-type dopant, such as phosphorus, arsenic, other n-type dopants, or a combination thereof. In some embodiments, the substrate 101 includes a doped region formed by a combination of a p-type dopant and an n-type dopant.

[0020] In some embodiments, Figure 1B In the cross section shown in the figure, the substrate 101 further includes an isolation region 102 at the first surface 101A of the substrate 101. For example, the isolation region 102 may be a shallow trench isolation (STI) arranged alternately with the semiconductor fins (which can be observed from another cross section cut along the semiconductor fins, rather than from the cross section as shown in FIG. Figure 1B101A is a cross-sectional view taken along the STI as shown in FIG. 101B ). The first surface 101A may be a top surface of the STI. The isolation region 102 may be used to define an active region and electrically isolate various device elements formed above / in the substrate 101. In some embodiments, a first insulating layer 103 may be formed above the isolation region 102. In some embodiments, the thickness of the first insulating layer 103 is in a range of about 8 nm to about 10 nm.

[0021] In some embodiments, the semiconductor structure 100 further includes a gate structure 111 and a first conductive region contact 131, which are laterally surrounded by the first insulating layer 103 and are located above the isolation region 102. In some embodiments, the gate structure 111 is connected to the isolation region 102 and the semiconductor fin (not shown). Figure 1B Each of the gate structure 111 and the first conductive region contact 131 extends along a secondary direction Y substantially orthogonal to the primary direction X. In some embodiments, the gate structure 111 may be a metal gate. In some embodiments, a top surface of the gate structure 111 is coplanar with a top surface of the first insulating layer 103.

[0022] In some embodiments, the low-k spacer 112 is formed over the sidewall of each of the gate structures 111 and thus laterally contacts the sidewall of each of the gate structures 111. In some embodiments, a first etch stop layer 113 is formed over a portion of the isolation region 102 that is not occupied by the gate structure 111. The first etch stop layer 113 also separates the low-k spacer 112 from the first insulating layer 103. In some embodiments, the low-k spacer 112 is laterally covered by the first etch stop layer 113. In some embodiments, a silicon nitride (SiN) layer 114 may be formed in the first insulating layer 103 and penetrate the first etch stop layer 113 for contacting the isolation region 102 of the substrate 101. In some embodiments, the thickness of the low-k spacer 112 is in a range of about 2 nm to about 5 nm.

[0023] In some embodiments, the first insulating layer 103 is made of silicon oxide (SiO 2 ) having a dielectric constant / k value in a range of about 4 to about 6. In some embodiments, the first etch stop layer 113 has a thickness in a range of about 4 nm to about 5 nm.

[0024] In some embodiments, the low-k spacer 112 is made of a low-k material such as SiOCN. In some embodiments, the concentration of silicon (Si) in the low-k spacer 112 is in a range of about 25% to about 35%. The concentration of oxygen (O) in the low-k spacer 112 is in a range of about 4% to about 6%. The concentration of carbon (C) in the low-k spacer 112 is in a range of about 35% to about 45%. The concentration of nitrogen (N) in the low-k spacer 112 is in a range of about 15% to about 25%. In some embodiments, the dielectric constant / k value of the low-k spacer 112 is less than the dielectric constant / k value of the first etch stop layer 113. In some embodiments, the dielectric constant / k value of the low-k spacer 112 is less than the dielectric constant / k value of the first insulating layer 103. In other words, the low-k spacer 112 may have the lowest dielectric constant between the gate structure 111 and the first conductive region contact 131, and may be used to reduce the influence between the currents in the gate structure 111 and the first conductive region contact 131, which may cause a resistance-capacitance (RC) delay. Therefore, by using the low-k spacer 112, the charge mobility in the gate structure 111 and the first conductive region contact 131 may be independent of each other. In some embodiments, the dielectric constant of the low-k spacer 112 is in the range of about 2 to about 3.

[0025] In some embodiments, the second etch stop layer 104 may be formed over the first insulating layer 103 and the gate structure 111. The second etch stop layer 104 may include silicon nitride (SiN). In some embodiments, the thickness of the second etch stop layer 104 may be in the range of about 3 nm to about 5 nm. In some embodiments, the second insulating layer 105 may be disposed over the second etch stop layer 104.

[0026] In some embodiments, the thickness of the second insulating layer 105 may be greater than the thickness of the second etch stop layer 104, for example, in the range of about 8 nm to about 12 nm. In some embodiments, the second insulating layer 105 may include an oxide such as plasma enhanced silicon oxide (PEOX). In some embodiments, the thickness of the second insulating layer 105 may be in the range of about 13 nm to about 16 nm.

[0027] In some embodiments, a third etch stop layer 106 may be formed on the second insulating layer 105, wherein the third etch stop layer 106 may include silicon nitride (SiN). In some embodiments, a third insulating layer 107 may be formed on the third etch stop layer 106. The third insulating layer 107 may be an interlayer dielectric. In some embodiments, the thickness of the third etch stop layer 106 may be greater than the thickness of the second etch stop layer 104. For example, the thickness of the third etch stop layer 106 may be in the range of about 8 nm to about 12 nm. In some embodiments, the thickness of the third insulating layer 107 may be greater than the thickness of the second insulating layer 105. For example, the thickness of the third insulating layer 107 may be in the range of about 30 nm to about 40 nm.

[0028] In some embodiments, the substrate 101 may further include a conductive region 121 at the first surface 101A of the substrate 101. As described above, the conductive region 121, such as an epitaxial region used as a source or drain of a transistor, may be formed on adjacent semiconductor fins ( Figure 1B 102 and the merging portion of the conductive region 121 is then surrounded by the isolation region 102 separating adjacent semiconductor fins. In some embodiments, the conductive region 121 is at a location between the two gate structures 111. In some embodiments, the conductive region 121 may include an epitaxial material such as silicon germanium (SiGe), silicon phosphide (SiP), silicon (Si), or other suitable source / drain materials. The conductive region 121 may optionally be doped with an implant, such as a p-type dopant or an n-type dopant.

[0029] In some embodiments, the first conductive region contact 131 may be formed on the conductive region 121 and electrically connected to the conductive region 121. In some embodiments, the first conductive region contact 131 may include a conductive material, such as cobalt (Co) or other suitable metals or alloys. In some embodiments, cobalt provides a lower resistance and may be a material used in devices that require a higher operating speed. However, due to the lack of adhesion of the first insulating layer 103 to the low-k material, cobalt may be susceptible to material loss during subsequent operations (such as annealing, chemical mechanical planarization, cleaning, etc.). Therefore, the present invention provides techniques and configurations for improving the reliability of the first conductive region contact 131 in some embodiments. For example, the first conductive region contact 131 may also include an outer layer 131' having a greater hardness than the inner layer. This can be achieved by adjusting the properties using different types of deposition techniques under different formation conditions. In some embodiments, from the perspective of the cross-sectional view, the first conductive region contact 131 may have a tapered structure, and therefore the top of the first conductive region contact 131 may have a larger critical dimension than the bottom of the first conductive region contact 131, as measured in the X direction.

[0030] In some embodiments, the top surface of the first conductive region contact 131 and the top surface of the gate structure 111 are connected to the through-hole contact, respectively. In some embodiments, the through-hole contact above the gate structure 111 is the gate contact 132A. In some embodiments, the through-hole contact above the first conductive region contact 131 is the second conductive region contact 132B. In some embodiments, the spacer 133 may be disposed at the sidewall (or a portion thereof) of the gate contact 132A and the sidewall (or a portion thereof) of the second conductive region contact 132B. In some embodiments, the top surface of the gate contact 132A and the top surface of the second conductive region contact 132B are coplanar with the top surface of the third insulating layer 107. In some embodiments, the material of the gate contact 132A or the second conductive region contact 132B may be different from the material of the first conductive region contact 131. For example, the first conductive region contact 131 includes cobalt, and the gate contact 132A or the second conductive region contact 132B includes tungsten (W). In some embodiments, from a cross-sectional perspective view, the gate contact 132A and the second conductive region contact 132B may both have a tapered structure, and thus the minimum distance between the gate contact 132A and the first conductive region contact 131 is aligned with the top surface of the second insulating layer 105. In some embodiments, the top of the gate contact 132A may have a larger critical dimension (measured in the X direction) than the bottom of the gate contact 132A. For example, the top dimension of the gate contact 132A may be in the range of about 18 nm to about 22 nm, and the bottom dimension of the gate contact 132A may be in the range of about 14 nm to about 18 nm. In some embodiments, the contacts 131, 132B, 132A may include multiple layers.

[0031] In some embodiments, the gate contact 132A is completely bonded to the top surface of the gate structure 111. However, in some embodiments of the present invention, because the gate contact 132A is laterally surrounded by the low-k spacer 112 or also by the first etch stop layer 113, the gate contact 132A may be offset from the first conductive region contact 131 by a distance D1 (see FIG. Figure 2 and Figure 3). In other embodiments, the gate contact 132A may be offset in the opposite direction by the offset distance D1, and thus further away from the first conductive region contact 131. In some embodiments, regardless of the offset of the gate contact 132A, the proximity distance D2 between the sidewall of the gate contact 132A and the top of the first conductive region contact 131 along the top surface of the second insulating layer 105 may be in a range from about 4 nm to about 7 nm. In some embodiments, where the geometric size of the semiconductor structure has been reduced, especially in advanced technology updates, the gate contact 132A may be offset toward or away from the first conductive region contact 131 within the offset distance D1 in a range of less than about 4 nm.

[0032] like Figure 2 and Figure 3 As shown, in some embodiments, the center 132C of the gate contact 132A is offset from the centerline 111C of the gate structure 111 by an offset distance D1, which is smaller than the offset distance D1 previously described. Figure 1B This limitation is based on the fact that the gate contact 132A may not contact the first conductive region contact 131. In some embodiments, if the gate contact 132A is offset toward the first conductive region contact 131, the distance D2′ between the sidewall of the gate contact 132A and the top of the conductive region contact 131 is less than about 7 nm.

[0033] For example, once the offset distance D1 is greater than D2 (e.g., about 4 nm), the gate contact 132A may be too close to the first conductive region contact 131 and cause a risk of short circuit between the gate contact 132A and the first conductive region contact 131. As previously mentioned, the thickness of the low-k spacer 112 is in the range of about 2 nm to about 5 nm. Therefore, in some embodiments, Figure 2 As shown, the bottom surface of the gate contact 132A can contact the top surface of the low-k spacer 112, while the low-k spacer 112 can still prevent the short circuit between the gate contact 132A and the first conductive region contact 131. Figure 3 As shown, in some embodiments, because the thickness of the low-k spacer 112 can be less than about 4 nm, the bottom surface of the gate contact 132A can also contact the top surface of the first etch stop layer 113. In such an embodiment, both the low-k spacer 112 and the first etch stop layer 113 can be used to prevent a short circuit between the gate contact 132A and the first conductive region contact 131. In other words, the coplanarity of the top surface of the first etch stop layer 113, the top surface of the low-k spacer 112, and the top surface of the gate structure 111 can provide a larger overlay offset budget for the bonding of the gate contact 132A, which can correspondingly provide better device reliability and yield.

[0034] On the other hand, the present invention may have a multi-spacer structure around the gate structure 111, wherein the multi-spacer structure includes at least a low-k spacer 112 and a first etch stop layer 113, or further includes a first insulating layer 103. In the case where the dielectric constant of the multi-spacer structure is low, especially by using the low-k spacer 112, the multi-spacer structure can not only alleviate the problem of parasitic capacitance, leakage and / or dielectric breakdown that may occur due to closely arranged conductive features (i.e., the proximity of the gate contact 132A and the first conductive region contact 131), but also widen the tolerance window for the overlay offset of the gate contact 132A formed above the gate structure 111. In some embodiments, due to the thickness of the low-k spacer 112 and the first etch stop layer 113, the gate contact 132A may not contact the top surface of the first etch stop layer 113; that is, before contacting the top surface of the first etch stop layer 113, the offset of the gate contact 132A may exceed the limit of the offset distance D1.

[0035] Figure 4A is a cross-sectional view of a semiconductor structure during an intermediate stage of a manufacturing operation according to some embodiments of the present invention. Figure 4A As shown, a substrate 101 is provided, wherein the material of the substrate 101 is previously Figures 1A to 3 In such an embodiment, the substrate 101 has an isolation region 102 formed at the first surface 101A of the substrate 101. The isolation region 102 may include a shallow trench isolation (STI). As previously described, a plurality of gate structures 111 are formed in the isolation region 102 and in the semiconductor fins ( Figure 4A ), and a conductive region 121, such as an epitaxial region used as a source or drain of a transistor, may be formed on an adjacent semiconductor fin ( Figure 4A ), and the merged portion of the conductive region 121 is then surrounded by an isolation region 102 that separates adjacent semiconductor fins. In some embodiments, the gate structure 111 may be a metal gate. In some embodiments, the gate structure 111 may be formed by a replacement gate technique, in which a sacrificial gate (not shown) and a low-k spacer 112 are formed, and then a first insulating layer 103 is formed over a first etch stop layer 113, and then a planarization operation is performed from the top, and then the sacrificial gate is replaced with a conductive material. Optionally, the formation of the gate structure 111 may be performed by a gate-first approach, a gate-last approach, deposition, etching, a planarization operation, or other suitable operations. In some embodiments, a silicon nitride layer 114 may be formed in the first insulating layer 103 and penetrate the first etch stop layer 113.

[0036] Subsequently, second etch stop layer 104 is formed over first insulating layer 103, and second insulating layer 105 is formed over second etch stop layer 104. In some embodiments, second etch stop layer 104 may include silicon nitride (SiN), and second insulating layer 105 may include an oxide such as plasma enhanced silicon oxide (PEOX).

[0037] In some embodiments, the first conductive region contact 131 is subsequently formed over the conductive region 121. In some embodiments, the first conductive region contact 131 may be formed by etching a groove through the first etch stop layer 113, the first insulating layer 103, the second etch stop layer 104, and the second insulating layer 105. In some embodiments, the etching operation stops when the bottom of the groove reaches the conductive region 121. In some embodiments, boron implantation may be performed to enhance the electrical characteristics of the conductive region 121. Next, in some embodiments, a conductive material may be formed in the groove. In some embodiments, the conductive material is cobalt, which may be formed by chemical vapor deposition. In some embodiments, a silicide layer may be formed between the conductive material of the first conductive region contact 131 and the conductive region 121. Optionally, the formation of the conductive material may include one or more deposition steps, wherein different conditions / techniques may result in different physical properties. For example, the conductive material may include a hardened conductive material near the sidewalls of the groove for forming the outer layer 131'. In addition, a planarization operation such as a chemical mechanical planarization operation may be performed to remove excess conductive material to form the first conductive region contact 131. Therefore, the first conductive region contact 131 is surrounded by the first insulating layer 103, the second etch stop layer 104, and the second insulating layer 105, and the top surface of the first conductive region contact 131 is flush with the top surface of the second insulating layer 105. In some embodiments, the top critical dimension of the first conductive region contact 131 is in a range from about 14 nm to about 17 nm, for example, about 15 nm.

[0038] Figure 4B is a cross-sectional view of a semiconductor structure during an intermediate stage of a manufacturing operation according to some embodiments of the present invention. Figure 4B As shown, after the first conductive region contact 131 is formed in the first insulating layer 103 and the second insulating layer 105, an insulating stack may be formed over the substrate. In some embodiments, the insulating stack includes a third etch stop layer 106 and a third insulating layer 107. In some embodiments, the third etch stop layer 106 is formed over the second insulating layer 105, wherein the third etch stop layer 106 may include silicon nitride. In some embodiments, the third insulating layer 107 is formed over the third etch stop layer 106.

[0039] Figure 4C , Figure 4D and Figure 4E is a cross-sectional view of a semiconductor structure during a subsequent intermediate stage of a manufacturing operation according to some embodiments of the present invention. As shown in these figures, a first recess 140 and a second insulating layer 105 can be formed above the gate structure 111 through an isolation stack (e.g., a third etch stop layer 106 and a third insulating layer 107). In some embodiments, the first recess 140 is aligned with a top surface of the gate structure 111 and a top surface of the low-k spacer 112. In other words, the first recess 140 can be aligned not only with the top surface of the gate structure 111 to be bonded thereto, but also with the top surface of the low-k spacer 112 to be bonded thereto. In some embodiments, the first recess 140 is aligned with a top surface of the gate structure 111, a top surface of the low-k spacer 112, and a top surface of the first etch stop layer 113. That is, in some embodiments, from a top perspective view, the process window for forming the first recess 140 can be as wide as the critical dimension of the combination of the gate structure 111, the low-k spacer 112, and the first etch stop layer 113. Therefore, as Figure 4C As shown, the bottom of the first groove 140 may only overlap with the gate structure 111; in other embodiments, such as Figure 4D As shown, the bottom of the first groove 140 may overlap with the gate structure 111 and the low-k spacer 112. Figure 4E As shown, in other embodiments, the bottom of the first recess 140 may overlap with the gate structure 111 , the low-k spacer 112 , and the first etch stop layer 113 .

[0040] In some embodiments, the first groove 140 can be formed by patterning by photolithography technology (such as extreme ultraviolet, EUV). In some embodiments, the bottom of the first groove 140 is at the second etch stop layer 104, and thus the gate structure 111 is not exposed when the first groove 140 is formed. In some embodiments, the first groove 140 has a tapered profile from a cross-sectional perspective view. In some embodiments, the angle θ1 between the sidewall of the first groove 140 and the top surface of the second etch stop layer 104 is in a range of about 85 degrees to about 90 degrees, for example, about 88 degrees. In some embodiments, the distance D3 between the sidewall of the first groove 140 and the first conductive region contact 131 at the top surface of the second insulating layer 105 is in a range of less than about 7nm, for example, about 5.5nm.

[0041] Figure 4F is a cross-sectional view of a semiconductor structure during an intermediate stage of a manufacturing operation according to some embodiments of the present invention. Figure 4FAs shown, a second recess 141 passing through the isolation stack (e.g., the third etch stop layer 106 and the third insulating layer 107) can be formed above the first conductive region contact 131. In some embodiments, the second recess 141 is aligned with the top surface of the first conductive region contact 131. In some embodiments, the second recess 141 can be formed by patterning by photolithography (such as extreme ultraviolet, EUV). In some embodiments, the bottom of the second recess 141 is at the third etch stop layer 106, and thus when the second recess 141 is formed, the first conductive region contact 131 is not exposed. In some embodiments, after the second recess 141 is formed, the thickness of the third etch stop layer 106 remaining above the first conductive region contact 131 is about 7.5 nm. In some embodiments, from a cross-sectional perspective view, the second recess 141 has a tapered profile. In some embodiments, the angle θ2 between the sidewall of the second recess 141 and the top surface of the third etch stop layer 106 is in the range of about 85 degrees to about 90 degrees, for example, about 88 degrees.

[0042] Figure 4G is a cross-sectional view of a semiconductor structure during an intermediate stage of a manufacturing operation according to some embodiments of the present invention. Figure 4G As shown, a heavy capping layer 142 may be formed over the isolation stack (e.g., the third etch stop layer 106 and the third insulating layer 107), the first recess 140, and the second recess 141. In such an embodiment, the heavy capping layer 142 is a continuous layer that may cover the top surface of the isolation stack, the sidewalls of the first recess 140, the bottom surface of the first recess 140, the sidewalls of the second recess 141, and the bottom surface of the second recess 141. In some embodiments, the heavy capping layer 142 is made of silicon nitride (SiN), which may be the same material as the second etch stop layer 104 and the third etch stop layer 106.

[0043] Figure 4H is a cross-sectional view of a semiconductor structure during an intermediate stage of a manufacturing operation according to some embodiments of the present invention. Figure 4H As shown, the top and bottom portions of the heavy cover layer 142 may be removed by an etching operation. In some embodiments, the heavy cover layer 142 is partially removed by an anisotropic etching operation (e.g., dry etching), and thus after the etching operation, only the portion of the heavy cover layer 142 covering the sidewalls of the first recess 140 and the second recess 141 remains. The remaining heavy cover layer is previously Figures 1B to 3 In such an embodiment, the top surface of the gate structure 111 and the top surface of the conductive region contact 131 are also exposed due to the removal of the portion of the etch stop layer thereon, and thus can contact the via contact in a subsequent operation.

[0044] Fig. 4I and Figure 4J is a cross-sectional view of a semiconductor structure during an intermediate stage of a manufacturing operation according to some embodiments of the present invention. Fig. 4I As shown, the first through-hole contact (i.e., gate contact 132A) and the second through-hole contact (i.e., second conductive region contact 132B) may be formed in the first groove 140 and the second groove 141, respectively. In some embodiments, the gate contact 132A and the second conductive region contact 132B may be formed by depositing a conductive material such as tungsten (W) in the grooves. Figure 4J As shown, in some embodiments, a planarization operation such as chemical mechanical planarization may be performed to remove excess conductive material, and thus the thickness of the second insulating layer 107 may be reduced, for example, from greater than about 40 nm to a range of about 30 nm to about 40 nm.

[0045] It should be noted that Figure 4F-4J In the following steps shown in the figure, you can provide Figure 4C , Figure 4D , Figure 4E any configuration.

[0046] According to the present invention, a semiconductor structure and a method for manufacturing the same are disclosed. In general, the present invention can provide a greater tolerance for the overlay offset problem of the gate contact, for example, by using a low-k spacer and a first etch stop layer that laterally surrounds the gate structure, and the tolerance window for forming the overlay offset of the gate contact can be widened or expanded by the top surface of the low-k spacer and the first etch stop layer. In addition, the low-k spacer is not only used to generate an allowable offset distance for the bonding of the gate contact, but also used to reduce the parasitic capacitance between the gate contact and the conductive area contact. Therefore, through the present invention, the RC delay problem and the challenge of the bonding of the gate contact under the geometric contraction of the semiconductor device can be alleviated, and therefore the stability and reliability of the performance of the semiconductor device can be ensured.

[0047] In one exemplary aspect, a semiconductor structure is provided. The semiconductor structure includes a substrate, a conductive region, a first insulating layer, a second insulating layer, a gate structure, a low-k spacer, a gate contact, and a conductive region contact. The substrate has a first surface. The conductive region is located in the substrate. The first insulating layer is located above the first surface. The second insulating layer is located above the first insulating layer. The gate structure is located above the first surface of the substrate and is surrounded by the first insulating layer. The low-k spacer is located between the sidewall of the gate structure and the first insulating layer. The gate contact is bonded to the top surface of the gate structure. The conductive region contact is located above the conductive region and is surrounded by the first insulating layer and the second insulating layer. The top surface of the conductive region contact is flush with the top surface of the second insulating layer. The adjacent distance between the sidewall of the gate contact and the conductive region contact along the top surface of the second insulating layer is in the range of from about 4nm to about 7nm.

[0048] In some embodiments, the gate contact is bonded to the gate structure and the low-k spacer. In some embodiments, the gate contact is offset from the center of the gate structure by an offset distance that is less than the proximity distance. In some embodiments, the substrate also has an isolation region at the first surface, and the gate structure contacts the isolation region. In some embodiments, the semiconductor structure also includes a first etch stop layer located above the isolation region, and the low-k spacer is laterally covered by the first etch stop layer. In some embodiments, the top surface of the first etch stop layer, the top surface of the low-k spacer, and the top surface of the gate structure are coplanar. In some embodiments, the bottom surface of the gate contact contacts the top surface of the low-k spacer. In some embodiments, the bottom surface of the gate contact also contacts the top surface of the first etch stop layer. In some embodiments, the dielectric constant of the low-k spacer is less than the dielectric constant of the first insulating layer. In some embodiments, the substrate also has a conductive region at the first surface of the substrate, and the conductive region contact is located above the conductive region and electrically connected to the conductive region.

[0049] In another exemplary aspect, a semiconductor structure is provided. The semiconductor includes a substrate, a conductive region, a first insulating layer, a second insulating layer, a gate structure, a low-k spacer, a gate contact, and a conductive region contact. The substrate has a first surface. The conductive region is located in the substrate. The first insulating layer is located above the first surface. The second insulating layer is located above the first insulating layer. The gate structure is located above the first surface of the substrate and is surrounded by the first insulating layer. The low-k spacer is located between the sidewall of the gate structure and the first insulating layer. The gate contact is bonded to the top surface of the gate structure and the top surface of the low-k spacer. The conductive region contact is located above the conductive region and is surrounded by the first insulating layer and the second insulating layer.

[0050] In some embodiments, the distance between the sidewall of the gate contact and the top surface of the conductive region contact is less than 7 nm. In some embodiments, the bottom dimension of the gate contact is in the range of 14 nm to 18 nm. In some embodiments, the top surface of the first insulating layer is coplanar with the top surface of the gate structure. In some embodiments, the top surface of the second insulating layer is coplanar with the top surface of the conductive region contact. In some embodiments, the minimum distance between the gate contact and the conductive region contact is aligned with the top surface of the second insulating layer. In some embodiments, the center of the gate contact is offset away from the center of the gate structure by an offset distance of less than 4 nm.

[0051] In another exemplary aspect, a method for manufacturing a semiconductor structure is provided. The method includes the following operations. An isolation stack is formed above a substrate. The substrate has a conductive region and an isolation region at a first surface of the substrate, and has a conductive region contact and a gate structure above the conductive region and the isolation region, respectively. The gate structure is laterally surrounded by a low-k spacer. A first groove passing through the isolation stack is formed above the gate structure by aligning the first groove with the top surface of the gate structure and the top surface of the low-k spacer. A second groove passing through the isolation stack is formed above the conductive contact. A heavy cover layer is formed above the isolation stack, the first groove, and the second groove. A first through-hole contact and a second through-hole contact are formed in the first groove and the second groove, respectively.

[0052] In some embodiments, the method further comprises: removing a top portion of the heavy cover layer and a bottom portion of the heavy cover layer in the first groove and the second groove, thereby exposing a top surface of the gate structure and a top surface of the low-k spacer from the heavy cover layer. In some embodiments, after forming the first groove and the second groove, the gate structure and the conductive region contact are not exposed.

[0053] The foregoing summarizes the structures of several embodiments so that those skilled in the art can better understand the various aspects of the present invention. Those skilled in the art should understand that they can easily use the present invention as a basis for designing or modifying other processes and structures to achieve the same purposes and / or achieve the same advantages as the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent constructions do not deviate from the spirit and scope of the present invention, and that various changes, substitutions and modifications may be made without departing from the spirit and scope of the present invention.

Claims

1. A semiconductor structure comprising: A substrate having a first surface; a conductive region located in the substrate; a first insulating layer, located above the first surface; a second insulating layer, located above the first insulating layer; a gate structure located above the first surface of the substrate and surrounded by the first insulating layer; a low-k spacer located between a sidewall of the gate structure and the first insulating layer, wherein the low-k spacer comprises SiOCN, and wherein a concentration of silicon (Si) in the low-k spacer is in a range of 25% to 35%, a concentration of oxygen (O) in the low-k spacer is in a range of 4% to 6%, a concentration of carbon (C) in the low-k spacer is in a range of 35% to 45%, and a concentration of nitrogen (N) in the low-k spacer is in a range of 15% to 25%; a gate contact bonded to a top surface of the gate structure; and A conductive area contact, located above the conductive area and surrounded by the first insulating layer and the second insulating layer, wherein a top surface of the conductive area contact is flush with a top surface of the second insulating layer; Wherein, along the top surface of the second insulating layer, the proximity distance between the sidewall of the gate contact and the conductive region contact is in the range of 4 nm to 7 nm, wherein the gate contact comprises a side wall extending from a first end region to a second end region, and a heavy covering layer is arranged on an intermediate region of the side wall of the gate contact between the first end region and the second end region, wherein the gate contact extends beyond the heavy covering layer and encapsulates the heavy covering layer therein, and wherein the side walls of the gate contact at the first end region and the second end region are aligned on the same line with the outermost wall of the heavy covering layer at the intermediate region.

2. The semiconductor structure according to claim 1, wherein: The gate contact is bonded to the gate structure and the low-k spacer.

3. The semiconductor structure according to claim 2, wherein: The gate contact is offset from a center of the gate structure by an offset distance that is less than the proximity distance.

4. The semiconductor structure according to claim 1, wherein: The substrate also has an isolation region at the first surface, and the gate structure is in contact with the isolation region. 5 . The semiconductor structure of claim 4 , further comprising a first etch stop layer over the isolation region, and the low-k spacer is laterally covered by the first etch stop layer.

6. The semiconductor structure according to claim 5, wherein: A top surface of the first etch stop layer, a top surface of the low-k spacer, and a top surface of the gate structure are coplanar.

7. The semiconductor structure according to claim 6, wherein: A bottom surface of the gate contact contacts the top surface of the low-k spacer.

8. The semiconductor structure according to claim 7, wherein: The bottom surface of the gate contact also contacts the top surface of the first etch stop layer.

9. The semiconductor structure according to claim 1, wherein: The dielectric constant of the low-k spacer is less than the dielectric constant of the first insulating layer.

10. The semiconductor structure according to claim 4, wherein: The substrate also has a conductive region at the first surface of the substrate, and the conductive region contact is located over and electrically connected to the conductive region.

11. A semiconductor structure comprising: A substrate having a first surface; a conductive region located in the substrate; a first insulating layer, located above the first surface; a second insulating layer, located above the first insulating layer; a gate structure located above the first surface of the substrate and surrounded by the first insulating layer; a low-k spacer located between a sidewall of the gate structure and the first insulating layer; a gate contact extending through the second insulating layer and bonded to a top surface of the gate structure and a top surface of the low-k spacer, wherein the gate contact includes a sidewall extending from a first end region to a second end region, and a heavy capping layer is disposed on an intermediate region of the sidewall of the gate contact between the first end region and the second end region, and wherein the first end region and the second end region are free of the heavy capping layer; and A conductive region contact located above the conductive region and surrounded by the first insulating layer and the second insulating layer, wherein the gate contact extends beyond the heavy covering layer and encapsulates the heavy covering layer therein, and wherein the side walls of the gate contact at the first end region and the second end region are aligned on the same line with the outermost wall of the heavy covering layer at the middle region.

12. The semiconductor structure according to claim 11, wherein: The distance between the sidewall of the gate contact and the top surface of the conductive region contact is less than 7 nm.

13. The semiconductor structure according to claim 11, wherein: The bottom dimension of the gate contact is in the range of 14 nm to 18 nm.

14. The semiconductor structure according to claim 11, wherein: A top surface of the first insulating layer is coplanar with the top surface of the gate structure.

15. The semiconductor structure according to claim 11, wherein: A top surface of the second insulating layer is coplanar with a top surface of the conductive region contact.

16. The semiconductor structure according to claim 15, wherein: A minimum distance between the gate contact and the conductive region contact is aligned with the top surface of the second insulating layer.

17. The semiconductor structure according to claim 11, wherein: The center of the gate contact is offset away from the center of the gate structure by an offset distance of less than 4 nm.

18. A method for manufacturing a semiconductor structure, comprising: forming an isolation stack over a substrate having a conductive region and an isolation region at a first surface of the substrate, and having a conductive region contact and a gate structure over the conductive region and the isolation region, respectively, wherein the gate structure is laterally surrounded by a low-k spacer; forming the first recess through the isolation stack over the gate structure by aligning the first recess with a top surface of the gate structure and a top surface of the low-k spacer; forming a second recess through the isolation stack above the conductive region contact; forming a heavy blanket layer over the isolation stack, the first recess, and the second recess; removing a top portion of the heavy cover layer and a bottom portion of the heavy cover layer in the first groove and the second groove, and forming a first through-hole contact and a second through-hole contact in the first groove and the second groove, respectively, wherein the first through-hole contact comprises a sidewall extending from a first end region to a second end region, and the heavy cover layer is arranged on an intermediate region of the sidewall of the first through-hole contact located between the first end region and the second end region, and wherein the first end region and the second end region have no heavy cover layer, wherein the first through-hole contact extends beyond the heavy cover layer and encloses the heavy cover layer therein, and wherein the sidewall of the first through-hole contact and the sidewall of the heavy cover layer are both in contact with the sidewall of the first groove.

19. The method according to claim 18, wherein: After removing the top portion of the heavy capping layer and the bottom portion of the heavy capping layer in the first and second recesses, a top surface of the gate structure and a top surface of the low-k spacer are exposed from the heavy capping layer.

20. The method according to claim 18, wherein: After forming the first recess and the second recess, the gate structure and the conductive region contact are not exposed.

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