Counter unit

Abstract

A counter unit is provided that can handle any output device, whether single-phase output, two-phase output or three-phase output, without waste. The counter unit (10) includes: a plurality of signal input terminals, each of which inputs pulse signals output from a plurality of external output devices (50); an input circuit (21a-21f) connected to each of the plurality of signal input terminals; a single-phase counter (13) and a multi-phase counter (15), wherein the single-phase counter (13) counts based on a single-phase pulse signal and the multi-phase counter (15) counts based on a multi-phase pulse signal; and a switching unit (16) that switches between connecting the input circuit (21a-21f) to the single-phase counter (13) and the multi-phase counter (15).

Description

Technical Field

[0001] The present invention relates to a counter unit for counting input digital pulses. Background Art

[0002] Conventionally, in a control system, there is known a counter unit having a plurality of input channels and capable of counting count values ​​of the plurality of channels. Some of these counter units have a three-phase input of A, B, and Z phases for each channel (for example, see Patent Document 1) or a two-phase input of A and B phases for each channel (for example, see Patent Document 2).

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent Publication No. 2010-14578

[0006] Patent Document 2: Japanese Patent Publication No. 2010-135974 Summary of the invention

[0007] Problems to be solved by the invention

[0008] The counter unit corresponding to the three-phase or two-phase output device includes an input channel including three input terminals corresponding to the three-phase pulse signal, or an input channel including two input terminals corresponding to the two-phase pulse signal. In addition, there is also a counter unit including a plurality of input channels corresponding to the three-phase or two-phase output device.

[0009] On the other hand, output devices used in connection with counter units having multiple input channels include flowmeters and other output devices that perform single-phase pulse output. When such output devices that perform single-phase pulse output are connected to counter units that perform three-phase or two-phase input, or when output devices that perform two-phase pulse output are connected to counter units having three-phase input, there is a problem of waste caused by unused inputs.

[0010] An embodiment of the present invention is made in view of the above situation, and its object is to provide a counter unit that can efficiently utilize multiple signal input terminals to connect any output device of single-phase output, two-phase output or three-phase output.

[0011] Technical means of solving problems

[0012] In order to solve the above-mentioned problem, a counter unit of one embodiment of the present invention includes: a plurality of signal input terminals, which respectively input pulse signals output from a plurality of external output machines; an input circuit, which is connected to each of the plurality of signal input terminals; a single-phase counter and a multi-phase counter, wherein the single-phase counter counts based on a single-phase pulse signal, and the multi-phase counter counts based on a multi-phase pulse signal; and a switching unit, which switches whether the input circuit is connected to the single-phase counter or the multi-phase counter.

[0013] Effects of the Invention

[0014] According to an embodiment of the present invention, regardless of whether the output device is a single-phase output, a two-phase output, or a three-phase output, multiple signal input terminals can be efficiently used for connection. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 This is a block diagram showing a schematic configuration of a control system using a counter unit according to an embodiment of the present invention.

[0016] Figure 2 is a block diagram showing the hardware configuration of a counter unit.

[0017] Figure 3 : is a figure which shows an example of the wiring board of the counter unit.

[0018] Figure 4 This is a diagram showing the structure of oversampling processing.

[0019] Figure 5 This is a wiring connection diagram for the counter unit in single-phase mode when used by connecting to an output device with single-phase output.

[0020] Figure 6 This is a wiring connection diagram for the counter unit in three-phase mode when used by connecting to an output device with three-phase output.

[0021] Figure 7 This is a wiring connection diagram for a counter unit in two-phase mode when used by connecting to an output device with two-phase output.

[0022] Figure 8 This is a wiring connection diagram for a counter unit in two-phase mode when used by connecting to an output device with two-phase output.

[0023] [Explanation of Symbols]

[0024] 1: Control system

[0025] 10: Counter unit

[0026] 11: Ministry of Communications

[0027] 12: Signal processing unit

[0028] 13: Single-phase counter

[0029] 15: Three-phase counter (multi-phase counter)

[0030] 16: Switching Department

[0031] 22: USB communication unit (switching receiving unit)

[0032] 21: Input circuit group

[0033] 21a~21f:Input circuit

[0034] 30: PLC (host device)

[0035] 50: Output machine

[0036] A1, A2, B1, B2, A3, B3, Z1, Z2: Signal input terminals DETAILED DESCRIPTION

[0037] Hereinafter, a camera module manufacturing apparatus 100 according to an embodiment will be described with reference to the drawings. First, an embodiment according to one aspect of the present invention (hereinafter also referred to as "this embodiment") will be described below with reference to the drawings.

[0038] §1. Application examples

[0039] (Overall overview of the control system)

[0040] Figure 1 1 is a block diagram showing a schematic structure of the entire control system 1 including the counter unit 10. Figure 1 As shown, the control system 1 includes a counter unit 10 and a programmable logic controller (PLC) 30. The control system 1 further includes a plurality of output devices 50 for outputting pulse signals. Moreover, the control system 1 may also include a notebook personal computer (PC) 40 as a setting device.

[0041] In the control system 1, the counter unit 10 receives a pulse signal generated by the output device 50 as an input, and uses a count value for counting the number of pulses of the received pulse signal to measure the operating state of the output device 50, such as an encoder. In addition, the counter unit 10 sends information represented by the count value for counting the pulse signal output by the output device 50 to the PLC 30 in each control cycle of the PLC 30.

[0042] The counter unit 10 includes: a plurality of signal input terminals (details will be described later) to which pulse signals output from one or more external output devices 50 are respectively input; and an input circuit group 21 connected to each of the plurality of signal input terminals.

[0043] Moreover, the counter unit 10 includes: a single-phase counter 13, which counts the number of pulses of the pulse signal from the single-phase output machine 50; a two-phase counter 14, which counts the number of pulses of the pulse signal from the two-phase output machine 50; and a three-phase counter 15, which counts the number of pulses of the pulse signal from the three-phase output machine 50.

[0044] Furthermore, the counter unit 10 includes a switching unit 16 that switches which of the single-phase counter 13, the two-phase counter 14, and the three-phase counter 15 the input circuit group 21 is connected to. The switching unit 16 switches which of the single-phase counter 13, the two-phase counter 14, and the three-phase counter 15 the input circuit group 21 is connected to, depending on whether the output device 50 connected to each signal input terminal is a single-phase output device, a two-phase output device, or a three-phase output device.

[0045] The counter unit 10 can be used by connecting the output device 50 of single-phase output to each of the six signal input terminals, for example. Furthermore, the counter unit 10 can be used by connecting the output device 50 of three-phase output to the first channel Ch1 including three signal input terminals and the second channel Ch2 including another three signal input terminals, for example. Furthermore, the counter unit 10 can be used by connecting two output devices 50 of two-phase output to the first channel Ch1 including two signal input terminals and the second channel Ch2 including another two signal input terminals, for example. Furthermore, the output device 50 of two-phase output can be used by connecting it to the third channel Ch3 including another two signal input terminals.

[0046] When a single-phase output device 50 is connected to any one of the signal input terminals, the switching unit 16 connects the corresponding input circuit to the single-phase counter 13. Furthermore, when a two-phase output device 50 is connected to any one of the signal input terminals, the switching unit 16 connects the corresponding input circuit to the two-phase counter 14. Furthermore, when a three-phase output device 50 is connected to any one of the signal input terminals, the switching unit 16 connects the corresponding input circuit to the three-phase counter 15.

[0047] In this way, the counter unit 10 can switch which of the single-phase counter 13, the two-phase counter 14, and the three-phase counter 15 to connect the input circuit group 21 connected to the output device 50. Therefore, it is possible to provide a counter unit 10 that can efficiently use a plurality of signal input terminals and can cope with any output device 50 of single-phase output, two-phase output, and three-phase output.

[0048] §2.Structure example

[0049] Below, refer to Figures 1 to 3 The structure of the counter unit 10 of the embodiment is described in detail. In the present embodiment, the output machine 50 connected to the counter unit 10 is assumed to be a machine of NPN type open collector output. The output machine 50 is, for example, an encoder, a flow meter, a linear scale, a photoelectric sensor, a proximity sensor, etc. that outputs a single-phase pulse signal of an open collector. Moreover, the output machine 50 is a two-phase output type rotary encoder that outputs a two-phase pulse signal of the A and B phases, etc. Moreover, the output machine 50 is a three-phase output type rotary encoder that outputs a three-phase pulse signal of the A, B, and Z phases, etc.

[0050] The output device 50 is not limited to an NPN type device, and may be a PNP type open collector output device. Furthermore, the output device 50 may be a line driver output device. The counter unit 10 receives a pulse signal generated by the output device 50 as an input, and measures the state of a workpiece etc. using a count value obtained by counting the number of pulses of the received pulse signal.

[0051] The counter unit 10 is connected to the PLC 30 so as to be communicable via a field network, for example, and transmits and receives data to and from the PLC 30. The PLC 30 is a control device (controller) that controls the entire control system 1 in a comprehensive manner. The counter unit 10 transmits and receives data to and from the PLC 30 at a fixed cycle in each control cycle of the PLC 30. For example, the counter unit 10 transmits information represented by a count value of a pulse signal output by the output device 50 to the PLC 30 in each control cycle of the PLC 30.

[0052] Furthermore, the user can change the switching operation of the switching section 16 of the counter unit 10 by operating a setting program (tool) running on the notebook PC 40 .

[0053] In addition, in the present embodiment, as an example of a setting machine for changing the switching action of the switching unit 16, a configuration in which the notebook PC 40 is connected to the counter unit 10 is illustrated, but the configuration is not limited to the notebook PC 40, and any terminal machine may be used as the setting machine, the terminal machine including a display unit including a liquid crystal panel, etc. and an operation unit including a touch panel, a keyboard, a mouse, etc. Furthermore, the following configuration may be adopted: the PLC 30 functions as a setting machine, and an instruction for changing the switching action of the switching unit 16 is sent from the PLC 30 to the counter unit 10.

[0054] (Regarding the Structure of Counter Unit 10)

[0055] The counter unit 10 includes a communication unit 11, a signal processing unit 12, and an input circuit group 21. Furthermore, the counter unit 10 includes a switching unit 16. Furthermore, the counter unit 10 includes a Universal Serial Bus (USB) communication unit 22.

[0056] The communication unit 11 repeatedly communicates with the PLC 30 and performs data transmission and reception in each control cycle of the PLC 30. The communication unit 11 is implemented using an integrated circuit such as a communication integrated circuit (IC), for example.

[0057] The counter unit 10 and the PLC 30 can also be connected to each other via a field network, for example. As a field network connecting the counter unit 10 and the PLC 30, various industrial Ethernets (registered trademarks) can be typically used. As industrial Ethernet (Ethernet (registered trademark)), for example, EtherCAT (registered trademark), Profinet IRT, MECHATROLINK (registered trademark)-III, Powerlink, SERCOS (registered trademark)-III, CIP Motion, etc. are known, and any of them can be used. Furthermore, field networks other than industrial Ethernet (registered trademark) can also be used. For example, if motion control is not performed, DeviceNet, CompoNet / IP (registered trademark), etc. can also be used.

[0058] Furthermore, the counter unit 10 may be formed integrally with the PLC 30 , or may be connected to the PLC 30 via an internal bus so as to be communicable therewith.

[0059] The signal processing unit 12 includes a single-phase counter 13, a two-phase counter 14, and a three-phase counter 15. The signal processing unit 12 counts the number of pulses of the pulse signal output by the output device 50 according to a preset setting value through the functions of the counters 13, 14, and 15. The signal processing unit 12 can also use the counter function inside the microprocessor (Micro Processor Unit, MPU) and other hardware to realize the functions of the counters 13, 14, and 15. In addition, the signal processing unit 12 can also use ICs such as Field Programmable Gate Array (FPGA) and Application Specified IC (ASIC) to realize the functions of the counters 13, 14, and 15.

[0060] The signal processing unit 12 uses the counting results obtained by the counters 13, 14, and 15 to measure the state of the workpiece, etc. The signal processing unit 12 is implemented by software using, for example, a central processing unit (CPU) or a microprocessor (MPU). The counting results of the signal processing unit 12 are output to the PLC 30 as a host device through the communication unit 11 via the communication line at each predetermined communication cycle.

[0061] The input circuit group 21 includes a plurality of signal input terminals A1, A2, B1, B2, Z1, and Z2 and input circuits 21a to 21f connected to the signal input terminals, respectively (see Figures 5 to 8 ). The pulse signals output from one or more output devices 50 are input to the signal input terminals A1, A2, B1, B2, Z1, and Z2, respectively. In addition, the input circuit group 21 includes a plurality of common signal terminals COMA1, COMA2, COMB1, COMB2, COMZ1, and COMZ2, which are respectively connected to the common signal lines of the one or more output devices 50.

[0062] The switching section 16 switches the connection of the input circuits 21 a to 21 f between the single-phase counter 13 , the two-phase counter 14 , and the three-phase counter 15 .

[0063] The USB communication unit 22 includes a USB port and communicates with the notebook PC 40 via a USB cable connected to the USB port. The USB communication unit 22 receives a signal indicating an instruction of a setting program running on the notebook PC 40. The signal indicating an instruction of a setting program running on the notebook PC 40 received by the USB communication unit 22 includes an instruction of a switching operation performed by the switching unit 16, and the USB communication unit 22 functions as a switching receiving unit that receives the instruction of the switching operation via the communication line.

[0064] In this way, the counter unit 10 can receive an instruction of the switching action performed by the switching unit 16 from the notebook PC 40 via the USB communication unit 22, and control the switching unit 16 to switch which of the single-phase counter 13, the two-phase counter 14 and the three-phase counter 15 the input circuit is connected to according to the instruction.

[0065] (Hardware structure of counter unit)

[0066] Figure 2 2 is a diagram showing the hardware configuration of the counter unit 10 . Figure 3 1 is a diagram showing an example of the arrangement of the terminal block of the counter unit 10. Figure 2 as well as Figure 3 As shown, the counter unit 10 includes signal input terminals A1, A2, B1, B2, Z1, Z2, common signal terminals COMA1, COMA2, COMB1, COMB2, COMZ1, COMZ2 and control signal input terminals IN1 to IN4 as input terminals.

[0067] Furthermore, the counter unit 10 includes comparator output terminals OUT1 to OUT6, six positive power supply terminals IOV, and four negative power supply terminals IOG as output terminals. The power supply terminals IOV and IOG include power supply output terminals (5V, 0V) for the encoder and power supply output terminals (24V, 0V) for the external power supply.

[0068] The power supply terminals IOV and IOG are connected to a power supply circuit 25 inside the counter unit 10 .

[0069] The switch unit 16 has: (1) a function of performing digital filtering processing on the input pulse signal; and (2) a function of switching the connection of the input circuits 21a to 21f between the single-phase counter 13, the two-phase counter 14, and the three-phase counter 15. In addition, regarding the filtering processing of the switch unit 16, the enable / disable of filtering and the filtering conditions can be set by the user by setting the program of the PLC 30 or operating the notebook PC 40. The switch unit 16 is implemented by, for example, a complex programmable logic device (CPLD), an FPGA, or an ASIC.

[0070] The signal processing unit 12 is implemented by a CPU, for example. The signal processing unit 12 counts pulse signals and outputs counting results through the functions of the counters 13, 14, and 15. The single-phase counter 13, the two-phase counter 14, and the three-phase counter 15 each include a buffer for temporarily storing multiple counting results.

[0071] The signal processing unit 12 performs oversampling processing, and outputs the plurality of count results temporarily stored in the buffers of the counters 13 , 14 , and 15 to the PLC 30 via the communication line by the function of the communication unit 11 at each predetermined communication cycle.

[0072] The signal processing unit 12 performs interrupt processing during oversampling or interrupt processing based on input synchronization. The signal processing unit 12 is not limited to a configuration implemented by a CPU, and may be implemented by a CPLD, FPGA, or ASIC.

[0073] (About oversampling processing)

[0074] Figure 4 : is a diagram showing the structure of the oversampling process performed by the signal processing unit 12. Figure 4 , an example of oversampling processing by the signal processing unit 12 is shown. The signal processing unit 12 uses the time up of the MPU built-in timer as a trigger to count the pulse signal through the DSTC (Descriptor System Data Transfer Controller).

[0075] The signal processing unit 12 synchronizes the timer of the communication unit 11 for input synchronization, which synchronizes the communication between the communication unit 11 and the PLC 30, with the MPU internal timer for oversampling. The signal processing unit 12 also uses the MPU internal timer for time stamp generation.

[0076] First, the signal processing unit 12 performs interrupt processing (input synchronization) at the synchronization timing of the timer of the communication unit 11 (step S1), and the interrupt processing is set to start the MPU built-in timer using DSTC when the time comes next.

[0077] Then, the signal processing unit 12 starts the MPU internal timer using the DSTC (step S2). In addition, the MPU internal timer is set so that the time is up immediately for the first time.

[0078] The signal processing unit 12 uses the expiration of the MPU built-in timer as a trigger to obtain and hold the value that is the basis for counting of the high-speed counter through the DSTC (step S3).

[0079] The signal processing unit 12 performs the interrupt processing (oversampling) as follows during the interrupt processing, that is, generates a high-speed counter value (count result) based on the value held in step S3, and writes the value to the buffer area of ​​the communication unit 11 (step S4). In addition, the buffer area of ​​the communication unit 11 has a double buffer structure, and the signal processing unit 12 switches to a different buffer area in each cycle to write the count result.

[0080] The signal processing unit 12 stops the MPU internal timer at the time point when the processing of the number of samples in each cycle is completed (step S5). The signal processing unit 12 restarts the processing from step S2 in the next cycle to regain synchronization.

[0081] Then, at the start of the next cycle of processing, the signal processing unit 12 performs an interrupt process (input synchronization) to start a process of generating another buffer data and transmitting the data in the buffer area of ​​the communication unit 11 (step S6).

[0082] (Single-phase input mode)

[0083] Figure 5 1 is a diagram showing the wiring connection state of the counter unit 10 when the output device 50 with single-phase output is connected to each of the first signal input terminal to the sixth signal input terminal including the signal input terminals A1, A2, B1, B2, Z1, and Z2. Figure 5 As shown, when the single-phase output machine 50 is connected to each of the first signal input terminal to the sixth signal input terminal, the user uses the operation of the notebook PC 40 to switch the connection of the switching unit 16 to connect the first input circuit 21a to the sixth input circuit 21f to the first single-phase counter 13a to the sixth single-phase counter 13f respectively and independently.

[0084] The switch unit 16 connects each of the first to sixth input circuits 21 a to 21 f to single-phase signal lines (single-phase 1 to 6 ) connected to the first to sixth single-phase counters 13 a to 13 f , respectively.

[0085] The signal processing unit 12 counts based on the single-phase pulse signals input to the first single-phase counter 13a to the sixth single-phase counter 13f. The signal processing unit 12 sends the counting results stored in the buffers corresponding to the first single-phase counter 13a to the sixth single-phase counter 13f to the PLC 30 via the communication unit 11 in each specified communication cycle.

[0086] (Three-phase input mode)

[0087] Figure 61 is a diagram showing the wiring connection state of the counter unit 10 when the output device 50 of the three-phase output is connected to the channel Ch1 including the signal input terminals A1, B1, and Z1 and the channel Ch2 including the signal input terminals A2, B2, and Z2. Figure 6 As shown, when the output device 50 of the three-phase output is connected to each of the channels Ch1 and Ch2, the user uses the operation of the notebook PC 40 to switch the connection of the switching unit 16, so as to independently connect the first input circuit 21a to the third input circuit 21c to the first three-phase counter 15a, and connect the fourth input circuit 21d to the sixth input circuit 21f to the second three-phase counter 15b.

[0088] The switching unit 16 connects the first to third input circuits 21a to 21c to the A-phase signal line AIN1, the B-phase signal line BIN1, and the Z-phase signal line ZIN1 connected to the first three-phase counter 15a, respectively. Furthermore, the switching unit 16 connects the fourth to sixth input circuits 21d to 21f to the A-phase signal line AIN2, the B-phase signal line BIN2, and the Z-phase signal line ZIN2 connected to the second three-phase counter 15b, respectively.

[0089] The signal processing unit 12 counts based on the three-phase pulse signals of the A phase, the B phase, and the Z phase input to the first three-phase counter 15a and the second three-phase counter 15b, respectively. The signal processing unit 12 sends the counting results stored in the buffers corresponding to the first three-phase counter 15a and the second three-phase counter 15b to the PLC 30 via the communication unit 11 at each predetermined communication cycle.

[0090] (Two-phase input mode)

[0091] Figure 7 1 is a diagram showing the wiring connection state of the counter unit 10 when the output device 50 of the two-phase output is connected to the channel Ch1 including the signal input terminals A1, B1, and Z1 and the channel Ch2 including the signal input terminals A2, B2, and Z2. Figure 7 As shown, when the two-phase output device 50 is connected to each of the channels Ch1 and Ch2, the signal lines are connected to the signal input terminals A1 and B1 and the signal input terminals A2 and B2, and the signal input terminals Z1 and Z2 are set to the Not Connected (NC) state where the signal lines are not connected.

[0092] Moreover, when connecting the two-phase output device 50 to each of the channels Ch1 and Ch2, the user uses the operation of the notebook PC 40 to switch the connection of the switching unit 16, so as to independently connect the first input circuit 21a and the second input circuit 21b to the first three-phase counter 15a, and connect the fourth input circuit 21d and the fifth input circuit 21e to the second three-phase counter 15b.

[0093] The switch unit 16 connects the first input circuit 21a and the second input circuit 21b to the A-phase input line AIN1 and the B-phase input line BIN1 connected to the first three-phase counter 15a, respectively. Furthermore, the switch unit 16 connects the fourth input circuit 21d and the fifth input circuit 21e to the A-phase input line AIN2 and the B-phase input line BIN2 connected to the second three-phase counter 15b, respectively. Furthermore, the switch unit 16 disconnects the third input circuit 21c and the sixth input circuit 21f from the three-phase counters 15a and 15b.

[0094] The signal processing unit 12 counts based on the pulse signals of the two phases of the A phase and the B phase input to the first three-phase counter 15a and the second three-phase counter 15b, respectively. The signal processing unit 12 sends the counting results stored in the buffers corresponding to the first three-phase counter 15a and the second three-phase counter 15b to the PLC 30 via the communication unit 11 at each predetermined communication cycle.

[0095] In this way, the counter unit 10 makes the three-phase counter that counts based on the three-phase pulse signal function as a multi-phase counter that counts corresponding to both the two-phase pulse signal and the three-phase pulse signal, thereby responding to the two-phase output and three-phase output output devices 50. That is, at this time, the first three-phase counter 15a and the second three-phase counter 15b will function as the two-phase counter 14.

[0096] Figure 8 1 is a diagram showing an example of another wiring connection state of the counter unit 10 when the counter unit 10 is used in the two-phase input mode. Figure 8 As shown, the counter unit 10 may be configured so that a two-phase output device 50 can be connected to each of the three channels Ch1 , Ch2 , and Ch3 .

[0097] The first channel Ch1 includes signal input terminals A1 and B1, and a first input circuit 21a and a second input circuit 21b connected to the signal input terminals A1 and B1, respectively. The second channel Ch2 includes signal input terminals A2 and B2, and a third input circuit 21c and a fourth input circuit 21d connected to the signal input terminals A2 and B2, respectively. The third channel Ch3 includes signal input terminals A3 and B3, and a fifth input circuit 21e and a sixth input circuit 21f connected to the signal input terminals A3 and B3, respectively.

[0098] In the signal processing unit 12, in addition to the first three-phase counter 15a and the second three-phase counter 15b, a third three-phase counter 15c and a fourth three-phase counter 15d dedicated to the two-phase mode are provided. That is, the signal processing unit 12 allows the third three-phase counter 15c and the fourth three-phase counter 15d dedicated to the two-phase mode to function as a two-phase counter 14 that counts based on a two-phase pulse signal. The third three-phase counter 15c is connected to the switching unit 16 using the signal line AIN3 of the A phase and the signal line BIN3 of the B phase. The fourth three-phase counter 15d is connected to the switching unit 16 using the signal line AIN4 of the A phase and the signal line BIN4 of the B phase.

[0099] When connecting the two-phase output device 50 to each of the channels Ch1, Ch2, and Ch3, the user operates the notebook PC 40 to switch the connection of the switching unit 16, so as to independently connect the first input circuit 21a and the second input circuit 21b to the first three-phase counter 15a, the third input circuit 21c and the fourth input circuit 21d to the third three-phase counter 15c, and the fifth input circuit 21e and the sixth input circuit 21f to the fourth three-phase counter 15d.

[0100] The switching unit 16 connects the first input circuit 21a and the second input circuit 21b to the A-phase signal line AIN1 and the B-phase signal line BIN1 connected to the first three-phase counter 15a. Furthermore, the switching unit 16 connects the third input circuit 21c and the fourth input circuit 21d to the A-phase signal line AIN3 and the B-phase signal line BIN3 connected to the third three-phase counter 15c. Furthermore, the switching unit 16 connects the fifth input circuit 21e and the sixth input circuit 21f to the A-phase signal line AIN4 and the B-phase signal line BIN4 connected to the fourth three-phase counter 15d.

[0101] The signal processing unit 12 counts based on the pulse signals of the two phases of the A phase and the B phase input to the first three-phase counter 15a, the third three-phase counter 15c, and the fourth three-phase counter 15d. The signal processing unit 12 sends the counting results stored in the buffers corresponding to the first three-phase counter 15a, the third three-phase counter 15c, and the fourth three-phase counter 15d to the PLC 30 via the communication unit 11 at each predetermined communication cycle.

[0102] In this way, the counter unit 10 adopts a structure in which the third three-phase counter 15c and the fourth three-phase counter 15d that can connect the signal input of the A phase and the signal input of the B phase to the switching unit 16 are used exclusively for the two-phase input, thereby enabling three two-phase output devices 50 to be connected to six input signal terminals for use. Therefore, unused input signal terminals are not generated, and the counter unit 10 can be used without waste.

[0103] (Summarize)

[0104] In order to solve the above-mentioned problem, a counter unit of one embodiment of the present invention includes: a plurality of signal input terminals, which respectively input pulse signals output from a plurality of external output machines; an input circuit, which is connected to each of the plurality of signal input terminals; a single-phase counter and a multi-phase counter, wherein the single-phase counter counts based on a single-phase pulse signal, and the multi-phase counter counts based on a multi-phase pulse signal; and a switching unit, which switches whether the input circuit is connected to the single-phase counter or the multi-phase counter.

[0105] According to the above configuration, since it is switched whether the input circuits connected to the plurality of signal input terminals are connected to the single-phase counter or the multi-phase counter, the plurality of output devices can be connected using the plurality of signal input terminals efficiently.

[0106] In the counter unit of an embodiment of the present invention, the multi-phase counter is a three-phase counter that counts based on a three-phase pulse signal.

[0107] In the counter unit of an embodiment of the present invention, the three-phase counter counts in response to both the two-phase pulse signal and the three-phase pulse signal.

[0108] According to the above configuration, the three-phase counter can cope with both output devices that output two-phase pulse signals and output devices that output three-phase pulse signals.

[0109] In a counter unit of one embodiment of the present invention, the single-phase counter and the multi-phase counter respectively include buffers for temporarily storing multiple counting results, and the counter unit also includes a communication unit, which outputs the multiple counting results temporarily stored in the buffers corresponding to the single-phase counter and the multi-phase counter to a host device via a communication line in each specified communication cycle.

[0110] According to the above configuration, multiple count results of the single-phase counter and the multi-phase counter can be outputted to the host device in a lump at each predetermined communication cycle.

[0111] The counter unit according to one embodiment of the present invention further includes a switching accepting unit configured to accept an instruction of a switching operation to be performed by the switching unit via a communication line.

[0112] According to the above configuration, the switching operation can be controlled from the outside via the communication line.

[0113] The present invention is not limited to the above-described embodiments, and various modifications can be made within the scope of the claims. Embodiments obtained by appropriately combining technical components disclosed in different embodiments are also included in the technical scope of the present invention.

Claims

1. A counter unit, comprising: A plurality of signal input terminals are used to input pulse signals output from a plurality of external output devices respectively; An input circuit connected to each of the plurality of signal input terminals; A single-phase counter and a multi-phase counter, wherein the single-phase counter counts based on a single-phase pulse signal and the multi-phase counter counts based on a plurality of phase pulse signals; and A switching unit switches whether the input circuit is connected to the single-phase counter or the multi-phase counter, wherein The multi-phase counter is a three-phase counter that counts in response to both a two-phase pulse signal and a three-phase pulse signal.

2. The counter unit according to claim 1, wherein The single-phase counter and the multi-phase counter each include a buffer for temporarily storing multiple counting results. The counter unit further includes a communication unit configured to output a plurality of count results temporarily stored in the buffers corresponding to the single-phase counter and the multi-phase counter to a host device via a communication line at each predetermined communication cycle.

3. The counter unit according to claim 1, further comprising: The switching receiving unit receives an instruction of a switching operation to be performed by the switching unit via the communication line.

4. A counter unit, comprising: A plurality of signal input terminals are used to input pulse signals output from a plurality of external output devices respectively; An input circuit connected to each of the plurality of signal input terminals; A single-phase counter and a multi-phase counter, wherein the single-phase counter counts based on a single-phase pulse signal, and the multi-phase counter counts based on a plurality of phase pulse signals; as well as A switching unit switches whether the input circuit is connected to the single-phase counter or the multi-phase counter, wherein The single-phase counter and the multi-phase counter each include a buffer for temporarily storing multiple counting results. The counter unit further includes a communication unit configured to output a plurality of count results temporarily stored in the buffers corresponding to the single-phase counter and the multi-phase counter to a host device via a communication line at each predetermined communication cycle.

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