Data Organization of Page Stripes and Method and Apparatus for Writing Data to Page Stripes

Abstract

A method and apparatus for data organization of page stripes and writing data to page stripes are disclosed. The disclosed method includes writing first partial data of a first page stripe to multiple first physical pages from multiple logical units; backing up first check data generated based on the first partial data of the first page stripe in a first memory; writing first partial data of a second page stripe to multiple second physical pages from the multiple logical units; caching second check data generated based on the first partial data of the second page stripe in the first memory; writing second partial data of the first page stripe to multiple third physical pages from the multiple logical units; wherein the first physical page and the third physical page are not adjacent in the physical space of the non-volatile memory. Thus, a small amount of storage space is used to calculate check data for multiple page stripes, and data is written to multiple page stripes simultaneously.

Description

Technical Field

[0001] This application relates to a Solid Storage Device (SSD), and more particularly, to organizing data on a storage medium to improve reliability. Background Art

[0002] Refer to Figure 1 , which shows a block diagram of a storage device. The solid-state storage device 102 is coupled to a host and is used to provide storage capabilities for the host. The host and the solid-state storage device 102 can be coupled in various ways, including but not limited to coupling the host and the solid-state storage device 102 through, for example, SATA (Serial Advanced Technology Attachment), SCSI (Small Computer System Interface), SAS (Serial Attached SCSI), IDE (Integrated Drive Electronics), USB (Universal Serial Bus), PCIE (Peripheral Component Interconnect Express, PCIe), NVMe (NVM Express), Ethernet, Fibre Channel, a wireless communication network, etc. The host can be an information processing device capable of communicating with the storage device through the above-mentioned ways. For example, a personal computer, a tablet computer, a server, a portable computer, a network switch, a router, a cellular phone, a personal digital assistant, etc. The storage device 102 includes an interface 103, a control component 104, one or more NVM chips 105, and DRAM (Dynamic Random Access Memory) 110.

[0003] Common NVMs include NAND flash memory, phase change memory, FeRAM (Ferroelectric RAM), MRAM (Magnetic Random Access Memory), RRAM (Resistive Random Access Memory), etc.

[0004] The interface 103 can be adapted to exchange data with the host through, for example, SATA, IDE, USB, PCIE, NVMe, SAS, Ethernet, Fibre Channel, etc.

[0005] The control component 104 is used to control data transfer between the interface 103, the NVM chip 105, and the DRAM 110, and is also used for storage management, mapping of host logical addresses to flash physical addresses, wear leveling, bad block management, etc. The control component 104 can be implemented in a variety of ways, such as software, hardware, firmware, or a combination thereof. For example, the control component 104 can be in the form of an FPGA (Field-Programmable Gate Array), an ASIC (Application Specific Integrated Circuit), or a combination thereof. The control component 104 can also include a processor or a controller, and software is executed in the processor or controller to manipulate the hardware of the control component 104 to process IO (Input / Output) commands. The control component 104 can also be coupled to the DRAM 110 and can access the data in the DRAM 110. The FTL table and / or the data of the cached IO commands can be stored in the DRAM.

[0006] The control component 104 includes a flash interface controller (or referred to as a media interface controller, a flash channel controller). The flash interface controller is coupled to the NVM chip 105 and issues commands to the NVM chip 105 in a manner that follows the interface protocol of the NVM chip 105 to operate the NVM chip 105 and receives the command execution results output from the NVM chip 105. Known NVM chip interface protocols include "Toggle", "ONFI", etc.

[0007] A memory target is one or more logical units (Logic Unit) that share the chip enable (CE) signal within the flash memory die 105 package. Each logical unit has a logical unit number (LUN, Logic Unit Number). One or more dies can be included within a NAND flash memory package. Typically, a logical unit corresponds to a single die. A logical unit can include multiple planes. Multiple planes within a logical unit can be accessed in parallel, and multiple logical units within a NAND flash memory chip can execute commands and report status independently of each other. In the "Open NAND Flash Interface Specification (Revision 3.2)" obtained from http: / / www.onfi.org / ~ / media / ONFI / specs / ONFI_3_2%20Gold.pdf, the meanings of target, logical unit, LUN, plane, etc. are provided, and the commands for operating the NVM chip are also provided.

[0008] Data is usually stored and read on a storage medium page by page, while data is erased block by block. A block contains multiple pages. The pages on the storage medium (referred to as physical pages) have a fixed size, such as 17664 bytes. Physical pages can also have other sizes. A physical page can include multiple data frames, and the data frames have a specified size, such as 4096 or 4416 bytes.

[0009] In a solid-state storage device, an FTL (Flash Translation Layer) is used to maintain the mapping information from logical addresses to physical addresses. The logical addresses constitute the storage space of the solid-state storage device perceived by upper-layer software such as the operating system. The physical address is the address used to access the physical storage units of the solid-state storage device. In the prior art, address mapping can also be implemented using an intermediate address form. For example, a logical address is mapped to an intermediate address, and then the intermediate address is further mapped to a physical address.

[0010] Among them, the table structure storing the mapping information from logical addresses to physical addresses is called an FTL table. The FTL table is important metadata in a solid-state storage device. Usually, the data items of the FTL table record the address mapping relationship in the solid-state storage device in units of data pages.

[0011] The FTL table includes multiple FTL table entries (or called table items). In one example, each FTL table entry records the correspondence between a logical page address and a physical page. In another example, each FTL table entry records the correspondence between a continuous plurality of logical page addresses and a continuous plurality of physical pages. In yet another example, each FTL table entry records the correspondence between a logical block address and a physical block address. In still another embodiment, the FTL table records the mapping relationship between the logical block address and the physical block address, and / or the mapping relationship between the logical page address and the physical page address.

[0012] When processing a read command from a host, the solid-state storage device obtains the corresponding physical address from the FTL table using the logical address carried in the read command, issues a read request to the NVM chip based on the physical address, and receives the data output by the NVM chip in response to the read request. When processing a write command from a host, the solid-state storage device allocates a physical address for the write command, records the correspondence between the logical address of the write command and the allocated physical address in the FTL table, and issues a write request to the NVM chip based on the allocated physical address.

[0013] The solid-state storage device includes multiple NVM chips. Each NVM chip includes one or more dies or logical units (LUNs, Logic UNits). The dies or logical units can respond to read and write operations in parallel. Multiple read, write, or erase operations on the same die or logical unit are executed sequentially.

[0014] Figure 2 A schematic diagram of a large block is shown. The large block includes physical blocks from each of a plurality of logical units. Preferably, each logical unit provides one physical block for the large block. By way of example, large blocks are constructed on every 16 logical units (LUNs). Each large block includes 16 physical blocks, one from each of the 16 logical units (LUNs). In Figure 2 the example of, large block 0 includes physical block 0 from each of the 16 logical units (LUNs), and large block 1 includes physical block 1 from each logical unit (LUN). There can also be many other ways to construct large blocks.

[0015] As an alternative way, page stripes are constructed in the large block, and physical pages with the same physical address within each logical unit (LUN) form a "page stripe". Figure 2 In, physical pages 0-0, 0-1... and physical page 0-x form page stripe 0, where physical pages 0-0, 0-1... 0-14 are used to store user data, and physical page 0-15 is used to store parity data calculated based on all user data within the stripe. Similarly, Figure 2 in, physical pages 2-0, 2-1... and physical page 2-x form page stripe 2. Optionally, the physical page for storing parity data can be located at any position within the page stripe.

[0016] One or more physical blocks in the large block may be bad blocks. Data should not be written to bad blocks. Thus, the amount of user data that can be accommodated in a page stripe depends on the number of bad blocks in the large block where the page stripe is located. A physical page includes one or more data units. The number of valid data units of a page stripe is the number of data units that can accommodate user data in the page stripe. By way of example, removing the physical pages provided by bad blocks in the page stripe and removing the physical page for storing parity data, the number of data units of the remaining physical pages is the number of valid data units of the page stripe.

[0017] To write data to a page stripe, the control component (104) of the solid-state storage device (see Figure 1 ) provides a parity data calculator. Taking the calculation of parity data using the exclusive OR operation as an example, for a page stripe including N + 1 physical pages, the exclusive OR of the user data of N physical pages is calculated (e.g., (P0-1) XOR (P0-1) XOR (P0-2) XOR... XOR (P0-15)), and the calculation result is written to the physical page (e.g., P0-X) for storing parity data of the page stripe. Optionally, multiple parity data calculators (e.g., M) are provided in the control component (104) to write data to M page stripes simultaneously. SUMMARY OF THE INVENTION

[0018] The check data calculation unit needs to store a large amount of check data calculation results, and calculating the check data for a page stripe requires all user data of the page stripe to participate in the calculation. Therefore, to write data to multiple page stripes simultaneously, more high-speed storage resources are needed, which will result in high costs and high static power consumption of the integrated circuit chip. If a relatively small amount of storage resources is used, the concurrency of writing data to page stripes is restricted. An effective technical means is needed to utilize a relatively small amount of storage resources to support the check data calculation when writing data to multiple page stripes concurrently.

[0019] According to a first aspect of the present application, there is provided a first method for writing data to a non-volatile memory according to the first aspect of the present application, including: writing a first part of data of a first page stripe to a plurality of first physical pages from a plurality of logical units; writing a first part of data of a second page stripe to a plurality of second physical pages from the plurality of logical units; writing a second part of data of the first page stripe to a plurality of third physical pages from the plurality of logical units; wherein the first physical page and the third physical page are not adjacent in the physical space of the non-volatile memory.

[0020] According to the first method for writing data to a non-volatile memory according to the first aspect of the present application, there is provided a second method for writing data to a non-volatile memory according to the first aspect of the present application, wherein the first physical page and the third physical page are not adjacent in the physical space of the non-volatile memory includes that the first physical page and the third physical page do not belong to the same word line, do not belong to the same layer of the 3D memory, and / or do not belong to adjacent layers of the 3D memory.

[0021] According to the first or second method for writing data to a non-volatile memory according to the first aspect of the present application, there is provided a third method for writing data to a non-volatile memory according to the first aspect of the present application, wherein the first physical page and the second physical page are adjacent in the physical space of the non-volatile memory.

[0022] According to one of the first to third methods for writing data to a non-volatile memory according to the first aspect of the present application, there is provided a fourth method for writing data to a non-volatile memory according to the first aspect of the present application, wherein the second physical page and the third physical page are adjacent in the physical space of the non-volatile memory.

[0023] According to one of the first to third methods for writing data to a non-volatile memory according to the first aspect of the present application, there is provided a fifth method for writing data to a non-volatile memory according to the first aspect of the present application, further including: after writing a first part of data of the second page stripe to a plurality of second physical pages from the plurality of logical units, and before writing a third part of user data of the first page stripe to a plurality of third physical pages from the plurality of logical units, writing a first part of data of a third page stripe to a plurality of fourth physical pages from the plurality of logical units; wherein the second physical page and the fourth physical page are adjacent in the physical space of the non-volatile memory.

[0024] The method for writing data to a non-volatile memory according to the fifth aspect of the present application provides a method for writing data to a non-volatile memory according to the sixth aspect of the present application, wherein the third physical page and the fourth physical page are adjacent in the physical space of the non-volatile memory.

[0025] One of the methods for writing data to a non-volatile memory according to the first to sixth aspects of the present application provides a method for writing data to a non-volatile memory according to the seventh aspect of the present application, wherein for each of the plurality of logical units, two or more physical pages provided for the same page strip are not adjacent to each other in the physical space of the non-volatile memory.

[0026] One of the methods for writing data to a non-volatile memory according to the first to seventh aspects of the present application provides a method for writing data to a non-volatile memory according to the eighth aspect of the present application, wherein each of the plurality of logical units provides one physical page among the plurality of first physical pages; each of the plurality of logical units provides one physical page among the plurality of second physical pages; and each of the plurality of logical units provides one physical page among the plurality of third physical pages.

[0027] The method for writing data to a non-volatile memory according to the eighth aspect of the present application provides a method for writing data to a non-volatile memory according to the ninth aspect of the present application, wherein each of the plurality of logical units provides two or more physical pages for a page strip.

[0028] One of the methods for writing data to a non-volatile memory according to the first to ninth aspects of the present application provides a method for writing data to a non-volatile memory according to the tenth aspect of the present application, further comprising: backing up first check data generated from a first part of data of a first page strip in a first memory; and caching second check data generated from a first part of data of a second page strip in the first memory.

[0029] The method for writing data to a non-volatile memory according to the tenth aspect of the present application provides a method for writing data to a non-volatile memory according to the eleventh aspect of the present application, further comprising: backing up the second check data generated from the first part of data of the second page strip in the first memory; and caching third check data generated from a second part of data of the first page strip in the first memory.

[0030] The method for writing data to a non-volatile memory according to the eleventh aspect of the present application provides a method for writing data to a non-volatile memory according to the twelfth aspect of the present application, further comprising: obtaining check data of the first page strip according to the third check data and writing it to physical pages from the plurality of logical units.

[0031] One of the methods for writing data to a non-volatile memory according to the tenth to twelfth aspects of the present application provides a method for writing data to a non-volatile memory according to the thirteenth aspect of the present application, wherein: after generating first check data based on the first part of data of a first page stripe in a first memory, the first check data is backed up; and in response to backing up the first check data, second check data generated based on the first part of data of a second page stripe is cached in the first memory.

[0032] One of the methods for writing data to a non-volatile memory according to the tenth to thirteenth aspects of the present application provides a method for writing data to a non-volatile memory according to the fourteenth aspect of the present application, wherein: after writing the first part of data of a first page stripe to a plurality of first physical pages from a plurality of logical units, the first check data is backed up; and during the process of writing the first part of data of a second page stripe to a plurality of second physical pages from the plurality of logical units, second check data generated based on the first part of data of the second page stripe is cached in the first memory.

[0033] The method for writing data to a non-volatile memory according to the tenth aspect of the present application provides a method for writing data to a non-volatile memory according to the eleventh aspect of the present application, further comprising: backing up second check data generated based on the first part of data of a second page stripe in the first memory; transmitting the first check data to the first memory; and caching, in the first memory, check data of the first page stripe generated based on the first check data and the second part of data of the first page stripe.

[0034] The method for writing data to a non-volatile memory according to the fifteenth aspect of the present application provides a method for writing data to a non-volatile memory according to the sixteenth aspect of the present application, further comprising: writing the check data of the first page stripe to physical pages from the plurality of logical units.

[0035] One of the methods for writing data to a non-volatile memory according to the fifteenth to sixteenth aspects of the present application provides a method for writing data to a non-volatile memory according to the seventeenth aspect of the present application, wherein: after generating second check data based on the first part of data of a second page stripe in a first memory, the second check data is backed up; and in response to backing up the second check data, the first check data is transmitted to the first memory.

[0036] One of the methods for writing data to a non-volatile memory according to the fifteenth to seventeenth aspects of the present application provides a method for writing data to a non-volatile memory according to the eighteenth aspect of the present application, wherein: after writing the first part of the data of the second page strip to a plurality of second physical pages from a plurality of logical units, the second check data is backed up; and during the process of writing the second part of the data of the first page strip to a plurality of third physical pages from the plurality of logical units, the check data of the first page strip generated according to the second part of the data of the first page strip is cached in the first memory.

[0037] One of the methods for writing data to a non-volatile memory according to the first to ninth aspects of the present application provides a method for writing data to a non-volatile memory according to the nineteenth aspect of the present application, further including: writing the first part of the data of the third page strip to a plurality of first physical pages from a second plurality of logical units; writing the first part of the data of the fourth page strip to a plurality of second physical pages from the second plurality of logical units; writing the second part of the data of the third page strip to a plurality of third physical pages from the second plurality of logical units; wherein the first physical page of the second plurality of logical units is not adjacent to the third physical page of the second plurality of logical units in the physical space of the non-volatile memory.

[0038] One of the methods for writing data to a non-volatile memory according to the first to ninth or nineteenth aspects of the present application provides a method for writing data to a non-volatile memory according to the twentieth aspect of the present application, further including: caching the first check data generated according to the first part of the data of the first page strip in the first memory during the process of writing the first part of the data of the first page strip to a plurality of first physical pages from a plurality of logical units, writing the first part of the data of the third page strip to a plurality of first physical pages from a second plurality of logical units, and caching the fourth check data generated according to the first part of the data of the third page strip in the second memory.

[0039] The method for writing data to a non-volatile memory according to the nineteenth or twentieth aspect of the present application provides a method for writing data to a non-volatile memory according to the twenty-first aspect of the present application, further including: backing up the first check data generated according to the first part of the data of the first page strip in the first memory; caching the second check data generated according to the first part of the data of the second page strip in the first memory; backing up the fourth check data generated according to the first part of the data of the third page strip in the second memory; caching the fifth check data generated according to the first part of the data of the fourth page strip in the second memory.

[0040] A method for writing data to a non-volatile memory according to the nineteenth or twentieth aspect of the present application provides a method for writing data to a non-volatile memory according to the twenty-second aspect of the present application, further including: backing up first check data generated from a first part of data of a first page stripe in a first memory; transmitting the first check data to the first memory; caching, in the first memory, check data of the first page stripe generated from the first check data and a second part of data of the first page stripe; backing up fourth check data generated from a first part of data of a third page stripe in a second memory; transmitting the fourth check data to the second memory; and caching, in the second memory, check data of the third page stripe generated from the fourth check data and a second part of data of the third page stripe.

[0041] According to a second aspect of the present application, there is provided a first media interface controller according to the second aspect of the present application, including a check data calculator and a first memory. The check data calculator calculates check data for data corresponding to a programming command, and the check data is stored in the first memory. The media interface controller is further coupled to a CPU and a second memory; the check data calculator is also coupled to the CPU and the second memory; in response to completion of calculation of check data for a first part of data of a page stripe, the media interface controller or the check data calculator stores the check data in the first memory into the second memory.

[0042] A first media interface controller according to the second aspect of the present application provides a second media interface controller according to the second aspect of the present application, wherein the media interface controller or the check data calculator sends a first interrupt signal to the CPU and provides a storage address in the second memory of the check data to the CPU.

[0043] A first or second media interface controller according to the second aspect of the present application provides a third media interface controller according to the second aspect of the present application, wherein in response to completion of a write operation of writing check data to a page stripe, the media interface controller or the check data calculator sends a second interrupt signal to the CPU to indicate that the check data in the second memory can be released.

[0044] One of the first to third media interface controllers according to the second aspect of the present application provides a fourth media interface controller according to the second aspect of the present application, characterized in that in response to the first interrupt signal, the CPU generates a programming command to write the check data in the second memory to the page stripe and indicates that no check data needs to be calculated for the generated programming command.

[0045] One of the first to third media interface controllers according to the second aspect of the present application provides a fifth media interface controller according to the second aspect of the present application, wherein the CPU, the media interface controller, or the check data calculator stores the check data in the second memory into the first memory.

[0046] One of the first to fifth media interface controllers according to the second aspect of the present application provides a sixth media interface controller according to the second aspect of the present application, wherein the check data calculator calculates check data for the data in the first memory and the data corresponding to the programming command.

[0047] One of the first to sixth media interface controllers according to the second aspect of the present application provides a seventh media interface controller according to the second aspect of the present application, wherein the media interface controller sends the data corresponding to the programming command to the non-volatile memory.

[0048] One of the first to seventh media interface controllers according to the second aspect of the present application provides an eighth media interface controller according to the second aspect of the present application, further including a third memory for storing check data.

[0049] One of the first to eighth media interface controllers according to the second aspect of the present application provides a ninth media interface controller according to the second aspect of the present application, wherein in response to a programming command provided by the CPU, the media interface controller writes the first part of the data of the first page strip into a plurality of first physical pages from a plurality of logical units; in response to a programming command provided by the CPU, the media interface controller writes the first part of the data of the second page strip into a plurality of second physical pages from the plurality of logical units; in response to a programming command provided by the CPU, the media interface controller writes the second part of the data of the first page strip into a plurality of third physical pages from the plurality of logical units; wherein the first physical page and the third physical page are not adjacent in the physical space of the non-volatile memory.

[0050] Based on the ninth media interface controller according to the second aspect of the present application, a tenth media interface controller according to the second aspect of the present application is provided, wherein the first physical page and the third physical page not being adjacent in the physical space of the non-volatile memory includes that the first physical page and the third physical page do not belong to the same word line, do not belong to the same layer of the 3D memory, and / or do not belong to adjacent layers of the 3D memory.

[0051] Based on the ninth or tenth media interface controller according to the second aspect of the present application, an eleventh media interface controller according to the second aspect of the present application is provided, wherein the first physical page and the second physical page are adjacent in the physical space of the non-volatile memory.

[0052] According to one of the ninth to eleventh media interface controllers of the second aspect of the present application, a twelfth media interface controller according to the second aspect of the present application is provided, wherein a second physical page and a third physical page are adjacent in the physical space of the non-volatile memory.

[0053] According to one of the ninth to eleventh media interface controllers of the second aspect of the present application, a thirteenth media interface controller according to the second aspect of the present application is provided, wherein in response to a programming command provided by the CPU, after the media interface controller writes the first part of the data of the second page strip to a plurality of second physical pages from the plurality of logical units, and before writing the third part of the user data of the first page strip to a plurality of third physical pages from the plurality of logical units, the media interface controller also writes the first part of the data of the third page strip to a plurality of fourth physical pages from the plurality of logical units; wherein the second physical page and the fourth physical page are adjacent in the physical space of the non-volatile memory.

[0054] According to one of the ninth to thirteenth media interface controllers of the second aspect of the present application, a fourteenth media interface controller according to the second aspect of the present application is provided, wherein two or more physical pages provided by each of the plurality of logical units for the same page strip are not adjacent to each other in the physical space of the non-volatile memory.

[0055] According to one of the ninth to fourteenth media interface controllers of the second aspect of the present application, a fifteenth media interface controller according to the second aspect of the present application is provided, wherein each of the plurality of logical units provides one physical page among the plurality of first physical pages; each of the plurality of logical units provides one physical page among the plurality of second physical pages; and each of the plurality of logical units provides one physical page among the plurality of third physical pages.

[0056] According to the fifteenth media interface controller of the second aspect of the present application, a sixteenth media interface controller according to the second aspect of the present application is provided, wherein each of the plurality of logical units provides two or more physical pages for the page strip.

[0057] According to one of the ninth to sixteenth media interface controllers of the second aspect of the present application, a seventeenth media interface controller according to the second aspect of the present application is provided, wherein the CPU, the media interface controller or the check data calculator backs up first check data generated according to the first part of the data of the first page strip in the first memory; and uses the first memory to cache second check data generated according to the first part of the data of the second page strip.

[0058] According to the seventeenth media interface controller of the second aspect of the present application, an eighteenth media interface controller according to the second aspect of the present application is provided, wherein the CPU, the media interface controller, or the check data calculator backs up the second check data generated from the first part of the data according to the second page stripe in the first memory; and the first memory is used to cache the third check data generated from the second part of the data according to the first page stripe.

[0059] According to the seventeenth media interface controller of the second aspect of the present application, a nineteenth media interface controller according to the second aspect of the present application is provided, wherein the media interface controller or the check data calculator backs up the second check data generated from the first part of the data according to the second page stripe in the first memory; the CPU transfers the first check data in the second memory to the first memory; and the check data calculator caches the check data of the first page stripe generated from the first check data and the second part of the data of the first page stripe in the first memory.

[0060] According to one of the first to nineteenth media interface controllers of the second aspect of the present application, a twentieth media interface controller according to the second aspect of the present application is provided, further including a third memory for storing the check data generated by the check data calculator; wherein during the media interface controller writes the first part of the data of the first page stripe into multiple first physical pages from multiple logical units, the check data calculator caches the first check data generated from the first part of the data of the first page stripe in the first memory, the media interface controller writes the first part of the data of the third page stripe into multiple first physical pages from a second plurality of logical units, and the check data calculator also caches the fourth check data generated from the first part of the data of the third page stripe in the third memory.

[0061] According to the third aspect of the present application, a device for writing data to a non-volatile memory according to the third aspect of the present application is provided, including: a first writing module for writing the first part of the data of the first page stripe into multiple first physical pages from multiple logical units; a second writing module for writing the first part of the data of the second page stripe into multiple second physical pages from the multiple logical units; a third writing module for writing the second part of the data of the first page stripe into multiple third physical pages from the multiple logical units; wherein the first physical page and the third physical page are not adjacent in the physical space of the non-volatile memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0062] When read in conjunction with the drawings, the present application, as well as the preferred mode of use and its further objects and advantages, will be best understood by reference to the following detailed description of the illustrative embodiments, in which the drawings include:

[0063] Figure 1Schematic diagram of a solid - state storage device in the prior art;

[0064] Figure 2 Schematic diagram of the structure of a page stripe;

[0065] Figure 3 Schematic diagram of the control component of the solid - state storage device according to an embodiment of the present application;

[0066] Figure 4 Schematic diagram of the media interface controller according to another embodiment of the present application;

[0067] Figure 5 Schematic diagram of the media interface controller according to another embodiment of the present application;

[0068] Figure 6 Schematic diagram of the media interface controller according to still another embodiment of the present application;

[0069] Figure 7 Schematic diagram of the data organization on the NVM chip according to an embodiment of the present application;

[0070] Figure 8 For Figure 7 Schematic diagram of writing data to a page stripe using an XOR cache according to an embodiment;

[0071] Figure 9 Schematic diagram of the data organization on the NVM chip according to another embodiment of the present application; and

[0072] Figure 10 Is a flowchart of writing data to a page stripe according to an embodiment of the present application. Detailed implementation manners

[0073] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are some, but not all, of the embodiments of the present application. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present application without creative efforts shall fall within the protection scope of the present application.

[0074] Figure 3It is a block diagram of a control component of a solid-state storage device according to an embodiment of the present application. The control component 104 of the solid-state storage device includes a host interface 310, a front-end processing module 320, a flash memory management module 330, and one or more media interface controllers 340. The host interface 310 is used to exchange commands and data with the host. The flash memory management module 330 provides functions such as logical address to physical address mapping, wear leveling, garbage collection, etc., and generates IO commands to send to the media interface controller 340. The media interface controller is coupled to the NVM chip 105. There is one or more media interface controllers, and each interface controller is coupled to its respective NVM chip 105. The media interface controller receives the IO commands and issues IO commands (commands such as read, program, erase, pause, read feature, and / or set feature, etc.) to the NVM chip according to the IO commands.

[0075] In one example, the media interface controller provides multiple queues with different priorities (such as queue 342 and queue 344, where queue 342 is a high-priority queue and queue 344 is a low-priority queue) to receive IO commands. The flash memory management module 330 fills the read commands into the high-priority queue of the interface controller, so that the media interface controller gives priority to processing the read commands. And fills the program commands, erase commands, and / or read commands (such as read commands that do not require processing delay) into the low-priority queue of the media interface controller. The media interface controller will give priority to processing the commands in the high-priority queue 342, and process the commands in the queue 344 with low priority. It can be understood that the flash memory management module can also fill other types of IO commands into the high-priority queue.

[0076] According to an embodiment of the present application, generally, the media interface controller gives priority to processing the IO commands in the high-priority queue, and processes the IO commands in the low-priority queue with low priority.

[0077] According to an embodiment of the present application, in order to reduce the processing delay of the IO commands of the solid-state storage device, if there is a program command (P1) or an erase command (E1) being executed on a logical unit (L1), and there is a read command (R1) to be processed in the high-priority queue, where the read command R1 and the program command P1 access the same logical unit (L1). Then the media interface controller issues a pause command to the logical unit (L1) to pause the processing of the program command (P1) or the erase command (E1), and processes the read command (R1). And after the read command (R1) is processed, issues a resume command to the logical unit (L1) to resume the processing of the program command (P1) or the erase command (E1).

[0078] Understandably, the IO commands in the high-priority queue / low-priority queue may have different formats from the IO commands sent to the logical unit, but the same commands in different stages, with different formats but the same meaning, are indicated by the same tags (such as R1, P1, E1, etc.).

[0079] According to another embodiment of the present application, the media interface controller discovers a read command (R2) to be processed in the high-priority queue, and a programming command (P2) to be processed in the low-priority queue. Instead of processing the read command (R2) first, the media interface controller processes the programming command (P2) in the low-priority queue first. After sending the programming command (P2) to the logical unit (L2), if the read command (R2) and the programming command (P2) access the same logical unit (L2), then immediately send a pause command to the logical unit (L2) to pause the processing of the programming command (P2). And the media interface controller processes the read command (R2) from the high-priority queue, sends the read command (R2) to the logical unit (L2), and after the read command (R2) is processed, sends a resume command to the logical unit (L2) to resume the processing of the programming command (P2). If the read command (R2) and the programming command (P2) access different logical units, then directly process the read command (R2) without pausing the programming command (P2).

[0080] According to another embodiment of the present application, the media interface controller discovers a read command (R3) to be processed in the high-priority queue, and an erase command (E3) to be processed in the low-priority queue. Instead of processing the read command (R3) first, the media interface controller processes the erase command (E3) in the low-priority queue first. After sending the erase command (E3) to the logical unit (L3), if the read command (R3) and the erase command (E3) access the same logical unit (L3), then immediately send a pause command to the logical unit (L3) to pause the processing of the erase command (E3). And the media interface controller processes the read command (R3) from the high-priority queue, sends the read command (R3) to the logical unit (L3), and after the read command (R3) is processed, sends a resume command to the logical unit (L3) to resume the processing of the erase command (E3). If the read command (R3) and the erase command (E3) access different logical units, then directly process the read command (R3) without pausing the erase command (E3). Further, if a programming (P4) / erase (E4) command (for a logical unit other than the logical unit L3) that accesses another logical unit appears in the low-priority queue next, and a read command (R4) appears in the high-priority queue, then execute the programming (P4) / erase (E4) command, and pause the programming (P4) / erase (E4) command, then execute the read command (R4) and resume the processing of the programming (P4) / erase (E4) command.

[0081] Optionally, each logical unit has a corresponding media interface controller or an execution context of the media interface controller, so that IO commands being processed by the same media interface controller access the same logical unit. In this case, the media interface controller does not need to determine whether read commands and programming / erase commands access the same logical unit, and when a read command is received from the high-priority queue after programming / erase has been executed, a pause command is sent to the logical unit to pause the processing of the programming / erase command. Then the read command is sent, and after the execution of the read command is completed, the execution of the programming / erase command is resumed.

[0082] Figure 4 is a block diagram of a media interface controller 440 according to another embodiment of the present application. The media interface controller includes a plurality of queues (for example, queue 342 and queue 344). Each queue has a different priority. For example, queue 342 is a high-priority queue, and queue 344 is a low-priority queue. The media interface controller 440 includes a command scheduling module 410 and a check data calculator 420. By way of example, the check data calculator 420 performs an exclusive OR operation on the input data to obtain check data. An XOR cache (422 / 424 / 426) is further included in the check data calculator 420, and the calculated check data is stored in the XOR cache (422 / 424 / 426).

[0083] Optionally, the media interface controller 440 is also coupled to a DRAM (see Figure 1 , DRAM 110).

[0084] The command scheduling module 410 fetches commands from queue 342 / 344 and executes the commands to access the NVM chip. For a programming command, during the process of sending the data corresponding to the programming command to the NVM chip, a specified XOR cache (for example, XOR cache 422) is designated, and the check data calculator 420 performs an exclusive OR operation on the data corresponding to the programming command and the data cached in the XOR cache (for example, XOR cache 422), and the result of the exclusive OR operation is stored in the XOR cache (for example, XOR cache 422).

[0085] By way of example, one physical page is allocated on each of the NVM chips 405 / 415 / 425 to construct a page stripe (S1). Two physical pages in the page stripe (S1) are used to store user data, and one physical page is used to store check data.

[0086] The command scheduling module 410 fetches a programming command (P5) from the command queue, allocates an XOR cache (422), performs an exclusive OR operation on the data of the programming command (P5) and the XOR cache (422), stores the calculation result in the XOR cache (422), and sends the programming command (P5) to the NVM chip 405.

[0087] Next, the command scheduling module 410 fetches the programming command (P7) from the command queue, allocates the XOR cache (426), performs an exclusive OR operation on the data of the programming command (P7) with the XOR cache (426), stores the calculation result in the XOR cache (426), and sends the programming command (P7) to the NVM chip 435.

[0088] Among them, the programming command (P5) writes data to the page strip (S1), and before the page strip (S1) is completely written, the XOR cache (422) is occupied to generate the check data for the page strip (S1). Similarly, the programming command (P7) writes data to the page strip (S2), and the XOR cache (426) is occupied to generate the check data for the page strip (S2).

[0089] Next, a read command (R5) appears in the high-priority queue, and a programming command (P6) appears in the low-priority queue. Although the priority of the read command (R5) is higher than that of the programming command (P6), in order to reduce the occupation time of the XOR cache (422), the command scheduling module 410 preferentially processes the programming command (P6), and the programming command (P6) writes data to the page strip (S1). An exclusive OR operation is performed on the data corresponding to the programming command (P6) with the XOR cache (422), and the exclusive OR result is stored in the XOR cache (422). And the programming command (P6) is sent to the NVM chip 415.

[0090] At this time, since all 2 pages of user data to be written to the page strip (S1) have been received, the data stored in the XOR cache (422) is used as the check data for the page strip (S1) and written to the NVM chip 425 (by generating the programming command PX5), and the XOR cache (422) is released.

[0091] In an embodiment according to the present application, after performing an exclusive OR operation on the data corresponding to the programming command (P6) with the XOR cache (422) and storing the exclusive OR result in the XOR cache (422), the command scheduling module 410 processes the read command (R5) from the high-priority queue 342. If there is a programming command (such as programming commands P6 / P7 / PX5) or an erase command being processed on the logical unit (L5) accessed by the read command (R5), a pause command is sent to the logical unit (L5) to pause the programming command or erase command being executed on the logical unit (L5), a read command (R5) is sent to the logical unit (L5), and after the read command (R5) is executed, a resume command is sent to the logical unit (L5) to resume the paused programming command or erase command.

[0092] Optionally, the data corresponding to the programming command is XORed with an XOR cache (e.g., XOR cache 422), the XOR result is stored in the XOR cache (e.g., XOR cache 422), and after the programming command is sent to the logic unit, the content stored in the XOR cache (422) (e.g., user data or parity data for page strip (S1)) is written into the DRAM (see Figure 1 , DRAM 110), so that the XOR cache (422) can be released, and the XOR cache (422) is allocated to calculate the parity data of another page strip (e.g., page strip (S3)). And in response to receiving a programming command to write data to page strip (S1), the content of the stored XOR cache (422) is retrieved from the DRAM and stored in the XOR cache (e.g., 422 / 426), and the programming command to write data to page strip (S1) is continued to be processed.

[0093] Figure 5 Shows a media interface controller according to another embodiment of the present application. Figure 5 In the embodiment of Figure 1 , the control component 104 (see

[0094] ) includes a plurality of media interface controllers (540 / 550). The media interface controller includes a plurality of queues (e.g., queues 542 / 544, 552 / 554). Each queue has a different priority. For example, queues 542 / 552 are high-priority queues, while queues 544 / 554 are low-priority queues. The media interface controllers 540 / 550 are coupled to the parity data calculator 520. By way of example, the parity data calculator 520 XORs the input data to obtain parity data, and the XOR cache (522 / 524 / 526) is also included in the parity data calculator 520. Figure 1 , DRAM 110).

[0095] Among them, the media interface controller 540 is dedicated to accessing the logical unit (LUN 505), and the media interface controller 550 is dedicated to accessing the logical unit (LUN 515). Thus, for accessing LUN 505, the corresponding commands are added to queues 542 / 544, and for accessing LUN 515, the corresponding commands are added to queues 552 / 554.

[0096] It can be understood that multiple sets of execution contexts can be stored in the media interface controller, and each set of execution contexts is dedicated to accessing one of the logical units. By switching the execution context of the media interface controller, at each moment, the media interface controller is dedicated to accessing the (one) logical unit corresponding to the current execution context.

[0097] InFigure 5 In an embodiment, multiple media interface controllers (540 / 550) share the parity data calculator 520 and also share the DRAM.

[0098] As an example, in response to processing a programming command (P10), the programming command (P10) writes data to a page strip (S10). The media interface controller 540 allocates an XOR buffer (522) for the programming command (P10), XORs the data corresponding to the programming command (P10) with the XOR buffer (522), stores the XOR result in the XOR buffer (522), and sends the programming command (P10) to the LUN 505.

[0099] Next, a read command (R10) to be processed appears on the high-priority queue 542. Since the media interface controller 540 is dedicated to accessing the logical unit (LUN 505), it implies that both the read command (R10) and the programming command (P10) access the logical unit (LUN 505). The media interface controller 540 discovers that the programming command (P10) is being executed on the LUN 505. To reduce the processing latency of the read command (R10), it issues a pause command to the LUN 505 to pause the execution of the programming command (P10), and sends the read command (R10) to the LUN 505. And in response to the completion of the execution of the read command (R10), it issues a resume command to the LUN 505 to resume the execution of the programming command (P10).

[0100] Next, a pending read command (R11) appears on the high-priority queue 542, and a pending programming command (P11) appears on the low-priority queue 544. Also, the programming command (P10) has been executed. Since the media interface controller 540 is dedicated to accessing the logical unit (LUN 505), it implies that both the read command (R11) and the programming command (P11) access the logical unit (LUN505), and the media access controller 540 does not need to check whether the received commands access the same logical unit. Although the priority of the read command (R11) is higher than that of the programming command (P11), the media access controller 540 gives priority to processing the programming command (P11). The programming command (P11) is used to write data to the page strip (S11). The media interface controller 540 allocates the XOR cache (524) for the programming command (P11), XORs the data corresponding to the programming command (P11) with the XOR cache (524), stores the XOR result in the XOR cache (524), and sends the programming command (P11) to the LUN 505. Next, the media access controller 540 issues a pause command to the LUN 505 to pause the execution of the programming command (P11) and sends the read command (R11) to the LUN 505. Also, in response to the completion of the execution of the read command (R11), a resume command is issued to the LUN 505 to resume the execution of the programming command (P11).

[0101] Next, in response to a pending read command (R12) appearing on the high-priority queue 552 and a pending programming command (P12) appearing on the low-priority queue 554, since the media interface controller 550 is dedicated to accessing the logical unit (LUN 515), it implies that both the read command (R12) and the programming command (P12) access the logical unit (LUN 515), and the media access controller 550 does not need to check whether the received commands access the same logical unit. Even though the priority of the read command (R12) is higher than that of the programming command (P12), the media access controller 550 gives priority to processing the programming command (P12). The programming command (P12) is used to write data to the page strip (S12). The media interface controller 550 allocates the XOR cache (526) for the programming command (P12), XORs the data corresponding to the programming command (P12) with the XOR cache (526), stores the XOR result in the XOR cache (526), and sends the programming command (P12) to the LUN 515. Next, the media access controller 550 issues a pause command to the LUN 515 to pause the execution of the programming command (P12) and sends the read command (R12) to the LUN 515. Also, in response to the completion of the execution of the read command (R12), a resume command is issued to the LUN 515 to resume the execution of the programming command (P12).

[0102] Next, in response to a pending read command (R13) appearing on the high-priority queue 552 and a pending programming command (P13) appearing on the low-priority queue 554, even though the priority of the read command (R13) is higher than that of the programming command (P13), the media access controller 550 preferentially processes the programming command (P13). The programming command (P13) is used to write data to the page strip (S14). The media interface controller 550 allocates an XOR cache for the programming command (P13). Since the XOR caches (522 / 524 / 526) are all occupied, the content stored in one of the XOR caches (e.g., XOR cache 526) is transferred to the DRAM. The XOR cache (526) is initialized, the data corresponding to the programming command (P13) is XORed with the XOR cache (526), the XOR result is stored in the XOR cache (526), and the programming command (P13) is sent to the LUN 515. Next, the media access controller 550 issues a pause command to the LUN 515 to pause the execution of the programming command (P13) and sends the read command (R13) to the LUN 515. And in response to the completion of the execution of the read command (R13), a resume command is issued to the LUN 515 to resume the execution of the programming command (P13).

[0103] Next, regardless of which of the media interface controllers 540 / 550 receives a programming command to write data to the page strip (S12), the storage information of the XOR cache (526) for the page strip (S12) is transferred to the DRAM, and the content of the XOR cache previously stored for the page strip (S12) is retrieved from the DRAM and stored in the XOR cache (526).

[0104] Figure 6 A media interface controller showing yet another embodiment of the present invention is presented. Figure 6 In an embodiment, the media interface controller 640 includes a plurality of queues (e.g., queues 542 / 544). Each queue has a different priority. For example, queue 542 is a high-priority queue and queue 544 is a low-priority queue. The media interface controller 640 is coupled to a parity data calculator 620. By way of example, the parity data calculator 620 XORs the input data to obtain parity data, and the XOR caches (622 / 624 / 626) are also included in the parity data calculator 620.

[0105] Optionally, the media interface controller 640 is also coupled to the DRAM (see Figure 1 , DRAM 110).

[0106] Wherein, the media interface controller 640 is dedicated to accessing the logical unit (LUN 505), and thus corresponding commands are added to the queues 542 / 544 for accessing the LUN 505.

[0107] Understandably, a plurality of sets of execution contexts may be included in the media interface controller, and each set of execution contexts is dedicated to accessing one of the logical units. Switching the execution context of the media interface controller causes the media interface controller to be dedicated to accessing the (one) logical unit corresponding to the current execution context at each moment.

[0108] Figure 6 The illustrated media interface controller 640 is also coupled to the CPU and the DRAM via the bus 630, so as to process the IO commands more efficiently with the assistance of the CPU. The parity data calculator 620 exchanges data with the DRAM via the bus 630, and indicates an interruption to the CPU via the bus 630. The interruptions include an interruption (R_CPL) indicating the completion of the parity data calculation for the page strip, and an interruption (P_CPL) for indicating the completion of the write operation processing to the page strip. Understandably, the interruption (P_CPL) may also be generated by the media interface controller 640. The completion of the write operation processing to the page strip means that the user data and the parity data of the page strip are written into the NVM chip 105 via a plurality of programming commands. In some cases, one or more programming commands fail to execute. By responding to the interruption (P_CPL), the CPU will also be aware of the programming commands that have failed to execute.

[0109] As an example, data is written to the page strip (S14), and the page strip (S14) includes 3 physical pages for storing 2 pages of user data and 1 page of parity data. One page of user data has already been written to the page strip (S14). The media interface controller 640 receives the programming command (P14), and the programming command (P14) is used to write the second page of user data to the page strip (S14). The parity data for the page strip (S14) is recorded in the XOR cache (622) of the parity data calculator 620. The media interface controller 640 allocates the XOR cache (622) for the programming command (P14), performs an exclusive OR operation on the data corresponding to the programming command (P14) stored in the DRAM and the data stored in the XOR cache (622), stores the exclusive OR result in the XOR cache (622), and sends the programming command (P14) to the LUN 505.

[0110] Next, since the XOR calculation of all user data for the page stripe (S14) has been completed, the parity data (X1) for the page stripe (S14) is stored in the XOR cache (622). The parity data calculator 620 transmits the parity data in the XOR cache (622) to the DRAM via the bus, generates an interrupt (R_CPL) and sends it to the CPU (e.g., via the bus 630). The CPU learns from the interrupt (R_CPL) that the parity data for the page stripe (S14) has been calculated and learns the storage location of the parity data for the page stripe (S14) in the DRAM. Next, the CPU or the media interface controller 640 can initialize the XOR cache (622) and allocate it to other page stripes to which data is to be written.

[0111] At any subsequent time, the CPU fills the command queues 542 / 544 with a programming command (P15) to write the parity data (X1) in the DRAM to the page stripe (S14) and indicates to the media interface controller 640 that no parity data needs to be calculated for the programming command (P15).

[0112] Next, in response to the LUN 505 indicating that the execution of the programming command (P15) is complete, the media interface controller 640 generates an interrupt (P_CPL) for the CPU, indicating the execution result of the programming command (P15) in the interrupt. If the execution of the programming command (P15) is successful, the CPU discards the parity data (X1) in the DRAM; if the execution of the programming command (P15) fails, the CPU generates another programming command (P15) to write the parity data (X1) in the DRAM to the NVM chip again. Further, if the execution of the programming command (P15) fails, since the page stripe (S14) has not been completely written, the data that has been written to the page stripe (S14) needs to be read out and written to another page stripe.

[0113] Continue to refer to Figure 6, in another embodiment, in response to receiving and executing a programming command (P14), parity data (X1) for a page strip (S14) is generated in the XOR cache (622). The media interface controller 640 writes the data (X1) in the XOR cache (622) to the LUN 505 via the programming command (P16), and writes the data in the XOR cache (622) to the DRAM via the bus. In response to the parity data (X1) being written to the register of the LUN 505 and the DRAM, an interruption (R_CPL) is generated to the CPU. In response to the interruption (R_CPL), the CPU knows that the parity data (X1) has been sent to the LUN 505 and there is a copy of the parity data (X1) in the DRAM. Next, the CPU or the media interface controller 640 can initialize the XOR cache (622) and allocate it to other page strips to be written with data. And when the LUN 505 indicates to the media interface controller 640 that the execution of the programming command (P16) is completed, the media interface controller 740 generates an interruption (P_CPL) to indicate to the CPU that the operation on the page strip (S14) is completed.

[0114] In Figure 6 the embodiment of, when writing to a page strip, the XOR cache can be released earlier, and the released XOR cache can be allocated to other programming commands, so that the solid-state storage device can execute more programming commands concurrently, reducing the limitation of the limited XOR cache resources on the number of concurrently executed programming commands, also reducing the probability that the programming commands wait for the XOR cache resources, reducing the processing delay of the programming commands, and improving the performance of the solid-state storage device.

[0115] Optionally, even if no interruption is received, the CPU can also instruct to write the data in the XOR cache to the DRAM via the bus 630. Or the media interface controller 640 instructs to write the data in the XOR cache to the DRAM.

[0116] Figure 7 Shows a schematic diagram of data organization on an NVM chip according to another embodiment of the present application. In a page strip, the ratio of the quantity of user data to parity data affects the storage space utilization rate of the NVM chip of the solid-state storage device. The more user data in the page strip, the more parts of the storage space are used to store user data, and the higher the storage space utilization rate. However, limited by the number of NVM chips of the solid-state storage device, the number of logical units (LUNs) may be small. In Figure 7 the embodiment of, the number of physical pages in a page strip is greater than the number of logical units that provide physical pages for the page strip, so that one or more logical units provide two or more physical pages for the page strip.

[0117] In Figure 7In an embodiment, four logical units (LUN 0, LUN 1, LUN 2, and LUN 3) and two page stripes (page stripe 0 and page stripe 1) are shown. Each logical unit provides two physical pages for one page stripe ( Figure 7 One of the physical pages is indicated by a reference numeral in the form of Sa-b). Page stripe 0 occupies physical pages S0-0, S0-1, S0-2, S0-3, S0-4, S0-5, S0-6, and physical page S0-P. Among them, physical page S0-P stores parity data, and the other physical pages store user data. Page stripe 1 occupies eight physical pages indicated by reference numerals in the form of S1-b, where physical page S1-P stores parity data, and the other physical pages store user data.

[0118] and Figure 7 In, the physically adjacent physical pages in each logical unit are adjacent in the physical position of the NVM chip. For example, physical page S0-0 and its Figure 7 The corresponding bits in the physically adjacent physical page S1-0 in each logical unit come from the same MLC (Multiple Level Cell) memory cell. For another example, physical page S0-0 and its Figure 7 The physically adjacent physical pages in each logical unit belong to word lines that are spatially adjacent. As another example, physical page S0-0 and its Figure 7 The physically adjacent physical pages in each logical unit belong to two adjacent layers on the Z axis of the 3D memory. Since they come from the same MLC unit or physically adjacent memory units, Figure 7 The probability that physically adjacent physical pages in each logical unit fail simultaneously is greater than the probability that physically non-adjacent physical pages fail simultaneously. Therefore, in order for the page stripe to provide effective reliability, physical pages with a low probability of simultaneous failure are needed to form the page stripe.

[0119] The probability that physical pages from different logical units fail simultaneously is low. When limited by the number of logical units and multiple two or more physical pages need to be provided for a single page stripe by the same logical unit, physical pages that are not physically adjacent in the physical space of the NVM chip, do not belong to the same word line, and / or do not belong to the same layer of the 3D memory are selected to construct the page stripe.

[0120] As an example, Figure 7In the embodiments, physical pages in the same row (e.g., physical page S0-0, physical page S0-1, physical page S0-2, and physical page S0-3) have the same physical address (block address and page address), facilitating the acquisition of each physical page in the page strip. There can also be various other ways to select physical pages to construct a page strip. For example, construct a block strip in the manner provided in Chinese Patent Application No. 201610814552.5, and construct a page strip by providing one or more physical pages from each physical block of the block strip.

[0121] And when writing data to the NVM chip, data is usually written in the order of physical page addresses. Refer to Figure 7 , after writing data to the first part of page strip 0, on logical unit 0, data needs to be written to physical page S1-0, on logical unit 1, data needs to be written to physical page S1-1, on logical unit 2, data needs to be written to physical page S1-2, and on logical unit 3, data needs to be written to physical page S1-3. And physical pages S1-0, physical page S1-1, physical page S1-2, and physical page S1-3 belong to page strip 1, so next, data to be written to page strip 1 needs to be provided.

[0122] Return to refer to Figure 4 , Figure 5 or Figure 6 , for writing to the first part of page strip 0, use an XOR cache (e.g., XOR cache 622) to calculate parity data for the page strip. When writing to the first part of page strip 0 is completed, data needs to be written to the first part of page strip 1. During the process of writing data to the first part of page strip 1, the XOR cache (e.g., XOR cache 622) used for the first part of page strip 0 will not be used. To improve the utilization rate of the XOR cache, or to allocate an XOR cache for writing data to the first part of page strip 1, store the data that has been calculated according to the first part of page strip 0 in the XOR cache 622 into the DRAM, clear the XOR cache 622, and use it to calculate parity data for the first part of page strip 1. And after writing the first part of page strip 1 to the NVM chip, store the data of the XOR cache 622 into the DRAM, move the data stored in the DRAM according to the first part of page strip 0 to the XOR cache, and then continue to calculate parity data according to the second part of page strip 0 (excluding the data to be written to physical page S0-P). The result obtained is used as the parity data of page strip 1 and written to physical page S0-P. Next, move the data stored in the DRAM according to the first part of page strip 1 to the XOR cache, and then continue to calculate parity data according to the second part of page strip 1 (excluding the data to be written to physical page S1-P). The result obtained is used as the parity data of page strip 2 and written to physical page S1-P.

[0123] In this way, by using only one XOR cache, the parity data is calculated alternately for two page stripes, making full use of the bandwidth of the write (programming) operation of the NVM chip in the case of limited XOR cache resources, and without affecting the throughput capacity of the solid-state storage device due to limited XOR cache resources.

[0124] Understandably, in another embodiment according to the present application, a page stripe may include other numbers of physical pages. To ensure that two or more physical pages provided by the same logical unit for a single page stripe are not adjacent in the physical space of the NVM chip, do not belong to the same word line, and / or do not belong to the same layer of the 3D memory, one, two, or more physical pages may exist between these two or more physical pages.

[0125] Still understandably, in another embodiment according to the present application, a page stripe is divided into three parts or other numbers of parts. When the page stripe is divided into three parts, during the process of writing data to the page stripe, after writing the first part or the second part of the page stripe, the data in the XOR cache is moved to the DRAM to allocate the XOR cache to other page stripes.

[0126] Figure 8 is a schematic diagram of writing data to a page stripe using an XOR cache according to Figure 7 the embodiment of. Figure 8 In, the direction of the passage of time is shown from left to right. Using a single XOR cache (e.g., Figure 6 the XOR cache 624 of) to write data to page stripe 0 and page stripe 1 (see Figure 7 ).

[0127] See Figure 8 , in time period 810, the XOR cache 624 is used to calculate the parity data for the first part of page stripe 0. Since there are 4 physical pages of data in the first part of page stripe 0 (see Figure 8 , S0-0, S0-1, S0-2, and S0-3), after calculating the parity data for the data of one physical page, this part of the data is written to the physical page. As an example, in time period 810, first calculate the parity data for the data of physical page S0-0. After T_xor time, the calculation is completed, the parity data is stored in the XOR cache, and the data is started to be written to physical page S0-0 (indicated by time period 820). Next, in time period 810, calculate the parity data for the other physical pages of the first part of page stripe 0, store it in the XOR cache, and write the data to the physical page. Since the time required to write data to the physical page of the NVM chip is much longer than the time required to calculate the parity data, in Figure 8 , the length of time period 820 is much longer than the length of time period 810.

[0128] After time period 810, the data in the XOR cache 624 is stored into the DRAM while the operation of writing data to the first part of page strip 0 is still in progress. At this time, the XOR cache 624 has been released and can be used to calculate parity data for other page strips. Figure 8 In Figure 8 , during time period 812, the XOR cache 624 is used to calculate parity data for the first part of page strip 1. And after generating parity data for a physical page (e.g., S1-0) in the first part of page strip 1 (T_xor time starting from time period 820), writing data to the first part of page strip 1 starts (indicated by time period 822).

[0129] After time period 812, the data (for the first part of page strip 1) in the XOR cache 624 is stored into the DRAM. During time period 814, the XOR cache 624 is allocated to page strip 0 again. For the parity data to be generated for the first part of page strip 0 in the DRAM and the user data of the second part of page strip 0, the XOR cache 624 is used to calculate parity data. And the data is written to the second part of page strip 0 during time period 824.

[0130] During time period 816, the XOR cache 624 is allocated to page strip 1 again. For the parity data to be generated for the first part of page strip 1 in the DRAM and the user data of the second part of page strip 1, the XOR cache 624 is used to calculate parity data. And the data is written to the second part of page strip 1 during time period 826.

[0131] Figure 9 Shows a schematic diagram of data organization on an NVM chip according to another embodiment of the present application. In Figure 9 's embodiment, 4 logical units (LUN 0, LUN 1, LUN 2, and LUN3) and 3 page strips (page strip 0, page strip 1, and page strip 2) are shown. Each logical unit provides 2 physical pages for a page strip ( Figure 9 In Figure 9 , one of the physical pages is indicated by a reference numeral in the form of Sa-b). As an example, page strip 0 occupies physical pages S0-0, S0-1, S0-2, S0-3, S0-4, S0-5, S0-6, and S0-P. Among them, the physical page S0-P stores parity data, and the other physical pages store user data.

[0132] Figure 9In the illustrated embodiment, in the same logical unit, there are two physical pages between the physical pages provided for the first part and the second part of page stripe 0. Thus, even if physical page S0-0 fails and causes physical pages S1-0 and S2-0 to be damaged, the data of physical page S0-0 can still be restored through page stripe 0, the data of physical page S1-0 can be restored through page stripe 1, and the data of physical page S2-0 can be restored through page stripe 2.

[0133] As an example, an XOR cache 624 (see Figure 6 ) is used to calculate parity data for page stripe 0, page stripe 1, and page stripe 2. After writing data to the first part of page stripe 0, the data in the XOR cache 624 is moved to an external memory (DRAM), the XOR cache 624 is cleared, and parity data is calculated for the first part of page stripe 1. After writing data to the first part of page stripe 1, the data in the XOR cache 624 is moved to an external memory (DRAM), the XOR cache 624 is cleared, and parity data is calculated for the first part of page stripe 2. Next, the parity data calculated for the first part of page stripe 0 is moved from the DRAM to the XOR cache, data is written to the second part of page stripe 0 (excluding S0-P), and the data in the XOR cache 624 is written to S0-P as the parity data of page stripe 0. And the parity data calculated for the first part of page stripe 1 is moved from the DRAM to the XOR cache, data is written to the second part of page stripe 1 (excluding S1-P), and the data in the XOR cache 624 is written to S1-P as the parity data of page stripe 1. And similarly, the parity data of page stripe 2 is generated using the XOR cache 624.

[0134] As another example, an XOR cache 622 (see Figure 6 ) is used to calculate parity data for page stripe 0 and page stripe 1. And an XOR cache 624 (see Figure 6 ) is used to calculate parity data for page stripe 2.

[0135] As yet another example, the page stripe is divided into N parts (N is a positive integer), and 1 XOR cache is used to calculate parity data for each part of the page stripe, and the data in the XOR cache is moved to an external memory. When calculating the m-th part of the page stripe (m is a positive integer), instead of obtaining the content of the XOR cache from the external memory, parity data is calculated for the m-th part of the page stripe, and the data in the XOR cache is moved to the external memory again. For the N parts of the page stripe (each part can have a different size), N pieces of cached data are obtained in the external memory. And then the XOR cache is used to calculate parity data for the N pieces of cached data, and the result obtained is used as the parity data of the page stripe.

[0136] By dividing a page stripe into multiple parts and calculating check data using an XOR cache respectively, during the process of generating check data for a page stripe, the XOR cache can be temporarily used to calculate check data for other page stripes, and each part of a single page stripe is stored on non - adjacent physical pages of an NVM chip.

[0137] Figure 10 FIG. is a flowchart of writing data to a page stripe according to an embodiment of the present application. The page stripe is divided into multiple parts. Preferably, each of the multiple physical pages corresponding to each part of the page stripe comes from different logical units. And each logical unit provides a physical page for each part of the page stripe. It can be understood that "page stripe" is also used to indicate the data to be written to the page stripe.

[0138] To write data, part of the user data of the first page stripe (see Figure 7 , page stripe 0) is written to the first physical pages (1010) of each of the multiple logical units that make up the first part of the first page stripe (see also Figure 7 , physical page S0 - 0, physical page S0 - 1, physical page S0 - 2, and physical page S0 - 3).

[0139] Next, part of the user data of the second page stripe (see Figure 7 , page stripe 1) is written to the second physical pages (1020) of each of the multiple logical units that make up the first part of the second page stripe (see also Figure 7 , physical page S1 - 0, physical page S1 - 1, physical page S1 - 2, and physical page S1 - 3).

[0140] Preferably, the addresses of the first physical page and the second physical page are consecutive, adjacent in physical space, or belong to the same layer of the 3D memory.

[0141] Optionally, part of the user data of one or more other page stripes is also written to one or more other physical pages of each of the multiple logical units that make up the parts of the other page stripes. These physical pages are consecutive in address with the second physical page, adjacent in physical space, or belong to the same layer of the 3D memory, so that the third physical page in step 1030 is not adjacent in physical space to the first physical page, does not belong to the same word line, and / or does not belong to the same layer of the 3D memory.

[0142] Next, part of the user data and the check data of the first page stripe (see Figure 7 , page stripe 0) are written to the third physical pages (1030) of each of the multiple logical units that make up the second part of the first page stripe (see also Figure 7 , physical page S0 - 4, physical page S0 - 5, physical page S0 - 6, and physical page S0 - P).

[0143] Optionally, XOR resources are allocated for each page strip. For example, XOR resource 622 is allocated for page strip 0, and XOR resource 624 is allocated for page strip 1 (also see Figure 6 ). At steps 1010 and 1030, XOR resource 622 is used to calculate check data for page strip 0, and at step 1020, XOR resource 624 is used to calculate check data for page strip 1.

[0144] As another implementation, multiple page strips use a single XOR resource (e.g., XOR resource 626). For example, at step 1010, check data calculator 620 uses XOR resource 626 to calculate check data for page strip 0 and stores the calculation result of the check data for the first part of the user data of page strip 0 in an external memory. At step 1020, check data calculator 620 uses XOR resource 626 to calculate check data for page strip 1 and stores the calculation result of the check data for the first part of the user data of page strip 1 in an external memory. At step 1030, check data calculator 620 uses XOR resource 626 to calculate check data for page strip 0, and writes the check data calculated from the calculation result of the check data for the second part of the user data of page strip 0 and the calculation result of the check data for the first part of the user data of page strip 0 stored in the external memory as the check data of page strip 0 to a physical page.

[0145] The XOR operation satisfies the commutative law and the associative law. When calculating check data using the XOR operation, the order of multiple operands is not restricted. Thus, for multiple parts of a page strip, check data of the complete page strip is generated using the multiple generated check data.

[0146] Multiple embodiments of the present application have been disclosed above using an NVM chip as an example. Those skilled in the art will realize that the embodiments of the present application can also be applied to other types of storage media that support erase suspension and / or erase recovery commands, such as phase change memory, resistive memory, ferroelectric memory, etc.

[0147] The description of the present application has been presented for purposes of illustration and description, and is not intended to be exhaustive or limiting of the present application in the form disclosed. Many modifications and variations will be apparent to those skilled in the art.

Claims

1. A method for writing data to a non-volatile memory, comprising: Writing a first portion of data of a first page stripe to a plurality of first physical pages from a plurality of logical units; Backing up first parity data generated based on the first portion of data of the first page stripe in a first memory; Writing a first portion of data of a second page stripe to a plurality of second physical pages from the plurality of logical units; Caching second parity data generated based on the first portion of data of the second page stripe in the first memory; Writing a second portion of data of the first page stripe to a plurality of third physical pages from the plurality of logical units; Wherein the first physical page and the third physical page are not adjacent in the physical space of the non-volatile memory; wherein, Each of the plurality of logical units provides at least two physical pages for a page stripe, and the at least two physical pages are not adjacent in the physical space of the non-volatile memory; physical pages having the same physical address among the physical pages provided by the plurality of logical units belong to the same page stripe.

2. The method according to claim 1, wherein The first physical page and the third physical page not being adjacent in the physical space of the non-volatile memory includes that the first physical page and the third physical page do not belong to the same word line, do not belong to the same layer of the 3D memory, and / or do not belong to adjacent layers of the 3D memory.

3. The method according to any one of claims 1-2, further comprising: After writing the first portion of data of the second page stripe to a plurality of second physical pages from the plurality of logical units and before writing a third portion of user data of the first page stripe to a plurality of third physical pages from the plurality of logical units, writing a first portion of data of a third page stripe to a plurality of fourth physical pages from the plurality of logical units; Wherein the second physical page and the fourth physical page are adjacent in the physical space of the non-volatile memory.

4. The method according to one of claims 1-2, wherein: Each of the plurality of logical units provides two or more physical pages for the same page stripe that are not adjacent to each other in the physical space of the non-volatile memory.

5. The method according to claim 4, wherein: After writing the first portion of data of the second page stripe to a plurality of second physical pages from a plurality of logical units, backing up the second parity data; And during the process of writing the second portion of data of the first page stripe to a plurality of third physical pages from the plurality of logical units, caching parity data of the first page stripe generated based on the second portion of data of the first page stripe in the first memory.

6. The method according to one of claims 1-2, wherein Further comprising: writing a first portion of data of a third page stripe to a plurality of first physical pages from a second plurality of logical units; writing a first portion of data of a fourth page stripe to a plurality of second physical pages from the second plurality of logical units; writing a second portion of data of the third page stripe to a plurality of third physical pages from the second plurality of logical units; wherein the first physical page of the second plurality of logical units and the third physical page of the second plurality of logical units are not adjacent in the physical space of the non-volatile memory.

7. The method according to claim 6, wherein, Further comprising: During writing the first part of data of the first page strip into multiple first physical pages from multiple logical units, caching first parity data generated according to the first part of data of the first page strip in a first memory, writing the first part of data of the third page strip into multiple first physical pages from a second multiple of logical units, and caching fourth parity data generated according to the first part of data of the third page strip in a second memory.

8. The method according to claim 7, wherein: Back up the first parity data generated according to the first part of data of the first page strip in the first memory; cache second parity data generated according to the first part of data of the second page strip in the first memory; Back up the fourth parity data generated according to the first part of data of the third page strip in the second memory; cache fifth parity data generated according to the first part of data of the fourth page strip in the second memory.

9. According to the method of claim 8, wherein: Back up the first parity data generated according to the first part of data of the first page strip in the first memory; transfer the first parity data to the first memory; Cache the parity data of the first page strip generated according to the first parity data and the second part of data of the first page strip in the first memory; Back up the fourth parity data generated according to the first part of data of the third page strip in the second memory; Transfer the fourth parity data to the second memory; And cache the parity data of the third page strip generated according to the fourth parity data and the second part of data of the third page strip in the second memory.

10. A media interface controller, characterized in that, Comprising a parity data calculator and a first memory, the parity data calculator calculates parity data for data corresponding to a programming command, and the parity data is stored in the first memory; a media interface controller is also coupled to the CPU and a second memory; the parity data calculator is also coupled to the CPU and the second memory; the media interface controller executes the method according to any one of claims 1-9; wherein, in response to completion of calculation of parity data for the first part of data of a page strip, the media interface controller or the parity data calculator stores the parity data in the first memory into the second memory; wherein, The CPU, the media interface controller or the parity data calculator backs up the first parity data generated according to the first part of data of the first page strip in the first memory; and caches second parity data generated according to the first part of data of the second page strip in the first memory.

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