Organic light emitting diode display device and pixel thereof

Abstract

This application discloses an organic light-emitting diode (OLED) display device and its pixels. The pixels of the OLED display device include a capacitor, a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, and an OLED. The third transistor includes a first sub-transistor and a second sub-transistor connected in series between the drain and gate nodes of the first transistor, and the fourth transistor includes a third sub-transistor and a fourth sub-transistor connected in series between an initialization voltage line and a gate node. The eighth transistor applies a reference voltage to a first node between the first and second sub-transistors in response to a transmission signal, and the ninth transistor applies a reference voltage to a second node between the third and fourth sub-transistors in response to a transmission signal.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to display apparatuses, and more particularly to a pixel of an organic light emitting diode display apparatus and an organic light emitting diode display apparatus. BACKGROUND

[0002] In an organic light emitting diode ("OLED") display apparatus employed in a portable apparatus such as a smart phone or a tablet computer, reduction of power consumption can be desirable. Recently, a low frequency driving technique of reducing a driving frequency when displaying a still image has been developed to reduce power consumption of the OLED display apparatus. SUMMARY

[0003] In an organic light emitting diode ("OLED") display apparatus, when low frequency driving is performed, the OLED display apparatus can not drive a display panel at one frame or a plurality of frames, and the display panel can display an image based on a stored data voltage to reduce power consumption. However, although the display panel displays an image based on the stored data voltage, the stored data voltage can be distorted due to a leakage current of a transistor included in a pixel of the display panel, and thus image quality of the OLED display apparatus can be deteriorated.

[0004] Embodiments of the present application provide a pixel of an OLED display apparatus in which a leakage current of the pixel is substantially reduced or effectively prevented.

[0005] Embodiments provide an OLED display apparatus in which a leakage current of each pixel is substantially reduced or effectively prevented.

[0006] According to an embodiment, a pixel of an OLED display apparatus includes a capacitor including a first electrode coupled to a line of a first power voltage and a second electrode coupled to a gate node, a first transistor including a gate coupled to the gate node, a second transistor transmitting a data voltage to a source of the first transistor in response to a scan signal, a third transistor diode connecting the first transistor in response to the scan signal, wherein the third transistor includes first and second sub-transistors coupled to each other in series between a drain of the first transistor and the gate node, a fourth transistor applying an initialization voltage to the gate node in response to an initialization signal, wherein the fourth transistor includes third and fourth sub-transistors coupled to each other in series between a line of the initialization voltage and the gate node, a fifth transistor coupling the line of the first power voltage with the source of the first transistor in response to an emission signal, a sixth transistor coupling the drain of the first transistor with an anode of an organic light emitting diode in response to the emission signal, a seventh transistor applying the initialization voltage to the anode of the organic light emitting diode in response to the initialization signal, an eighth transistor applying a reference voltage to a first node between the first and second sub-transistors in response to the emission signal, a ninth transistor applying the reference voltage to a second node between the third and fourth sub-transistors in response to the emission signal, and the organic light emitting diode including the anode and a cathode coupled to a line of a second power voltage.

[0007] In an embodiment, the eighth transistor can apply the reference voltage to the first node in an emission period such that a leakage current between the gate node and the first node is reduced in the emission period, and the ninth transistor can apply the reference voltage to the second node in the emission period such that a leakage current between the gate node and the second node is reduced in the emission period.

[0008] In an embodiment, a voltage level of the reference voltage can be determined based on the data voltage and a threshold voltage of the first transistor.

[0009] In an embodiment, the first sub-transistor can include a gate receiving the scan signal, a first terminal coupled to the drain of the first transistor, and a second terminal coupled to the first node, the second sub-transistor can include a gate receiving the scan signal, a first terminal coupled to the first node, and a second terminal coupled to the gate node, the third sub-transistor can include a gate receiving the initialization signal, a first terminal coupled to the line of the initialization voltage, and a second terminal coupled to the second node, and the fourth sub-transistor can include a gate receiving the initialization signal, a first terminal coupled to the second node, and a second terminal coupled to the gate node.

[0010] In an embodiment, the second transistor can include a gate receiving the scan signal, a first terminal coupled to the data line, and a second terminal coupled to the source of the first transistor, the fifth transistor can include a gate receiving the emission signal, a first terminal coupled to the line of the first power supply voltage, and a second terminal coupled to the source of the first transistor, the sixth transistor can include a gate receiving the emission signal, a first terminal coupled to the drain of the first transistor, and a second terminal coupled to the anode of the organic light emitting diode, and the seventh transistor can include a gate receiving the initialization signal, a first terminal coupled to the line of the initialization voltage, and a second terminal coupled to the anode of the organic light emitting diode.

[0011] In an embodiment, the eighth transistor can include a gate receiving the emission signal, a first terminal coupled to the line of the reference voltage, and a second terminal coupled to the first node, and the ninth transistor can include a gate receiving the emission signal, a first terminal coupled to the line of the reference voltage, and a second terminal coupled to the second node.

[0012] In an embodiment, the frame period for the pixel can include an initialization period in which the gate node and the anode of the organic light emitting diode are initialized, a data write period in which a voltage obtained by subtracting a threshold voltage of the first transistor from the data voltage is stored at the second electrode of the capacitor, and an emission period in which the organic light emitting diode emits light.

[0013] In an embodiment, in the initialization period, the fourth transistor and the seventh transistor can be turned on, the fourth transistor can apply the initialization voltage to the gate node so that the gate node is initialized, and the seventh transistor can apply the initialization voltage to the anode of the organic light emitting diode so that the anode of the organic light emitting diode is initialized.

[0014] In an embodiment, in the data write period, the second transistor and the third transistor can be turned on, the second transistor can transmit the data voltage to the source of the first transistor, and the third transistor can diode-connect the first transistor so that the voltage obtained by subtracting the threshold voltage of the first transistor from the data voltage is stored at the second electrode of the capacitor.

[0015] In an embodiment, in the data write period, the fifth transistor, the sixth transistor, the eighth transistor, and the ninth transistor can be turned on, the first transistor can generate a driving current based on the voltage of the gate node, the fifth transistor and the sixth transistor can form a path of the driving current from the line of the first power supply voltage to the line of the second power supply voltage, the eighth transistor can apply the reference voltage to the first node, and the ninth transistor can apply the reference voltage to the second node.

[0016] In an embodiment, the first through ninth transistors can be implemented using P-type metal oxide semiconductor ("PMOS") transistors.

[0017] In an embodiment, the first, second, and fifth through ninth transistors can be implemented using PMOS transistors, and the third and fourth transistors can be implemented using N-type metal oxide semiconductor ("NMOS") transistors.

[0018] According to an embodiment, a pixel of an OLED display apparatus includes a capacitor including a first electrode coupled to a line of a first power voltage and a second electrode coupled to a gate node; a first transistor including a gate coupled to the gate node; a second transistor transmitting a data voltage to a source of the first transistor in response to a scan signal; a third transistor diode connecting the first transistor in response to the scan signal, wherein the third transistor includes first and second sub-transistors coupled to each other in series between a drain of the first transistor and the gate node; a fourth transistor applying an initialization voltage to the gate node in response to an initialization signal, wherein the fourth transistor includes third and fourth sub-transistors coupled to each other in series between a line of the initialization voltage and the gate node; a fifth transistor coupling the line of the first power voltage with the source of the first transistor in response to an emission signal; a sixth transistor coupling the drain of the first transistor with an anode of an organic light emitting diode in response to the emission signal; a seventh transistor applying the initialization voltage to the anode of the organic light emitting diode in response to the initialization signal; an eighth transistor applying a first reference voltage to a first node between the first and second sub-transistors in response to the emission signal; a ninth transistor applying a second reference voltage to a second node between the third and fourth sub-transistors in response to the emission signal; and the organic light emitting diode including the anode and a cathode coupled to a line of a second power voltage.

[0019] In an embodiment, the first and second reference voltages can be voltages identical to each other.

[0020] In an embodiment, the first and second reference voltages can be voltages different from each other.

[0021] According to an embodiment, an OLED display apparatus includes a display panel including a plurality of pixels, a data driver providing a data voltage to each of the plurality of pixels, a scan driver applying a scan signal and an initialization signal to each of the plurality of pixels, an emission driver providing an emission signal to each of the plurality of pixels, a power management circuit providing a first power voltage, a second power voltage, an initialization voltage, and a reference voltage to the display panel, and a controller controlling the data driver, the scan driver, the emission driver, and the power management circuit. Each of the plurality of pixels includes a capacitor including a first electrode coupled to a line of the first power voltage and a second electrode coupled to a gate node, a first transistor including a gate coupled to the gate node, a second transistor transferring the data voltage to a source of the first transistor in response to the scan signal, a third transistor diode connecting the first transistor in response to the scan signal, wherein the third transistor includes a first sub-transistor and a second sub-transistor coupled to each other in series between a drain of the first transistor and the gate node, a fourth transistor applying the initialization voltage to the gate node in response to the initialization signal, wherein the fourth transistor includes a third sub-transistor and a fourth sub-transistor coupled to each other in series between a line of the initialization voltage and the gate node, a fifth transistor coupling the line of the first power voltage with the source of the first transistor in response to the emission signal, a sixth transistor coupling the drain of the first transistor with an anode of an organic light emitting diode in response to the emission signal, a seventh transistor applying the initialization voltage to the anode of the organic light emitting diode in response to the initialization signal, an eighth transistor applying the reference voltage to a first node between the first sub-transistor and the second sub-transistor in response to the emission signal, a ninth transistor applying the reference voltage to a second node between the third sub-transistor and the fourth sub-transistor in response to the emission signal, and the organic light emitting diode including the anode and a cathode coupled to a line of the second power voltage.

[0022] In an embodiment, the controller can include a reference voltage determination block that determines a voltage level of the reference voltage based on image data for the plurality of pixels and a threshold voltage of the first transistor of the plurality of pixels.

[0023] In an embodiment, the reference voltage determination block can include a threshold voltage storage block that stores a representative threshold voltage of the first transistor of the plurality of pixels, a representative value calculation block that calculates a representative value of the image data for the plurality of pixels, and a control block that determines a representative data voltage corresponding to the representative value of the image data and determines the voltage level of the reference voltage by subtracting the representative threshold voltage from the representative data voltage.

[0024] In an embodiment, the display panel can be divided into a plurality of blocks, and the reference voltage provided to the display panel can include a plurality of block reference voltages provided to the plurality of blocks, respectively.

[0025] In an embodiment, the controller can include a reference voltage determination block that determines a voltage level of each of the plurality of block reference voltages based on image data for the plurality of pixels in each of the plurality of blocks and threshold voltages of the plurality of pixels in each of the plurality of blocks.

[0026] In an embodiment of the present application, as described above, in the pixel of the OLED display apparatus and the OLED display apparatus, the third transistor can include first and second sub-transistors coupled in series with each other between the drain and the gate node of the first transistor, the fourth transistor can include third and fourth sub-transistors coupled in series with each other between the line of the initialization voltage and the gate node, the eighth transistor can apply the reference voltage to a first node between the first and second sub-transistors in response to the emission signal, and the ninth transistor can apply the reference voltage to a second node between the third and fourth sub-transistors in response to the emission signal. Accordingly, a leakage current between the gate node and the first node and a leakage current between the gate node and the second node in the emission period can be greatly reduced, and the image quality of the OLED display apparatus can be improved. BRIEF DESCRIPTION OF DRAWINGS

[0027] The above and other features of embodiments of the present application will become more apparent by describing in detail embodiments thereof from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0028] Figure 1 FIG. 1 is a circuit diagram illustrating a pixel of an organic light emitting diode (“OLED”) display apparatus according to an embodiment.

[0029] Figure 2 FIG. 2 is a graph illustrating an example of luminance according to a driving frequency of a pixel not including an eighth transistor and a ninth transistor.

[0030] Figure 3 FIG. 3 is a timing diagram for describing an operation of the pixel according to an embodiment.

[0031] Figure 4 FIG. 4 is a circuit diagram for describing an embodiment of an operation of the pixel in an initialization period.

[0032] Figure 5 FIG. 5 is a circuit diagram for describing an embodiment of an operation of the pixel in a data write period.

[0033] Figure 6 FIG. 6 is a circuit diagram for describing an embodiment of an operation of the pixel in an emission period.

[0034] Figure 7 FIG. 7 is a circuit diagram illustrating a pixel of an OLED display apparatus according to an alternative embodiment.

[0035] Figure 8 is a timing diagram for describing the operation of a pixel according to an alternative embodiment.

[0036] Figure 9 is a circuit diagram showing a pixel of an OLED display apparatus according to another alternative embodiment.

[0037] Figure 10 is a circuit diagram showing a pixel of an OLED display apparatus according to yet another alternative embodiment.

[0038] Figure 11 is a block diagram showing an OLED display apparatus according to an embodiment.

[0039] Figure 12 is a block diagram showing an embodiment of a reference voltage determination block included in an OLED display apparatus.

[0040] Figure 13 is a block diagram showing an OLED display apparatus according to an alternative embodiment.

[0041] Figure 14 is an electronic device including an OLED display apparatus according to an embodiment. DETAILED DESCRIPTION

[0042] The present application will now be described more fully hereinafter with reference to the accompanying drawings, in which various embodiments are shown. The present application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the application to those skilled in the art. Like reference numerals refer to like elements throughout.

[0043] It will be understood that when an element is referred to as being "on" another element, it can be directly on the other element or intervening elements can be present therebetween. In contrast, when an element is referred to as being "directly on" another element, there are no intervening elements present.

[0044] It will be understood that, although the terms "first", "second", "third", etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, "a first element", "a first component", "a first region", "a first layer" or "a first portion" discussed below could be named a second element, a second component, a second region, a second layer or a second portion without departing from the teachings herein.

[0045] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, "a," "an," "the," and "at least one" are intended to include both singular and plural, unless the context clearly indicates otherwise. For example, "a member" is intended to mean, "at least one member," unless the context clearly indicates otherwise. "At least one" is not to be construed as limiting "one." "Or" means "and / or." As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. It will be further understood that the terms "comprises" and / or "comprising," when used in this specification, specify the presence of stated features, regions, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, regions, integers, steps, operations, elements, components, and / or groups thereof.

[0046] In addition, relative terms, such as "lower" or "bottom" and "upper" or "top," can be used herein to describe one element's or feature's relationship to another element or feature as illustrated in the figures. These relative terms are intended to encompass different orientations of the device in addition to the orientation depicted in the figures. For example, if the device in one of the figures is turned over, elements described as being on the "lower" side of other elements would then be oriented on the "upper" sides of the other elements. The term "lower" can thereby

[0047] "About" or "approximately," as used herein, includes within an acceptable range of a value being described and the average value one of ordinary skill in the art would understand to be within the range of values associated with the particular quantity being measured (i.e., the limitations of the measurement system). For example, "about" can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, or ±5% of the value.

[0048] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0049] The embodiments described herein should not be interpreted to be limited to the particular shapes of regions as shown herein, but include deviations in shapes that can result, for example, from manufacturing. For example, regions shown or described as flat can generally have rough and / or nonlinear features. Also, sharp corners shown can be rounded. Thus, the regions illustrated in the figures are schematic and their shapes are not intended to illustrate the precise shape of a region and are not intended to limit the scope of the claims.

[0050] Hereinafter, embodiments of the present application will be described in detail with reference to the accompanying drawings.

[0051] Figure 1 is a circuit diagram illustrating a pixel of an organic light emitting diode ("OLED") display apparatus according to an embodiment, and Figure 2 is a graph illustrating an example of luminance of a pixel according to a driving frequency, which does not include an eighth transistor and a ninth transistor.

[0052] Referring to Figure 1 , an embodiment of a pixel 100 of an OLED display apparatus can include a capacitor CST, a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, and an organic light emitting diode EL.

[0053] The capacitor CST can store a data voltage DV transmitted through the second transistor T2 and the (diode-connected) first transistor T1. The capacitor CST can be referred to as a storage capacitor. In an embodiment, the capacitor CST can include a first electrode coupled (or connected) to a line of a first power supply voltage ELVDD and a second electrode coupled to a gate node NG.

[0054] The first transistor T1 can generate a driving current based on a voltage of the second electrode of the capacitor CST or a voltage of the gate node NG. The first transistor T1 can be referred to as a driving transistor for driving the organic light emitting diode EL. In an embodiment, the first transistor T1 can include a gate coupled to the second electrode of the capacitor CST or the gate node NG, a first terminal (or source) coupled to a second terminal of the fifth transistor T5, and a second terminal (or drain) coupled to a first terminal of the sixth transistor T6.

[0055] The second transistor T2 can transmit the data voltage DV to the source of the first transistor T1 in response to a scan signal SS. The second transistor T2 can be referred to as a switching transistor or a scan transistor for transmitting the data voltage DV of a data line. In an embodiment, the second transistor T2 can include a gate receiving the scan signal SS, a first terminal coupled to the data line, and a second terminal coupled to the source of the first transistor T1.

[0056] The third transistor T3 can diode-connect the first transistor T1 in response to the scan signal SS. The third transistor T3 can be referred to as a threshold voltage compensation transistor for compensating for a threshold voltage of the first transistor T1. When the scan signal SS is applied, the data voltage DV transmitted by the second transistor T2 can be stored to the capacitor CST through the first transistor T1 diode-connected by the third transistor T3. Accordingly, the capacitor CST can store the data voltage DV compensated for the threshold voltage of the first transistor T1.

[0057] In an embodiment, as shown in FIG. 1A, the third transistor T3 can be implemented as a diode-connected transistor including a first sub-transistor T3-1 and a second sub-transistor T3-2 coupled in series with each other between the drain of the first transistor T1 and the gate node NG. In such an embodiment, the third transistor T3 can be implemented as a diode-connected transistor including the first sub-transistor T3-1 and the second sub-transistor T3-2 coupled in series with each other between the drain of the first transistor T1 and the gate node NG. Figure 1 In an embodiment, as shown in FIG. 1A, the third transistor T3 can be implemented as a diode-connected transistor including a first sub-transistor T3-1 and a second sub-transistor T3-2 coupled in series with each other between the drain of the first transistor T1 and the gate node NG. In such an embodiment, the third transistor T3 can be implemented as a diode-connected transistor including the first sub-transistor T3-1 and the second sub-transistor T3-2 coupled in series with each other between the drain of the first transistor T1 and the gate node NG.

[0058] The fourth transistor T4 can apply the initialization voltage VINT to the gate node NG in response to an initialization signal SI. The fourth transistor T4 can be referred to as a gate initialization transistor for initializing the gate node NG. When the initialization signal SI is applied, the fourth transistor T4 can apply the initialization voltage VINT to the gate node NG, and the gate of the first transistor T1 and the capacitor CST can be initialized based on the initialization voltage VINT of the gate node NG.

[0059] In an embodiment, as shown in FIG. 1A, the third transistor T3 can be implemented as a diode-connected transistor including a first sub-transistor T3-1 and a second sub-transistor T3-2 coupled in series with each other between the drain of the first transistor T1 and the gate node NG. In such an embodiment, the third transistor T3 can be implemented as a diode-connected transistor including the first sub-transistor T3-1 and the second sub-transistor T3-2 coupled in series with each other between the drain of the first transistor T1 and the gate node NG. Figure 1As illustrated in FIG. 10, the fourth transistor T4 can be implemented as a bi-transistor including a third sub-transistor T4-1 and a fourth sub-transistor T4-2 coupled to each other in series between the line of the initialization voltage VINT and the gate node NG. In this case, a leakage current of the fourth transistor T4 from or to the gate node NG can be greatly reduced. Further, in an embodiment, the third sub-transistor T4-1 can include a gate receiving the initialization signal SI, a first terminal coupled to the line of the initialization voltage VINT, and a second terminal coupled to a second node N2 between the third sub-transistor T4-1 and the fourth sub-transistor T4-2, and the fourth sub-transistor T4-2 can include a gate receiving the initialization signal SI, a first terminal coupled to the second node N2, and a second terminal coupled to the gate node NG.

[0060] The fifth transistor T5 can couple (or connect) the line of the first power voltage ELVDD to the source of the first transistor T1 in response to the emission signal EM, and the sixth transistor T6 can couple the drain of the first transistor T1 to the anode of the organic light emitting diode EL in response to the emission signal EM. The fifth transistor T5 and the sixth transistor T6 can be referred to as emission transistors for allowing the organic light emitting diode EL to emit light. When the emission signal EM is applied, the fifth transistor T5 and the sixth transistor T6 can be turned on to form a path of a driving current from the line of the first power voltage ELVDD to the line of the second power voltage ELVSS. In an embodiment, the fifth transistor T5 can include a gate receiving the emission signal EM, a first terminal coupled to the line of the first power voltage ELVDD, and a second terminal coupled to the source of the first transistor T1, and the sixth transistor T6 can include a gate receiving the emission signal EM, a first terminal coupled to the drain of the first transistor T1, and a second terminal coupled to the anode of the organic light emitting diode EL.

[0061] The seventh transistor T7 can apply the initialization voltage VINT to the anode of the organic light emitting diode EL in response to the initialization signal SI. The seventh transistor T7 can be referred to as a diode initialization transistor for initializing the organic light emitting diode EL. When the initialization signal SI is applied, the seventh transistor T7 can initialize the organic light emitting diode EL by using the initialization voltage VINT. In an embodiment, the seventh transistor T7 can include a gate receiving the initialization signal SI, a first terminal coupled to the line of the initialization voltage VINT, and a second terminal coupled to the anode of the organic light emitting diode EL.

[0062] The eighth transistor T8 can apply the reference voltage VREF to the first node N1 between the first sub transistor T3-1 and the second sub transistor T3-2 in response to the emission signal EM, and the ninth transistor T9 can apply the reference voltage VREF to the second node N2 between the third sub transistor T4-1 and the fourth sub transistor T4-2 in response to the emission signal EM. The eighth transistor T8 and the ninth transistor T9 can be referred to as node control transistors for controlling the first node N1 and the second node N2. When the emission signal EM is applied, the eighth transistor T8 and the ninth transistor T9 can apply the reference voltage VREF to the first node N1 and the second node N2, and a leakage current between the gate node NG and the first node N1 and a leakage current between the gate node NG and the second node N2 can be substantially reduced based on the reference voltage VREF applied to the first node N1 and the second node N2. In an embodiment, the eighth transistor T8 can include a gate that receives the emission signal EM, a first terminal coupled to a line of the reference voltage VREF, and a second terminal coupled to the first node N1, and the ninth transistor T9 can include a gate that receives the emission signal EM, a first terminal coupled to a line of the reference voltage VREF, and a second terminal coupled to the second node N2.

[0063] In an embodiment, as shown in FIG. 1A, the first transistor T1 to the ninth transistor T9 can be implemented using P-type metal oxide semiconductor (“PMOS”) transistors. In one embodiment, for example, the first transistor T1 to the ninth transistor T9 can be implemented using low temperature poly silicon (“LTPS”) PMOS transistors. Figure 1

[0064] The organic light emitting diode EL can emit light based on the driving current generated by the first transistor T1. When the emission signal EM is applied, the driving current generated by the first transistor T1 can be provided to the organic light emitting diode EL, and the organic light emitting diode EL can emit light based on the driving current. In an embodiment, the organic light emitting diode EL can include an anode coupled to the second terminal of the sixth transistor T6 and a cathode coupled to a line of the second power voltage ELVSS.

[0065] ​In an embodiment, an OLED display device including the pixel 100 can perform low-frequency driving, for example, when displaying a still image, to reduce power consumption. In such an embodiment, when the low-frequency driving is performed, each pixel 100 can not receive the initialization signal SI, the scan signal SS, and the data voltage DV in at least a portion of a plurality of frame periods or in a low-frequency hold period, and can emit light based on the data voltage DV stored in the capacitor CST in a previous frame period. In such an embodiment, the data voltage DV stored in the capacitor CST or the voltage of the gate node NG can be distorted due to the leakage current of the transistors T1 to T7 of the pixel 100 (for example, the leakage current of the third transistor T3 and the fourth transistor T4 directly coupled to the second electrode or the gate node NG of the capacitor CST), and thus, the image quality of the OLED display device can be degraded. In an embodiment of the pixel 100, as described above, the third transistor T3 can be implemented as a double transistor including a first sub-transistor T3-1 and a second sub-transistor T3-2, and the fourth transistor T4 can be implemented as a double transistor including a third sub-transistor T4-1 and a fourth sub-transistor T4-2, to reduce the leakage current of the third transistor T3 and the fourth transistor T4. Accordingly, the leakage current of the third transistor T3 and the fourth transistor T4 from or to the gate node NG can be greatly reduced.

[0066] In such an embodiment, in a case where the third transistor T3 includes a first sub-transistor T3-1 and a second sub-transistor T3-2, a parasitic capacitor can be formed between the first node N1 and a line of the pixel 100 (e.g., a line of the scan signal SS) between the first sub-transistor T3-1 and the second sub-transistor T3-2, and thus a leakage current of the second sub-transistor T3-2 from the first node N1 to the gate node NG can occur. In such an embodiment, in a case where the fourth transistor T4 includes a third sub-transistor T4-1 and a fourth sub-transistor T4-2, a parasitic capacitor can be formed between the second node N2 and a line of the pixel 100 (e.g., a line of the initialization signal SI) between the third sub-transistor T4-1 and the fourth sub-transistor T4-2, and thus a leakage current of the fourth sub-transistor T4-2 from the second node N2 to the gate node NG can occur. Accordingly, due to the leakage currents of the second sub-transistor T3-2 and the fourth sub-transistor T4-2, the voltage of the gate node NG can increase, the driving current of the first transistor T1 can decrease, and thus the luminance of the organic light emitting diode EL can decrease. Accordingly, in the conventional pixel which does not include the eighth transistor T8 and the ninth transistor T9, the voltage of the gate node NG can increase due to the leakage current to the gate node NG, and the luminance of the organic light emitting diode EL can decrease. Specifically, as the driving frequency of the conventional OLED display device including the conventional pixel increases, the luminance of the conventional OLED display device can further decrease, and flicker caused by the luminance difference can be perceived in the conventional OLED display device operating at a low driving frequency. When the conventional OLED display device operates at a driving frequency of about 60 Hz, as shown in 210 of FIG. 2B, for example, the luminance of the conventional pixel can decrease from a luminance of about 420 nits to a luminance of about 417 nits by about 0.71% in each frame period. Further, in a case where the driving current decreases, or in a case where the conventional OLED display device operates at a driving frequency of about 30 Hz, as shown in 230 of FIG. 2B, the luminance of the conventional pixel can decrease from a luminance of about 420 nits to a luminance of about 384.6 nits by about 8.43% in each frame period, and flicker caused by a luminance difference between about 384.6 nits and about 420 nits can be perceived. Figure 2 Figure 2

[0067] ​​In an embodiment of the pixel 100 of the OLED display apparatus according to the present application, the eighth transistor T8 can apply the reference voltage VREF to the first node N1 in the emission period to reduce a leakage current between the gate node NG and the first node N1 in the emission period, and the ninth transistor T9 can apply the reference voltage VREF to the second node N2 in the emission period to reduce a leakage current between the gate node NG and the second node N2 in the emission period. In such an embodiment, a voltage level of the reference voltage VREF can be determined based on the data voltage DV and the threshold voltage of the first transistor T1, so that the reference voltage VREF can have a voltage level close to a voltage of the gate node NG. In one embodiment, for example, the reference voltage VREF can be determined as a voltage obtained by subtracting the threshold voltage of the first transistor T1 from the data voltage DV. In an embodiment, the reference voltage VREF can be determined as a voltage obtained by subtracting an average of the threshold voltages of the first transistors T1 of all the pixels 100 of the OLED display apparatus from an average of the data voltages DV of the all the pixels 100. In an alternative embodiment, the pixels 100 of the OLED display apparatus can be grouped into a plurality of blocks, and the reference voltage VREF for each block can be determined as a voltage obtained by subtracting an average of the threshold voltages of the first transistors T1 of the pixels 100 in the block from an average of the data voltages DV of the pixels 100 in the block. In another alternative embodiment, the reference voltage VREF for each pixel 100 can be determined as a voltage obtained by subtracting the threshold voltage of the first transistor T1 of the pixel 100 from the data voltage DV of the pixel 100. Thus, in such an embodiment, all of the voltage of the first node N1, the voltage of the second node N2, and the voltage of the gate node NG can become substantially the same voltage as each other, or a voltage obtained by subtracting the threshold voltage of the first transistor T1 from the data voltage DV, and thus a leakage current between the gate node NG and the first node N1 and a leakage current between the gate node NG and the second node N2 can be effectively prevented or greatly reduced.

[0068] As described above, in the embodiment of the pixel 100 according to the present application, the third transistor T3 can include a first sub-transistor T3-1 and a second sub-transistor T3-2 coupled in series with each other between the drain of the first transistor T1 and the gate node NG, the fourth transistor T4 can include a third sub-transistor T4-1 and a fourth sub-transistor T4-2 coupled in series with each other between the line of the initialization voltage VINT and the gate node NG, the eighth transistor T8 can apply the reference voltage VREF to a first node N1 between the first sub-transistor T3-1 and the second sub-transistor T3-2 in response to the emission signal EM, and the ninth transistor T9 can apply the reference voltage VREF to a second node N2 between the third sub-transistor T4-1 and the fourth sub-transistor T4-2 in response to the emission signal EM. Thus, the leakage current between the gate node NG and the first node N1 and the leakage current between the gate node NG and the second node N2 can be greatly reduced, and the image quality of the OLED display apparatus including the pixel 100 can be improved.

[0069] Figure 3 is a timing diagram for describing the operation of the pixel according to the embodiment, Figure 4 is a circuit diagram for describing the embodiment of the operation of the pixel in the initialization period, Figure 5 is a circuit diagram for describing the embodiment of the operation of the pixel in the data write period, and Figure 6 is a circuit diagram for describing the embodiment of the operation of the pixel in the emission period.

[0070] Referring to Figure 1 and Figure 3 , the frame period FP for the pixel 100 can include an initialization period IP, a data write period DWP, and an emission period EMP. In the embodiment, the first transistor T1 to the ninth transistor T9 of the pixel 100 can be implemented using PMOS transistors, and the initialization signal SI, the scan signal SS, and the emission signal EM can be active low signals having a low level as an on level and a high level as an off level.

[0071] In the initialization period IP, the gate node NG and the anode of the organic light emitting diode EL can be initialized. In the initialization period IP, as shown in Figure 3 , the emission signal EM and the scan signal SS can have an off level, and the initialization signal SI can have an on level. In such an embodiment, as shown in Figure 4As illustrated in FIG. 1, in the initialization period IP, the fourth transistor T4 and the seventh transistor T7 can be turned on in response to the initialization signal SI having an on level. Accordingly, the fourth transistor T4 can apply the initialization voltage VINT to the gate node NG, and thus the gate node NG or the gate of the first transistor T1 and the capacitor CST can be initialized. In the initialization period IP, the seventh transistor T7 can apply the initialization voltage VINT to the anode of the organic light emitting diode EL, and thus the anode of the organic light emitting diode EL can be initialized.

[0072] In the data write period DWP, a voltage obtained by subtracting the threshold voltage of the first transistor T1 from the data voltage DV is stored at the second electrode of the capacitor CST. In the data write period DWP, as illustrated in FIG. 1, the second transistor T2 and the third transistor T3 can be turned on in response to the scan signal SS having an on level. Accordingly, the second transistor T2 can transfer the data voltage DV of the data line to the source of the first transistor T1. In the data write period DWP, the third transistor T3 can diode-connect the first transistor T1, and thus a voltage DV-VTH obtained by subtracting the threshold voltage (VTH) of the first transistor T1 from the data voltage DV can be stored at the second electrode of the capacitor CST through the diode-connected first transistor T1. Figure 3 Figure 5 In the data write period DWP, as illustrated in FIG. 1, the second transistor T2 and the third transistor T3 can be turned on in response to the scan signal SS having an on level. Accordingly, the second transistor T2 can transfer the data voltage DV of the data line to the source of the first transistor T1. In the data write period DWP, the third transistor T3 can diode-connect the first transistor T1, and thus a voltage DV-VTH obtained by subtracting the threshold voltage (VTH) of the first transistor T1 from the data voltage DV can be stored at the second electrode of the capacitor CST through the diode-connected first transistor T1.

[0073] In the emission period EMP, the organic light emitting diode EL can emit light. In the emission period EMP, as illustrated in FIG. 1, the initialization signal SI and the scan signal SS can have an off level, and the emission signal EM can have an on level. In the emission period EMP, as illustrated in FIG. 1, the first transistor T1 can be turned on in response to the emission signal EM having an on level, and thus the data voltage DV stored at the second electrode of the capacitor CST can be applied to the gate of the first transistor T1 through the first transistor T1. Accordingly, the first transistor T1 can be turned on in response to the data voltage DV, and thus the data voltage DV can be applied to the source of the first transistor T1 through the second transistor T2. Figure 3 Figure 6 ​​As shown, the fifth transistor T5, the sixth transistor T6, the eighth transistor T8, and the ninth transistor T9 can be turned on in response to a transmit signal EM having a conduction level. The first transistor T1 can generate a drive current IDR based on the voltage DV-VTH of the gate node NG or the voltage DV-VTH of the second electrode of the capacitor CST. The fifth transistor T5 and the sixth transistor T6 can form a path for the drive current IDR from the line of the first power supply voltage ELVDD to the line of the second power supply voltage ELVSS, and the organic light-emitting diode EL can emit light based on the drive current IDR generated by the first transistor T1. Therefore, since the drive current IDR is generated based on the voltage DV-VTH obtained by subtracting the threshold voltage (VTH) of the first transistor T1 from the data voltage DV, the drive current IDR can be determined based on the data voltage DV and is independent of the threshold voltage (VTH) of the first transistor T1.

[0074] During the launch period EMP, such as Figure 6 As shown, the eighth transistor T8 can apply a reference voltage VREF to the first node N1 between the first sub-transistor T3-1 and the second sub-transistor T3-2, and the ninth transistor T9 can apply the reference voltage VREF to the second node N2 between the third sub-transistor T4-1 and the fourth sub-transistor T4-2. During the emitter phase (EMP), the reference voltage VREF can have a voltage level close to the gate node NG's voltage DV-VTH, and therefore the leakage current between the gate node NG and the first node N1, as well as the leakage current between the gate node NG and the second node N2, can be significantly reduced.

[0075] Figure 7 This is a circuit diagram illustrating the pixels of an OLED display device according to an alternative embodiment, and Figure 8 It is a timing diagram used to describe the operation of pixels according to an alternative embodiment.

[0076] refer to Figure 7 An embodiment of the pixel 300 of an OLED display device may include a capacitor CST, a first transistor T1, a second transistor T2, a third transistor NT3, a fourth transistor NT4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, and an organic light-emitting diode EL. Except that the third transistor NT3 and the fourth transistor NT4 can be implemented using N-type metal-oxide-semiconductor (“NMOS”) transistors, Figure 7 The 300 pixels can have the same Figure 1 The configuration of pixels 100 is basically the same. In such an embodiment, except for the signals NSS and NSI (such as...) applied to the third transistor NT3 and the fourth transistor NT4... Figure 8The signals PSS, PSI and EM (as shown in FIG. 3) applied to the pixel 300 can be active low signals, in addition to Figure 7 The signals PSS, PSI and EM (as shown in FIG. 3) applied to the pixel 300 can be active low signals, in addition to Figure 8 The signals PSS, PSI and EM (as shown in FIG. 3) applied to the pixel 300 can be active low signals, in addition to Figure 1 The signals PSS, PSI and EM (as shown in FIG. 3) applied to the pixel 300 can be active low signals, in addition to Figure 3 The signals PSS, PSI and EM (as shown in FIG. 3) applied to the pixel 300 can be active low signals, in addition to

[0077] In another alternative embodiment of the pixel 300, the first transistor Tl, the second transistor T2, and the fifth through ninth transistors T5, T6, T7, T8 and T9 can be implemented using PMOS transistors, and the third transistor NT3 and the fourth transistor NT4 can be implemented using NMOS transistors. In one embodiment, for example, the first transistor Tl, the second transistor T2, and the fifth through ninth transistors T5, T6, T7, T8 and T9 can be implemented using LTPS PMOS transistors, and the third transistor NT3 and the first sub-transistor NT3-1, the second sub-transistor NT3-2, the third sub-transistor NT4-1 and the fourth sub-transistor NT4-2 of the fourth transistor NT4 can be implemented using oxide NMOS transistors. In such an embodiment, the third transistor NT3 and the fourth transistor NT4 or the first sub-transistor NT3-1, the second sub-transistor NT3-2, the third sub-transistor NT4-1 and the fourth sub-transistor NT4-2 directly coupled to the capacitor CST can be implemented using NMOS transistors having relatively small leakage current, and thus the leakage current from or to the gate node NG of the third transistor NT3 and the fourth transistor NT4 can be further reduced.

[0078] In an embodiment, as shown in Figure 7 and Figure 8 The initialization signal PSI, the scan signal PSS and the emission signal EM applied to the second transistor T2 and the fifth through ninth transistors T5, T6, T7, T8 and T9 can be active low signals having a low level as an on level and a high level as an off level, and the initialization signal NSI and the scan signal NSS applied to the third transistor NT3 and the fourth transistor NT4 can be active high signals having a high level as an on level and a low level as an off level, as shown in

[0079] Figure 9 is a circuit diagram showing a pixel of an OLED display apparatus according to another alternative embodiment.

[0080] Reference is made to Figure 9, an embodiment of the pixel 400 of the OLED display device can include the capacitor CST, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8', the ninth transistor T9', and the organic light emitting diode EL. Except that the eighth transistor T8' can be coupled to a line of the first reference voltage VREF1 and the ninth transistor T9' can be coupled to a line of the second reference voltage VREF2, Figure 9 The pixel 400 of the OLED display device can have substantially the same configuration as the pixel 100 of the OLED display device. Figure 1 The pixel 400 of the OLED display device can have substantially the same configuration as the pixel 100 of the OLED display device.

[0081] The eighth transistor T8' can apply the first reference voltage VREF1 to a first node N1 between the first sub-transistor T3-1 and the second sub-transistor T3-2 of the third transistor T3, and the ninth transistor T9' can apply the second reference voltage VREF2 to a second node N2 between the third sub-transistor T4-1 and the fourth sub-transistor T4-2 of the fourth transistor T4. In an embodiment, the first reference voltage VREF1 and the second reference voltage VREF2 can be substantially the same voltage as each other. In an alternative embodiment, the first reference voltage VREF1 and the second reference voltage VREF2 can be different voltages from each other. In such an embodiment, the first reference voltage VREF1 can have a voltage level suitable for the first node N1, the second reference voltage VREF2 can have a voltage level suitable for the second node N2, and thus a leakage current between the gate node NG and the first node N1 and a leakage current between the gate node NG and the second node N2 can be further reduced.

[0082] Figure 10 is a circuit diagram illustrating a pixel of an OLED display device according to still another alternative embodiment.

[0083] Referring to Figure 10 , an embodiment of the pixel 500 of the OLED display device can include the capacitor CST, the first transistor T1, the second transistor T2, the third transistor NT3, the fourth transistor NT4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8', the ninth transistor T9', and the organic light emitting diode EL. Except that the third transistor NT3 and the fourth transistor NT4 can be implemented using NMOS transistors, Figure 10 The pixel 500 of the OLED display device can have substantially the same configuration as the pixel 400 of the OLED display device. Figure 9 In such an embodiment, except that the signals NSS and NSI applied to the third transistor NT3 and the fourth transistor NT4 can be active high signals, the signals PSS, PSI, and EM provided to the pixel 500 illustrated in Figure 10 may be the same as the signals PSS, PSI, and EM provided to the pixel 400 of the OLED display deviceFigure 9 The signals SS, SI, and EM of the pixel 400 shown in FIG. 4A are substantially the same as those of the pixel 100 shown in FIG. 1A.

[0084] In an embodiment of the pixel 500, the first transistor T1, the second transistor T2, and the fifth to ninth transistors T5, T6, T7, T8', and T9' can be implemented using PMOS transistors, and the third transistor NT3 and the fourth transistor NT4 can be implemented using NMOS transistors. In such an embodiment, the third transistor NT3 and the fourth transistor NT4 or the first sub-transistor NT3-1, the second sub-transistor NT3-2, the third sub-transistor NT4-1, and the fourth sub-transistor NT4-2 directly coupled to the capacitor CST can be implemented using NMOS transistors having a relatively small leakage current, and thus the leakage current of the third transistor NT3 and the fourth transistor NT4 from or to the gate node NG can be further reduced.

[0085] Figure 11 is a block diagram illustrating an OLED display apparatus according to an embodiment, and Figure 12 is a block diagram illustrating an embodiment of a reference voltage determination block included in an OLED display apparatus.

[0086] Referring to Figure 11 , an embodiment of the OLED display apparatus 600 can include a display panel 610 including a plurality of pixels PX, a data driver 620 providing a data voltage DV to the plurality of pixels PX, a scan driver 630 providing a scan signal SS and an initialization signal SI to the plurality of pixels PX, an emission driver 640 providing an emission signal EM to the plurality of pixels PX, a power management circuit 650 providing a first power voltage ELVDD, a second power voltage ELVSS, an initialization voltage VINT, and a reference voltage VREF to the display panel 610, and a controller 660 controlling the data driver 620, the scan driver 630, the emission driver 640, and the power management circuit 650.

[0087] The display panel 610 can include a plurality of pixels PX. According to an embodiment, each pixel PX can be Figure 1 the pixel 100 of FIG. 1A, Figure 7 the pixel 300 of FIG. 3A, Figure 9 the pixel 400 of FIG. 4A, or Figure 10In each pixel PX, the third transistor can include a first sub-transistor and a second sub-transistor coupled in series with each other between the drain and the gate node of the first transistor, the fourth transistor can include a third sub-transistor and a fourth sub-transistor coupled in series with each other between the line of the initialization voltage VINT and the gate node, the eighth transistor can apply the reference voltage VREF to a first node between the first sub-transistor and the second sub-transistor in response to the emission signal EM, and the ninth transistor can apply the reference voltage VREF to a second node between the third sub-transistor and the fourth sub-transistor in response to the emission signal EM. Accordingly, a leakage current between the gate node and the first node and a leakage current between the gate node and the second node in the emission period can be significantly reduced, and the image quality of the OLED display apparatus 600 can be improved.

[0088] The data driver 620 can generate data voltages DV based on data control signals DCTRL and output image data ODAT received from the controller 660, and can provide the data voltages DV to the plurality of pixels PX. In an embodiment, the data control signals DCTRL can include, but are not limited to, an output data enable signal, a horizontal start signal, and a load signal. In an embodiment, the data driver 620 and the controller 660 can be implemented using a signal integrated circuit, and the signal integrated circuit can be referred to as a timing controller-embedded data driver ("TED"). In an alternative embodiment, the data driver 620 and the controller 660 can be implemented using separate integrated circuits, respectively.

[0089] The scan driver 630 can generate scan signals SS and initialization signals SI based on scan control signals SCTRL received from the controller 660, and can sequentially provide the scan signals SS and the initialization signals SI to the plurality of pixels PX on a row-by-row basis. In an embodiment, the scan control signals SCTRL can include, but are not limited to, an initialization start signal, an initialization clock signal, a scan start signal, and a scan clock signal. In an embodiment, the scan driver 630 can be integrated or formed in a peripheral portion of the display panel 610. In an alternative embodiment, the scan driver 630 can be implemented using one or more integrated circuits.

[0090] The emission driver 640 can generate emission signals EM based on emission control signals EMCTRL received from the controller 660, and can provide the emission signals EM to the plurality of pixels PX. In an embodiment, the emission signals EM can be global signals provided to the plurality of pixels PX substantially simultaneously. In an alternative embodiment, the emission signals EM can be provided to the plurality of pixels PX sequentially on a line-by-line basis. In an embodiment, the emission driver 640 can be integrated or formed in a peripheral portion of the display panel 610. In an alternative embodiment, the emission driver 640 can be implemented using one or more integrated circuits.

[0091] The power management circuit 650 can generate a first power voltage ELVDD, a second power voltage ELVSS, an initialization voltage VINT, and a reference voltage VREF provided to the display panel 610. In an embodiment, the power management circuit 650 can receive a reference voltage control signal VREFCS representing a voltage level of the reference voltage VREF from the controller 660, and can generate the reference voltage VREF having the voltage level represented by the reference voltage control signal VREFCS. In an embodiment, the power management circuit 650 can be implemented using an integrated circuit such as a power management integrated circuit (“PMIC”). In an alternative embodiment, the power management circuit 650 can be included in the data driver 620 or the controller 660.

[0092] The controller 660 (e.g., a timing controller) can receive input image data IDAT and control signals CTRL from an external host (e.g., an application processor (“AP”), a graphics processing unit (“GPU”), or a graphics card). In an embodiment, the control signals CTRL can include, but are not limited to, a vertical synchronization signal, a horizontal synchronization signal, an input data enable signal, a main clock signal, etc. The controller 660 can generate output image data ODAT, data control signals DCTRL, scan control signals SCTRL, emission control signals EMCTRL, and a reference voltage control signal VREFCS based on the input image data IDAT and the control signals CTRL. The controller 660 can control the operation of the data driver 620 by providing the output image data ODAT and the data control signals DCTRL to the data driver 620, can control the operation of the scan driver 630 by providing the scan control signals SCTRL to the scan driver 630, can control the operation of the emission driver 640 by providing the emission control signals EMCTRL to the emission driver 640, and can control the operation of the power management circuit 650 by providing the reference voltage control signal VREFCS to the power management circuit 650.

[0093] In an embodiment, as Figure 11As shown in FIG. 6, the controller 660 can include a reference voltage determination block 670 for controlling the reference voltage VREF. The reference voltage determination block 670 can determine a voltage level of the reference voltage VREF based on the input image data IDAT or the pixel image data for the plurality of pixels PX and the threshold voltage of the first transistor (or driving transistor) in the plurality of pixels PX. In an embodiment, as shown in FIG. 6, the reference voltage determination block 670 can include a threshold voltage storage block 672, a representative value calculation block 674, and a control block 676. Figure 12 As shown in FIG. 6, the reference voltage determination block 670 can include a threshold voltage storage block 672, a representative value calculation block 674, and a control block 676.

[0094] The threshold voltage storage block 672 can store a representative threshold voltage AVTH of the first transistor (or driving transistor) of the plurality of pixels PX of the display panel 610. In an embodiment, the representative threshold voltage AVTH can be an average value of the threshold voltages of the driving transistors of the plurality of pixels PX. In an alternative embodiment, the representative threshold voltage AVTH can be a median value of the threshold voltages of the driving transistors of the plurality of pixels PX. In an embodiment, the representative threshold voltage AVTH can be determined when the OLED display apparatus 600 is manufactured, and can be stored in the threshold voltage storage block 672. Different representative threshold voltages AVTH can be used in different OLED display apparatuses 600, and thus, the reference voltage VREF suitable for each of the different OLED display apparatuses 600 can be determined independently of each other.

[0095] The representative value calculation block 674 can receive the input image data IDAT or the plurality of pixel image data PXDAT for the plurality of pixels PX of the display panel 610, and can calculate a representative value RV of the plurality of pixel image data PXDAT. In an embodiment, the representative value calculation block 674 can calculate an average value of the plurality of pixel image data PXDAT as the representative value RV. In an alternative embodiment, the representative value calculation block 674 can calculate a median value of the plurality of pixel image data PXDAT as the representative value RV. In another alternative embodiment, the representative value calculation block 674 can calculate any value of the plurality of pixel image data PXDAT other than the average value and the median value as the representative value RV.

[0096] The control block 676 can determine a representative data voltage corresponding to the representative value RV received from the representative value calculation block 674. In one embodiment, for example, the control block 676 can determine a data voltage DV corresponding to a gray value represented by the representative value RV as the representative data voltage by using a lookup table. In an embodiment, the control block 676 can determine a voltage level of the reference voltage VREF by subtracting the representative threshold voltage AVTH from the representative data voltage. The control block 676 can provide a reference voltage control signal VREFCS representing the determined voltage level of the reference voltage VREF to the power management circuit 650, and the power management circuit 650 can generate the reference voltage VREF having the voltage level represented by the reference voltage control signal VREFCS. Accordingly, in each of the pixels PX, the reference voltage VREF obtained by subtracting the representative threshold voltage AVTH from the representative data voltage can be applied to the first node between the first and second sub-transistors and the second node between the third and fourth sub-transistors. Accordingly, the leakage current between the gate node and the first node and the leakage current between the gate node and the second node can be greatly reduced, and the image quality of the OLED display apparatus 600 can be improved.

[0097] Figure 13 is a block diagram illustrating an OLED display apparatus according to an alternative embodiment.

[0098] Reference Figure 13 An embodiment of the OLED display apparatus 700 can include a display panel 710, a data driver 720, a scan driver 730, an emission driver 740, a power management circuit 750, and a controller 760. Except that the display panel 710 can be divided into a plurality of blocks PXB1 and PXB2, Figure 13 The OLED display apparatus 700 of Figure 11 The OLED display apparatus 700 can have substantially the same configuration and substantially the same operation as the OLED display apparatus 600 of

[0099] In such an embodiment of the OLED display apparatus 700, the reference voltage determination block 770 of the controller 760 can determine the plurality of block reference voltages VREFB1 and VREFB2 with respect to the plurality of blocks PXB1 and PXB2, respectively.

[0100] The reference voltage determination block 770 can determine a voltage level of each of the plurality of block reference voltages VREFB1 and VREFB2 based on input image data IDAT for the plurality of pixels PX in each of the plurality of blocks PXB1 and PXB2 and a threshold voltage of a first transistor (or driving transistor) of the plurality of pixels PX in each of the plurality of blocks PXB1 and PXB2. In one embodiment, for example, as shown in FIG. 7B, the reference voltage determination block 770 can determine a voltage level of the first block reference voltage VREFB1 provided to the first block PXB1 based on a representative value of the input image data IDAT for the plurality of pixels PX in the first block PXB1 and a representative threshold voltage of the driving transistor of the plurality of pixels PX in the first block PXB1, and can determine a voltage level of the second block reference voltage VREFB2 provided to the second block PXB2 based on a representative value of the input image data IDAT for the plurality of pixels PX in the second block PXB2 and a representative threshold voltage of the driving transistor of the plurality of pixels PX in the second block PXB2. Figure 13 The display panel 710 can be divided into a first block PXB1 (or upper block) and a second block PXB2 (or lower block), but is not limited thereto. For example, the display panel 710 can be divided into a plurality of blocks PXB1 and PXB2 each including two or more pixels PX, and different (block) reference voltages VREFB1 and VREFB2 can be applied to the plurality of blocks PXB1 and PXB2 each including two or more pixels PX.

[0101] Figure 13 An electronic device including an OLED display apparatus according to an embodiment is provided. Figure 13 An electronic device including an OLED display apparatus according to an embodiment is provided.

[0102] Figure 14 An electronic device including an OLED display apparatus according to an embodiment is provided. An electronic device including an OLED display apparatus according to an embodiment is provided.

[0103] Reference Figure 14Embodiments of the electronic device 1100 can include a processor 1110, a memory device 1120, a storage device 1130, an input / output (I / O) device 1140, a power supply 1150, and an OLED display device 1160. The electronic device 1100 can further include a plurality of ports that communicate with a video card, a sound card, a memory card, a universal serial bus (“USB”) device, other electronic devices, and the like.

[0104] The processor 1110 can perform various computing functions or tasks. The processor 1110 can be an AP, a microprocessor, a central processing unit (“CPU”), or the like. The processor 1110 can be coupled to other components via an address bus, a control bus, a data bus, or the like. In an embodiment, the processor 1110 can be further coupled to an expansion bus, such as a peripheral component interconnect (“PCI”) bus.

[0105] The memory device 1120 can store data for operation of the electronic device 1100. In one embodiment, for example, the memory device 1120 can include at least one non-volatile memory device, such as an erasable programmable read-only memory (“EPROM”) device, an electrically erasable programmable read-only memory (“EEPROM”) device, a flash memory device, a phase change random access memory (“PRAM”) device, a resistive random access memory (“RRAM”) device, a nanoscale floating gate memory (“NFGM”) device, a polymer random access memory (“PoRAM”) device, a magnetic random access memory (“MRAM”) device, a ferroelectric random access memory (“FRAM”) device, or the like, and / or at least one volatile memory device, such as a dynamic random access memory (“DRAM”) device, a static random access memory (“SRAM”) device, a mobile DRAM device, or the like.

[0106] The storage device 1130 can be a solid state drive (“SSD”) device, a hard disk drive (“HDD”) device, a CD-ROM device, or the like. The I / O device 1140 can be an input device, such as a keyboard, a keypad, a mouse, a touchscreen, or the like, and an output device, such as a printer, a speaker, or the like. The power supply 1150 can supply power for operation of the electronic device 1100. The OLED display device 1160 can be coupled to other components by a bus or other communication link.

[0107] In each pixel of such an embodiment of the OLED display device 1160, the third transistor can include first and second sub-transistors coupled in series with each other between the drain and gate node of the first transistor, the fourth transistor can include third and fourth sub-transistors coupled in series with each other between the line of the initialization voltage and the gate node, the eighth transistor can apply the reference voltage to a first node between the first and second sub-transistors in response to the emission signal, and the ninth transistor can apply the reference voltage to a second node between the third and fourth sub-transistors in response to the emission signal. Accordingly, a leakage current between the gate node and the first node and a leakage current between the gate node and the second node in the emission period can be greatly reduced, and the image quality of the OLED display device 1160 can be improved.

[0108] Embodiments of the present application can be applied to any OLED display device 1160 and any electronic device 1100 including the OLED display device 1160. In one embodiment, for example, embodiments of the present application can be applied to a mobile phone, a smart phone, a wearable electronic device, a tablet computer, a television ("TV"), a digital TV, a three-dimensional ("3D") TV, a personal computer ("PC"), a home appliance, a laptop computer, a personal digital assistant ("PDA"), a portable multimedia player ("PMP"), a digital camera, a music player, a portable game machine, a navigation device, etc.

[0109] The present application should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the inventive concept to those skilled in the art.

[0110] While the present application has been particularly shown and described with reference to embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and details can be made therein without departing from the spirit or scope of the present application as defined by the following claims.

Claims

1. A pixel of an organic light emitting diode display apparatus, the pixel comprising: a capacitor including a first electrode coupled to a line of a first supply voltage and a second electrode coupled to a gate node; a first transistor including a gate coupled to the gate node; a second transistor transmitting a data voltage to a source of the first transistor in response to a scan signal; a third transistor diode connecting the first transistor in response to the scan signal, wherein the third transistor includes a first sub-transistor and a second sub-transistor coupled to each other in series between a drain of the first transistor and the gate node; a fourth transistor applying an initialization voltage to the gate node in response to an initialization signal, wherein the fourth transistor includes a third sub-transistor and a fourth sub-transistor coupled to each other in series between a line of the initialization voltage and the gate node; a fifth transistor coupling the line of the first supply voltage with the source of the first transistor in response to an emission signal; a sixth transistor coupling the drain of the first transistor with an anode of an organic light emitting diode in response to the emission signal; a seventh transistor applying the initialization voltage to the anode of the organic light emitting diode in response to the initialization signal; an eighth transistor applying a first reference voltage to a first node between the first sub-transistor and the second sub-transistor in response to the emission signal; a ninth transistor applying a second reference voltage different from the first reference voltage to a second node between the third sub-transistor and the fourth sub-transistor in response to the emission signal; and the organic light emitting diode including the anode and a cathode coupled to a line of a second supply voltage. 2.The pixel of claim 1, wherein: the eighth transistor applies the first reference voltage to the first node in an emission period such that a leakage current between the gate node and the first node is reduced in the emission period, and wherein the ninth transistor applies the second reference voltage to the second node in the emission period such that a leakage current between the gate node and the second node is reduced in the emission period. 3.The pixel of claim 1, wherein voltage levels of the first reference voltage and the second reference voltage are determined based on a threshold voltage of the first transistor and the data voltage. 4.The pixel of claim 1, wherein the first sub-transistor includes a gate receiving the scan signal, a first terminal coupled to the drain of the first transistor, and a second terminal coupled to the first node, wherein the second sub-transistor includes a gate receiving the scan signal, a first terminal coupled to the first node, and a second terminal coupled to the gate node, wherein the third sub-transistor includes a gate receiving the initialization signal, a first terminal coupled to the line of the initialization voltage, and a second terminal coupled to the second node, and the fourth sub-transistor includes a gate receiving the initialization signal, a first terminal coupled to the line of the initialization voltage, and a second terminal coupled to the second node. wherein the fourth transistor includes a gate that receives the initialization signal, a first terminal coupled to the second node, and a second terminal coupled to the gate node.

5. The pixel of claim 1, wherein the second transistor includes a gate that receives the scan signal, a first terminal coupled to a data line, and a second terminal coupled to the source of the first transistor, wherein the fifth transistor includes a gate that receives the emission signal, a first terminal coupled to the line of the first supply voltage, and a second terminal coupled to the source of the first transistor, wherein the sixth transistor includes a gate that receives the emission signal, a first terminal coupled to the drain of the first transistor, and a second terminal coupled to the anode of the organic light emitting diode, and wherein the seventh transistor includes a gate that receives the initialization signal, a first terminal coupled to the line of the initialization voltage, and a second terminal coupled to the anode of the organic light emitting diode.

6. The pixel of claim 1, wherein the eighth transistor includes a gate that receives the emission signal, a first terminal coupled to a line of the first reference voltage, and a second terminal coupled to the first node, and wherein the ninth transistor includes a gate that receives the emission signal, a first terminal coupled to a line of the second reference voltage, and a second terminal coupled to the second node.

7. The pixel of any one of claims 1 to 6, wherein a frame period for the pixel includes: an initialization period in which the gate node and the anode of the organic light emitting diode are initialized; a data write period in which a voltage resulting from subtracting a threshold voltage of the first transistor from the data voltage is stored at the second electrode of the capacitor; and an emission period in which the organic light emitting diode emits light. In the initialization period, 8. The pixel of claim 7, wherein, the fourth transistor and the seventh transistor are turned on, the fourth transistor applies the initialization voltage to the gate node such that the gate node is initialized, and the seventh transistor applies the initialization voltage to the anode of the organic light emitting diode such that the anode of the organic light emitting diode is initialized.

9. An organic light emitting diode display apparatus comprising: a display panel including a plurality of pixels; a data driver that provides a data voltage to each of the plurality of pixels; a scan driver that provides a scan signal and an initialization signal to each of the plurality of pixels; an emission driver that provides an emission signal to each of the plurality of pixels; a power management circuit that provides a first supply voltage, a second supply voltage, an initialization voltage, a first reference voltage, and a second reference voltage different from the first reference voltage to the display panel; and a controller that controls the data driver, the scan driver, the emission driver, and the power management circuit, wherein each of the plurality of pixels includes: a first transistor that includes a gate that receives the scan signal, a first terminal coupled to a data line, and a second terminal coupled to the gate node, a second transistor that includes a gate that receives the initialization signal, a first terminal coupled to the initialization voltage, and a second terminal coupled to the gate node, a third transistor that includes a gate that receives the emission signal, a first terminal coupled to the line of the first supply voltage, and a second terminal coupled to the gate node, a fourth transistor that includes a gate that receives the initialization signal, a first terminal coupled to the line of the initialization voltage, and a second terminal coupled to the gate node, a fifth transistor that includes a gate that receives the emission signal, a first terminal coupled to the line of the first supply voltage, and a second terminal coupled to the gate node, a sixth transistor that includes a gate that receives the emission signal, a first terminal coupled to the line of the second supply voltage, and a second terminal coupled to the gate node, a seventh transistor that includes a gate that receives the initialization signal, a first terminal coupled to the line of the initialization voltage, and a second terminal coupled to the gate node, an eighth transistor that includes a gate that receives the emission signal, a first terminal coupled to the line of the first reference voltage, and a second terminal coupled to the gate node, and a ninth transistor that includes a gate that receives the emission signal, a first terminal coupled to the line of the second reference voltage, and a second terminal coupled to the gate node. a capacitor including a first electrode coupled to a line of the first supply voltage and a second electrode coupled to a gate node; a first transistor including a gate coupled to the gate node; a second transistor transmitting the data voltage to a source of the first transistor in response to the scan signal; a third transistor diode connecting the first transistor in response to the scan signal, wherein the third transistor includes a first sub-transistor and a second sub-transistor coupled to each other in series between a drain of the first transistor and the gate node; a fourth transistor applying the initialization voltage to the gate node in response to the initialization signal, wherein the fourth transistor includes a third sub-transistor and a fourth sub-transistor coupled to each other in series between a line of the initialization voltage and the gate node; a fifth transistor coupling the line of the first supply voltage with the source of the first transistor in response to the emission signal; a sixth transistor coupling the drain of the first transistor with an anode of an organic light emitting diode in response to the emission signal; a seventh transistor applying the initialization voltage to the anode of the organic light emitting diode in response to the initialization signal; an eighth transistor applying the first reference voltage to a first node between the first sub-transistor and the second sub-transistor in response to the emission signal; a ninth transistor applying the second reference voltage to a second node between the third sub-transistor and the fourth sub-transistor in response to the emission signal; and the organic light emitting diode including the anode and a cathode coupled to a line of the second supply voltage.

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