Storage device and operation method thereof

Abstract

The present disclosure relates to a storage device and an operation method thereof. The storage device includes: a memory device including a memory cell array storing normal data and mapping data; and a storage controller configured to control the overall operation of the memory device including a programming operation, a reading operation, and an erasing operation in response to a request from a host. The memory device is configured to send first mapping data to the storage controller by reading first mapping data among the mapping data stored in the memory cell array during a mapping data loading operation, and to send second mapping data to a page buffer group of the memory device by reading second mapping data among the mapping data.

Description

Technical Field

[0001] The present disclosure relates to electronic devices, and more particularly, to a storage device and a method of operating the storage device. Background Art

[0002] A storage device is a device that stores data under the control of a host device such as a computer or a smart phone. A storage device may include a memory device that stores data and a storage controller that controls the memory device. A memory device may be a volatile memory device or a non-volatile memory device.

[0003] A volatile memory device is a device that stores data only when power is supplied and loses the stored data when the power is cut off. Volatile memory devices include, for example, static random access memory (SRAM), dynamic random access memory (DRAM), and the like.

[0004] Nonvolatile memory devices are devices that do not lose data even if the power is turned off. Nonvolatile memory devices include, for example, read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, etc. Summary of the invention

[0005] Embodiments of the present disclosure relate to a storage device capable of increasing a load capacity of map data and improving an operation speed and a method of operating the storage device.

[0006] A storage device according to an embodiment of the present disclosure includes: a memory device including a memory cell array storing normal data and mapping data; and a storage controller configured to control overall operations of the memory device including programming operations, reading operations, and erasing operations in response to a request from a host. The memory device is configured to send first mapping data to the storage controller by reading first mapping data among the mapping data stored in the memory cell array during a mapping data loading operation, and to send second mapping data to a page buffer group of the memory device by reading second mapping data among the mapping data.

[0007] A method for operating a storage device according to an embodiment of the present disclosure includes the following steps: reading first mapping data and second mapping data among mapping data stored in a system block of a memory cell array; sending the first mapping data to a storage controller, storing the first mapping data in a memory buffer of the storage controller, and storing the second mapping data in a page buffer group; and when the page buffer group receives a logical block address from the storage controller, performing a mapping data search operation to search whether the search mapping data corresponding to the received logical block address is included in the second mapping data.

[0008] A method for operating a storage device according to an embodiment of the present disclosure includes the following steps: during a mapping data loading operation, first mapping data among mapping data stored in a system block is stored in a storage controller, and second mapping data among the mapping data is stored in a page buffer group of the memory device; during a mapping data search operation, the memory device receives a logical block address from the storage controller, and searches whether the search mapping data corresponding to the received logical block address is included in the second mapping data; during a data programming operation, the memory device receives normal data and the logical block address from the storage controller, stores the normal data in a memory cell array, and then leaves the mapping data among the second mapping data corresponding to the logical block address in the page buffer group; and during a mapping data refresh operation, stores the mapping data remaining in the page buffer group in the memory cell array. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a diagram illustrating a storage device according to an embodiment of the present disclosure.

[0010] Figure 2 It is shown Figure 1 A diagram of the structure of a memory device.

[0011] Figure 3 It is shown Figure 2 FIG. 1 is a diagram of an embodiment of a memory cell array.

[0012] Figure 4 It is shown Figure 3 Circuit diagram of a memory block BLKa among the memory blocks BLK1 to BLKz.

[0013] Figure 5 It is shown Figure 3 1 is a circuit diagram of another embodiment of a memory block BLKb among the memory blocks BLK1 to BLKz.

[0014] Figure 6 is a diagram showing region division of a memory cell array according to a program operation.

[0015] Figure 7 It is shown that the Figure 2 Diagram of page buffers in a page buffer group.

[0016] Figure 8 is a diagram illustrating a loading operation of map data according to an embodiment of the present disclosure.

[0017] Fig. 9 is a flowchart illustrating a mapping data search operation according to an embodiment of the present disclosure.

[0018] Fig.10 is a diagram illustrating movement of map data during a map data search operation according to an embodiment of the present disclosure.

[0019] Fig.11 is a diagram illustrating signals transmitted between a storage controller and a memory device during a map data search operation according to an embodiment of the present disclosure.

[0020] Fig.12 is a diagram illustrating movement of data during an update operation of data according to an embodiment of the present disclosure.

[0021] Fig.13 is a diagram illustrating signals transmitted between a memory controller and a memory device during a program operation of data according to an embodiment of the present disclosure.

[0022] Fig.14 is a diagram illustrating movement of map data during a refresh operation of the map data according to an embodiment of the present disclosure.

[0023] Fig.15 is a diagram illustrating signals transmitted between a memory controller and a memory device during a refresh operation of map data according to an embodiment of the present disclosure.

[0024] Fig.16 It is shown Figure 1 FIG. 1 is a diagram of another embodiment of a storage controller.

[0025] Fig.17 is a block diagram illustrating a memory card system to which a storage device according to an embodiment of the present disclosure is applied.

[0026] Fig.18 is a block diagram illustrating a solid state drive (SSD) system to which a storage device according to an embodiment of the present disclosure is applied.

[0027] Fig.19 is a block diagram illustrating a user system to which a storage device according to an embodiment of the present disclosure is applied. DETAILED DESCRIPTION

[0028] Only the specific structure or functional description of the implementation of the concept disclosed in this specification or application is shown to describe the implementation of the concept according to the present disclosure. The implementation of the concept according to the present disclosure can be implemented in various forms, and these descriptions are not limited to the implementation described in this specification or application.

[0029] Hereinafter, the present disclosure will be described in detail by describing embodiments of the present disclosure with reference to the accompanying drawings. Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0030] Figure 1 is a diagram illustrating a storage device according to an embodiment of the present disclosure.

[0031] Reference Figure 1 , the storage device 50 may include a memory device 100 and a storage controller 200 that controls the operation of the memory device. The storage device 50 is a device that stores data under the control of a host 300 (e.g., a cellular phone, a smart phone, an MP3 player, a laptop computer, a desktop computer, a game console, a TV, a tablet PC, or an in-vehicle infotainment system).

[0032] The storage device 50 may be manufactured as one of various types of storage devices according to a host interface as a communication method with the host 300. For example, the storage device 50 may be configured as any of various types of storage devices, such as multimedia cards in the form of SSD, MMC, eMMC, RS-MMC, and micro-MMC, secure digital cards in the form of SD, mini-SD, and micro-SD, a universal serial bus (USB) storage device, a universal flash memory (UFS) device, a personal computer memory card international association (PCMCIA) card type storage device, a peripheral component interconnect (PCI) card type storage device, a high-speed PCI (PCI-E) card type storage device, a compact flash (CF) card, a smart media card, and a memory stick.

[0033] The memory device 50 may be manufactured into any of various types of packages. For example, the memory device 50 may be manufactured into any of various types of package types such as package on package (POP), system on package (SIP), system on chip (SOC), multi-chip package (MCP), chip on board (COB), wafer-level fabrication package (WFP), and wafer-level stacked package (WSP).

[0034] The memory device 100 may store normal data and mapping data. For example, the normal data is data associated with the normal operation of the device including the memory device 100. The mapping data is data indicating how the normal memory is laid out in the memory device 100. The memory device 100 operates under the control of the memory controller 200. The memory device 100 may include a memory cell array 110 including a plurality of memory cells storing the normal data and the mapping data.

[0035] Each memory cell may be configured as a single level cell (SLC) storing one data bit, a multi level cell (MLC) storing two data bits, a triple level cell (TLC) storing three data bits, or a quad level cell (QLC) storing four data bits.

[0036] The memory cell array 110 may include a plurality of memory blocks. Each memory block may include a plurality of memory cells. One memory block may include a plurality of pages. In an embodiment, a page may be a unit for storing data in the memory device 100 or reading data stored in the memory device 100. A memory block may be a unit for erasing data. In an embodiment, the memory device 100 may include a double data rate synchronous dynamic random access memory (DDR SDRAM), a low power double data rate 4 (LPDDR4) SDRAM, a graphic double data rate (GDDR) SDRAM, a low power DDR (LPDDR), a Rambus dynamic random access memory (RDRAM), a NAND flash memory, a vertical NAND flash memory, a NOR flash memory device, a resistance random access memory (RRAM), a phase change memory (PRAM), a magnetoresistive random access memory (MRAM), a ferroelectric random access memory (FRAM), a spin transfer torque random access memory (STT-RAM), etc. In this specification, for the convenience of description, it is assumed that the memory device 100 includes a NAND flash memory.

[0037] The memory device 100 is configured to receive a command and an address from the memory controller 200 and access an area selected by the address in the memory cell array. That is, the memory device 100 can perform a command-based operation on the area selected by the address. For example, the memory device 100 can perform a write operation (programming operation), a read operation, and an erase operation. During the programming operation, the memory device 100 can program data to the area selected by the address. During the read operation, the memory device 100 can read data from the area selected by the address. During the erase operation, the memory device 100 can erase the data stored in the area selected by the address.

[0038] In an embodiment, the memory device 100 may include a page buffer group 123. During a program operation, the page buffer group 123 receives and temporarily stores data to be programmed, and then stores the temporarily stored data in the memory cell array 110. In addition, during a read operation, the page buffer group 123 reads data stored in the memory cell array 110 and outputs the read data to the memory controller 200. In addition, the page buffer group 123 may read and store mapping data stored in the memory cell array 110. The page buffer group 123 may perform an operation of searching for mapping data corresponding to a logical block address (LBA) among the stored mapping data by receiving the LBA from the memory controller 200.

[0039] The memory controller 200 controls the overall operation of the memory device 50 .

[0040] When power is applied to the memory device 50, the memory controller 200 may execute the firmware FW. When the memory device 100 is a flash memory device, the memory controller 200 may operate firmware such as a flash translation layer (FTL) for controlling communication between the host 300 and the memory device 100.

[0041] In an embodiment, the storage controller 200 may receive mapping data from the memory device 100 and store the mapping data. In an embodiment, the storage controller 200 may receive data and a logical block address (LBA) from the host 300 and convert the LBA into a physical block address (PBA) indicating an address of a memory cell where data included in the memory device 100 is to be stored using the mapping data.

[0042] The memory controller 200 may control the memory device 100 to perform a program operation, a read operation, or an erase operation in response to a request from the host 300. During a program operation, the memory controller 200 may provide a program command, an LBA, and normal data to the memory device 100. During a read operation, the memory controller 200 may provide a read command and a PBA to the memory device 100. During an erase operation, the memory controller 200 may provide an erase command and a PBA to the memory device 100.

[0043] In an embodiment, the memory controller 200 may generate a program command, an address, and data and send them to the memory device 100 regardless of a request from the host 300. For example, the memory controller 200 may provide commands, addresses, and data to the memory device 100 to perform background operations such as a program operation for wear leveling and a program operation for garbage collection.

[0044] In an embodiment, the memory controller 200 may control at least two memory devices 100. In this case, the memory controller 200 may control the memory devices 100 according to an interleaving method to improve operation performance. The interleaving method may be an operation method that overlaps operation periods of at least two memory devices 100.

[0045] In an implementation, the memory controller 200 may include a processor 210 and a memory buffer 220 .

[0046] The processor 210 may control the overall operation of the storage controller 200 and perform logical operations. The processor 210 may communicate with the external host 300 and communicate with the memory device 100. In addition, the processor 210 may communicate with the memory buffer 220. The processor 210 may control the operation of the storage device 50 using the memory buffer 220 as an operating memory, a cache memory, or a buffer memory.

[0047] The processor 210 may perform the function of a flash translation layer (FTL). The processor 210 may convert a logical block address (LBA) provided from the host 300 into a physical block address (PBA) through the FTL. The FTL may convert the LBA into the PBA using mapping data. The FTL may perform an address conversion operation using a mapping table stored in the memory buffer 220.

[0048] For an embodiment, the processor 210 is configured to randomize data received from the host 300. For example, the processor 210 may randomize data received from the host 300 using a randomization seed. The randomized data is provided to the memory device 100 as data to be stored and is programmed in the memory cell array 110.

[0049] The processor 210 is configured to derandomize data received from the memory device 100 during a read operation. For example, the processor 210 may derandomize the data received from the memory device using a derandomization seed. The derandomized data may be output to the host 300.

[0050] As an embodiment, the processor 210 may utilize driver software or firmware to perform randomization and de-randomization.

[0051] The memory buffer 220 may be used as an operation memory, a cache memory, or a buffer memory of the processor 210. The memory buffer 220 may store codes and commands executed by the processor 210. The memory buffer 220 may store mapping data. The memory buffer 220 may store data processed by the processor 210. The memory buffer 220 may include a static RAM (SRAM) or a dynamic RAM (DRAM).

[0052] The memory buffer 220 may include a write / read buffer 221 and a mapping cache buffer 222 .

[0053] The write / read buffer 221 stores normal data received from the host 300 during a program operation and transmits the stored data to the memory device 100. In addition, the write / read buffer 221 stores normal data received from the memory device 100 during a read operation and transmits the stored data to the host 300.

[0054] The mapping cache buffer 222 may receive mapping data from the memory device 100 and store the mapping data. For example, during a power-on operation of the memory device, the memory device 100 may read some of the mapping data stored in the memory cell array 110 and transmit the read data to the memory controller 200, and the memory controller 200 may store the mapping data received from the memory device 100 in the mapping cache buffer 222.

[0055] The host 300 may communicate with the storage device 50 using at least one of various communication methods such as a universal serial bus (USB), a serial AT attachment (SATA), a serial attached SCSI (SAS), a high-speed inter-chip (HSIC), a small computer system interface (SCSI), a peripheral component interconnect (PCI), PCI express (PCIe), a non-volatile memory express (NVMe), a universal flash memory (UFS), a secure digital (SD), a multimedia card (MMC), an embedded MMC (eMMC), a dual in-line memory module (DIMM), a registered DIMM (RDIMM), and a load reduced DIMM (LRDIMM).

[0056] The memory device 50 according to the embodiment of the present disclosure described above may read first mapping data among the mapping data stored in the memory cell array 110 of the memory device 100 to store the first mapping data in the mapping cache buffer 222 of the memory controller 200, and may read second mapping data to store in the page buffer group 123 of the memory device 100. Therefore, the data storage capacity capable of storing the read mapping data may be increased.

[0057] In an embodiment, the first mapping data may be cold data having a relatively low number of accesses among the mapping data stored in the memory cell array 110, and the second mapping data may be hot data having a relatively high number of accesses among the mapping data stored in the memory cell array 110. In addition, in an embodiment, the first mapping data may be mapping data first read through the storage capacity of the mapping cache buffer 222 among the mapping data stored in the memory cell array 110, and the second mapping data may be mapping data read through the mapping data storage capacity of the page buffer group 123 after reading the first mapping data among the mapping data stored in the memory cell array 110.

[0058] Figure 2 It is shown Figure 1 A diagram of the structure of a memory device.

[0059] Reference Figure 2 , the memory device 100 may include a memory cell array 110 , a peripheral circuit 120 , and a control logic 130 .

[0060] The memory cell array 110 includes a plurality of memory blocks BLK1 to BLKz. The plurality of memory blocks BLK1 to BLKz are connected to the address decoder 121 through the row line RL. The plurality of memory blocks BLK1 to BLKz are connected to the page buffer group 123 through the bit lines BL1 to BLm. As an embodiment, at least one memory block (e.g., BLK1) among the plurality of memory blocks BLK1 to BLKz may be a system block. The system block may store a read recovery table and mapping data. The mapping data may include a plurality of mapping tables. A detailed description of the mapping data is provided later. Each of the plurality of memory blocks BLK1 to BLKz includes a plurality of memory cells. As an embodiment, the plurality of memory cells are nonvolatile memory cells. The memory cells connected to the same word line among the plurality of memory cells are defined as a page. That is, the memory cell array 110 is configured by a plurality of pages. According to an embodiment of the present disclosure, each of the plurality of memory blocks BLK1 to BLKz included in the memory cell array 110 may include a plurality of dummy cells. At least one dummy cell may be connected in series between the drain select transistor and the memory cell and between the source select transistor and the memory cell.

[0061] Each memory cell of the memory device 100 may be configured as a single level cell (SLC) storing one data bit, a multi level cell (MLC) storing two data bits, a triple level cell (TLC) storing three data bits, or a quad level cell (QLC) storing four data bits.

[0062] The peripheral circuit 120 may include an address decoder 121 , a voltage generator 122 , a page buffer group 123 , a data input / output circuit 124 , and a sensing circuit 125 .

[0063] The peripheral circuit 120 drives the memory cell array 110. For example, the peripheral circuit 120 may drive the memory cell array 110 to perform a program operation, a read operation, and an erase operation.

[0064] The address decoder 121 is connected to the memory cell array 110 through a row line RL. The row line RL may include a drain selection line, a word line, a source selection line, and a common source line. According to an embodiment of the present disclosure, the word line may include a normal word line and a dummy word line. According to an embodiment of the present disclosure, the row line RL may also include a pipe selection line.

[0065] The address decoder 121 is configured to operate in response to the control of the control logic 130. The address decoder 121 receives an address ADDR from the control logic 130.

[0066] The address decoder 121 is configured to decode the block address of the received address ADDR. The address decoder 121 selects at least one memory block among the memory blocks BLK1 to BLKz according to the decoded block address. The address decoder 121 is configured to decode the row address RADD of the received address ADDR. The address decoder 121 can select at least one word line of the selected memory block by applying the voltage provided from the voltage generator 122 to at least one word line WL according to the decoded row address RADD.

[0067] During a program operation, the address decoder 121 may apply a program voltage to a selected word line and apply a pass voltage having a level less than the program voltage to unselected word lines. During a program verification operation, the address decoder 121 may apply a verification voltage to a selected word line and apply a verification pass voltage having a level greater than the verification voltage to unselected word lines.

[0068] During a read operation, the address decoder 121 may apply a read voltage to a selected word line and apply a read pass voltage having a level greater than that of the read voltage to unselected word lines.

[0069] According to an embodiment of the present disclosure, an erase operation of the memory device 100 is performed in units of memory blocks. The address ADDR input to the memory device 100 during the erase operation includes a block address. The address decoder 121 may decode the block address and select a memory block according to the decoded block address. During the erase operation, the address decoder 121 may apply a ground voltage to a word line input to the selected memory block.

[0070] According to an embodiment of the present disclosure, the address decoder 121 may be configured to decode a column address of the transmitted address ADDR. The decoded column address may be transmitted to the page buffer group 123. As an example, the address decoder 121 may include components such as a row decoder, a column decoder, and an address buffer.

[0071] The voltage generator 122 is configured to generate a plurality of operating voltages Vop using an external power supply voltage supplied to the memory device 100. The voltage generator 122 operates in response to the control of the control logic 130.

[0072] As an example, the voltage generator 122 may generate the internal power supply voltage by adjusting the external power supply voltage. The internal power supply voltage generated by the voltage generator 122 is used as an operating voltage of the memory device 100.

[0073] As an embodiment, the voltage generator 122 may use an external power supply voltage or an internal power supply voltage to generate a plurality of operating voltages Vop. The voltage generator 122 may be configured to generate various voltages required by the memory device 100. For example, the voltage generator 122 may generate a plurality of erase voltages, a plurality of program voltages, a plurality of pass voltages, a plurality of select read voltages, and a plurality of non-select read voltages.

[0074] To generate a plurality of operating voltages Vop having various voltage levels, the voltage generator 122 may include a plurality of pumping capacitors receiving an internal voltage and selectively enable the plurality of pumping capacitors in response to the control logic 130 to generate the plurality of operating voltages Vop.

[0075] The generated plurality of operating voltages Vop may be supplied to the memory cell array 110 through the address decoder 121 .

[0076] The page buffer group 123 includes first to mth page buffers PB1 to PBm connected to the memory cell array 110 through first to mth bit lines BL1 to BLm, respectively. The first to mth page buffers PB1 to PBm operate in response to the control of the control logic 130 .

[0077] The first to m-th page buffers PB1 to PBm communicate data DATA with the data input / output circuit 124. At the time of programming, the first to m-th page buffers PB1 to PBm receive data DATA to be stored through the data input / output circuit 124 and the data lines DL.

[0078] During a programming operation, when a programming pulse is applied to a selected word line, the first page buffer PB1 to the mth page buffer PBm may transmit the data DATA to be stored (i.e., the data DATA received by the data input / output circuit 124) to the selected memory cell through the bit lines BL1 to BLm. The memory cells of the selected page are programmed according to the transmitted data DATA. The memory cells connected to the bit lines to which a programming permission voltage (e.g., a ground voltage) is applied may have an increased threshold voltage. The threshold voltage of the memory cells connected to the bit lines to which a programming inhibition voltage (e.g., a power supply voltage) is applied may be maintained. During a programming verification operation, the first page buffer PB1 to the mth page buffer PBm read the data DATA stored in the memory cells from the selected memory cells through the bit lines BL1 to BLm.

[0079] During a read operation, the page buffer group 123 may read data DATA from memory cells of a selected page through the bit lines BL and store the read data DATA in the first to m-th page buffers PB1 to PBm.

[0080] During an erase operation, the page buffer group 123 may float the bit line BL. As an embodiment, the page buffer group 123 may include a column selection circuit.

[0081] During the mapping data loading operation, the first to m-th page buffers PB1 to PBm may read first mapping data among the mapping data stored in the system block BLK1. The read first mapping data is transmitted to the system block BLK1 through the data input / output circuit 124. Figure 1 In addition, during the mapping data loading operation, the first to m-th page buffers PB1 to PBm read second mapping data among the mapping data stored in the system block BLK1 and store the read second mapping data. During the mapping data searching operation, the first to m-th page buffers PB1 to PBm may search for mapping data corresponding to the LBA received from the storage controller 200 among the stored second mapping data.

[0082] The data input / output circuit 124 is connected to the first to m-th page buffers PB1 to PBm through the data lines DL. The data input / output circuit 124 operates in response to the control of the control logic 130.

[0083] The data input / output circuit 124 may include a plurality of input / output buffers (not shown) that receive input data DATA. During a program operation, the data input / output circuit 124 receives normal data DATA to be stored from an external controller (not shown). During a read operation, the data input / output circuit 124 outputs normal data DATA transmitted from the first page buffer PB1 to the mth page buffer PBm included in the page buffer group 123 to the external controller.

[0084] During a read operation or a verification operation, the sensing circuit 125 may generate a reference current in response to a signal of a permission bit VRYBIT generated by the control logic 130, and may compare a sensing voltage VPB received from the page buffer group 123 with a reference voltage generated by the reference current to output a pass signal or a fail signal to the control logic 130.

[0085] The control logic 130 may be connected to the address decoder 121, the voltage generator 122, the page buffer group 123, the data input / output circuit 124, and the sensing circuit 125. The control logic 130 may be configured to control all operations of the memory device 100. The control logic 130 may operate in response to a command CMD transmitted from an external device. The control logic 130 may be implemented as hardware, software, or a combination of hardware and software. For example, the control logic 130 may be a control logic circuit operating according to an algorithm and / or a processor executing a control logic code.

[0086] The control logic 130 may generate various signals in response to the command CMD and the address ADDR to control the peripheral circuit 120. For example, the control logic 130 may generate an operation signal OPSIG, a row address RADD, a read / write circuit control signal PBSIGNALS, and a permission bit VRYBIT in response to the command CMD and the address ADDR. The control logic 130 may output the operation signal OPSIG to the voltage generator 122, the row address RADD to the address decoder 121, the read / write control signal to the page buffer group 123, and the permission bit VRYBIT to the sensing circuit 125. In addition, the control logic 130 may determine whether the verification operation passes or fails in response to the pass signal PASS or the fail signal FAIL output by the sensing circuit 125.

[0087] In an implementation, the control logic 130 may store data received from the memory controller 200 in the page buffer 123 of the page buffer group 123 under the control of the memory controller 200 .

[0088] The control logic 130 may program normal data or mapping data stored in the page buffers 123 of the page buffer group 123 to the memory cell array 110 under the control of the memory controller 200 .

[0089] For example, when the control logic 130 receives a program command from the memory controller 200, the control logic 130 may program normal data stored in the page buffers 123 of the page buffer group 123 in the memory cell array 110 in response to the program command. When the control logic 130 receives a mapping data refresh command from the memory controller 200, the control logic 130 may program the searched mapping data stored in the page buffers 123 of the page buffer group 123 in the system block BLK1 of the memory cell array 110 in response to the mapping data refresh command.

[0090] The control logic 130 may read normal data stored in the memory cell array 110 under the control of the memory controller 200. Specifically, the control logic 130 may first program the data stored in the page buffers 123 of the page buffer group 123 in the memory cell array 110, and then store the data read from the memory cell array 110 in the page buffers 123 of the page buffer group 123. The control logic 130 may provide the data stored in the page buffers of the page buffer group 123 to the memory controller 200 through the data input / output circuit 124.

[0091] The control logic 130 may read the mapping data stored in the system block BLK1 of the memory cell array 110 under the control of the memory controller 200. Specifically, the control logic 130 may provide the first mapping data among the mapping data read from the system block BLK1 to the memory controller 200 through the data input / output circuit 124. In addition, the control logic 130 may store the second mapping data among the mapping data read from the system block BLK1.

[0092] Figure 3 It is shown Figure 2 FIG. 1 is a diagram of an embodiment of a memory cell array.

[0093] Reference Figure 3 , the memory cell array 110 includes a plurality of memory blocks BLK1 to BLKz. Each memory block has a three-dimensional structure. Each memory block includes a plurality of memory cells stacked on a substrate. These plurality of memory cells are arranged along the +X direction, the +Y direction, and the +Z direction. Figure 4 and Figure 5 The structure of each memory block is described in more detail.

[0094] Figure 4 It is shown Figure 3 Circuit diagram of a memory block BLKa among the memory blocks BLK1 to BLKz.

[0095] Reference Figure 4 , the memory block BLKa includes a plurality of cell strings CS11 to CS1m and CS21 to CS2m. As an embodiment, each of the plurality of cell strings CS11 to CS1m and CS21 to CS2m may be formed in a "U" shape. In the memory block BLKa, m cell strings are arranged in a row direction (ie, +X direction). Figure 5 In FIG. 1 , two cell strings are arranged in the column direction (ie, +Y direction). However, this is for convenience of description, and it can be understood that three or more cell strings may be arranged in the column direction.

[0096] Each of the plurality of cell strings CS11 to CS1m and CS21 to CS2m includes at least one source select transistor SST, first to nth memory cells MC1 to MCn, a pipe transistor PT, and at least one drain select transistor DST.

[0097] Each of the selection transistors SST and DST and the memory cells MC1 to MCn may have a similar structure. As an embodiment, each of the selection transistors SST and DST and the memory cells MC1 to MCn may include a channel layer, a tunnel insulating film, a charge storage film, and a blocking insulating film. As an embodiment, a column for providing a channel layer may be provided in each cell string. As an embodiment, a column for providing at least one of a channel layer, a tunnel insulating film, a charge storage film, and a blocking insulating film may be provided in each cell string.

[0098] The source selection transistor SST of each cell string is connected between the common source line CSL and the memory cells MC1 to MCp.

[0099] As an embodiment, source selection transistors of cell strings arranged in the same row are connected to a source selection line extending in the row direction, and source selection transistors of cell strings arranged in different rows are connected to different source selection lines. Figure 4 In the embodiment, source selection transistors of the cell strings CS11 to CS1m of the first row are connected to the first source selection line SSL1. Source selection transistors of the cell strings CS21 to CS2m of the second row are connected to the second source selection line SSL2.

[0100] As another embodiment, source selection transistors of the cell strings CS11 to CS1m and CS21 to CS2m may be commonly connected to one source selection line.

[0101] The first to n-th memory cells MC1 to MCn of each cell string are connected between a source select transistor SST and a drain select transistor DST.

[0102] The first to nth memory cells MC1 to MCn may be divided into the first to pth memory cells MC1 and the (p+1)th memory cells MCp+1 to the nth memory cells MCn. The first to pth memory cells MC1 to MCp are sequentially arranged in a direction opposite to the +Z direction and are connected in series between the source selection transistor SST and the tube transistor PT. The (p+1)th memory cells MCp+1 to the nth memory cells MCn are sequentially arranged in the +Z direction and are connected in series between the tube transistor PT and the drain selection transistor DST. The first to pth memory cells MC1 and the (p+1)th memory cells MCp+1 to the nth memory cells MCn are connected to each other through the tube transistor PT. The gates of the first to nth memory cells MC1 to MCn of each cell string are respectively connected to the first to nth word lines WL1 to WLn.

[0103] The gate of the tube transistor PT of each cell string is connected to the pipeline PL.

[0104] The drain selection transistors DST of each cell string are connected between the corresponding bit line and the memory cells MCp+1 to MCn. The cell strings arranged in the row direction are connected to the drain selection lines extending in the row direction. The drain selection transistors of the cell strings CS11 to CS1m of the first row are connected to the first drain selection line DSL1. The drain selection transistors of the cell strings CS21 to CS2m of the second row are connected to the second drain selection line DSL2.

[0105] The cell strings arranged in the column direction are connected to the bit lines extending in the column direction. Figure 4 In the embodiment, the cell strings CS11 and CS21 of the first column are connected to the first bit line BL1. The cell strings CS1m and CS2m of the mth column are connected to the mth bit line BLm.

[0106] Memory cells connected to the same word line in the cell strings arranged in the row direction configure one page. For example, memory cells connected to the first word line WL1 among the cell strings CS11 to CS1m of the first row configure one page. Memory cells connected to the first word line WL1 among the cell strings CS21 to CS2m of the second row configure another page. Cell strings arranged in one row direction can be selected by selecting any one of the drain selection lines DSL1 and DSL2. One page of the selected cell string can be selected by selecting any one of the word lines WL1 to WLn.

[0107] As another embodiment, even bit lines and odd bit lines may be provided instead of the first to mth bit lines BL1 to BLm. In addition, even-numbered cell strings among the cell strings CS11 to CS1m or CS21 to CS2m arranged in the row direction may be connected to the bit lines, respectively, and odd-numbered cell strings among the cell strings CS11 to CS1m or CS21 to CS2m arranged in the row direction may be connected to the odd bit lines, respectively.

[0108] As an embodiment, at least one of the first to nth memory cells MC1 to MCn may be used as a dummy memory cell. For example, at least one dummy memory cell is provided to reduce the electric field between the source select transistor SST and the memory cells MC1 to MCp. Alternatively, at least one dummy memory cell is provided to reduce the electric field between the drain select transistor DST and the memory cells MCp+1 to MCn. As more dummy memory cells are provided, the reliability of the operation of the memory block BLKa improves, however, the size of the memory block BLKa increases. As fewer memory cells are provided, the size of the memory block BLKa may be reduced, however, the reliability of the operation of the memory block BLKa may be reduced.

[0109] In order to effectively control at least one dummy memory cell, each dummy memory cell may have a desired threshold voltage. Before or after the erase operation of the memory block BLKa, a programming operation for all or part of the dummy memory cells may be performed. When an erase operation is performed after the programming operation is performed, the dummy memory cells may have a desired threshold voltage by controlling the voltage applied to the dummy word line connected to each dummy memory cell.

[0110] Figure 5 It is shown Figure 3 1 is a circuit diagram of another embodiment of a memory block BLKb among the memory blocks BLK1 to BLKz.

[0111] Reference Figure 5 , the memory block BLKb includes a plurality of cell strings CS11' to CS1m' and CS21' to CS2m'. Each of the plurality of cell strings CS11' to CS1m' and CS21' to CS2m' extends along the +Z direction. Each of the plurality of cell strings CS11' to CS1m' and CS21' to CS2m' includes at least one source selection transistor SST, first to nth memory cells MC1 to MCn, and at least one drain selection transistor DST stacked on a substrate (not shown) below the memory block BLK1'.

[0112] The source selection transistors SST of each cell string are connected between a common source line CSL and memory cells MC1 to MCn. The source selection transistors of the cell strings arranged in the same row are connected to the same source selection line. The source selection transistors of the cell strings CS11' to CS1m' arranged in the first row are connected to the first source selection line SSL1. The source selection transistors of the cell strings CS21' to CS2m' arranged in the second row are connected to the second source selection line SSL2. As another embodiment, the source selection transistors of the cell strings CS11' to CS1m' and CS21' to CS2m' may be connected together to one source selection line.

[0113] The first to nth memory cells MC1 to MCn of each cell string are connected in series between the source selection transistor SST and the drain selection transistor DST. Gates of the first to nth memory cells MC1 to MCn are connected to the first to nth word lines WL1 to WLn, respectively.

[0114] The drain selection transistors DST of each cell string are connected between the corresponding bit line and the memory cells MC1 to MCn. The drain selection transistors of the cell strings arranged in the row direction are connected to the drain selection lines extending in the row direction. The drain selection transistors of the cell strings CS11' to CS1m' of the first row are connected to the first drain selection line DSL1. The drain selection transistors of the cell strings CS21' to CS2m' of the second row are connected to the second drain selection line DSL2.

[0115] As a result, in addition to excluding the tube transistor PT from each cell string, Figure 5 The memory block BLKb has Figure 4 The equivalent circuit of the storage block BLKa is similar.

[0116] As another embodiment, even bit lines and odd bit lines may be provided instead of the first to mth bit lines BL1 to BLm. In addition, even-numbered cell strings among the cell strings CS11' to CS1m' or CS21' to CS2m' arranged in the row direction may be connected to the even bit lines, respectively, and odd-numbered cell strings among the cell strings CS11' to CS1m' or CS21' to CS2m' arranged in the row direction may be connected to the odd bit lines, respectively.

[0117] As an embodiment, at least one of the first memory cell MC1 to the nth memory cell MCn may be used as a dummy memory cell. For example, at least one dummy memory cell is provided to reduce the electric field between the source selection transistor SST and the memory cells MC1 to MCn. Alternatively, at least one dummy memory cell is provided to reduce the electric field between the drain selection transistor DST and the memory cells MC1 to MCn. As more dummy memory cells are provided, the reliability of the operation of the memory block BLKb is improved, however, the size of the memory block BLKb is increased. As fewer memory cells are provided, the size of the memory block BLKb may be reduced, however, the reliability of the operation of the memory block BLKb may be reduced.

[0118] In order to effectively control at least one dummy memory cell, each dummy memory cell may have a desired threshold voltage. Before or after the erase operation for the memory block BLKb, a programming operation for all or part of the dummy memory cells may be performed. When the erase operation is performed after the programming operation is performed, the dummy memory cells may have a desired threshold voltage by controlling the voltage applied to the dummy word line connected to each dummy memory cell.

[0119] Figure 6 is a diagram showing region division of a memory cell array according to a program operation.

[0120] Reference Figure 6, the memory cell array 110 may divide a storage space into a static SLC area, a dynamic SLC area, and a TLC area according to a programming method during a programming operation.

[0121] For example, the static SLC area and the dynamic SLC area are areas programmed in an SLC programming method during a program operation, and the TLC area is an area programmed in a TLC programming method during a program operation.

[0122] In order to improve the programming operation speed and stability during the programming operation, the memory device receives data to be programmed, and then programs the received data in the static SLC area or the dynamic SLC area in the SLC programming method. Thereafter, during the background operation of the memory device, the data stored in the static SLC area or the dynamic SLC area is read, and the read data is programmed in the TLC area.

[0123] Therefore, programming operation speed and data reliability can be improved by performing the programming operation in the SLC programming method during the programming operation, and data storage efficiency can be improved by programming data stored in the static SLC area or the dynamic SLC area in the TLC area in the TLC programming method during a background operation (e.g., a garbage collection operation).

[0124] The static SLC area is a fixed area of ​​the set data capacity of the memory cell array 110, and the dynamic SLC area is a area that can be changed according to the capacity of the data to be programmed. Therefore, the dynamic SLC area can be adjacent to the static SLC area, or can be set between the TLC areas.

[0125] Figure 7 It is shown that the Figure 2 Diagram of page buffers in a page buffer group.

[0126] Each of the plurality of page buffers PB1 to PBm may include a main buffer Main Buffer, a cache buffer Cache Buffer, a first map buffer 1st Map Buffer, and a second map buffer 2nd Map Buffer.

[0127] The main buffer Main Buffer of each of the page buffers PB1 to PBm may be referred to as the main buffer level 123A, the cache buffer Cache Buffer of each of the page buffers PB1 to PBm may be referred to as the cache buffer level 123B, the first map buffer 1st Map Buffer of each of the page buffers PB1 to PBm may be referred to as the first map buffer level 123C, and the second map buffer 2nd Map Buffer of each of the page buffers PB1 to PBm may be referred to as the second map buffer level 123D.

[0128] During a programming operation, the primary buffer stage 123A may adjust the Figure 2 During a read operation, the main buffer stage 123A may sense the potentials or current amounts of the bit lines BL1 to BLm and store the sensed data.

[0129] During a programming operation, cache buffer stage 123B may receive data from outside of memory device 100 (eg, Figure 1 Cache buffer level 123B receives data to be programmed from main buffer level 123A and transmits the data to the outside of memory device 100 (e.g., Figure 1 storage controller 200).

[0130] During the map data loading operation, the first map buffer stage 123C stores second map data among the map data stored in the system block.

[0131] During a map data search operation, the second map buffer stage 123D stores data from outside the memory device 100 (eg, Figure 1 The logical block address (LBA) received by the storage controller 200).

[0132] During the map data search operation, each of the page buffers PB1 to PBm may search whether map data corresponding to the LBA stored in the second map buffer stage 123D is stored in the first map buffer stage 123C.

[0133] Figure 8 is a diagram illustrating a loading operation of map data according to an embodiment of the present disclosure.

[0134] Reference Figure 8During a load operation of mapping data, mapping data stored in a system block of a memory device may be read and stored in a mapping cache buffer 222 of a memory controller and a page buffer group 123 of the memory device.

[0135] For example, the first mapping data G1 among the mapping data stored in the system block SystemBlock of the memory device may be read by the page buffer group 123 of the memory device, and the read first mapping data G1 may be sent to the mapping cache buffer 222 of the memory controller and stored. The second mapping data G2 among the mapping data stored in the system block System Block may be read by the page buffer group 123 and may be stored.

[0136] For example, the first mapping data G1 may be cold data with a relatively low number of accesses among the mapping data stored in the system block System Block, and the second mapping data G2 may be hot data with a relatively high number of accesses among the mapping data stored in the system block System Block.

[0137] In another embodiment, the first mapping data G1 may be mapping data stored in the system block System Block that is first read through the storage capacity of the mapping cache buffer 222, and the second mapping data G2 may be mapping data stored in the system block System Block that is read through the mapping data storage capacity of the page buffer group 123 after reading the first mapping data G1.

[0138] Fig. 9 is a flowchart illustrating a mapping data search operation according to an embodiment of the present disclosure.

[0139] Fig.10 is a diagram illustrating movement of map data during a map data search operation according to an embodiment of the present disclosure.

[0140] Fig.11 is a diagram illustrating signals transmitted between a storage controller and a memory device during a map data search operation according to an embodiment of the present disclosure.

[0141] The mapping data search operation according to the embodiment of the present disclosure refers to Figure 1 , Figure 2 and Figures 9 to 11 Described below.

[0142] In step S910, when receiving the command 00h, the system address System ADDR, the logical block address LBA, and the address length information Length of the logical block address from the memory controller 200, the memory device 100 reads the mapping data corresponding to the system address System ADDR among the mapping data stored in the system block of the memory cell array 110, and stores the mapping data in the mapping cache buffer 222 of the memory controller 200 and the first mapping buffer level 123C of the page buffer group 123. For example, the first mapping data among the read mapping data may be stored in the mapping cache buffer, and the second mapping data may be stored in the first mapping buffer level 123C.

[0143] In addition, the logical block address LBA is stored in the second mapping buffer stage 123D according to the received logical block address LBA and the address length information Length of the logical block address.

[0144] In step S920, a command 33h corresponding to a mapping data search operation is received from the storage controller 200, and the control logic 130 of the memory device 100 checks whether mapping data corresponding to the logical block address LBA stored in the second mapping buffer level 123D is stored in the first mapping buffer level 123C in response to the command 33h.

[0145] As a result of the check in step S920, when the mapping data corresponding to the logical block address LBA stored in the second mapping buffer stage 123D is stored in the first mapping buffer stage 123C, the result in step S930 is “yes”, and the control logic 130 of the memory device 100 sets the status register signal SRBUS to “0”. <0> Set to logic high and the status register signal SRBUS <0> Sent to the storage controller 200.

[0146] The memory controller 200 may be based on the logic high status register signal SRBUS <0> It is recognized that the logical block address LBA transmitted to the memory device 100 matches (corresponds to) the second mapping data loaded in the first mapping buffer stage 123C.

[0147] Thereafter, a status check operation may be performed, and a result of the status check operation may be output to the memory controller 200 as status register information SR.

[0148] As a result of the check in the above step S920, when the mapping data corresponding to the logical block address LBA stored in the second mapping buffer stage 123D is not stored in the first mapping buffer stage 123C, "No" is given in step S950, and the control logic 120 of the memory device 130 controls the peripheral circuit 120 to read other mapping data stored in the system block (e.g., BLK1). Therefore, the new second mapping data is loaded into the first mapping buffer stage 123C. Thereafter, the operation is repeated from the above step S920.

[0149] As described above, according to an embodiment of the present disclosure, when a logical block address LBA is received from the memory controller 200 , mapping data corresponding to the received logical block address LBA may be searched among the second mapping data stored in the first mapping buffer stage 123C of the page buffer group 123 .

[0150] When the storage controller 200 receives the logical block address LBA from the host 300, the storage controller 200 may perform a mapping data search operation among the first mapping data stored in the mapping cache buffer 222 of the storage controller 200 according to the received logical block address LBA, or may perform a mapping data search operation among the second mapping data stored in the first mapping buffer level 123C by sending the logical block address LBA to the memory device. For example, when the logical block address LBA received from the host 300 corresponds to cold data, the mapping data search operation may be performed among the first mapping data stored in the mapping cache buffer 222 of the storage controller 200, and when the logical block address LBA received from the host 300 corresponds to hot data, the mapping data search operation may be performed among the second mapping data stored in the first mapping buffer level 123C.

[0151] Fig.12 is a diagram illustrating movement of data during an update operation of data according to an embodiment of the present disclosure.

[0152] Fig.13 is a diagram illustrating signals transmitted between a memory controller and a memory device during a program operation of data according to an embodiment of the present disclosure.

[0153] The operation of data programming according to the embodiment of the present disclosure refers to Figure 1 , Figure 2 , Fig.12 and Fig.13 Described below.

[0154] As the above basis Fig. 9As a result of the mapping data search operation, when a logic high status register signal SRBUS is received from the memory device 100 <0> When the program is executed, the memory controller 200 sends a command 80h corresponding to the program operation, a logical block address LBA, address length information Length of the logical block address, and normal data DATA to be programmed to the memory device 100.

[0155] The page buffer group 123 of the memory device 100 receives and stores the input normal data. For example, the cache buffer level 123B of the page buffer group 123 receives and temporarily stores the normal data, and sends the temporarily stored normal data to the main buffer level 123A. At this time, among the mapping data stored in the first mapping buffer level 123C, the mapping data matching the logical block address LBA can be retained.

[0156] In response to the specific command 77 h , the memory device 100 performs a refresh operation of the normal data stored in the main buffer stage 123A, that is, a program operation of storing the normal data stored in the main buffer stage 123A in a selected area of ​​the memory cell array 110 .

[0157] The programming operation may be performed in an SLC programming method. That is, normal data is programmed in a static SLC region or a dynamic SLC region of a storage space of the memory cell array 110 in an SLC programming method. Therefore, during the programming operation, each of the page buffers PB1 to PBm of the page buffer group 123 may perform a programming operation using only one buffer (i.e., a main buffer).

[0158] Thereafter, a status check operation according to a result of the program operation may be performed, and a result of the status check operation may be output to the memory controller 200 as status register information SR.

[0159] According to the above-described embodiment of the present disclosure, when the logical block address LBA received from the host 300 does not match the mapping data stored in the mapping cache buffer 222 of the storage controller 200 and the first mapping buffer level 123C of the page buffer group, new mapping data is read and stored in the first mapping buffer level 123C of the page buffer group. In this case, the operation of loading the new mapping data to the storage controller 200 may be skipped after the new mapping data is stored in the page buffer group, thereby improving the operation speed of the storage device 50.

[0160] Fig.14 is a diagram illustrating movement of map data during a refresh operation of the map data according to an embodiment of the present disclosure.

[0161] Fig.15is a diagram illustrating signals transmitted between a memory controller and a memory device during a refresh operation of map data according to an embodiment of the present disclosure.

[0162] The refresh operation of the mapping data according to the embodiment of the present disclosure will refer to Figure 1 , Figure 2 , Fig.14 and Fig.15 Described below.

[0163] When the above Fig.12 and Fig.13 When the update operation of the data is repeatedly performed, the matched mapping data may be accumulated in the page buffer group 123 of the memory device 100.

[0164] For example, a command 80h corresponding to a program operation, a logical block address LBA, and address length information Length of the logical block address may be continuously transmitted to the memory device 100, and thus the memory device 100 may repeatedly perform a program operation of normal data a plurality of times.

[0165] In this case, the matching map data is accumulated in the first map buffer stage 123C of the page buffer group 123 .

[0166] When the matched map data is accumulated in the first map buffer stage 123C, the memory device 100 performs a refresh operation of the map data stored in the first map buffer stage 123C in response to the specific command 78h.

[0167] For example, the mapping data stored in the first mapping buffer stage 123C is temporarily transmitted to the main buffer stage 123A and temporarily stored. The peripheral circuit 120 of the memory device 100 performs a refresh operation of the mapping data stored in the main buffer stage 123A, that is, a program operation of storing the mapping data in a selected area of ​​the memory cell array 110. At this time, the selected area may be a storage area other than the system block BLK1.

[0168] The programming operation may be performed in an SLC programming method. That is, the mapping data is programmed in a static SLC region or a dynamic SLC region of a storage space of the memory cell array 110 in an SLC programming method. Therefore, during the programming operation, each of the page buffers PB1 to PBm of the page buffer group 123 may perform the programming operation using only one buffer (i.e., the main buffer).

[0169] Thereafter, a status check operation according to a result of the program operation may be performed, and a result of the status check operation may be output to the memory controller 200 as status register information SR.

[0170] According to the above embodiment of the present disclosure, during the refresh operation of the mapping data, the mapping data stored in the page buffer group 123 is programmed in the selected storage area of ​​the memory cell array 110. Therefore, the operation of receiving the mapping data from the memory controller 200 does not occur, and thus the operation speed of the memory device 50 can be improved.

[0171] Fig.16 It is shown Figure 1 FIG. 1 is a diagram of another embodiment of a storage controller.

[0172] Reference Fig.16 , the storage controller 1000 is connected to the host Host and the memory device. The storage controller 1000 is configured to access the memory device in response to a request from the host Host. For example, the storage controller 1000 is configured to control the write operation, read operation, erase operation and background operation of the memory device. The storage controller 1000 is configured to provide an interface between the memory device and the host Host. The storage controller 1000 is configured to drive firmware for controlling the memory device.

[0173] The memory controller 1000 may include a processor 1010 , a memory buffer 1020 , an error correction component (ECC) 1030 , a host interface 1040 , a buffer controller 1050 , a memory interface 1060 , and a bus 1070 .

[0174] The bus 1070 may be configured to provide a channel between components of the memory controller 1000 .

[0175] The processor 1010 may control the overall operation of the memory controller 1000 and may perform logic operations. The processor 1010 may communicate with an external host through a host interface 1040 and communicate with a memory device through a memory interface 1060. In addition, the processor 1010 may communicate with a memory buffer 1020 through a buffer controller 1050. The processor 1010 may control the operation of the memory device using the memory buffer 1020 as an operating memory, a cache memory, or a buffer memory.

[0176] The processor 1010 may perform the function of a flash translation layer (FTL). The processor 1010 may convert a logical block address (LBA) provided by the host into a physical block address (PBA) through the FTL. The FTL may receive the LBA using mapping data and convert the LBA into a PBA. The FTL may perform an address conversion operation using the mapping data stored in the memory buffer 1020.

[0177] The processor 1010 is configured to randomize data received from the host Host. For example, the processor 1010 may randomize data received from the host Host using a randomization seed. The randomized data is provided to the memory device as data to be stored and is programmed into the memory cell array.

[0178] The processor 1010 is configured to derandomize data received from the memory device during a read operation. For example, the processor 1010 may derandomize data received from the memory device using a derandomization seed. The derandomized data may be output to the host Host.

[0179] As an implementation, the processor 1010 may perform randomization and de-randomization by driving software or firmware.

[0180] The memory buffer 1020 may be used as an operation memory, a cache memory, or a buffer memory of the processor 1010. The memory buffer 1020 may store codes and commands executed by the processor 1010. The memory buffer 1020 may store mapping data. The memory buffer 1020 may store data processed by the processor 1010. The memory buffer 1020 may include a static RAM (SRAM) or a dynamic RAM (DRAM).

[0181] The ECC 1030 may perform error correction. The ECC 1030 may perform error correction coding (ECC coding) based on data to be written to the memory device through the memory interface 1060. The error correction coded data may be transmitted to the memory device through the memory interface 1060. The ECC 1030 may perform error correction decoding (ECC decoding) on ​​data received from the memory device through the memory interface 1060. For example, the ECC 1030 may be included in the memory interface 1060 as a component of the memory interface 1060.

[0182] The host interface 1040 is configured to communicate with an external host under the control of the processor 1010. The host interface 1040 may be configured to perform communication using at least one of various communication methods such as a universal serial bus (USB), a serial AT attachment (SATA), a serial attached SCSI (SAS), a high-speed inter-chip (HSIC), a small computer system interface (SCSI), a peripheral component interconnect (PCI Express), a non-volatile memory Express (NVMe), a universal flash memory (UFS), a secure digital (SD), a multimedia card (MMC), an embedded MMC (eMMC), a dual in-line memory module (DIMM), a registered DIMM (RDIMM), and a load reduction DIMM (LRDIMM).

[0183] The buffer controller 1050 is configured to control the memory buffer 1020 under the control of the processor 1010 .

[0184] The memory interface 1060 is configured to communicate with the memory device under the control of the processor 1010. The memory interface 1060 may communicate commands, addresses, and data with the memory device through a channel.

[0185] For example, the memory controller 1000 may not include the memory buffer 1020 and the buffer controller 1050 .

[0186] For example, the processor 1010 may use the code to control the operation of the storage controller 1000. The processor 1010 may load the code from a nonvolatile memory device (eg, a read-only memory) provided inside the storage controller 1000. As another example, the processor 1010 may load the code from the memory device through the memory interface 1060.

[0187] For example, the bus 1070 of the memory controller 1000 may be divided into a control bus and a data bus. The data bus may be configured to send data within the memory controller 1000, and the control bus may be configured to send control information such as commands and addresses within the memory controller 1000. The data bus and the control bus may be separated from each other and may not interfere with or affect each other. The data bus may be connected to the host interface 1040, the buffer controller 1050, the ECC 1030, and the memory interface 1060. The control bus may be connected to the host interface 1040, the processor 1010, the buffer controller 1050, the memory buffer 1202, and the memory interface 1060.

[0188] Fig.17 is a block diagram illustrating a memory card system to which a storage device according to an embodiment of the present disclosure is applied.

[0189] Reference Fig.17 , the memory card system 2000 includes a memory controller 2100 , a memory device 2200 , and a connector 2300 .

[0190] The storage controller 2100 is connected to the memory device 2200. The storage controller 2100 is configured to access the memory device 2200. For example, the storage controller 2100 may be configured to control the read operation, write operation, erase operation, and background operation of the memory device 2200. The storage controller 2100 is configured to provide an interface between the memory device 2200 and the host. The storage controller 2100 is configured to drive firmware for controlling the memory device 2200. The storage controller 2100 may be connected to the memory device 2200 with reference to Figure 1 The described storage controller 200 is implemented identically.

[0191] For example, the memory controller 2100 may include components such as a random access memory (RAM), a processor, a host interface, a memory interface, and an ECC.

[0192] The storage controller 2100 can communicate with an external device through the connector 2300. The storage controller 2100 can communicate with an external device (e.g., a host) according to a specific communication standard. For example, the storage controller 2100 is configured to communicate with an external device through at least one of various communication standards such as Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (MCM), Peripheral Component Interconnect (PCI), High Speed ​​PCI (PCI-E), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, Universal Flash Memory (UFS), Wi-Fi, Bluetooth, and NVMe. For example, the connector 2300 may be defined by at least one of the various communication standards mentioned above.

[0193] For example, the memory device 2200 may be configured by various nonvolatile memory elements such as electrically erasable programmable ROM (EEPROM), NAND flash memory, NOR flash memory, phase change RAM (PRAM), resistive RAM (ReRAM), ferroelectric RAM (FRAM), and spin-torque magnetic RAM (STT-MRAM).

[0194] The storage controller 2100 and the memory device 2200 may be integrated into one semiconductor device to configure a memory card. For example, the storage controller 2100 and the memory device 2200 may be integrated into one semiconductor device to configure a memory card such as a PC card (Personal Computer Memory Card International Association (PCMCIA)), a Compact Flash card (CF), a Smart Media Card (SM or SMC), a Memory Stick, a Multimedia Card (MMC, RS-MMC, MMCmicro or eMMC), an SD card (SD, miniSD, microSD or SDHC), and a Universal Flash Storage (UFS).

[0195] Fig.18 is a block diagram illustrating a solid state drive (SSD) system to which a storage device according to an embodiment of the present disclosure is applied.

[0196] Reference Fig.18, the SSD system 3000 includes a host 3100 and an SSD 3200. The SSD 3200 exchanges a signal SIG with the host 3100 through a signal connector 3001, and receives power PWR through a power connector 3002. The SSD 3200 includes an SSD controller 3210, a plurality of flash memories 3221 to 322n, an auxiliary power supply device 3230, and a buffer memory 3240.

[0197] According to an embodiment of the present disclosure, the SSD controller 3210 may execute reference Figure 1 The functions of the storage controller 200 are described.

[0198] The SSD controller 3210 may control the plurality of flash memories 3221 to 322n in response to a signal SIG received from the host 3100. For example, the signal SIG may be a signal based on an interface between the host 3100 and the SSD 3200. For example, the signal SIG may be a signal defined by at least one of interfaces such as a universal serial bus (USB), a multimedia card (MMC), an embedded MMC (MCM), a peripheral component interconnect (PCI), PCI-Express (PCI-E), an advanced technology attachment (ATA), a serial ATA, a parallel ATA, a small computer system interface (SCSI), an enhanced small disk interface (ESDI), an integrated drive electronics (IDE), FireWire, a universal flash memory (UFS), Wi-Fi, Bluetooth, and NVMe.

[0199] The auxiliary power supply device 3230 is connected to the host 3100 through the power connector 3002. The auxiliary power supply device 3230 may receive power PWR from the host 3100 and may be charged with the power. When the power supply from the host 3100 is not stable, the auxiliary power supply device 3230 may provide power to the SSD 3200. For example, the auxiliary power supply device 3230 may be provided in the SSD 3200 or may be provided outside the SSD 3200. For example, the auxiliary power supply device 3230 may be provided on the mainboard and may provide auxiliary power to the SSD 3200.

[0200] The buffer memory 3240 operates as a buffer memory of the SSD 3200. For example, the buffer memory 3240 may temporarily store data received from the host 3100 or data received from the plurality of flash memories 3221 to 322n, or may temporarily store metadata (e.g., a mapping table) of the flash memories 3221 to 322n. The buffer memory 3240 may include a volatile memory such as DRAM, SDRAM, DDR SDRAM, LPDDR SDRAM, and GRAM, or a nonvolatile memory such as FRAM, ReRAM, STT-MRAM, and PRAM.

[0201] Fig.19 is a block diagram illustrating a user system to which a storage device according to an embodiment of the present disclosure is applied.

[0202] Reference Fig.19 , the user system 4000 includes an application processor 4100 , a memory module 4200 , a network module 4300 , a storage module 4400 , and a user interface 4500 .

[0203] The application processor 4100 may drive components included in the user system 4000, an operating system (OS), a user program, etc. For example, the application processor 4100 may include a controller, an interface, a graphic engine, etc. that controls components included in the user system 4000. The application processor 4100 may be provided as a system chip (SoC).

[0204] The memory module 4200 may operate as a main memory, an operating memory, a buffer memory, or a cache memory of the user system 4000. The memory module 4200 may include a volatile random access memory such as DRAM, SDRAM, DDR SDRAM, DDR2 SDRAM, DDR3 SDRAM, LPDDR SDRAM, LPDDR2 SDRAM, and LPDDR3 SDRAM, or a nonvolatile random access memory such as PRAM, ReRAM, MRAM, and FRAM. For example, the application processor 4100 and the memory module 4200 may be packaged based on a package on package (POP) and provided as one semiconductor package.

[0205] The network module 4300 may communicate with an external device. For example, the network module 4300 may support wireless communications such as code division multiple access (CDMA), global system for mobile communications (GSM), wideband CDMA (WCDMA), CDMA-2000, time division multiple access (TDMA), long term evolution, Wimax, WLAN, UWB, Bluetooth, and Wi-Fi. For example, the network module 4300 may be included in the application processor 4100.

[0206] The storage module 4400 may store data. For example, the storage module 4400 may store data received from the application processor 4100. Alternatively, the storage module 4400 may send data stored in the storage module 4400 to the application processor 4100. For example, the storage module 4400 may be implemented as a non-volatile semiconductor memory element such as a phase change RAM (PRAM), a magnetic RAM (MRAM), a resistive RAM (RRAM), a NAND flash memory, a NOR flash memory, and a three-dimensional NAND flash memory. For example, the storage module 4400 may be provided as a removable storage device (removable drive) such as a memory card and an external drive of the user system 4000.

[0207] For example, the storage module 4400 may include a plurality of nonvolatile memory devices, and the plurality of nonvolatile memory devices may be associated with the reference Figure 1 The memory module 4400 may be similar to the memory device 100 described in the prior art. Figure 1 The described storage device 50 operates identically.

[0208] The user interface 4500 may include an interface for inputting data or instructions to the application processor 4100 or for outputting data to an external device. For example, the user interface 4500 may include a user input interface such as a keyboard, a keypad, a button, a touch panel, a touch screen, a touch pad, a touch ball, a camera, a microphone, a gyro sensor, a vibration sensor, and a piezoelectric element. The user interface 4500 may include a user output interface such as a liquid crystal display (LCD), an organic light emitting diode (OLED) display device, an active matrix OLED (AMOLED) display device, an LED, a speaker, and a monitor.

[0209] Although the detailed description of the present disclosure describes specific embodiments, various modifications may be made without departing from the scope and technical spirit of the present disclosure. Therefore, the scope of the present disclosure should not be limited to the above embodiments, but should be determined by the equivalents of the claims of the present disclosure and the following claims.

[0210] CROSS-REFERENCE TO RELATED APPLICATIONS

[0211] This application claims the priority of Korean Patent Application No. 10-2020-0068098 filed on June 5, 2020, in the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference.

Claims

1. A storage device, comprising: a memory device including a memory cell array storing normal data and mapping data; as well as a memory controller configured to control overall operations of the memory device including programming operations, reading operations, and erasing operations in response to a request from a host, wherein the memory device is configured to send the first mapping data to the memory controller by reading first mapping data among the mapping data stored in the memory cell array during a mapping data loading operation, and to send the second mapping data to the page buffer group of the memory device by reading second mapping data among the mapping data having a higher access number than the first mapping data, and The page buffer group includes: a first mapping buffer level, which stores the second mapping data by reading the second mapping data among the mapping data stored in the memory cell array; and a second mapping buffer level, which stores the logical block address received from the storage controller.

2. The storage device according to claim 1, wherein: The memory controller includes a memory buffer, wherein the memory buffer is configured to store the first map data received from the memory device during the map data loading operation.

3. The storage device according to claim 1, wherein: The first mapped data is cold data having a relatively low number of accesses among the mapped data, and the second mapped data is hot data having a relatively high number of accesses among the mapped data.

4. The storage device according to claim 1, wherein: The page buffer group further includes: a primary buffer stage configured to at least one of: sense data stored in the memory cell array; and temporarily store data to be programmed in the memory cell array; and A cache buffer stage is configured to at least one of: output data stored in the primary buffer stage to the memory controller; and send data to be programmed received from the memory controller to the primary buffer stage.

5. The storage device according to claim 4, wherein: The storage controller is configured to receive the logical block address together with a request from the host, and when the received logical block address corresponds to the second mapping data, send the logical block address to the memory device.

6. The storage device according to claim 5, wherein: The page buffer group is configured to perform a map data search operation of searching whether search map data corresponding to the logical block address received from the memory controller and stored in the second map buffer stage is included in the second map data stored in the first map buffer stage.

7. The storage device according to claim 6, wherein: The memory device is configured to send a status register signal of a specific logic level to the memory controller when the search map data is determined to be included in the second map data during the map data search operation, and The memory controller is configured to recognize, based on the status register signal, that the logical block address matches the second map data stored in the first map buffer stage.

8. The storage device according to claim 7, wherein: The memory device is configured to store, in the memory cell array, mapping data matching the logical block address among the second mapping data stored in the first mapping buffer stage.

9. The storage device according to claim 6, wherein: The memory device is configured to, when it is determined during the mapping data search operation that the search mapping data is not included in the second mapping data, store the new second mapping data in the first mapping buffer level by reading the new second mapping data from among the mapping data stored in the memory cell array, and perform the mapping data search operation again.

10. The storage device according to claim 1, wherein: The memory cell array includes a single-level cell region and a triple-level cell region, and The single level cell region is programmed using a single level cell programming method, and the triple level cell region is programmed using a triple level cell programming method.

11. The storage device according to claim 10, wherein: The memory device is configured to program the normal data or the mapping data in the single level cell region during a programming operation of the normal data or the mapping data, and During a background operation, the normal data or the mapping data stored in the single level cell region is read, and the read normal data or mapping data is programmed in the triple level cell region.

12. A method for operating a storage device, the method comprising the steps of: reading first mapping data and second mapping data having a higher access count than the first mapping data among mapping data stored in a system block of a memory cell array; sending the first mapping data to a storage controller and storing the first mapping data in a memory buffer of the storage controller; storing the second map data in a first map buffer stage included in a page buffer group of a memory device; receiving a logical block address from the memory controller to the page buffer group, and storing the logical block address in a second mapping buffer level included in the page buffer group; as well as A mapping data search operation of searching whether mapping data corresponding to the received logical block address is included in the second mapping data is performed.

13. The method according to claim 12, further comprising the steps of: when the search mapping data is determined to be included in the second mapping data as a result of the mapping data search operation, transmitting a specific signal to the storage controller; as well as When it is determined as a result of the map data search operation that the search map data is not included in the second map data, new second map data among the map data stored in the system block is read and stored in the page buffer group.

14. The method according to claim 13, further comprising the steps of: during a normal data programming operation, sending the logical block address and the normal data to be programmed from the storage controller to the memory device; programming the normal data into the memory cell array; as well as A mapping data refresh operation of storing mapping data corresponding to the logical block address among the second mapping data in the memory cell array is performed.

15. The method according to claim 14, wherein: The memory cell array includes a single-level cell region and a triple-level cell region, and The single level cell region is programmed in a single level cell programming method, and the triple level cell region is programmed in a triple level cell programming method.

16. The method according to claim 15, wherein: The mapping data or the normal data corresponding to the logical block address is programmed in the single level cell region of the memory cell array.

17. The method according to claim 12, wherein: The first mapped data is cold data having a relatively low number of accesses among the mapped data, and the second mapped data is hot data having a relatively high number of accesses among the mapped data.

18. A method for operating a storage device, the method comprising the steps of: During a map data loading operation, storing first map data among the map data stored in the system block in a memory controller, and storing second map data among the map data having a higher access number than the first map data in a first map buffer stage included in a page buffer group of a memory device; During a mapping data search operation, receiving, by the memory device, a logical block address from the memory controller, storing the logical block address in a second mapping buffer stage included in the page buffer group, and searching whether search mapping data corresponding to the received logical block address is included in the second mapping data; During a data programming operation, the memory device receives normal data and the logical block address from the memory controller, stores the normal data in a memory cell array, and then leaves mapping data corresponding to the logical block address among the second mapping data in the page buffer group; as well as During a mapping data refresh operation, the mapping data remaining in the page buffer group is stored in the memory cell array.

19. The method according to claim 18, wherein: The first mapped data is cold data having a relatively low number of accesses among the mapped data, and the second mapped data is hot data having a relatively high number of accesses among the mapped data.

20. The method according to claim 18, wherein: The memory cell array includes a single-level cell region and a triple-level cell region, The single-level cell region is programmed using a single-level cell programming method, the triple-level cell region is programmed using a triple-level cell programming method, and The normal data or the mapping data remaining in the page buffer group is programmed in the single level cell region of a memory cell array.

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