Memory device and memory cell

Abstract

A memory device includes a memory array including a plurality of memory cells. Each memory cell includes a first word line, a second word line, and a bit line. A first signal is applied to the first word line to select each memory cell to read data from or write data to each memory cell. A second signal is applied to the second word line to select each memory cell to read data from or write data to each memory cell. The bit line reads data from or provides data to be written to each memory cell when at least one of the first word line or the second word line selects each memory cell.

Description

Technical Field

[0001] The present disclosure relates to memory devices, and more particularly to optimized static random access memory cells. Background Art

[0002] Memory devices are used in a variety of applications. A memory device is composed of a plurality of memory cells, which are typically arranged in an array of multiple columns and multiple rows. One type of memory cell is a static random access memory (SRAM) cell. In some applications, a memory device based on SRAM cells may be more preferred than other types of memory devices based on memory cells because the SRAM-based memory device has a faster rate and less power consumption. As applications require more and more memory, the number of SRAM cells in a memory device continues to increase. In addition, with the increasing demand for product diversification, the cooperation between circuit design and semiconductor manufacturing of SRAM cells becomes more and more important. However, the current configuration and operation of SRAM memory cells limit the SRAM memory cells. Summary of the Invention

[0003] Embodiments of the present disclosure relate to a memory device including a memory array including a plurality of memory cells, each memory cell including a first word line, a second word line, and a bit line. The first word line applies a first signal to select each memory cell to read data from or write data to each memory cell. The second word line applies a second signal to select each memory cell to read data from or write data to each memory cell. The bit line reads data from or provides data to be written to each memory cell when at least one of the first word line or the second word line selects each memory cell.

[0004] Embodiments of the present disclosure relate to a memory cell including a first word line, a second word line, and a bit line. The memory cell includes a first word line extending in a first direction and having a first width in a second direction perpendicular to the first direction, a second word line extending in the first direction and having a second width in the second direction, and a bit line extending in the second direction and having a third width in the first direction. At least one of the first word line or the second word line applies a signal to select the memory cell to read data from or write data to the memory cell. The third width is greater than the first width and the second width.

[0005] Embodiments of the present disclosure relate to a memory cell, comprising a substrate, a first interconnect layer, a second interconnect layer, a third interconnect layer, and a fourth interconnect layer. The memory cell includes a substrate having a front side and a back side, wherein transistors of the memory cell are formed on the front side, and wherein the back side is the opposite side of the front side. The memory cell also includes a first interconnect layer on the front side to provide bit lines of the memory cell, a second interconnect layer on the front side to provide word lines of the memory cell, a third interconnect layer on the back side to provide supply voltage to the memory cell, and a fourth interconnect layer on the back side to provide ground voltage to the memory cell. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Aspects of the present disclosure are best understood when read in conjunction with the accompanying drawings in the following embodiments. It should be emphasized that, in accordance with industry standard practices, many features are not drawn to scale. In fact, for the sake of discussion clarity, the dimensions of many features may be arbitrarily increased or reduced. Figure 1

[0007] Figure 1 FIG. is a schematic block diagram of a memory device having a SRAM array according to some embodiments.

[0008] Figure 2 According to some embodiments Figure 1 FIG. is a schematic circuit diagram of a SRAM cell of a SRAM array according to some embodiments.

[0009] Figure 3 And Figure 4 FIG. is a schematic block diagram of a portion of a SRAM array showing additional details of a SRAM cell according to some embodiments. Figure 2 Figure 1

[0010] Figure 5 And Figure 6 According to some embodiments Figure 1 FIG. is a standard cell layout design of SRAM cells at two adjacent positions of a SRAM array according to some embodiments.

[0011] Figure 7 According to some embodiments, a exemplary computing system for generating Figure 5 And Figure 6 the standard cell layout design.

[0012] DESCRIPTION OF REFERENCE NUMERALS:

[0013] 100: SRAM device

[0014] 105: SRAM array

[0015] 107: SRAM cell

[0016] 110: X direction

[0017] 115: Y direction

[0018] 120: Height

[0019] 130: Column decoder

[0020] 135: Write circuit

[0021] 140: Sense amplifier

[0022] 145, 245A~245O: SRAM cell

[0023] 150, 155: Inverter

[0024] 160, 200, Q, Q’: Output node

[0025] 165: Input node

[0026] 170, 190, P1, P2: p-type pull-up transistor

[0027] 175, 195, N1, N3: n-type pull-down transistor

[0028] 180: Supply voltage

[0029] 185: Ground voltage

[0030] 205, 215, BL, BL’, BLB: Bit line

[0031] 210, N2: First access transistor

[0032] 220, N4: Second access transistor

[0033] 225, 230: Gate terminal

[0034] 235, WL: Word line

[0035] 240: Portion

[0036] 250: First word line

[0037] 260, 275: Width

[0038] 265: First bit line portion

[0039] 270: Second bit line portion

[0040] 280, 285, 290, 295: Interconnection structure

[0041] 300, 305: Layout design

[0042] 310, 315, 320, 325, 365: Active region

[0043] 330, 335, 340, 345, 350, 355, 360, 370: Gate structure

[0044] 375, 380, 385, 400, 415, 420, 425, 440, 455, 460, 475, 480, 485: Interconnect layer

[0045] 390, 395, 405, 410, 430, 435, 445, 450, 465, 470, 490, 495, 500, 505, 510, 515: Interconnect structure

[0046] 520: Cross-sectional view

[0047] 525: Semiconductor substrate

[0048] 530: Front side

[0049] 535: Back side

[0050] 540: Interconnection point

[0051] 545: Computing system

[0052] 550: Host device

[0053] 555: Memory device

[0054] 560: Input device

[0055] 565: Output device

[0056] 570A, 570B, 570C: Interface

[0057] 575A~575N: Central processing unit core

[0058] 580: Standard cell layout application

[0059] 585: Memory controller

[0060] 590: Memory array

[0061] 595: Manufacturing tool Detailed implementation

[0062] The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. Specific instances of components and arrangements, etc. are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature above or over a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features may be formed between the first and second features such that the first and second features may not be in direct contact. Additionally, the present disclosure may repeat reference numerals and / or letters in various instances. This repetition is for purposes of simplicity and clarity and does not in itself represent a relationship between the various embodiments and / or configurations discussed.

[0063] Furthermore, spatially relative terms, such as "beneath", "below", "lower", "above", "upper", etc., as depicted in the figures, may be used to more easily describe the relationship between one feature and another. Spatially relative terms are intended to encompass different orientations of the device in addition to the orientation depicted in the figures during steps or use. The device may be oriented in other ways (rotated 90 degrees or in other directions), and the spatially relative descriptive terms used herein may be interpreted accordingly.

[0064] Now referring to Figure 1 , according to some embodiments of the present disclosure, Figure 1 a static random access memory (SRAM) device 100 is shown. The SRAM device 100 includes an SRAM array 105. The SRAM array 105 includes a plurality of SRAM cells 107 arranged in one or more columns extending along an X direction 110 (also referred to herein as a column direction or word line (WL) direction) and one or more rows extending along a Y direction 115 (also referred to herein as a row direction or bit line (BL) direction). The number of columns and rows in the SRAM array 105 depends on the size of the SRAM array. Generally, the larger the size of the SRAM array 105, the more columns and / or rows in the SRAM array. Depending on the number of columns, the SRAM array 105 may have a height 120 in the Y direction 115. Similarly, depending on the number of rows, the SRAM array 105 may have a width 125 in the X direction 110. Each SRAM cell of the SRAM array 105 may also have a height extending in the Y direction 115 and may also have a width extending in the X direction 110.

[0065] The SRAM device 100 may also include a column decoder 130 (word line driver), coupled to the SRAM array 105. Each SRAM cell of the SRAM array 105 may also be connected to a word line extending in the X direction 110, and may also be connected to a bit line extending in the Y direction 115. For example, each SRAM cell in a particular column of the SRAM array 105 may also be connected to the same word line, and each SRAM cell in a particular row of the SRAM array may also be connected to the same bit line. Thus, the SRAM array 105 may be coupled to multiple word lines and multiple bit lines. A "word line" is a conductive wire through which a voltage signal of a suitable voltage level can be applied to a particular SRAM cell, and the particular SRAM cell is connected to the word line to select the SRAM cell as one of reading data from the SRAM cell or writing data to the SRAM cell. A "bit line" is a conductive wire that reads data from the SRAM cell when the word line selects the SRAM cell, or provides data to be written to the SRAM cell when the word line selects the SRAM cell. Thus, the word line is used to select the SRAM cell before data can be read or written to the SRAM cell, and the bit line is used to provide data for reading from or writing to the SRAM cell.

[0066] The column decoder 130 can be utilized to select a particular word line of the SRAM array 105. For example, the column decoder 130 can receive an address input and convert the address input into a suitable word line. In some embodiments, the column decoder 130 may be associated with additional or other types of circuitry or components that facilitate the selection of a word line.

[0067] The SRAM device 100 may also include a write circuit (read / write block) 135 and a sense amplifier 140, which can be used to read data from a particular SRAM cell of the SRAM array 105 or provide data to be written to a particular SRAM cell of the SRAM array 105 through a bit line. In some embodiments, the write circuit 135 and the sense amplifier 140 may be associated with latches and / or other circuitry that allow data to be read from a particular SRAM cell and written to a particular SRAM cell. For example, in some embodiments, the data read from the SRAM array 105 may be sensed by the sense amplifier 140. In some embodiments, the data to be written to the SRAM array 105 may be provided to the write circuit 135 for programming within the SRAM array. The SRAM device 100 may additionally include a control region (not shown), which can be configured to control the operation of the column decoder 130, the write circuit 135, the sense amplifier 140, and any other circuitry of the SRAM device 100. It is to be understood that inFigure 1 Only some components of the SRAM device 100 are shown. Nevertheless, the SRAM device 100 is intended to include other components required or considered desirable for operating the SRAM device and performing the functions described herein.

[0068] Figure 2 One SRAM cell 145 among the plurality of SRAM cells 107 of the SRAM array 105 is described in more detailed detail. In some embodiments, one or more of the plurality of SRAM cells 107 may be a 6-transistor cell or 6T SRAM cell, an example of which is shown in Figure 2 . A 6T SRAM cell (e.g., SRAM cell 145) may include 6 transistors (e.g., metal-oxide-semiconductor (MOS) transistors) configured to store one bit of data. Specifically, the 6T SRAM cell may include two cross-coupled inverters 150 and inverter 155 to form a latch circuit. Through the cross-coupled inverters 150 and inverter 155, an output node 160 (Q) of the inverter 150 may be connected to an input node 165 of the inverter 155 such that when one of the output nodes (e.g., output node 160 or the output node of the inverter 155) is pulled to a low voltage level, the other output node switches to a high voltage level.

[0069] The inverter 150 may include a p-type pull-up transistor 170 (P1) and an n-type pull-down transistor 175 (N1), connected between a supply voltage 180 (e.g., VDD) and a ground voltage 185 (e.g., VSS). The inverter 155 may similarly include a p-type pull-up transistor 190 (P2) and an n-type pull-down transistor 195 (N3), connected between the supply voltage 180 and the ground voltage 185. The output node 160 of the inverter 150 and an output node 200 (Q’) of the inverter 155 serve as storage nodes (e.g., data stored in the SRAM cell 145 is read therefrom, or data written to the SRAM cell is written herein). The output node 160 is coupled to a bit line 205 (BL) through a first access transistor 210 (N2), and the output node 200 is coupled to a bit line 215 (BL’ or referred to as BLB) through a second access transistor 220 (N4). The bit line 205 and the bit line 215 are the same but complementary lines, or in other words, inverse to each other. The respective gate terminals 225 and gate terminal 230 of the first access transistor 210 and the second access transistor 220 are connected to a word line 235 (WL).

[0070] The voltage levels on the word line 235 are used to turn on (ON) or turn off (OFF) the first access transistor 210 and the second access transistor 220 to allow or deny access to the output node 160 and the output node 200. When the first access transistor 210 and the second access transistor 220 are turned on, the SRAM cell 145 is considered to be selected. For example, when the word line 235 is asserted or switched to a high voltage level (e.g., VDD), the first access transistor 210 and the second access transistor 220 are turned on, and the bit lines 205 and 215 are allowed to access the output node 160 and the output node 200. When the first access transistor 210 and the second access transistor 220 are turned on, the data stored in the output node 160 and the output node 200 can be read through the bit lines 205 and 215. Similarly, when the first access transistor 210 and the second access transistor 220 are turned on, data can be written to the output node 160 and the output node 200 through the bit lines 205 and 215. When the word line 235 is de-asserted or switched to a low voltage level (e.g., VSS), the first access transistor 210 and the second access transistor 220 are turned off, and the output node 160 and the output node 200 are disconnected from the bit lines 205 and 215. Therefore, by adjusting the voltage levels on the word line 235, data can be stored or read from the output node 160 and the output node 200.

[0071] Although the SRAM cell 145 is described herein as a 6T SRAM cell, in other embodiments, the SRAM cell 145 may take other configurations. For example, in some embodiments, the SRAM cell 145 and other SRAM cells of the SRAM array 105 may be a 4T SRAM cell, an 8T SRAM cell, a 10T SRAM cell, a 12T SRAM cell, and so on. In other embodiments, the SRAM cell 145 and other SRAM cells of the SRAM array 105 may take any other configuration considered appropriate.

[0072] Now turning to Figure 3, According to some embodiments of the present disclosure, a exemplary block diagram of a portion 240 of the SRAM array 105 is shown in more detailed detail. As described above, the portion 240 of the SRAM array 105 includes the SRAM cell 145 and a plurality of additional SRAM cells 245A to SRAM cell 245O, arranged in an array of a plurality of columns and a plurality of rows. In some embodiments, the SRAM cell 145 can be identified as being located in the 255th column (i.e., the column farthest from the write circuit 135) and the 0th row (i.e., the row closest to the column decoder 130). Thus, the SRAM cell 245A can be identified as being located in the 255th column and the 1st row, the SRAM cell 245B can be identified as being located in the 255th column and the 2nd row, and so on. The SRAM cell 245D can be identified as being located in the 254th column and the 0th row, and so on. Although the portion 240 is shown as including 16 SRAM cells, the number of SRAM cells in the portion 240 and the entire SRAM array 105 may vary to include fewer than 16 SRAM cells or more than 16 SRAM cells. Further, for ease of explanation, the following description is regarding the SRAM cell 145. However, the following description is equally applicable to the SRAM cells 245A to SRAM cell 245O.

[0073] As described above, the SRAM array 105 includes a plurality of columns and a plurality of rows, respectively defining the height 120 and the width 125 of the SRAM array. Based on the current (I) flowing through the bit line and the word line, and based on the metal resistance value (R) provided by the bit line and the word line, each SRAM cell of the SRAM array 105 connected to a bit line and a word line experiences a voltage drop (i.e., current-resistance drop or IR drop). Depending on the number of columns in the SRAM array 105, SRAM cells farther from the write circuit 135 experience a larger IR drop compared to SRAM cells closer to the read / write block. For example, the SRAM cell 145 located in the 255th column may be the farthest from the write circuit 135 in some embodiments, and may experience an IR drop greater than that of the SRAM cell in the 100th column (the SRAM cell in the 100th column is closer to the read / write block) based on the bit line resistance. Similarly, the example of the SRAM cell 145 located in the 0th row may be the closest to the column decoder 130 in some embodiments, and may experience an IR drop less than that of the SRAM cell located in the 100th row (the SRAM cell in the 100th row is farther from the read / write block). In some embodiments, the IR drop provided by the bit line is more significant than the IR drop provided by the word line. For the SRAM cell farthest from the write circuit 135, the longer the bit line, the greater the IR drop.

[0074] This IR voltage drop adversely affects the performance (i.e., speed) of these SRAM cells. To reduce the IR voltage drop associated with long bit lines, particularly for those SRAM cells that are farther from the write circuit 135, such as SRAM cell 145, the present disclosure provides an optimized SRAM cell in which the widths of the bit lines and the word lines are adjusted, and the layout design of the SRAM cell is adjusted. Since wider lines have a smaller IR voltage drop compared to thinner lines, the present disclosure provides thinner word lines and wider bit lines to reduce the metal resistance value of the long bit lines. This configuration of wider bit lines and thinner word lines may be particularly beneficial for reducing the IR voltage drop for those SRAM cells that are farthest from the write circuit 135, such as SRAM cell 145. Thus, in some embodiments, only those SRAM cells in some designated columns that are farthest from the write circuit 135 may be optimized in the manner described herein. In other embodiments, all SRAM cells, regardless of their distance from the write circuit 135, may be optimized in the manner described herein. As described below, even those SRAM cells that are closest to the write circuit 135 (i.e., column 0) may have improved performance when optimized in the manner described herein.

[0075] To optimize SRAM cell 145, the SRAM cell includes two thin word lines and one wider bit line. As Figure 3 shown in the example, SRAM cell 145 includes a first word line 250 and a second word line 255, each extending along the X direction 110, spaced apart from each other, and each having a thickness or width 260 in the Y direction 115. The first word line 250 and the second word line 255 may be shared by all SRAM cells of the SRAM array 105 that are in the same column as SRAM cell 145 (i.e., column 255). Further, in some embodiments, the width 260 of the first word line 250 may be the same as or substantially similar to the width of the second word line 255. In other embodiments, the width 260 of the first word line 250 may be greater than or less than the width of the second word line 255. Also, in some embodiments, the width 260 of the first word line 250 and / or the width 260 of the second word line 255 may be the same as or substantially similar to the widths of other word lines in other columns outside the column in which SRAM cell 145 is located (i.e., column 255). In other embodiments, the width 260 of the first word line 250 and / or the width 260 of the second word line 255 may be different from the widths of other word lines in other columns outside the column in which SRAM cell 145 is located (i.e., column 255).

[0076] The first word line 250 and the second word line 255 may correspond to Figure 2character line 235. Accordingly, the first character line 250 and the second character line 255 can be connected to the first access transistor 210 and the second access transistor 220. However, as described below, in each SRAM cell, one of the first character line 250 or the second character line 255 is connected to the first access transistor 210 and the second access transistor 220. By asserting the bit line (either the first character line 250 or the second character line 255) connected to the first access transistor 210 and the second access transistor 220, this SRAM cell can be turned ON.

[0077] The SRAM cell 145 may also include a bit line corresponding to the bit line 205 and the bit line 215. The bit line includes a first bit line portion 265 and a second bit line portion 270, each extending along the Y direction 115, spaced apart from each other, and each having a width 275 in the X direction 110. The first bit line portion 265 and a second bit line portion 270 can be shared by all SRAM cells of the SRAM array 105 located in the same row as the SRAM cell 145 (i.e., row 0). Further, in some embodiments, the width 275 of the first bit line portion 265 can be the same as or substantially similar to the width of the second bit line portion 270. In other embodiments, the width 275 of the first bit line portion 265 can be greater than or less than the width of the second bit line portion 270. And, in some embodiments, the width 275 of the first bit line portion 265 and / or the width 275 of the second bit line portion 270 can be the same as or substantially similar to the width of other character lines in other rows outside the row in which the SRAM cell 145 is located (i.e., row 0). In other embodiments, the width 275 of the first bit line portion 265 and / or the width 275 of the second bit line portion 270 can be different from the width of other character lines in other rows outside the row in which the SRAM cell 145 is located (i.e., row 0).

[0078] In some embodiments, the first bit line portion 265 can correspond to the bit line 205 and the second bit line portion 270 can correspond to the bit line 215. In other embodiments, the first bit line portion 265 can correspond to the bit line 215 and the second bit line portion 270 can correspond to the bit line 205. When the SRAM cell 145 is turned on using an appropriate one of the first character line 250 or the second character line 255, the first bit line portion 265 and the second bit line portion 270 can be used to read data from or write data to the SRAM cell.

[0079] Thus, in some embodiments, the SRAM cell 145 includes a first word line 250 extending along the X direction 110 and having a width 260 in the Y direction 115, and a second word line 255. In some embodiments, the SRAM cell 145 also includes a first bit line portion 265 extending along the Y direction 115 and having a width 275 in the X direction 110, and a second bit line portion 270. Further, in some embodiments, the width 260 of the first word line 250 and / or the width of the second word line 255 may be less than the width 275 of the first bit line portion 265 and / or the second bit line portion 270. For example, in some embodiments, the width 275 of the first bit line portion 265 may be greater than the width 260 of each of the first word line 250 and the second word line 255. Similarly, in some embodiments, the width 275 of the second bit line portion 270 may be greater than the width 260 of each of the first word line 250 and the second word line 255. For example, in some embodiments, the width 260 of the first word line 250 and / or the second word line 255 may be a function of a unit height (see Figure 5 ):

[0080] (0.2 - 0.4)*(unit height) = approximately 10 nanometers to 50 nanometers

[0081] In some embodiments, the width 275 of the first bit line portion 265 and / or the second bit line portion 270 may be a function of a unit height (see Figure 5 ):

[0082] (0.4 - 0.6)*(unit height) = approximately 80 nanometers to 180 nanometers

[0083] Thus, the first bit line portion 265 and / or the second bit line portion 270 are wider than the first word line 250 and / or the second word line 255. By providing a wider bit line (i.e., the first bit line portion 265 and the second bit line portion 270), and since the wider bit line has a smaller IR voltage drop, the IR voltage drop of the SRAM cell based on a long bit line can be reduced. A bit line comparison between a 4 by 4 conventional SRAM array and a 4 by 4 SRAM array of the present disclosure can result in a 4-bit bit line loading, as compared to an 8-bit bit line loading of the conventional design. A bit line metal length (i.e., the length of the metal interconnect layer) can be 4Y as compared to 2X of the conventional design (where X:Y = 2.5:1, as Figure 3As shown). For an identical bit line load of 4 bits, the present disclosure provides a bit line metal length of 4Y as compared to X of a conventional design, thereby reducing the capacitance value and the resistance value (and thus the IR drop) by approximately 37%. A comparison of the word line loads of a conventional 4-by-4 SRAM array and a 4-by-4 array of the present disclosure can result in a word line load of 4 bits as compared to a word line load of 2 bits of a conventional design. A word line metal length (i.e., the length of the metal interconnect layer) can be 4X as compared to 8Y of a conventional design (X:Y = 2.5:1). For an identical word line load (i.e., 4 bits), the present disclosure provides a word line metal length of 4X as compared to 16Y, thereby increasing the resistance value by approximately 60%.

[0084] In some embodiments, the SRAM cell 145 can be configured to include a first word line 250 and a second word line 255, as described above, and a first bit line portion 265 and a second bit line portion 270, as described above. In other embodiments, the SRAM cells in the SRAM array 105 can be configured to include either the first word line 250 or the second word line 255, as described above, or the first bit line portion 265 and the second bit line portion 270, as described above. For example, in some embodiments, the SRAM cell 145 can have a conventional word line, and the bit lines can be configured as described herein to have a first bit line portion 265 and a second bit line portion 270. In other embodiments, the SRAM cell 145 can have conventional bit lines, and the word lines can be configured as described herein to have a first word line 250 and a second word line 255. This embodiment can be particularly advantageous for SRAM cells that are farther from the column decoder 130 but closer to the write circuit 135. In some embodiments, all of the SRAM cells of the SRAM array 105 can be configured similarly, and in other embodiments, different SRAM cells can be configured differently from the configurations described above.

[0085] Furthermore, in some embodiments, each of the first bit line portion 265 and the second bit line portion 270 can be configured such that each bit line portion is shared (i.e., adjacent to, facing, connected to) with a bit line portion of an adjacent SRAM cell in the same column. For example, in some embodiments, the first bit line portion 265 of the SRAM cell 145 is shared with the second bit line portion 270 of an adjacent SRAM cell (i.e., SRAM cell 245A), and the first bit line portion of the SRAM cell 245A can be shared with the second bit line portion of the SRAM cell 245B. Figure 4An example of the display portion 240 is shown, where the character lines of the portion 240 are removed for simplicity, and only the adjacent bit line portions shared by the first bit line portion 265 and the second bit line portion 270 of the SRAM cell are shown. By sharing the bit line portion of one SRAM cell (i.e., the first bit line portion 265) with the bit line portion of an adjacent SRAM cell in the same column (i.e., the second bit line portion 270), the bit line can be made wider, and based on the long bit line, the IR voltage drop of the SRAM cell can be further reduced.

[0086] However, by sharing the bit line portion of one SRAM cell with the bit line portion of an adjacent SRAM cell in the same column, when the character lines of this column (i.e., the first character line 250 and / or the second character line 255) are activated, both of these two SRAM cells will be turned on, and the bit line will attempt to read from or write to both of these two SRAM cells, resulting in an incorrect result. To prevent this incorrect result, the present disclosure provides a mechanism such that only one of the two adjacent SRAM cells will be turned on.

[0087] Specifically and as Figure 2 shown, one terminal (i.e., the drain terminal) of the first access transistor 210 is connected to the bit line 205, and one terminal (i.e., the drain terminal) of the second access transistor 220 is connected to the bit line 215. In some embodiments, an interconnect structure (e.g., a via connection) may be required to connect the first access transistor 210 to the bit line 205. For example, in some embodiments, the bit line 205 may be provided using a zero-th metal (or another layer) interconnect layer (metal 0 interconnect layer), and using the interconnect structure, the zero-th metal interconnect layer can be connected to the first access transistor 210. Similarly, in some embodiments, the bit line 215 may be provided using a zero-th metal (or another layer) interconnect layer, and using the interconnect structure, the zero-th metal interconnect layer can be connected to the second access transistor 220. The portion 240 of the SRAM array 105 shows the positions of this interconnect structure 280 and interconnect structure 285 that connect the SRAM cell 145 to the bit line in the first bit line portion 265 and in the second bit line portion 270, respectively.

[0088] The interconnect structure 280 and interconnect structure 285 are shown using solid dots in Figure 3 and Figure 4serve as a representative. In some embodiments, the interconnect structure 280 may represent a connection of the bit line 205 to the first access transistor 210, and the interconnect structure 285 may represent a connection of the bit line 215 to the second access transistor 220. However, based on the sharing of the first bit line portion 265 and the bit line portions of the second bit line portion 270 and adjacent SRAM cells, an incorrect result may occur when both the SRAM cell 145 and the SRAM cell 245A are turned on, as described above.

[0089] To prevent adjacent SRAM cells from being turned on, the positions of the interconnect structures related to the word lines may be staggered. For example, and as Figure 2 shown, the gate terminals 225 of the first access transistor 210 and the gate terminals 230 of the second access transistor 220 are connected to the word line 235. In some embodiments, the word line 235 may be provided using a first metal 1 (or another layer) interconnect layer (metal 1 interconnect layer), and the first metal interconnect layer may be connected to the first access transistor 210 and the second access transistor 220 using an interconnect structure such as a via connection. The portion 240 of the SRAM array 105 is represented by hollow dots on the first word line 250 in the SRAM cell 245 (e.g., SRAM cell 245A), showing this interconnect structure 290 and interconnect structure 295. For example, the interconnect structure 290 may represent the connection to the first access transistor (i.e., the first access transistor 210), and the interconnect structure 295 may represent the connection to the second access transistor (i.e., the second access transistor 220). Both the interconnect structure 290 and the interconnect structure 295 are provided on the first word line 250 of the SRAM array 245 (e.g., SRAM cell 245A). However, on the adjacent SRAM cell 245A, the interconnect structure 290 and the interconnect structure 295 are provided on the second word line 255. Therefore, the positions of the interconnect structure 290 and the interconnect structure 295 in the SRAM cells located in the same column are staggered or alternated. By staggering or alternating the positions of the interconnect structure 290 and the interconnect structure 295, these interconnect structures are provided on one of the first word line 250 or the second word line 255 of two adjacent SRAM cells. In other words, one of the first word line 250 or the second word line 255 of a particular SRAM cell is connected to the first access transistor 210 or the second access transistor 220.

[0090] In addition, in some embodiments, the interconnect structures 290 and 295 are located on the same word line for all SRAM cells sharing a common row. For example, the interconnect structures 290 and 295 on the first word line 250 of the SRAM cell 245 (e.g., SRAM cell 245A) can also be located on the first word line 250 of each SRAM cell in the same row as the SRAM cell 145 (i.e., row 0). To turn on the first access transistor (i.e., the first access transistor 210) and the second access transistor (i.e., the second access transistor 220), in some embodiments, the first word line 250 and the second word line 255 can be activated. However, due to the use of the interconnect structures 290 and 295, only one of these word lines is connected to the first access transistor 210 and the second access transistor 220, so only the word line with the interconnect structure is activated. For example, to select the SRAM cell 145 instead of the SRAM cell 245A, both the first word line 250 with the interconnect structures 290 and 295 and the second word line 255 can be activated. However, since the interconnect structures 290 and 295 are only provided on the first word line 250 of the SRAM cell 145 and the adjacent SRAM cell 245A does not have the interconnect structure on the first word line, although both the first word line and the second word line are activated, only the SRAM cell 145 is turned on. In other embodiments, to activate the SRAM cell 145, only the first word line 250 with the interconnect structures 290 and 295 can be activated. In this way, since the second word line 255 is not activated, the SRAM cell 245A is not activated.

[0091] Now refer to Figure 5 and Figure 6 , according to some embodiments of the present disclosure, an exemplary layout design and cross-sectional view of a portion of the SRAM array 105 are shown. Specifically, Figure 5 a front layout design 300 of two adjacent SRAM cells (i.e., SRAM cell 145 and SRAM cell 245A), a back layout design 305 of two adjacent SRAM cells, and a cross-sectional view of these SRAM cells showing specific elements of the adjacent SRAM cells are shown. The layout design 300 and the layout design 305 can be used to fabricate the implementation described above Figure 3 and Figure 4At least a portion of a semiconductor device with the functions described below. The following descriptions of layout design 300 and layout design 305 illustrate SRAM cell 145 and SRAM cell 245A respectively. However, this description can also be equally applied to other SRAM cells in SRAM array 105.

[0092] Layout design 300 and layout design 305 can define the characteristics of the active devices (i.e., p-type pull-up transistor 170, n-type pull-down transistor 175, p-type pull-up transistor 190, n-type pull-down transistor 195, first access transistor 210, second access transistor 220) of SRAM cell 145 along an active region. An "active region" can be a fin region of one or more three-dimensional field-effect transistors (i.e., fin field-effect transistors (FinFETs), gate-all-around (GAA) transistors, including nanosheet transistors and nanowire transistors), or an oxide-definition (OD) region of one or more planar metal-oxide-semiconductor field-effect transistors (MOSFETs). The active region can define the source or drain terminals of the active devices (i.e., the above-mentioned transistors). The gate terminals of these transistors can also be defined by a gate structure formed of one or more conductive materials (i.e., polysilicon, metal), and can cover the corresponding portions of the active region to define p-type pull-up transistor 170, n-type pull-down transistor 175, p-type pull-up transistor 190, n-type pull-down transistor 195, first access transistor 210, and second access transistor 220.

[0093] For example, layout design 300 shows active regions 310, 315, 320, and 325, which define the source and drain regions of p-type pull-up transistors 170, n-type pull-down transistors 175, p-type pull-up transistors 190, n-type pull-down transistors 195, first access transistors 210, and second access transistors 220. In some embodiments, active regions 310, 315, 320, and 325 may extend in an X direction (i.e., X direction 110). Layout design 300 also shows gate structures 330, 335, 340, and 345 covering active regions 310, 315, 320, and 325, and which define the gate terminals of p-type pull-up transistors 170, n-type pull-down transistors 175, p-type pull-up transistors 190, n-type pull-down transistors 195, first access transistors 210, and second access transistors 220. In some embodiments, gate structures 330, 335, 340, and 345 extend in a Y direction (i.e., Y direction 115). Portions of active regions 310, 315, 320, and 325 disposed on the left and right sides of one of the respective gate structures 330, 335, 340, and 345 may respectively define the source and drain terminals of p-type pull-up transistors 170, n-type pull-down transistors 175, p-type pull-up transistors 190, n-type pull-down transistors 195, first access transistors 210, and second access transistors 220.

[0094] Specifically, and in conjunction with Figure 2 referring together Figure 5 and Figure 6, the gate structure 330 covering the active region 310 defines the gate terminal of the n-type pull-down transistor 175, while the portions of the active region on the left and right sides of the gate structure 330 define the source terminal and the drain terminal of the n-type pull-down transistor 175. Similarly, the gate structure 335 covering the active region 310 defines the gate terminal of the first access transistor 210, while the portions of the active region on the left and right sides of the gate structure 335 define the source terminal and the drain terminal of the first access transistor 210. The gate structure 330 covering the active region 315 defines the gate terminal of the p-type pull-up transistor 170, while the portions of the active region on the left and right sides of the gate structure 330 define the source terminal and the drain terminal of the p-type pull-up transistor 170. The gate structure 340 covering the active region 325 defines the gate terminal of the second access transistor 220, while the portions of the active region on the left and right sides of the gate structure 340 define the source terminal and the drain terminal of the second access transistor 220. The gate structure 345 covering the active region 325 defines the gate terminal of the n-type pull-down transistor 195, while the portions of the active region on the left and right sides of the gate structure 345 define the source terminal and the drain terminal of the n-type pull-down transistor 195. The gate structure 345 covering the active region 320 defines the gate terminal of the p-type pull-up transistor 190, while the portions of the active region on the left and right sides of the gate structure 345 define the source terminal and the drain terminal of the p-type pull-up transistor 190.

[0095] Thus, the gate terminals of each of the p-type pull-up transistor 170, n-type pull-down transistor 175, p-type pull-up transistor 190, n-type pull-down transistor 195, and the first access transistor 210 are defined by one of the gate structures 330, gate structure 335, gate structure 340, and gate structure 345, and the source and drain terminals of these transistors are defined by one of the corresponding active regions 310, active region 315, active region 320, and active region 325 under any side of the gate structure. The SRAM cell 245A has a layout design similar to that of the SRAM cell 145. For example, the gate structure 350 covering the active region 310 defines the gate terminal of the first access transistor 210, and the left and right portions of the active region of the gate structure 350 define the source and drain terminals of the first access transistor 210. The gate structure 355 covering the active region 310 defines the gate terminal of the n-type pull-down transistor 175, the gate structure 355 covering the active region 315 defines the gate terminal of the p-type pull-up transistor 170, and a gate structure 360 covering the active region 325 defines the gate terminal of the n-type pull-down transistor 195. Similarly, a gate structure 360 covering an active region 365 defines the gate terminal of the p-type pull-up transistor 190, and a gate structure 370 covering the active region 325 defines the gate terminal of the second access transistor 220. The left and right portions of the respective active regions 310, active region 325, and active region 365 of the relevant gate structures 350, gate structure 360, and gate structure 370 define the source and drain terminals of the respective transistors.

[0096] In addition, the respective gate terminals 225 and gate terminal 230 of the first access transistor 210 and the second access transistor 220 can be connected to the word line 235, as Figure 2 shown. This connection can be facilitated by electrically connecting the gate structures of the first access transistor 210 and the second access transistor 220 to the interconnect layer representing the word line 235. For example, and as Figure 5 shown, the gate structure 335 that defines the gate terminal of the first access transistor 210 can be electrically connected to the interconnect layers 375 and 380 (in Figure 6As shown. In some embodiments, the interconnect layer 375 and the interconnect layer 380 may each comprise a conductive material, such as one or more metal materials, and may be formed using a first metal layer (metal 1 layer / M1 layer). In some embodiments, the M1 layer may be formed on a zero-th metal layer (metal 0 layer) (or M0 layer). In some embodiments, the M0 layer may be directly above the gate structures 330, 335, 340, and 345, and the M0 layer may be sandwiched between the M1 layer and these gate structures. In other embodiments, the interconnect layer 375 and the interconnect layer 380 may be formed on other interconnect layers.

[0097] Furthermore, in some embodiments, the M1 layer may extend in a direction perpendicular to (or substantially perpendicular to) the M0 layer. For example, in some embodiments, the M0 layer may extend in the X direction 110, while the M1 layer may extend in the Y direction 115. In other embodiments, the M0 layer and the M1 layer may extend in the same (or substantially similar) direction. Furthermore, in some embodiments, in order to connect the gate structure 335 to the interconnect layer 375 and the interconnect layer 380, the gate structure may be connected to the interconnect layer 385 through the interconnect structure 390. In some embodiments, the interconnect layer 385 may be an M0 layer. In some embodiments, the interconnect structure 390 may be a via structure providing an electrical connection between the gate structure and the M0 layer. Then the interconnect layer 385 may be connected to the interconnect layer 375 through the interconnect structure 395 (see Figure 6 ), and in some embodiments, the interconnect structure 395 may be a via structure. In some embodiments, the interconnect layer 375 is considered to be analogous to the first word line 250, and the interconnect layer 380 is considered to be analogous to the second word line 255. The interconnect structure 395 is considered to be analogous to the interconnect structure 290. Therefore, the gate structure 335 defining the gate terminal of the first access transistor 210 is connected to the interconnect layer 375 (i.e., the first word line 250) through the interconnect structure 395 (i.e., the interconnect structure 290).

[0098] Similarly, in order to connect the gate structure of the second access transistor 220 to the word line 235, the gate structure 340 defining the gate terminal of the second access transistor may be connected to the interconnect layer 375 and the interconnect layer 380, as Figure 6 shown. Similar to the interconnection of the gate structure 335, in order to connect the gate structure 340 to the interconnect layer 375 and the interconnect layer 380, the gate structure 340 may be connected to an interconnect layer 400 through an interconnect structure 405. In some embodiments, the interconnect layer 400 may be an M0 layer and the interconnect structure 405 may be a via structure. Then the interconnect layer 400 may be connected to the interconnect layer 375 through the interconnect structure 410 (see Figure 6) is connected to the interconnect layer 375, and in some embodiments, the interconnect structure 410 can be a via structure. Further, in some embodiments, the interconnect structure 410 is considered comparable to the interconnect structure 295. Thus, both the interconnect structure 395 and the interconnect structure 410 are located on the interconnect layer 375, and as described above, in some embodiments, they are considered comparable to the first word line 250.

[0099] The layout design 300 also shows the interconnection of the SRAM cell 245A to the word line 235. The word line 235 can include the first word line 250 and the second word line 255. The first word line 250 can be defined by an interconnect layer 415 (see Figure 6 ), and the second word line 255 can be defined by an interconnect layer 420 (see Figure 6 ). The gate structure 350 that defines the gate terminal of the first access transistor 210 can be connected to the interconnect layer 420. In some embodiments, the interconnect layer 415 and the interconnect layer 420 can be defined using the M1 layer. The gate structure 350 can be connected to an interconnect layer 425 through an interconnect structure 430 to be connected to the interconnect layer 420. In some embodiments, the interconnect layer 425 can be an M0 layer, and the interconnect structure 430 can be a via structure. The interconnect layer 425 can be connected to the interconnect layer 420 through an interconnect structure 435 (see Figure 6 ), and in some embodiments, the interconnect structure 435 can be a via structure. In some embodiments, the interconnect structure 435 is considered comparable to the interconnect structure 290.

[0100] To connect the gate structure 370 that defines the gate terminal of the second access transistor 220 to the interconnect layer 420, the gate structure can be connected to an interconnect layer 440 through an interconnect structure 445. In some embodiments, the interconnect layer 440 can be an M0 layer and the interconnect structure 445 can be a via structure. Then the interconnect layer 440 can be connected to the interconnect layer 420 through another interconnect structure 450 (see Figure 6 ). In some embodiments, the interconnect structure 450 can also be a via structure. Thus, both the interconnect structure 435 and the interconnect structure 450 are provided on the interconnect layer 420 and correspond to the second word line 255. Therefore, the SRAM cell 145 has the interconnect structure 395 and the interconnect structure 410 connected to the interconnect layer 375 (corresponding to the first word line 250), while the SRAM cell 245A (adjacent to the SRAM cell 145) has the interconnect structure 435 and the interconnect structure 450 connected to the interconnect layer 420 (corresponding to the second word line 255). Thus, as described above Figure 3 the positions of the alternating interconnect structures are arranged.

[0101] Further, as Figure 2As shown, a first access transistor 210 and a second access transistor 220 are connected to bit line 205 and bit line 215. This connection is shown in layout design 300 by means of interconnect layer 455 and interconnect layer 460. Specifically, in some embodiments, the active regions 310 that define the source and drain terminals of the first access transistor 210 can be connected to interconnect layer 455 through an interconnect structure 465, and the active regions 325 that define the source and drain terminals of the second access transistor 220 can be connected to interconnect layer 460 through an interconnect structure 470. Interconnect layer 455 and interconnect layer 460 can each be an M0 layer (i.e., a larger metal size and larger metal space provided for 3 metal tracks (i.e., bit line resistance and bit line capacitance)) in some embodiments, and interconnect structure 465 and interconnect structure 470 can each be a via structure in some embodiments. Interconnect layer 455 can correspond to bit line 205 (i.e., the first bit line portion 265), and interconnect layer 460 can correspond to bit line 215 (i.e., the second bit line portion 270).

[0102] Through layout design 300, two finer word lines in each SRAM cell can be provided (i.e., interconnect layer 375 / interconnect layer 380 of SRAM cell 145 and interconnect layer 415 / interconnect layer 420 of SRAM cell 245A). As described above, by alternating the positions of the interconnect structures on the two fine word lines, adjacent SRAM cells can be individually turned on without turning on the adjacent SRAM cells. Further, in a conventional design, active devices (i.e., transistors), bit lines, word lines, supply voltage, and ground voltage structures are all provided on the same side of a semiconductor substrate. Specifically, in a conventional design, active devices (i.e., transistors), bit lines, word lines, supply voltage, and ground voltage structures are all provided on the front or top surface of the semiconductor substrate of the SRAM cell. A "front" or "top surface" of a semiconductor substrate is the side or surface where the active devices (i.e., transistors of an integrated circuit (i.e., SRAM cell 145)) are formed. The side or surface of the semiconductor substrate opposite to the front or top surface is the "back" or "bottom surface". The semiconductor substrate will be discussed in more detail below.

[0103] By forming all active devices, bit lines, word lines, supply voltages, and ground voltage structures on the front side of the semiconductor surface, the overall area of an SRAM cell is increased, and higher levels of interconnect layers may be required for some structures. For example, in some conventional designs, the supply voltage along with the bit line structure may be defined in the M0 layer, and the ground voltage structure may be defined in the M2 layer. Higher interconnect layers increase the IR voltage drop. Therefore, to reduce the overall area of the SRAM cell and further reduce the IR voltage drop, the present disclosure provides a mechanism in which some structures may be defined on the back side of the substrate of the SRAM cell. For example, in some embodiments, as shown in layout design 300, the active devices (i.e., transistors), bit line structures, and word line structures may be formed on the front side of the semiconductor substrates of SRAM cell 145 and SRAM cell 245O, while the supply voltage and the ground voltage structures may be moved to the back side of the semiconductor substrate, as shown in layout design 305.

[0104] Thus, in some embodiments, layout design 300 corresponds to the layout design of the front side of the semiconductor substrates of SRAM cell unit 145 and SRAM cell 245A. Layout design 305 corresponds to the layout design of the back side of the semiconductor substrates of SRAM cell unit 145 and SRAM cell 245A. Layout design 305 shows interconnect layers 475 and 480 that define the ground voltage structure (corresponding to the ground voltage 185 in Figure 2 ), and interconnect layer 485 defines (corresponding to Figure 2A supply voltage structure of the supply voltage 180 in []. In some embodiments, the interconnect layer 475, the interconnect layer 480, and the interconnect layer 485 can each be a backside M0 layer. A backside M0 layer can be similar to the frontside M0 layer (i.e., the M0 layer described with respect to the layout design 300). Thus, in some embodiments, the backside M0 layer can extend in the X direction 110. However, the backside M0 layer can be wider than a frontside M0 layer in some embodiments. In other embodiments, the interconnect layer 475, the interconnect layer 480, and the interconnect layer 485 can each be formed on a different backside metal layer. Since the interconnect layer 475, the interconnect layer 480, and the interconnect layer 485 are provided on the backside, these interconnect layers need to be connected to the active regions (i.e., transistors) formed on the frontside, as shown in the layout design 300. In some embodiments, the interconnect layer 475 can be connected to the active region 310 provided on the frontside through an interconnect structure 490. In some embodiments, the interconnect structure 490 can be a via structure. The interconnect structure 490 can be utilized for both the SRAM cell 145 and the SRAM cell 245A. Many of the active regions and gate structures shown in the layout design 305 respectively correspond to the active regions and gate structures provided in the layout design 300, and their display in the layout design 305 is only for explanatory purposes. These active regions and gate structures do not extend to the backside. For example, the active region 310 shown in the layout design 305 is only for convenience of explanation. The active regions as shown in the layout design 300 are on the frontside and do not extend to the backside of the substrate.

[0105] Similar to the interconnect layer 475, the interconnect layer 480 can be connected to the active region 325 provided on the frontside (which is related to the n-type pull-down transistor 195 of the SRAM cell 145) through an interconnect structure 495. In some embodiments, the interconnect structure 495 can be a via structure. The interconnect layer 485 can be connected to the active region 320 provided on the frontside (which is related to the p-type pull-up transistor 190 of the SRAM cell 145) through an interconnect structure 500. The interconnect layer 485 can also be connected to the active region 315 provided on the frontside (which is related to the p-type pull-up transistor 170 of the SRAM cell 145 and the SRAM cell 245A) through an interconnect structure 505. The interconnect structure 500 and the interconnect structure 505 can each be a via structure in some embodiments. Again, the active region 315, the active region 320, and their related gate structures are only shown in the layout design 305 for convenience of explanation. These active regions and gate structures are only provided on the frontside as shown in the layout design 300.

[0106] The interconnect layer 480 can also be connected to the active region 325 provided on the front side (which is related to the n-type pull-down transistor 195 of the SRAM cell 245A) through an interconnect structure 510. In some embodiments, the interconnect structure 510 can be a via structure. The interconnect layer 485 can also be connected to the active region 320 provided on the front side (which is related to the p-type pull-up transistor 190 of the SRAM cell 245A) through an interconnect structure 515. The interconnect structure 515 can also be a via structure in some embodiments. By providing the supply voltage and ground voltage structures on the back side, the overall area of the SRAM cell can be reduced, and the resources (i.e., interconnect layers) that can be used for the power supply and ground structures on the front side are now available for other uses. Further, since the back-side interconnect layer may be wider than the front-side interconnect layer, the IR voltage drop can be reduced.

[0107] Continuing to refer Figure 5 , a cross-sectional view 520 of a semiconductor device showing the SRAM cell 145 and the SRAM cell 245A is also shown. The cross-sectional view 520 shows a semiconductor substrate 525 having a front side 530 and a back side 535. The active devices (i.e., transistors) of the SRAM cell 145 and the SRAM cell 245A are not shown in the cross-sectional view 520. Therefore, the active regions 310, 315, 320, 325 and the gate structures 330, 335, 340, 345 are not shown in the cross-sectional view 520. The cross-sectional view 520 shows specific interconnect structures and how the front side 530 of the semiconductor substrate 525 is connected to the back side 535 of the substrate. As described above, the supply voltage and ground voltage structures can be moved to the back side 535 of the semiconductor substrate 525, as shown by the interconnect layer 475 / interconnect layer 480 of the ground voltage structure and the interconnect layer 485 of the power supply structure. The ground voltage structure (i.e., interconnect layer 475 / interconnect layer 480) can be connected to the structures on the front side 530 of the semiconductor substrate 525 through the interconnect structures 490 and 495. The supply voltage structure (i.e., interconnect layer 485) can be connected to the structures on the front side 530 of the semiconductor substrate 525 through the interconnect structures 500 and 505.

[0108] On the front side 530 of the semiconductor substrate 525, the interconnect points 540 can connect the interconnect structures 490, 495, 500, and 505 to the respective active regions 310, 315, 320, 325, and can then be finally connected to the interconnect layer 455 (bit line interconnect layer), the interconnect layer 460 (bit line interconnect layer), and the interconnect layer 375 (word line interconnect layer), the interconnect layer 380 (word line interconnect layer), the interconnect layer 415 (word line interconnect layer), and the interconnect layer 420 (word line interconnect layer).

[0109] Steering Figure 7 , according to some embodiments of the present disclosure, an exemplary block diagram of a computing system 545 is shown. The computing system 545 may be a circuit or layout designer for performing a standard cell layout of a circuit. A "circuit" or "integrated circuit" as used herein is an interconnection of active devices (i.e., electrical components), such as resistors, transistors, batteries, or other types of semiconductor devices configured to implement a desired function. The computing system 545 includes a host device 550 associated with a memory device 555. The host device 550 may be configured to receive inputs from one or more input devices 560 and provide outputs to one or more output devices 565. The host device 550 may be configured to communicate with the memory device 555, the input device 560, and the output device 565 through appropriate interfaces 570A, interface 570B, and interface 570C, respectively. The computing system 545 may be implemented in many computing devices, such as a computer (i.e., desktop, laptop, server, data center, etc.), a tablet, a personal digital assistant, a mobile device (cell phone), other handheld or portable devices, or other computing units suitable for using the host device 550 to perform a standard cell layout.

[0110] The input device 560 may include any of a number of input technologies, such as a keyboard, a stylus, a touch screen, a mouse, a trackball, a keypad, a microphone, voice recognition, motion recognition, a remote control, an input terminal, one or more buttons, a dial, a rocker, and any other peripheral device related to the input of the host device 550, and allows an external source, such as a user (i.e., a circuit or layout designer), to input information (i.e., data) to the host device and transmit instructions to the host device. Similarly, the output device 565 may include various output technologies, such as an external memory, a printer, a speaker, a display, a microphone, a light-emitting diode, headphones, an imaging device, and any other output peripheral device configured to receive information (i.e., data) from the host device 550. The "data" input to the host device 550 and / or output from the host device may include any of a variety of text data, circuit data, signal data, semiconductor device data, image data, combinations of the foregoing, or other types of analog and / or digital data suitable for processing using the computing system 545.

[0111] The host device 550 includes or is related to one or more processing units / processors, such as CPU cores 575A to CPU cores 575N. The CPU cores 575A to 575N can be implemented as application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), or any other type of processing unit. Each of the CPU cores 575A to 575N can be configured to execute multiple instructions to run one or more application programs of the host device 550. In some embodiments, the instructions and data required to run the one or more application programs can be stored in the memory device 555. The host device 550 can also be configured to store the results of the one or more running application programs in the memory device 555. Thus, the host device 550 can be configured to request the memory device 555 to perform various operations. For example, the host device 550 can request the memory device 555 to read data, write data, update or delete data, and / or perform administrative or other operations.

[0112] One of the applications that the host device 550 may be configured to execute may be a standard cell layout application 580. The standard cell layout application 580 may be part of a computer-aided design or electronic digital automation software suite, which may be used by a user of the host device 550 to generate a standard cell layout of a circuit (also referred to herein as "layout", "layout diagram", "layout design", and similar terms). For example, the standard cell layout application 580 may be used to generate layout design 300 and layout design 305. The standard cell layout of a circuit may show the many elements / connections that will be fabricated. For example, the standard cell layout may show one or more active regions, gate electrodes, source electrodes, and drain electrodes, metal lines, via contacts, openings of pads, one or more metal layers, power supplies, etc. that represent the many elements of the circuit, and how they are interconnected when these elements are disposed on / within a semiconductor substrate (such as a silicon wafer). By following a design flow that may include one or more logical design, physical design, or placement and routing, the standard cell layout may be implemented. The standard cell layout may be represented in one or more data files, such as the GDSII file format or the DFII file format. In other embodiments, other file formats may be used. Thus, by using the standard cell layout application 580, a circuit designer may generate a standard cell layout of a circuit. In some embodiments, the instructions required to execute or run the standard cell layout application 580 may be stored in the memory device 555. The standard cell layout application with respect to the memory device 555 may be executed by one or more CPU cores 575A to CPU core 575N to execute the standard cell layout application 580.

[0113] Continuing to refer Figure 7, the memory device 555 includes a memory controller 585 configured to read data from or write data to a memory array 590. In some embodiments, the memory array 590 may include various volatile and / or non-volatile memories. For example, in some embodiments, the memory array 590 may include a NAND flash memory core, a NOR flash memory core, a static random access memory (SRAM) core, a dynamic random access memory (DRAM) core, a magnetoresistive random access memory (MRAM) core, a phase change memory (PCM) core, a resistive random access memory (ReRAM) core, a 3D XPoint memory core, a ferroelectric random access memory (FeRAM) core, and other memory core types suitable for use in the memory array. Generally, the memory array 590 may include any combination of random access memory (RAM), read only memory (ROM), programmable read only memory (PROM), erasable programmable read only memory (EPROM), electrically erasable programmable read only memory (EEPROM), hard disk drive, flash drive, memory tapes, optical drive, cloud memory, or primary and / or secondary memory suitable for performing the operations described herein.

[0114] The memories in the memory array 590 may be individually and independently controlled by the memory controller 585. In other words, the memory controller 585 may be configured to communicate individually and independently with each memory in the memory array 590. By communicating with the memory array 590, the memory controller 585 may be configured to read data from or write data to the memory array in response to instructions received from the host device 550. Although shown as part of the memory device 555, in some embodiments, the memory controller 585 may be part of the host device 550, or part of another element related to the memory device and the computing system 545. The memory controller 585 may be implemented as software, hardware, firmware, or a logic circuit in a combination of the foregoing to perform the functions described herein. For example, in some embodiments, the memory controller 585 may be configured to retrieve instructions regarding the standard cell layout application 580 stored in the memory array 590 of the memory device 555 when receiving a request from the host device 550.

[0115] In some embodiments, computing system 545 may also be related to a number of fabrication tools 595. Among other things, fabrication tools 595 may be used to prepare and fabricate a set of masks based on the standard cell layout generated by the standard cell layout application 580. The set of masks may define the geometries for the photolithography steps in the semiconductor process for the circuit. Although the fabrication tools 595 are shown separately from the host device 550, in some embodiments, at least some of the functions of the fabrication tools may be implemented by the host device, such as by the standard cell layout application 580 or other applications related to the standard cell layout application.

[0116] To prepare a set of masks, fabrication tools 595 may be used to translate the standard cell layout of the circuit into a representative data file (RDF). Then, the representative data file may be used to fabricate a set of physical masks to fabricate the circuit.

[0117] In some embodiments, preparing the set of masks may include performing an optical proximity correction (OPC) using lithography enhancement techniques to compensate for image errors in the circuit, such as diffraction, interference, other process effects, and other similar errors that are generated. In some embodiments, a mask rule checker (MRC) of the fabrication tools 595 may check the standard cell layout that has undergone the optical proximity correction process against a set of mask fabrication rules. The mask fabrication rules may include specific geometry and / or connectivity restrictions to ensure sufficient margins, to account for variability in the semiconductor process, and similar rules. In some embodiments, the mask rule checker may modify the standard cell layout to compensate for the restrictions in the process for the set of masks. In some embodiments, preparing the set of masks may also include resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution assist features, phase-shifting masks, and similar techniques or combinations of the foregoing.

[0118] In some embodiments, preparing the set of masks may further include lithography process checking (LPC), which can simulate the processes implemented to fabricate a circuit. Lithography process checking can simulate these processes based on the standard cell layout to fabricate an analog fabrication device for a circuit. Lithography process checking can consider many factors, such as aerial image contrast, depth of focus (DOF), mask error enhancement factor (MEEF), other suitable factors, and similar factors or combinations of the foregoing, to simulate the processes of a circuit. In some embodiments, after lithography process checking generates an analog fabrication device, if the simulated device does not meet specific design rules, optical proximity correction and / or mask rule checker can be repeated to further improve the standard cell layout.

[0119] To fabricate the set of masks, a mask writer can convert a representative data file into an image on a substrate (such as a mask (reticle) or a semiconductor wafer). In some embodiments, a mechanism using an electron beam (e-beam) or multiple electron beams can be utilized to form a mask pattern on a semiconductor wafer to form a mask. In some embodiments, the mask pattern can include one or more opaque regions and one or more transparent regions. A radiation beam, such as ultraviolet (UV) light, used to expose a layer of image-sensitive material (i.e., photoresist) coated on the semiconductor wafer can be blocked by the opaque regions and can pass through the transparent regions. In one example, the mask pattern can include a transparent substrate (i.e., fused quartz) and an opaque material (i.e., chromium) coated on the opaque regions to form a mask. In other embodiments, other or additional techniques can be utilized to fabricate masks.

[0120] Once the mask is fabricated, a process entity (i.e., a production facility or semiconductor manufacturing plant) can use the fabricated mask to fabricate a circuit. In some embodiments, fabricating the circuit may involve depositing one or more materials on / into a semiconductor wafer using the mask (or masks). The semiconductor wafer can include a silicon substrate or other substrate with material layers formed thereon. The semiconductor wafer can further include one or more various doped regions, dielectric features, multi-layer interconnect structures, and similar features formed using one or more masks.

[0121] It is to be understood that while the fabrication tool 595 is described as performing certain operations to prepare the set of masks and then fabricating the set of masks, in some embodiments, the various processes may be different from those described. In some embodiments, additional or other processes or operations may be utilized to prepare and fabricate the set of masks. It is also to be understood that only some elements of the computing system 545 are shown and described in Figure 7 . However, the computing system 545 may include other elements such as various batteries and power supplies, network interfaces, routers, switches, external memory systems, controllers, and the like. In general, the computing system 545 may include any of a variety of hardware, software, and / or firmware needed or deemed desirable to perform the functions described herein. Similarly, the host device 550, the input device 560, the output device 565, and the memory device 555 including the memory controller 585 and the memory array 590 may include any of a variety of hardware, software, and / or firmware needed or deemed desirable to perform the functions described herein.

[0122] Accordingly, the present disclosure provides an optimized SRAM cell having two thinner word lines and one wider bit line. By having a wider bit line, the IR voltage drop of the SRAM cell is reduced. The reduced IR voltage drop is particularly beneficial for SRAM cells that are farther from the read / write block location. The reduced IR voltage drop can increase the performance (i.e., speed) of the SRAM cell. For example, in some simulations, the inventors found that compared to a conventional SRAM array, the speed of an SRAM cell located at row 0, column 0 of an SRAM array according to the present disclosure increased by 102%, the speed of an SRAM cell located at row 0, column 255 increased by approximately 82%, and the speed of an SRAM cell located at row 127, column 255 increased by approximately 131%. Thus, a single wide bit line and two thin word lines can provide significant performance improvements in some embodiments. The increased performance of the SRAM cell results in an overall increase in the performance of the SRAM array employing such SRAM cells. Further, by moving the supply and ground power structures of the SRAM cell to the backside of a substrate and providing two types of cell metals for different word line and bit line loads, the overall layout design of the SRAM cell can be optimized, thereby further reducing the IR voltage drop of the SRAM cell and reducing the overall size (i.e., area) of the SRAM cell. While the present disclosure is described in terms of SRAM cells, it is to be understood that the present disclosure may also be applied to other types of memory cells.

[0123] According to some aspects of the present disclosure, a memory device includes a memory array including a plurality of memory cells, each memory cell including a first word line, a second word line, and a bit line. The first word line applies a first signal to select each memory cell to read data from or write data to each memory cell. The second word line applies a second signal to select each memory cell to read data from or write data to each memory cell. The bit line reads data from or provides data to be written to each memory cell when at least one of the first word line or the second word line selects each memory cell.

[0124] In some embodiments, each memory cell is a static random access memory cell. In some embodiments, the first word line extends in a first direction and has a first width in a second direction perpendicular to the first direction. The bit line extends in the second direction and has a second width in the first direction. The second width is greater than the first width. In some embodiments, the second word line extends in the first direction and has a first width in a second direction perpendicular to the first direction. The bit line extends in the second direction and has a second width in the first direction. The second width is greater than the first width. In some embodiments, the first word line extends in the first direction and has a first width in a second direction perpendicular to the first direction. The second word line extends in the first direction and has a second width in the second direction. The bit line extends in the second direction and has a third width in the first direction. The third width is greater than the first width and the second width. In some embodiments, the first width is substantially the same as the second width. In some embodiments, the first word line and the second word line are spaced apart from each other. In some embodiments, the bit line includes a first bit line portion and a second bit line portion spaced apart from the first bit line portion. In some embodiments, the first word line extends in the first direction and has a first width in a second direction perpendicular to the first direction. The first bit line portion and the second bit line portion extend in the second direction and have a second width in the first direction. The second width is greater than the first width. In some embodiments, the first bit line portion of the first memory cell of the memory cells is adjacent to the second bit line portion of the second memory cell adjacent to the first memory cell in the memory cells. In some embodiments, the first memory cell and the second memory cell of the memory cells each include a first access transistor and a second access transistor. The first memory cell is adjacent to the second memory cell. The first word line of the first memory cell is connected to the first access transistor and the second access transistor of the first memory cell to select the first memory cell. The second word line of the second memory cell is connected to the first access transistor and the second access transistor of the second memory cell to select the second memory cell.

[0125] According to some other aspects of the present disclosure, a memory cell includes a first word line, a second word line, and a bit line. The memory cell includes the first word line extending in a first direction and having a first width in a second direction perpendicular to the first direction, the second word line extending in the first direction and having a second width in the second direction, and the bit line extending in the second direction and having a third width in the first direction. Wherein at least one of the first word line or the second word line is applied with a signal to select the memory cell to read data from the memory cell or write data to the memory cell. The third width is greater than the first width and the second width.

[0126] In some embodiments, the bit line includes a first bit line portion and a second bit line portion, each of the first bit line portion and the second bit line portion having a fourth width and being spaced apart from each other. The fourth width is greater than the first width and the second width. In some embodiments, the first bit line portion abuts an adjacent bit line portion of a first adjacent memory cell, and the second bit line portion abuts another adjacent bit line portion of a second adjacent memory cell. In some embodiments, the memory cell is a static random access memory cell. In some embodiments, one of the first word line and the second word line is connected to an access transistor of the memory cell to select the memory cell.

[0127] According to some other aspects of the present disclosure, a memory cell includes a substrate, a first interconnect layer, a second interconnect layer, a third interconnect layer, and a fourth interconnect layer. The memory cell includes a substrate having a front surface and a back surface, wherein transistors of the memory cell are formed on the front surface, and wherein the back surface is the opposite side of the front surface. The memory cell also includes the first interconnect layer on the front surface to provide a bit line of the memory cell, the second interconnect layer on the front surface to provide a word line of the memory cell, the third interconnect layer on the back surface to provide a supply voltage to the memory cell, and the fourth interconnect layer on the back surface to provide a ground voltage to the memory cell.

[0128] In some embodiments, the first interconnect layer is the zeroth metal layer on the front surface, the second interconnect layer is the first metal layer on the front surface, the third interconnect layer is the zeroth metal layer on the back surface, and the fourth interconnect layer is the zeroth metal layer on the back surface. In some embodiments, the memory cell further includes a first interconnect structure connecting the third interconnect layer to a first active region located on the front surface, and includes a second interconnect structure connecting the fourth interconnect layer to a second active region on the front surface. In some embodiments, the second interconnect layer has a width smaller than the width of the first interconnect layer.

[0129] The foregoing has outlined features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they can readily use the present disclosure as a basis for designing other processes and structures for achieving the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that equivalent constructions do not depart from the spirit and scope of the present disclosure and that they may make various changes, substitutions, and alterations therein without departing from the spirit and scope of the present disclosure.

Claims

1. A memory device, comprising: A memory array including a plurality of memory cells, each memory cell comprising: A first word line to which a first signal is applied to select each of the memory cells to read data from or write data to each of the memory cells; A second word line to which a second signal is applied to select each of the memory cells to read data from or write data to each of the memory cells; A bit line to read data from each of the memory cells or provide data to be written to each of the memory cells when at least one of the first word line or the second word line selects each of the memory cells, wherein the bit line includes a first bit line portion and a second bit line portion spaced apart from the first bit line portion, wherein the first bit line portion of a first memory cell of the memory cells abuts and is connected to the second bit line portion of a second memory cell adjacent to the first memory cell among the memory cells.

2. The memory device of claim 1, wherein each of the memory cells is a static random access memory cell.

3. The memory device of claim 1, wherein: The first word line extends in a first direction and has a first width in a second direction perpendicular to the first direction; The bit line extends in the second direction and has a second width in the first direction; and The second width is greater than the first width.

4. The memory device of claim 1, wherein: The second word line extends in a first direction and has a first width in a second direction perpendicular to the first direction; The bit line extends in the second direction and has a second width in the first direction; and The second width is greater than the first width.

5. The memory device of claim 1, wherein: The first word line extends in a first direction and has a first width in a second direction perpendicular to the first direction; The second word line extends in the first direction and has a second width in the second direction; The bit line extends in the second direction and has a third width in the first direction; and The third width is greater than the first width and the second width.

6. The memory device of claim 5, wherein the first width is substantially the same as the second width.

7. The memory device of claim 1, wherein the first word line and the second word line are spaced apart from each other.

8. The memory device of claim 1, wherein: The first word line extends in a first direction and has a first width in a second direction perpendicular to the first direction; The first bit line portion and the second bit line portion extend in the second direction and have a second width in the first direction; And The second width is greater than the first width.

9. The memory device of claim 1, wherein: The first memory cell and the second memory cell of the memory cells each include a first access transistor and a second access transistor; The first memory cell is adjacent to the second memory cell; The first word line of the first memory cell is connected to the first access transistor and the second access transistor of the first memory cell to select the first memory cell; and The second word line of the second memory cell is connected to the first access transistor and the second access transistor of the second memory cell to select the second memory cell.

10. A memory device, comprising: A memory array including a plurality of memory cells; A first word line extending in a first direction and having a first width in a second direction perpendicular to the first direction; A second word line extending in the first direction and having a second width in the second direction; A first bit line portion, a second bit line portion, a third bit line portion, and a fourth bit line portion extending in the second direction and having a third width in the first direction; wherein the first bit line portion and the second bit line portion are connected to a first memory cell, and the third bit line portion and the fourth bit line portion are connected to a second memory cell adjacent to the first memory cell; wherein the second bit line portion abuts and is connected to the third bit line portion; wherein at least one of the first word line or the second word line applies a signal to select the memory cell to read data from the memory cell or write data to the memory cell; and the third width is greater than the first width and the second width.

11. The memory cell of claim 10, wherein the first bit line portion and the second bit line portion are spaced apart from each other, and the third bit line portion and the fourth bit line portion are spaced apart from each other.

12. The memory cell of claim 10, wherein the plurality of memory cells are static random access memory cells.

13. The memory cell of claim 10, wherein one of the first word line and the second word line is connected to an access transistor of the first memory cell to select the first memory cell.

14. A memory device, comprising: A memory array including a plurality of memory cells; A substrate having a front surface and a back surface, wherein a plurality of transistors of the plurality of memory cells of the memory array are formed on the front surface, and wherein the back surface is the opposite side of the front surface; A first interconnect layer on the front surface to provide a plurality of bit line portions of the memory array; A second interconnect layer on the front surface to provide a plurality of word lines of the memory array; A third interconnect layer on the back surface to provide a supply voltage to the memory array; and A fourth interconnect layer on the back surface to provide a ground voltage to the memory array; wherein the plurality of bit line portions include a first bit line portion, a second bit line portion, a third bit line portion, and a fourth bit line portion; wherein the first bit line portion and the second bit line portion are connected to a first memory cell of the plurality of memory cells, and the third bit line portion and the fourth bit line portion are connected to a second memory cell of the plurality of memory cells; Wherein the first memory cell is adjacent to the second memory cell, and the second bit line portion abuts and connects to the third bit line portion.

15. The memory cell of claim 14, wherein the first interconnect layer is a front-side zero-th metal layer, the second interconnect layer is a front-side first metal layer, the third interconnect layer is a back-side zero-th metal layer, and the fourth interconnect layer is a back-side zero-th metal layer.

16. The memory cell of claim 14, further comprising a first interconnect structure connecting the third interconnect layer to a first active region located on the front side, and comprising a second interconnect structure connecting the fourth interconnect layer to a second active region located on the front side.

17. The memory cell of claim 14, wherein the width of the plurality of word lines is less than the width of the plurality of bit line portions.

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