Memory devices and methods of operating memory devices

Abstract

Memory devices and methods of operating memory devices are disclosed. The methods include programming a set of information bits into one or more memory cells using a neural network based on a plurality of embedding parameters; determining a set of predicted information bits based on voltage levels of the one or more memory cells using a neural network including a plurality of network parameters trained with the plurality of embedding parameters; and reading information bits from the memory device based on the set of predicted information bits.

Description

Technical Field

[0001] The following generally pertains to memory devices, and more specifically, to selecting the programming voltage for memory devices. Background Technology

[0002] Memory devices are common electronic components used to store data. NAND flash memory devices allow multiple bits of data to be stored in each memory cell (or storage unit), thus providing improvements in manufacturing cost and performance. Memory cells that store multiple bits of data are called multilevel (or multi-stage) memory cells. Multilevel memory cells divide the threshold voltage range of the memory cell into multiple voltage states, and the data value written to the memory cell is extracted using the memory cell voltage level.

[0003] The voltage level used to program memory cells can be manually determined based on theoretical considerations. However, manual selection of the voltage level does not provide the optimal voltage level for minimizing read errors. Therefore, there is a need in the art for an improved system for determining the voltage level used to program data into memory cells. Summary of the Invention

[0004] A method, apparatus, non-transitory computer-readable medium, and system for selecting a programming voltage for a memory device are described. Embodiments of the method, apparatus, non-transitory computer-readable medium, and system may include: programming a set of information bits into one or more memory cells using a neural network embedding based on a plurality of embedding parameters; determining a set of predicted information bits based on the voltage level of the memory cells using a neural network including a plurality of network parameters trained together with the plurality of embedding parameters; and reading information bits from the memory device based on the set of predicted information bits.

[0005] A method, apparatus, non-transitory computer-readable medium, and system for selecting a programming voltage for a memory device are described. Embodiments of the method, apparatus, non-transitory computer-readable medium, and system may initialize a plurality of embedding parameters and a set of network parameters; map a set of information bits to voltage levels of one or more memory cells based on the plurality of embedding parameters; identify a set of predicted information bits using an artificial neural network (ANN) based on network parameters; and update the plurality of embedding parameters and network parameters at least in part based on the set of predicted information bits.

[0006] An apparatus, system, and method for selecting a programming voltage for a memory device are described. Embodiments of the apparatus, system, and method may include: a plurality of memory cells; a programming component including an embedding layer based on a plurality of embedding parameters; and a reading component including a neural network based on a plurality of network parameters, wherein the plurality of network parameters are trained together with the plurality of embedding parameters. Attached Figure Description

[0007] Figure 1 An example of an implementation of a data processing system including a memory system according to aspects of this disclosure is shown.

[0008] Figure 2 This disclosure illustrates aspects of the present disclosure. Figure 1 An example of a memory system.

[0009] Figure 3 This disclosure illustrates aspects of the present disclosure. Figure 1 Examples of non-volatile memory devices.

[0010] Figure 4 This disclosure illustrates aspects of the present disclosure. Figure 3 An example of a memory cell array.

[0011] Figure 5 This disclosure illustrates aspects of the present disclosure. Figure 4 An example of a memory block in a memory cell array.

[0012] Figure 6 An example of a voltage level constellation according to aspects of this disclosure is shown.

[0013] Figure 7 An example of a learning-based memory system according to aspects of this disclosure is shown.

[0014] Figure 8 An example of a programming network according to aspects of this disclosure is shown.

[0015] Figure 9 An example of a network for reading information according to aspects of this disclosure is shown.

[0016] Figure 10 An example of the processing of an operating memory device according to aspects of this disclosure is shown.

[0017] Figure 11 An example of a process for programming information into a memory device according to aspects of this disclosure is shown.

[0018] Figure 12 An example is shown of the processing of an ANN trained according to aspects of this disclosure for selecting the programming voltage of a memory device. Detailed Implementation

[0019] This disclosure relates to systems and methods for programming and reading data from a memory device, and more specifically, for selecting a programming voltage for the memory device. Specific embodiments of the disclosure specifically relate to NAND flash memory devices capable of storing 5 bits or 6 bits of data in each memory cell.

[0020] Memory devices are common electronic components used to store data. NAND flash memory devices allow multiple bits of data to be stored in each memory cell, thus providing improvements in manufacturing cost and performance. Memory cells that store multiple bits of data are called multi-level (or multi-stage) memory cells. Multi-level memory cells divide the threshold voltage range of the memory cell into multiple voltage states, and the data value written to the memory cell is extracted using the memory cell voltage level.

[0021] To read information from a memory device, the voltage of each cell is measured and the voltage level stored in the cell is inferred. The bits can then be recovered. A trade-off may exist between the number of voltage levels and memory reliability. A larger number of bits per cell allows more information to be stored on the memory device; in this case, more bits exist in each cell. Alternatively, because a larger number of distinguishable voltages are used within the same dynamic range, voltages representing different levels can be more tightly packed together. As a result, noise during cell programming or cell reading has a greater chance of changing a voltage level to another voltage representing a different level, thus revealing errors when reading cells.

[0022] There are multiple noise sources in memory devices that can lead to erroneous readings of information (such as write noise, interference noise, aging, and read operations). Write noise is the voltage of a cell immediately following programming, which differs from the expected voltage due to the programming process. Interference noise is a function of the voltage of a cell that changes as a result of programming different neighboring cells. Programming a cell causes interference that affects other cells. Aging is the increase in noise the more times the device is written to and read from. Furthermore, the longer the time between cell programming, the more noise the cell will generate. In addition, read operations can cause noise and interference.

[0023] A memory device may be referred to as a channel. The term "channel" is used because write and / or send operations can enter and / or pass through a channel. When information is read, it can be corrupted by noise, depending on the characteristics of the medium.

[0024] Memory programming is based on the complex process of applying voltage to memory cells. However, cell voltage can be affected by variables such as current and voltage levels, pulse power, and inter-cell interference. Cell voltage can also be affected by suppressed cell disruption, word-line (WL) coupling, and cell retention. Furthermore, the results of writing to a NAND device can be random. For example, data can also be noise that causes observed problems.

[0025] Conventional methods for selecting programming voltages employ manual optimization techniques (such as trial and error). These manual processes do not provide optimal performance and may not include statistical data. Furthermore, successful metrics (such as target voltage) are application-specific and may not be applicable to multiple applications. Additionally, manual optimization can be resource-intensive and involves trade-offs across various metrics to allow other metrics to operate more quickly or efficiently.

[0026] Therefore, the systems and methods disclosed herein can be used to find improved programming voltages for cells. Specific methods for finding the programming voltage of a cell utilize a learning-based memory system. A learning-based memory system includes a programming network, NAND memory (or NAND channels), and a read network. The NAND memory may have multiple memory cells, each of which can be programmed using multiple different voltage levels.

[0027] Embodiments of this disclosure can be used in flash memory controllers. Furthermore, this disclosure offers advantages over current manual optimization methods in terms of bit error rate and rapid development compared to manual optimization methods.

[0028] This disclosure describes a method for finding an optimized constellation for modulation given a number of bits per cell N and a number of cells K. The method can be automatic and can have data driven by data from a real NAND channel, thus finding a constellation that is particularly well-suited to that channel. For a given number of bits per cell, embodiments of this disclosure can find a constellation that produces a small number of errors during reads.

[0029] This disclosure utilizes machine learning to find constellations. Training processes can be performed offline during product development (not for each specific NAND chip instance). The training results can then be applied to all instances of NAND chips with similar specifications.

[0030] The machine learning setup consists of a programming network module, a readout network, and NAND channels. The programming network takes voltage levels as input and returns a sequence of voltage levels. The programming network performs mappings by a constellation. The programming network continuously optimizes the voltage. The readout network predicts the raw information based on the voltage levels of the detected memory cells.

[0031] In the following description, exemplary embodiments of the inventive concept will be described more fully with reference to the accompanying drawings. Throughout the drawings, the same reference numerals may denote the same elements.

[0032] It will be understood that the terms “first,” “second,” “third,” etc., are used herein to distinguish one element from another, and the elements are not limited by these terms. Thus, a “first” element in an exemplary embodiment may be described as a “second” element in another exemplary embodiment.

[0033] It should be understood that, unless the context clearly indicates otherwise, the description of features or aspects within each exemplary embodiment should generally be considered applicable to other similar features or aspects in other exemplary embodiments.

[0034] As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form.

[0035] Here, when a value is described as approximately equal to another value, or substantially the same as or equal to another value, it will be understood that these values ​​are equal to each other within measurement error, or, if measurably unequal, are sufficiently close in value to be functionally equal, as would be understood by one of ordinary skill in the art. For example, considering the problems and errors associated with the measurement of a particular quantity (i.e., limitations of the measurement system), the term “approximately” as used herein includes stated values ​​and indicates an acceptable range of deviation for a particular value as determined by one of ordinary skill in the art. For example, “approximately” may mean within one or more standard deviations as understood by one of ordinary skill in the art. Furthermore, it will be understood that while a parameter may be described herein as having a “approximately” specific value, according to exemplary embodiments, a parameter may be an exact specific value or an approximate specific value within measurement error as would be understood by one of ordinary skill in the art.

[0036] Exemplary memory system

[0037] Figure 1 This is a block diagram illustrating an implementation of a data processing system including a memory system according to an exemplary embodiment of the inventive concept.

[0038] Reference Figure 1 The data processing system 10 may include a host 100 and a storage system 200. Figure 1The memory system 200 shown can be used in various systems that include data processing functions. These various systems can be devices including, for example, mobile devices (such as smartphones or tablet computers). However, the various devices are not limited to this.

[0039] The memory system 200 may include various types of memory devices. Here, exemplary embodiments of the inventive concept will be described as including memory devices as non-volatile memory. However, exemplary embodiments are not limited thereto. For example, the memory system 200 may include memory devices as volatile memory.

[0040] According to an exemplary embodiment, the memory system 200 may include non-volatile memory devices (such as read-only memory (ROM), magnetic disks, optical disks, flash memory, etc.). Flash memory may be a memory that stores data based on changes in the threshold voltage of a metal-oxide-semiconductor field-effect transistor (MOSFET), and may include, for example, NAND and NOR flash memory. The memory system 200 may be implemented using a memory card that includes non-volatile memory devices (such as embedded multi-media card (eMMC), secure digital card (SD) card, microSD card, or universal flash memory (UFS)), or the memory system 200 may be implemented using, for example, an SSD that includes non-volatile memory devices. Here, it is assumed that the memory system 200 is a non-volatile memory system, and the configuration and operation of the memory system 200 will be described. However, the memory system 200 is not limited thereto. The host 100 may include, for example, a system-on-a-chip (SoC) application processor (AP) mounted on a mobile device, or a central processing unit (CPU) included in a computer system.

[0041] As described above, host 100 may include AP 110. AP 110 may include various intellectual property (IP) blocks. For example, AP 110 may include memory device driver 111 that controls memory system 200. Host 100 may communicate with memory system 200 to send commands related to memory operations and receive acknowledgment commands in response to the sent commands. Host 100 may also communicate with memory system 200 regarding information tables (e.g., INFO_TABLE) related to memory operations.

[0042] The memory system 200 may include, for example, a memory controller 210 and a memory device 220. The memory controller 210 may receive commands related to memory operations from the host 100, generate internal commands and internal clock signals using the received commands, and provide the internal commands and internal clock signals to the memory device 220. The memory device 220 may, in response to an internal command, store write data in a memory cell array, or may, in response to an internal command, provide read data to the memory controller 210.

[0043] Memory device 220 includes an array of memory cells that retains data stored therein even when memory device 220 is not powered on. The memory cell array may include memory cells (e.g., NAND or NOR flash memory, magnetoresistive random access memory (MRAM), resistive random access memory (RRAM), ferroelectric random access memory (FRAM), or phase-change memory (PCM)). For example, when the memory cell array includes NAND flash memory, the memory cell array may include multiple blocks and multiple pages. Data can be programmed and read in units of pages, and data can be erased in units of blocks. Figure 4 The image shows an example of a memory block included in a memory cell array.

[0044] Figure 2 This illustrates exemplary embodiments based on the inventive concept. Figure 1 Block diagram of the memory system 200.

[0045] Reference Figure 2 The memory system 200 includes a memory device 220 and a memory controller 210. The memory controller 210 may also be referred to herein as a controller circuit. The memory device 220 can perform write operations, read operations, or erase operations under the control of the memory controller 210.

[0046] The memory controller 210 can control the memory device 220 according to a request received from the host 100 or an internally specified schedule. The memory controller 210 may include a controller core 211, internal memory 214, a host interface block 215, and a memory interface block 216. The memory controller 210 may also include a device information storage device 217, which is configured to provide first device information DI1 to the host interface block 215 and second device information DI2 to the controller core 211.

[0047] The controller core 211 may include a memory control core 212 and a machine learning core 213, and each of these cores may be implemented by one or more processors. The memory control core 212 may control and access the memory device 220 according to requests received from the host 100 or internally specified scheduling. The memory control core 212 may manage and execute various metadata and code for managing or operating the memory system 200.

[0048] As described in further detail below, the machine learning kernel 213 can be used to perform training and inference of a neural network designed to perform noise cancellation on the memory device 220.

[0049] Internal memory 214 can be used as, for example, system memory used by controller core 211, cache memory for storing data in memory device 220, or a buffer memory for temporarily storing data between host 100 and memory device 220. Internal memory 214 may store a mapping table MT indicating the relationship between logical addresses allocated to memory system 200 and physical addresses of memory device 220. Internal memory 214 may include, for example, DRAM or SRAM.

[0050] In an exemplary embodiment, a neural network (such as, referenced) Figure 9 The described read network may be included in the internal memory 214 of the memory controller 210 or in a computer program stored in the memory device 220. The computer program including the neural network may be executed by the machine learning kernel 213 to denoise the data stored in the memory device 220. Therefore, according to an exemplary embodiment, the memory system 200 may denoise the data stored in the memory device 220 during normal read operations. That is, after the memory system 200 is manufactured, during normal operation of the memory system 200, specifically during normal read operations of the memory system 200 that read data from the memory device 220, the data being read from the memory device 220 may be denoised using a neural network locally stored and executed in the memory system 200, and the denoised data may be read from the memory device 220.

[0051] Host interface block 215 may include components (such as a physical block) for communicating with host 100. Memory interface block 216 may include components (such as a physical block) for communicating with memory device 220.

[0052] The operation of the memory system 200 over time will now be described. When power is supplied to the memory system 200, the memory system 200 can perform initialization with the host 100.

[0053] The host interface block 215 may provide the memory control core 212 with a first request REQ1 received from the host 100. The first request REQ1 may include a command (e.g., a read command or a write command) and a logical address. The memory control core 212 may translate the first request REQ1 into a second request REQ2 suitable for the memory device 220.

[0054] For example, memory control core 212 can convert the format of commands. Memory control core 212 can obtain address information AI by referring to the mapping table MT stored in internal memory 214. Memory control core 212 can translate logical addresses into physical addresses of memory device 220 using the address information AI. Memory control core 212 can provide a second request REQ2 suitable for memory device 220 to memory interface block 216.

[0055] The memory interface block 216 can register a second request REQ2 from the memory control core 212 in a queue. The memory interface block 216 can send the request that was first registered in the queue as a third request REQ3 to the memory device 220.

[0056] When the first request REQ1 is a write request, the host interface block 215 can write the data received from the host 100 to the internal memory 214. When the third request REQ3 is a write request, the memory interface block 216 can send the data stored in the internal memory 214 to the memory device 220.

[0057] When the data has been fully written, the memory device 220 may send a third response RESP3 to the memory interface block 216. In response to the third response RESP3, the memory interface block 216 may provide a second response RESP2 to the memory control core 212, indicating that the data has been fully written.

[0058] After the data is stored in the internal memory 214 or after the second response RESP2 is received, the memory control core 212 can send the first response RESP1, indicating that the request has been completed, to the host 100 via the host interface block 215.

[0059] When the first request REQ1 is a read request, the read request can be sent to the memory device 220 via the second request REQ2 and the third request REQ3. The memory interface block 216 can store the data received from the memory device 220 in the internal memory 214. When the data has been completely sent, the memory device 220 can send a third response RESP3 to the memory interface block 216.

[0060] When the third response RESP3 is received, the memory interface block 216 can provide the memory control core 212 with a second response RESP2 indicating that the data has been fully read. When the second response RESP2 is received, the memory control core 212 can send the first response RESP1 to the host 100 through the host interface block 215.

[0061] The host interface block 215 can send data stored in the internal memory 214 to the host 100. In an exemplary embodiment, if the data corresponding to the first request REQ1 is stored in the internal memory 214, the transmission of the second request REQ2 and the third request REQ3 can be omitted.

[0062] The memory device 220 can also send the first serial peripheral interface information SPI1 to the memory interface block 216. The memory interface block 216 can send the second serial peripheral interface information SPI2 to the controller core 211.

[0063] Figure 3 This is an exemplary embodiment of the concept of the present invention. Figure 1 A detailed block diagram of the non-volatile memory device 220. (Refer to...) Figure 3 The memory device 220 may include, for example, a memory cell array 221, control logic 222, a voltage generation unit 223, a row decoder 224, and a page buffer 225.

[0064] The memory cell array 221 can be connected to one or more serial select lines SSL, multiple word lines WL, one or more ground select lines GSL, and multiple bit lines BL. The memory cell array 221 may include multiple memory cells disposed at the intersections between the multiple word lines WL and the multiple bit lines BL.

[0065] Control logic 222 can receive commands (e.g., internal commands) and addresses (ADD) from memory controller 210, and also receives control signals (CTRL) from memory controller 210 for controlling various functional blocks within memory device 220. Control logic 222 can output various control signals for writing data to or reading data from memory cell array 221 based on commands (CMD), addresses (ADD), and control signals (CTRL). In this way, control logic 222 can control the overall operation of memory device 220.

[0066] Various control signals output by control logic 222 can be provided to voltage generation unit 223, row decoder 224, and page buffer 225. For example, control logic 222 can provide voltage control signal CTRL_vol to voltage generation unit 223, row address X-ADD to row decoder 224, and column address Y-ADD to page buffer 225.

[0067] The voltage generation unit 223 can generate various voltages for performing programming, reading, and erasing operations on the memory cell array 221 based on the voltage control signal CTRL_vol. For example, the voltage generation unit 223 can generate a first driving voltage VWL for driving multiple word lines WL, a second driving voltage VSSL for driving multiple string select lines SSL, and a third driving voltage VGSL for driving multiple ground select lines GSL. In this case, the first driving voltage VWL can be a programming voltage (e.g., write voltage), a read voltage, an erase voltage, a pass voltage, or a programming verification voltage. Furthermore, the second driving voltage VSSL can be a string select voltage (e.g., on or off voltage). Furthermore, the third driving voltage VGSL can be a ground select voltage (e.g., on or off voltage).

[0068] The row decoder 224 can be connected to the memory cell array 221 via multiple word lines WL, and can activate a portion of the multiple word lines WL in response to a row address X-ADD received from the control logic 222. For example, in a read operation, the row decoder 224 can apply a read voltage to the selected word line and apply a pass voltage to the unselected word line.

[0069] During programming operations, the line decoder 224 may apply a programming voltage to selected word lines and apply a pass voltage to unselected word lines. In one exemplary embodiment, in at least one of a plurality of programming cycles, the line decoder 224 may apply a programming voltage to selected word lines and additionally selected word lines.

[0070] Page buffer 225 can be connected to memory cell array 221 via multiple bit lines BL. For example, in a read operation, page buffer 225 can operate as a sense amplifier that outputs data stored in memory cell array 221. Alternatively, in a programming operation, page buffer 225 can operate as a write driver that writes desired data to memory cell array 221.

[0071] Figure 4 and Figure 5 An example of implementing a memory system 200 using three-dimensional flash memory is shown. The three-dimensional flash memory may include three-dimensional (e.g., vertical) NAND (e.g., VNAND) memory cells. An implementation of a memory cell array 221 including three-dimensional memory cells is described below. Each of the memory cells described below may be a NAND memory cell.

[0072] Figure 4 This is an exemplary embodiment of the concept of the present invention. Figure 3 A block diagram of the memory cell array 221.

[0073] Reference Figure 4The memory cell array 221 according to an exemplary embodiment includes a plurality of memory blocks BLK1 to BLKz (where z is a positive integer greater than 1). Each of the memory blocks BLK1 to BLKz has a three-dimensional structure (e.g., a vertical structure). For example, each of the memory blocks BLK1 to BLKz may include a structure extending upward in a first direction to a third direction. For example, each of the memory blocks BLK1 to BLKz may include a plurality of NAND strings extending in a second direction. The plurality of NAND strings may be arranged, for example, upward in the first direction to a third direction.

[0074] Each NAND string is connected to the bit line BL, the string select line SSL, the ground select line GSL, the word line WL, and the common source line CSL. That is, each of the memory blocks BLK1 to BLKz can be connected to multiple bit lines BL, multiple string select lines SSL, multiple ground select lines GSL, multiple word lines WL, and multiple common source lines CSL. The following will refer to... Figure 5 Memory blocks BLK1 to BLKz are described in further detail.

[0075] Figure 5 This is a circuit diagram of a memory block BLKi according to an exemplary embodiment of the present invention. Figure 5 Show Figure 4 An example of one of the memory blocks BLK1 to BLKz in the memory cell array 221. Figure 5 The number of memory cells and word lines depicted is merely an example, and any suitable number of memory cells and word lines can be used.

[0076] The memory block BLKi may include multiple cell strings CS11 to CS41 and CS12 to CS42. The multiple cell strings CS11 to CS41 and CS12 to CS42 may be arranged in column and row directions to form columns and rows. Each of the cell strings CS11 to CS41 and CS12 to CS42 may include a ground selection transistor GST, memory cells MC1 to MC6, and a string selection transistor SST. The ground selection transistor GST, memory cells MC1 to MC6, and string selection transistor SST included in each of the cell strings CS11 to CS41 and CS12 to CS42 may be stacked in a height direction substantially perpendicular to the substrate.

[0077] Columns of multiple cell strings CS11 to CS41 and CS12 to CS42 can be connected to different string select lines SSL1 to SSL4 respectively. For example, the string select transistors SST of cell strings CS11 and CS12 can be connected together to string select line SSL1. The string select transistors SST of cell strings CS21 and CS22 can be connected together to string select line SSL2. The string select transistors SST of cell strings CS31 and CS32 can be connected together to string select line SSL3. The string select transistors SST of cell strings CS41 and CS42 can be connected together to string select line SSL4.

[0078] Rows of multiple cell strings CS11 to CS41 and CS12 to CS42 can be connected to different bit lines BL1 and BL2, respectively. For example, the string select transistors SST of cell strings CS11 to CS41 can be connected to bit line BL1 together. The string select transistors SST of cell strings CS12 to CS42 can be connected to bit line BL2 together.

[0079] Columns of multiple cell strings CS11 to CS41 and CS12 to CS42 can be connected to different ground select lines GSL1 to GSL4 respectively. For example, the ground select transistors GST of cell strings CS11 and CS12 can be connected to ground select line GSL1. The ground select transistors GST of cell strings CS21 and CS22 can be connected to ground select line GSL2. The ground select transistors GST of cell strings CS31 and CS32 can be connected to ground select line GSL3. The ground select transistors GST of cell strings CS41 and CS42 can be connected to ground select line GSL4.

[0080] Memory cells positioned at the same height from the substrate (or ground select transistor GST) can be connected to a single word line, while memory cells positioned at different heights from the substrate can be connected to different word lines WL1 to WL6. For example, memory cell MC1 can be connected to word line WL1. Memory cell MC2 can be connected to word line WL2. Memory cell MC3 can be connected to word line WL3. Memory cell MC4 can be connected to word line WL4. Memory cell MC5 can be connected to word line WL5. Memory cell MC6 can be connected to word line WL6. The ground select transistors GST of cell strings CS11 to CS41 and CS12 to CS42 can be connected to the common source line CSL.

[0081] modulation

[0082] Figure 6An example of a voltage level constellation 600 according to aspects of this disclosure is shown. Voltage level constellation 600 represents an example of a modulation scheme that can be used to program data into a memory device according to embodiments of this disclosure. The modulation scheme may involve grouping memory cells into a given number (represented by K) of groups and dividing the voltage level of each memory cell into discrete levels (represented by N).

[0083] The voltage level constellation 600 comprises two cells with two bits per cell (bpc), i.e., N = 2 bpc and K = 2 cells. However, in other examples, different numbers of cells and bpcs may be used. Each cell is represented as an axis, and each information symbol 605 is represented by a pair of voltage levels (one voltage level per cell). The number of cells determines the number of axes, and the bpc determines the number of potential voltage levels.

[0084] For example, if bpc = N, then the number of voltage levels per unit can be 2. N Therefore, there are two axes, each with four levels, such that the voltage level constellation 600 includes 16 information symbols 605. Note that the positions of the information symbols 605 are not perfectly aligned. That is, the voltage levels may be unevenly spaced, and the voltage levels may not be the same for each unit.

[0085] Therefore, modulation can be used to write information into NAND devices. In short, instead of writing N bits per cell, modulation writes N×K bits per K cells. To store the bitstream into the NAND device, the information stream is divided into groups of (N×K) bits. Each group can have a value of 2. N×K There are several different combinations. Therefore, execution proceeds from each group to the range [0, (2... N×K The mapping of the number L in [-1)].

[0086] A single level is written to each non-interleaved set of K cells. Each level is associated with a unique sequence of K voltages (such as V1(L), V2(L), ..., VK(L)) through a fixed, predetermined mapping. Therefore, in order to store level L in K cells, the first cell to voltage V1(L), the second cell to voltage V2(L), and so on are jointly programmed.

[0087] If the constellation is calculated correctly, modulation increases reliability (e.g., reduces the bit error rate). This is true when there is interference noise between the jointly programmed units. In the telecommunications field, modulation is widely used for similar reasons. A suitable modulation scheme can be selected based on the physical channel and communication needs.

[0088] Modulation can provide the number of bits per unit to store a non-integer number of bits. For example, we can store 3 bits per unit by storing 7 bits in 2 units.1 / 2 bits. In other words, if we have 128 (128 = 2...) 7 If we write 128 levels on 2 units, then in terms of bits per unit, this is equivalent to 3 levels per unit. 1 / 2 bits.

[0089] In another example, even if N×K is not an integer, in 2 (N×K) Even with integer limitations, a non-integer number of bits per unit can be used. For example, a memory device could be based on K=3 units, and 2 (N×K) =30000. In this case, since the number of bits is N×K, and N×K may not be an integer, there may be a challenge in determining the set of information bits to be detected. That is, Therefore, this case (where N×K is not an integer) is limited to two conditions: 1) the number of information bits is obtained by rounding N×K to the nearest integer (i.e., 15 in this example), and 2) some combinations of information bits are not allowed in the input and output. This means that for the input, there can be fewer than 2... 15 There are several options. For example, the maximum number of allowed combinations is 30,000.

[0090] According to various embodiments, the programming voltage selection of a cell can be performed using a pulse amplitude modulation (PAM) algorithm, where the encoded bits are divided into groups of a number of bits per cell. For example, in a three-level cell (TLC), the number of bits per cell is 3. Each group of cells is called a symbol. For example, a symbol with bits 010 is equal to 2. The NV dynamic range is divided into 2 groups per cell. N Bits. For example, the 3V dynamic range is divided into 8 target voltages. Each target voltage is mapped to a symbol using Gray code, where only a single bit changes between adjacent target voltages. For example, if the dynamic range is between -3V and 4V, then the modulation for -3V is 111, for -2V it is 110, for -1V it is 100, for 0V it is 101, for 1V it is 001, for 2V it is 000, for 3V it is 010, and for 4V it is 011.

[0091] The example modulation corresponds to an additive white Gaussian noise (AWGN) channel. However, in many cases, the NAND channel and the AWGN channel are not the same, and PAM modulation is not necessarily optimal for the NAND channel. Optionally, heuristic optimization can be performed to find a target voltage with improved performance.

[0092] Learning-based memory

[0093] Figure 7An example of a learning-based memory system according to aspects of this disclosure is shown. The example shown includes a programming network 700, a memory device 705, and a read network 710.

[0094] In some examples, the programming network 700 and the reading network 710 may include an artificial neural network (ANN). An ANN can be a hardware or software component comprising multiple connected nodes (aka artificial neurons) that roughly correspond to neurons in the human brain. Each connection or edge (like a physical synapse in the brain) sends a signal from one node to another. When a node receives a signal, it processes the signal and then sends the processed signal to other connected nodes. In some cases, the signals between nodes include real numbers, and the output of each node can be computed as a function of the sum of the inputs to each node. Each node and edge may be associated with one or more node weights that determine how the signal is processed and sent.

[0095] It should be noted that this description of ANN is more descriptive than words. In other words, it describes one way to interpret ANN, but not necessarily how it is implemented. In the hardware or software implementation of ANN, sending and receiving signals may not be performed literally.

[0096] During training, these weights can be adjusted to improve the accuracy of the results (i.e., by minimizing a loss function that corresponds in some way to the difference between the current result and the target result). Edge weights can increase or decrease the strength of the signal transmitted between nodes. In some cases, nodes may have a threshold below which no signal is transmitted. Nodes can also be aggregated into layers. Different layers can perform different transformations on the inputs of different layers. The initial layer may be called the input layer, and the last layer may be called the output layer. In some cases, a signal may pass through a specific layer multiple times.

[0097] The programming network 700 maps a set of information bits to voltage levels of one or more memory cells based on a set of embedding parameters. The programming network 700 can program this set of information bits into one or more memory cells based on the mapping. The programming network 700 can also apply Gray code to this set of information bits, where the mapping is based on Gray code. In some examples, multiple memory cells may exist, and the set of embedding parameters comprises an array with a dimension equal to the number of memory cells. The dimension may differ from the number of elements in the array. For example, the number of elements in the array may be equal to the number of possible voltage levels (i.e., 2^32). (N×K) And each element of the array can be a K-dimensional vector.

[0098] Before training, the programming network 700 and the reading network 710 can be initialized with a set of embedding parameters and a set of network parameters. The programming network 700 may include a programming component containing embedding layers based on the set of embedding parameters. In some examples, the programming component also includes sigmoid layers and scaling layers. The programming network 700 can be a reference... Figure 8 Examples of one or more corresponding elements described or including references Figure 8 Aspects of one or more corresponding elements described.

[0099] The programming network 700 maps input symbols to "in", where "in" is taken from a finite discrete set K. For example, the input to the programming network can be a single symbol, which can be taken from the set [0,…,2]. (N×K) Any value of _1], where the input consists of N×K bits.

[0100] Furthermore, the programming network 700 can convert input symbols into programming voltages x1,...,xK. Unknown noise n is added to the channels such that y = x + n, where y represents the output of the memory device 705 and x represents the programming voltages x1,...,xK. The read network 710 retrieves the input symbol “in_predicted”. The output of the read network may include more than just predictions of the input symbols. For example, the output may include a score (or probability) for each possible input symbol. The symbol with the highest score (e.g., “predicted”) may be used as the prediction, but all scores may be used when the loss function (e.g., cross-entropy) is calculated.

[0101] In some examples, the programming network 700 and the reading network 710 can be trained together. For example, the programming network 700 and the reading network 710 can be trained by minimizing the cross-entropy between "in" and "in_predicted" or by using some other suitable loss function.

[0102] Example programming network 700 may contain embedding layers. Input can be from 2... (N×K) A single symbol representing a set of N×K bits. That is, the input can be N×K bits, and the output can be a sequence of K voltages.

[0103] Furthermore, the programming network 700 may include an S-shaped layer and a scaling layer for scaling to the dynamic range of the memory cell. Therefore, the programming network 700 finds the programming voltage of the cell.

[0104] Memory device 705 may include, as referenced Figures 1 to 5This describes a group of memory cells. In some examples, this group of memory cells includes NAND memory cells. The memory cells can be set to a specified voltage within a range known as the dynamic range. The terms write and program are used to describe the process of setting the cells to the desired voltage.

[0105] Below is an example process for storing information on a NAND device. Given a bitstream (b1, b2, b3, b4, b5, b6, b7, b8, b9, b10…), these bits are grouped into groups of size N bits. For example, if N = 4, these groups are represented as (b1, b2, b3, b4), (b5, b6, b7, b8), (b9, b10, b11, b12), etc., where N is the number of bits per unit. For each N-bit group, there exists a value of 2. N Different combinations. Therefore, execution proceeds from each group to the range [0, (2... N The mapping of integers L in [-1)]. The number L represents the level. A single level is written to each memory cell. Each level is associated with a unique voltage V(L) through a fixed, predetermined mapping. This type of mapping is called a constellation, where a constellation represents a mapping from level to voltage. Therefore, in order to store the level L in a cell, the voltage V(L) is programmed into that cell.

[0106] To read information from memory device 705, the voltage of each cell is measured and the voltage level stored in the cell is inferred. The bits can then be recovered. In some cases, there may be a trade-off between the value of N and memory reliability. The larger the value of N, the more information can be stored on the memory device, in which case more bits exist in each cell. Optionally, because a larger number of distinguishable voltages are used within the same dynamic range, voltages representing different levels can be more tightly packed together. As a result, noise in cell programming or cell reading has a greater chance of changing a voltage level to another voltage representing a different level, thus revealing errors when reading cells.

[0107] Multiple noise sources exist in the memory device 705 that can lead to erroneous reading of information (such as write noise, interference noise, aging, and read operations). Write noise is the cell voltage immediately following programming, which differs from the expected voltage due to the programming process. Interference noise is a function of the cell voltage that changes as different neighboring cells are programmed. Programming cells cause interference that affects other cells. Aging is the increase in noise the more times the memory device 705 is written to and read from. Furthermore, the longer the time between cell programming, the more noise the cell will generate. In addition, read operations can cause noise and interference.

[0108] The memory device 705 may be referred to as a channel. The term channel is used because write and / or send operations can enter and / or pass through the channel. When information is read, it will be corrupted by noise, depending on the characteristics of the medium.

[0109] The read network 710 detects the voltage levels of one or more memory cells to generate one or more detected voltage levels. The read network 710 can then use a neural network including a set of network parameters to identify a set of predicted information bits based on the one or more detected voltage levels. In some cases, the network parameters are trained together with embedding parameters.

[0110] According to one embodiment, the readout network 710 can use a neural network to generate a set of information bit probabilities based on detected voltage levels. The readout network 710 can then select the highest information bit probability from this set of information bit probabilities. In some cases, the predicted information bits are identified based on the highest information bit probability.

[0111] The reading network 710 can use an ANN based on network parameters to identify a set of predicted information bits. The reading network 710 may include a reading component, which comprises a neural network based on a set of network parameters. In some cases, the network parameters are trained together with embedding parameters. In some examples, the neural network includes a probability-based classifier. The reading network 710 may be a reference... Figure 9 Examples of one or more corresponding elements described or including references Figure 9 Aspects of one or more corresponding elements described.

[0112] Figure 8 An example of a programming network 800 according to aspects of this disclosure is shown. The programming network 800 may be a reference... Figure 7 Examples of one or more corresponding elements described or including references Figure 7 The description refers to aspects of one or more corresponding elements. The programming network 800 may include an embedding layer 805, an S-shaped layer 810, and a scaling layer 815.

[0113] Embedding layer 805 embeds a set of information bits into the embedding space based on embedding parameters to generate embedded symbols. Sigmoid layer 810 applies a sigmoid function to constrain the embedded information symbols to generate constrained symbols. Scaling layer 815 scales the constrained symbols to generate scaled symbols corresponding to voltages within the effective dynamic range. In some cases, the set of information bits is mapped based on the scaled symbols.

[0114] Figure 9 An example of a read network 900 according to aspects of this disclosure is shown. The read network 900 may be a reference... Figure 7 Examples of one or more corresponding elements described or including referencesFigure 7 The description refers to aspects of one or more corresponding elements. As shown, the readout network 900 may be a neural network comprising one or more fully connected layers (e.g., fully connected linear layers) 905 and one or more Rectified Linear Unit (ReLU) layers 910. In some examples, the fully connected layer 905 and the ReLU layer 910 are as follows: Figure 9 The arrangement is shown as an alternation. However, this arrangement is used as an example; any suitable neural network capable of learning the voltage level of the detection associated with the information bits can be used.

[0115] In some cases, one or more batch normalization operations can be used during the training of a neural network. In others, networks incorporating batch normalization can use higher learning rates without causing gradient vanishing or exploding. Furthermore, batch normalization can regularize the network, making it easier to generalize. Therefore, in some cases, dropout may not be necessary to mitigate overfitting. The network can also become more robust to different initialization schemes and learning rates. Batch normalization can be achieved by fixing the mean and variance of the inputs to each layer. In some cases, normalization can be performed over the entire training set. In other cases, normalization is restricted to each mini-batch during training.

[0116] In neural networks, activation functions are used to transform the weighted input from a node into the node's activation or output. ReLU layers can implement modified linear activation functions, which include piecewise linear functions. If the input is positive, the piecewise linear function outputs the input directly; otherwise, it outputs zero. Modified linear activation functions can be used as the default activation function for many types of neural networks.

[0117] Using the modified linear activation function (RLU) allows for the training of deep neural networks using stochastic gradient descent and backpropagation. RLU operates similarly to a linear function, but it enables the learning of complex relationships within the data. RLU also provides higher sensitivity to the sum of inputs to avoid saturation. Nodes or units implementing RLU are called modified linear activation units, or simply ReLU. Networks that use the modified function in their hidden layers are called modified networks.

[0118] operate

[0119] Figure 10 An example of processing of an operating memory device according to aspects of this disclosure is shown. According to various embodiments, the memory device may include an ANN, and operation of the memory device may include finding the output of the ANN based on voltage levels read from the memory device.

[0120] In some examples, these operations may be performed by a system including a processor that executes a set of code to control functional elements of the device. Additionally or alternatively, dedicated hardware may be used to perform the processing. Typically, these operations may be performed based on the methods and processes described in accordance with aspects of this disclosure. For example, the operations may consist of individual sub-steps or may be performed in combination with other operations described herein.

[0121] In operation 1000, the system maps a set of information bits to the voltage levels of one or more memory cells based on a set of embedding parameters. In some cases, this step can be referenced as follows. Figure 7 and Figure 8 The described programming network execution or can be performed by, as referenced Figure 7 and Figure 8 The described programming network execution. In some cases, it can be based on the use of references. Figure 6 The voltage level constellation described is used to map information bits using a modulation scheme. For example, programming network parameters may include the voltage level of each of multiple cells corresponding to each symbol in the constellation. (See reference...) Figure 11 Describe further details regarding the processing used to map information bits.

[0122] In operation 1005, the system programs the group of information bits into one or more memory cells based on the mapping. In some cases, this step can be referenced as follows. Figure 7 and Figure 8 The described programming network execution or can be performed by, as referenced Figure 7 and Figure 8 The program describes network execution.

[0123] Specifically, the programming network may include an embedding layer 2. N×K →K, Embedded layer 2 N×K →K may include the range [0, (2... N×K A table mapping integers in [-1)] to sequences of real numbers of length K. All entries in the table are treated as independent variables that can be optimized.

[0124] The output of the embedded layer is passed through a sigmoid function, which is a continuously differentiable monotonic function that takes the input and converts it into a number in the range [0,1]. Each element of a sequence of length K is passed through the sigmoid function. The result of this function is then rescaled to the range [VMIN, VMAX], where VMIN and VMAX are the minimum and maximum allowable voltages (i.e., the dynamic range). Rescaling is performed using the function x→x×(VMAX-VMIN)+VMIN. The sigmoid function and rescaling ensure that the output of the programmed network is within the effective range.

[0125] In operation 1010, the system detects the voltage level of one or more memory cells to generate one or more detected voltage levels. In some cases, this step can be referenced as follows: Figure 7 and Figure 9 The described reading network or can be obtained from, as referenced Figure 7 and Figure 9 The description reads the network execution.

[0126] In operation 1015, the system uses a neural network comprising a set of network parameters to identify a set of predicted information bits based on one or more detected voltage levels, wherein the network parameters are trained together with the embedding parameters. In some cases, this step can be referenced as follows. Figure 7 and Figure 9 The described reading network or can be obtained from, as referenced Figure 7 and Figure 9 The described read network performs this action. For example, the read network can identify predicted constellation symbols and identify a set of information bits associated with those symbols.

[0127] The read network can be a neural network classifier that takes a sequence of K voltages read from K cells of a memory device as input and returns a prediction of which level was written to those K cells. The read network can be any neural network or any differentiable model. The number of outputs of the read network is 2^k. N×K , of which 2 N×K Each of the numbers represents a fraction of the corresponding level given by the read network. For example, the fraction could represent the probability of being at the corresponding level. The channel can be a real memory channel or a model of a memory channel.

[0128] Figure 11 Examples of processes for programming information into a memory device according to aspects of this disclosure are shown. In some examples, these operations may be performed by a system including a processor that executes a set of code to control functional elements of the device. Additionally or alternatively, dedicated hardware may be used to perform the processing. Typically, these operations may be performed based on the methods and processes described according to aspects of this disclosure. For example, the operations may consist of individual sub-steps or may be performed in combination with other operations described herein.

[0129] In operation 1100, the system embeds the set of information bits into the embedding space based on the embedding parameters to generate an embedding symbol. In some cases, this step can be referenced as follows: Figure 8 The described embedding layer or may be derived from, as referenced Figure 8 The described embedded layer execution.

[0130] In operation 1105, the system applies a sigmoid function to constrain the embedded information symbols to generate constraint symbols. In some cases, this step can be referenced as follows: Figure 8 The described S-shaped layer or as referenced Figure 8 The S-shaped layer is described.

[0131] In operation 1110, the system scales the constraint symbols to produce scaled symbols corresponding to the voltages within the effective dynamic range, wherein the set of information bits is mapped based on the scaled symbols. In some cases, this step can be referenced as follows: Figure 8 The scaling layer or this step described can be referenced as follows. Figure 8 The scaling layer described is executed.

[0132] train

[0133] Figure 12 Examples of processes for training an ANN for selecting a programming voltage for a memory device, according to aspects of this disclosure, are shown. In some examples, these operations may be performed by a system including a processor that executes a set of code to control functional elements of the device. Additionally or alternatively, dedicated hardware may be used to perform the processes. Typically, these operations may be performed based on the methods and processes described in aspects of this disclosure. For example, the operations may consist of individual sub-steps or may be performed in combination with other operations described herein.

[0134] In operation 1200, the system initializes a set of embedding parameters and a set of network parameters. In some cases, this step can be referenced as follows: Figure 7 and Figure 8 The described programming network or can be obtained from, as referenced Figure 7 and Figure 8 The described programming network execution. In some examples, the training process randomly initializes the parameters of the programming network (i.e., the values ​​in the embedding layers). Then, the training process randomly initializes the parameters (weights and biases) of the read network.

[0135] In operation 1205, the system maps a set of information bits to the voltage levels of one or more memory cells based on embedding parameters. For example, the mapping may be based on the reference above. Figure 6 The programming constellation is described. In some cases, the operation of this step can be referenced as follows: Figure 7 and Figure 8 The described programming network or can be obtained from, as referenced Figure 7 and Figure 8 The program describes network execution.

[0136] In operation 1210, the system uses an ANN based on network parameters to identify a set of predicted information bits. In some cases, this step can be referenced as follows.Figure 7 and Figure 9 The described reading network or can be obtained from, as referenced Figure 7 and Figure 9 The description reads the network execution.

[0137] In operation 1215, the system updates the embedding parameters and network parameters, at least in part, based on the set of predicted information bits. For example, the parameters may be updated based on the output of the ANN, which may include additional information beyond the predicted information. Specifically, the ANN output may include scores for various combinations of information bits. In some cases, this step may be performed by or with reference to the training component.

[0138] The process of generating output using an ANN and then updating the ANN's parameters can be repeated multiple times before the training process is complete. For example, the training process can continue until a threshold accuracy is achieved, until a predetermined number of training iterations have been performed, or until the network parameters converge. According to one embodiment, the system can update the network parameters based on the embedding parameters to produce updated network parameters; and update the embedding parameters based on the updated network parameters to produce updated embedding parameters.

[0139] According to one embodiment, updating the network parameters can be accomplished using the following algorithm. For each iteration of the algorithm of this disclosure, the programming network and the reading network are optimized, and the cross-entropy is minimized. That is, the system can perform multiple training iterations, wherein the embedding parameters and network parameters are updated during each training iteration in the multiple training iterations. For each iteration, the cross-entropy is optimized twice. Let P(θ) be the programming network. Let R(φ) be the reading network. “Info” refers to the mini-batch of information bits used per network. It refers to a small batch of estimated information bits read from the network output. The variable λ φ , λ θ Indicates the learning rate. CrossEntropy(info, ) represents cross-entropy.

[0140]

[0141] Example training algorithm

[0142] Therefore, according to a specific embodiment, the loss function can be calculated using the predicted score and the actual voltage level. One option for the loss function is cross-entropy, but other options also exist. The gradient of the loss is calculated for all optimizable parameters in both the programming and reading networks. For example, the gradient of the classification loss function for the set of information bits and the set of predicted information bits is calculated, where the embedding parameters or network parameters are updated based on the gradient of the classification loss function. The parameters are updated using the gradient to minimize the loss. Any suitable optimization algorithm (such as stochastic gradient descent, Adam, etc.) can be used to perform the update. These steps are repeated until convergence occurs. An additional variation in training is switching between updating the programming network and updating the reading network at each step.

[0143] Note that gradients can be computed during training. Gradients can be computed as functions that are differentiable and have a well-defined mathematical form. Programming networks and reading networks are such functions and can be differentiated using standard libraries (such as TensorFlow and PyTorch). If a real memory model is used in the training loop, it cannot be differentiated through the training loop due to the lack of a mathematical expression. Therefore, an estimate called a reinforcement estimate can be used. In one example, the memory model can be updated based on data from additional memory cells.

[0144] Alternatively, a memory model can be used. A memory model is a generative model that takes K voltages as input and returns K voltages representing the voltages corrupted by noise. The generative model can be any mathematical expression (such as a parametric Gaussian model or a generative adversarial network) that is differentiable and has random components. The memory model can be used in conjunction with measurements collected from a physical memory device, such that the memory model mimics the behavior of a real memory as closely as possible. Fitting the generative model is a known training process. In other words, the memory model simulates the noise distribution of a real memory device. Once fitted, the memory model can be used in the training process described above, and the memory model can be differentiable.

[0145] When the memory model option is used, the model can be refitted during optimization. Refitting is necessary because memory and behavior can change depending on the constellation used. Therefore, after multiple steps of updating the programmed network, new measurements can be collected from the real memory device using the current constellation, and these measurements can be used to refit the memory model and continue training.

[0146] Therefore, this disclosure includes the following embodiments.

[0147] A method for selecting a programming voltage for a memory device is described. Embodiments of the method may include: mapping a set of information bits to voltage levels of one or more memory cells based on a plurality of embedding parameters; programming the set of information bits into the one or more memory cells based on the mapping; detecting voltage levels of the one or more memory cells to generate one or more detected voltage levels; and using a neural network including a plurality of network parameters to identify a set of predicted information bits based on the one or more detected voltage levels, wherein the plurality of network parameters are trained together with the plurality of embedding parameters.

[0148] A device for selecting a programming voltage for a memory device is described. The device may include a processor, a memory in electronic communication with the processor, and instructions stored in the memory. The instructions may be operable to cause the processor to: map a set of information bits to voltage levels of one or more memory cells based on a plurality of embedding parameters; program the set of information bits into the one or more memory cells based on the mapping; detect voltage levels of the one or more memory cells to generate one or more detected voltage levels; and identify a predicted set of information bits based on the one or more detected voltage levels using a neural network including a plurality of network parameters, wherein the plurality of network parameters are trained together with the plurality of embedding parameters.

[0149] A non-transitory computer-readable medium is described, storing code for selecting a programming voltage for a memory device. In some examples, the code includes instructions executable by a processor to: map a set of information bits to voltage levels of one or more memory cells based on a plurality of embedding parameters; program the set of information bits into the one or more memory cells based on the mapping; detect voltage levels of the one or more memory cells to generate one or more detected voltage levels; and identify a set of predicted information bits based on the one or more detected voltage levels using a neural network comprising a plurality of network parameters, wherein the plurality of network parameters are trained together with the plurality of embedding parameters.

[0150] Examples of the methods, apparatus, non-transitory computer-readable media, and systems described above may further include applying Gray code to the group information bits, wherein the mapping is based on Gray code. In some examples, the one or more memory cells comprise a plurality of memory cells, and the plurality of embedding parameters comprise an array having a dimension equal to the number of memory cells.

[0151] Examples of the methods, apparatus, non-transitory computer-readable media, and systems described above may further include: embedding the group information bits into an embedding space based on the plurality of embedding parameters to generate embedded symbols. Examples may further include: applying a sigmoid function to constrain the embedded information symbols to generate constrained symbols. Examples may further include: scaling the constrained symbols to generate scaled symbols corresponding to voltages within an effective dynamic range, wherein the group information bits are mapped based on the scaled symbols.

[0152] Some examples of the methods, apparatus, non-transitory computer-readable media, and systems described above may also include: using a neural network to generate a set of information bit probabilities based on detected voltage levels. Some examples may also include: selecting the highest information bit probability from the set of information bit probabilities, wherein the predicted information bits of the set are identified based on the highest information bit probability.

[0153] A method for selecting a programming voltage for a memory device is described. Embodiments of the method may include: initializing a plurality of embedding parameters and a set of network parameters; mapping a set of information bits to voltage levels of one or more memory cells based on the plurality of embedding parameters; identifying a set of predicted information bits using a network parameter-based ANN; and updating the plurality of embedding parameters and network parameters at least in part based on the set of predicted information bits.

[0154] A device for selecting a programming voltage for a memory device is described. The device may include a processor, a memory in electronic communication with the processor, and instructions stored in the memory. The instructions may be operable to cause the processor to: initialize a plurality of embedding parameters and a set of network parameters; map a set of information bits to voltage levels of one or more memory cells based on the plurality of embedding parameters; identify a set of predicted information bits using a network parameter-based ANN; and update the plurality of embedding parameters and network parameters at least in part based on the set of predicted information bits.

[0155] A non-transitory computer-readable medium is described, storing code for selecting a programming voltage for a memory device. In some examples, the code includes instructions executable by a processor to: initialize a plurality of embedding parameters and a set of network parameters; map a set of information bits to voltage levels of one or more memory cells based on the plurality of embedding parameters; identify a set of predicted information bits using a network parameter-based ANN; and update the plurality of embedding parameters and network parameters at least in part based on the set of predicted information bits.

[0156] Some examples of the methods, apparatus, non-transitory computer-readable media, and systems described above may also include: updating network parameters based on the plurality of embedding parameters to produce updated network parameters. Some examples further include: updating the plurality of embedding parameters based on the updated embedding parameters to produce updated embedding parameters.

[0157] Some examples of the methods, apparatuses, non-transitory computer-readable media and systems described above may also include: performing multiple training iterations, wherein the plurality of embedding parameters and network parameters are updated during each training iteration.

[0158] Some examples of the methods, apparatus, non-transitory computer-readable media and systems described above may also include: calculating the gradient of a classification loss function for the group information bits and the group predicted information bits, wherein the plurality of embedding parameters or network parameters are updated based on the gradient of the classification loss function.

[0159] In some examples, the gradient includes approximations of physical NAND channels. For example, the gradient may include a mathematical representation based on measurements obtained from one or more physical NAND channels. Some examples of the methods, apparatuses, non-transitory computer-readable media, and systems described above may also include: identifying a mathematical model of one or more memory cells, wherein the gradient of a classification loss function is computed based on the mathematical model. Some examples of the methods, apparatuses, non-transitory computer-readable media, and systems described above may also include: updating the mathematical model based on data from additional memory cells.

[0160] Examples of the methods, apparatus, non-transitory computer-readable media, and systems described above may further include: programming the group of information bits into the one or more memory cells based on a mapping. Some examples may further include: detecting voltage levels in the one or more memory cells to generate one or more detected voltage levels, wherein the group of predicted information bits is identified based on the one or more detected voltage levels.

[0161] Examples of the methods, apparatus, non-transitory computer-readable media, and systems described above may further include: using a neural network to generate a set of information bit probabilities based on detected voltage levels, wherein the set of predicted information bits is identified based on the highest information bit probability. In some examples, the one or more memory cells comprise a plurality of memory cells, and the plurality of embedding parameters comprise an array having a dimension equal to the number of memory cells.

[0162] Examples of the methods, apparatus, non-transitory computer-readable media, and systems described above may further include: embedding the group information bits into an embedding space based on the plurality of embedding parameters to generate an embedding symbol. Examples may further include: applying a sigmoid function to constrain the embedded information symbol to generate a constrained symbol. Examples may further include: scaling the constrained symbol to generate a scaled symbol, wherein the group information bits are mapped based on the scaled symbol.

[0163] An apparatus for selecting a programming voltage for a memory device is described. Embodiments of the apparatus may include a plurality of memory cells; a programming component including an embedding layer based on a plurality of embedding parameters; and a reading component including a neural network based on a plurality of network parameters, wherein the plurality of network parameters are trained together with the plurality of embedding parameters.

[0164] A method for manufacturing an apparatus for selecting a programming voltage for a memory device is described. The method may include providing a plurality of memory cells; providing a programming component including an embedding layer based on a plurality of embedding parameters; and providing a read component including a neural network based on a plurality of network parameters, wherein the plurality of network parameters are trained together with the plurality of embedding parameters.

[0165] A method is described using a device for selecting a programming voltage for a memory device. The method may include: using a plurality of memory cells; using a programming component comprising an embedding layer based on a plurality of embedding parameters; and using a read component comprising a neural network based on a plurality of network parameters, wherein the plurality of network parameters are trained together with the plurality of embedding parameters.

[0166] In some examples, the programming components also include sigmoid layers and scaling layers. In some examples, the neural network includes a probability-based classifier. In some examples, the plurality of memory cells include NAND memory cells.

[0167] Therefore, this disclosure provides automatic selection of programming voltage, which can be repeatedly invoked for each new memory device version or generation, thereby rapidly generating constellations (compared to manual labor). Embodiments of this disclosure, based on an optimized process (training process), provide the ability to find constellations faster than pre-built solutions and better than manual trial and error. Furthermore, embodiments of this disclosure use real data collected from memory devices to provide constellations suitable for specific problems, compared to conventionally programmed constellations.

[0168] The descriptions and accompanying drawings herein represent exemplary configurations and do not represent all embodiments within the scope of the claims. For example, operations and steps may be rearranged, combined, or otherwise modified. Furthermore, structures and apparatus may be represented in block diagram form to illustrate relationships between components and to avoid obscuring the concepts described. Similar components or features may have the same name but may have different reference numerals corresponding to different drawings.

[0169] For those skilled in the art, some modifications to this disclosure may be quite apparent, and the principles defined herein can be applied to other variations without departing from the scope of the disclosure. Therefore, the disclosure is not limited to the examples and designs described herein, but will be accorded the widest scope consistent with the principles and novel features disclosed herein.

[0170] The described methods can be implemented or performed by means of a device including a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof. A general-purpose processor can be a microprocessor, a conventional processor, a controller, a microcontroller, or a state machine. A processor can also be implemented as a combination of computing devices (e.g., a DSP with a microprocessor, multiple microprocessors, one or more microprocessors combined with a DSP core, or any other combination of such configurations). Therefore, the functions described herein can be implemented in hardware or software and can be performed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions can be stored on a computer-readable medium in the form of instructions or code.

[0171] Computer-readable media include both non-transitory computer storage media and communication media, with communication media including any medium that facilitates the transfer of code or data. Non-transitory storage media can be any readable medium accessible by a computer. For example, non-transitory computer-readable media may include random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), CD or other optical disc storage, magnetic disk storage, or any other non-transitory medium used to carry or store data or code.

[0172] Furthermore, connection components may be appropriately referred to as computer-readable media. For example, if code or data is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technology (such as infrared, radio, or microwave signals), then coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technology are included in the definition of media. Combinations of media are also included within the scope of computer-readable media.

[0173] In this disclosure and claims, the word "or" indicates an inclusive list, such that a list of, for example, X, Y, or Z represents X, or Y, or Z, or XY, or XZ, or YZ, or XYZ. Furthermore, the phrase "based on" is not used to indicate a closed set of conditions. For example, a step described as "based on condition A" may be based on both condition A and condition B. In other words, the phrase "based on" should be interpreted as meaning "at least partially based on". Additionally, the words "a" or "an" indicate "at least one".

Claims

1. A method of operating a memory device, comprising: The set of information bits is programmed into the one or more memory cells by mapping a set of information bits to input symbols corresponding to voltage levels of one or more memory cells based on multiple embedding parameters; Detect the voltage level of the one or more memory cells; A neural network comprising multiple network parameters trained together with the multiple embedding parameters using the same classification loss function is used to determine the predicted symbol corresponding to the input symbol based on the detected voltage level of the one or more memory cells. as well as The group information bits are obtained from the memory device based on the predicted symbols.

2. The method according to claim 1, wherein, The one or more memory cells include a plurality of memory cells, and the plurality of embedding parameters include an array having a dimension equal to the number of memory cells.

3. The method according to claim 1, further comprising: The group information bits are embedded into the embedding space based on the multiple embedding parameters to generate embedded symbols; Apply sigmoid functions to constrain embedded symbols to generate constraint symbols; as well as The constraint symbols are scaled to produce scaled symbols corresponding to the voltages within the effective dynamic range, wherein the group information bits are mapped based on the scaled symbols.

4. The method according to any one of claims 1 to 3, further comprising: A set of information bit probabilities is generated using a neural network based on the detected voltage levels of the one or more memory cells. as well as The highest information bit probability is selected from the group information bit probabilities, wherein the group information bits are obtained based on the highest information bit probability.

5. A method for training an artificial neural network for a memory device, comprising: Initialize multiple embedding parameters and network parameters; Based on the multiple embedding parameters, a set of information bits is mapped to the voltage level of one or more memory cells; Using an artificial neural network based on network parameters to identify a set of predicted information bits; as well as The plurality of embedding parameters and network parameters are updated at least in part based on the information bits predicted by the group.

6. The method according to claim 5, further comprising: The network parameters are updated based on the multiple embedded parameters to generate updated network parameters; as well as The plurality of embedding parameters are updated based on the updated network parameters to produce updated embedding parameters.

7. The method according to claim 5, further comprising: Multiple training iterations are performed, wherein the plurality of embedding parameters and network parameters are updated during each training iteration.

8. The method according to any one of claims 5 to 7, further comprising: Calculate the gradient of the classification loss function for the group information bits and the group predicted information bits, wherein the plurality of embedding parameters or network parameters are updated based on the gradient of the classification loss function.

9. The method according to claim 8, wherein, The gradient includes approximations of the physical NAND channels.

10. The method of claim 8, further comprising: A mathematical model is used to identify one or more memory cells, where the gradient of a classification loss function is calculated based on the mathematical model.

11. The method of claim 10, further comprising: The mathematical model is updated based on data from the additional memory unit.

12. The method according to any one of claims 5 to 7, further comprising: The group information bits are programmed into the one or more memory units based on the mapping; as well as The voltage level of the one or more memory cells is detected to generate one or more detected voltage levels, wherein the group of predicted information bits is identified based on the one or more detected voltage levels.

13. The method of claim 12, further comprising: A set of information bit probabilities is generated using a neural network based on the detected voltage level, wherein the set of predicted information bits is identified based on the highest information bit probability.

14. The method according to any one of claims 5 to 7, wherein, The one or more memory cells include a plurality of memory cells, and the plurality of embedding parameters include an array having a dimension equal to the number of memory cells.

15. The method according to any one of claims 5 to 7, further comprising: The group information bits are embedded into the embedding space based on the multiple embedding parameters to generate embedded symbols; Apply sigmoid functions to constrain embedded symbols to generate constraint symbols; as well as The constraint symbols are scaled to produce scaled symbols, wherein the group information bits are mapped based on the scaled symbols.

16. A memory device, comprising: Multiple memory units; Programming components, including an embedding layer based on multiple embedding parameters; as well as The reading component includes a neural network based on multiple network parameters, wherein the multiple network parameters are trained together with the multiple embedding parameters. The programming component is configured to map a set of information bits to the voltage levels of the plurality of memory cells based on the plurality of embedding parameters, and The reading component is configured to use a neural network based on the plurality of network parameters to identify a set of predicted information bits.

17. The memory device according to claim 16, wherein, The programming components also include an S-shaped layer and a scaling layer.

18. The memory device according to claim 16, wherein, Neural networks include probability-based classifiers.

19. The memory device according to claim 16, wherein, The plurality of memory cells include NAND memory cells.

20. A non-transitory computer-readable storage medium storing instructions, which, when executed by a processor, cause the processor to perform the method of any one of claims 1 to 15.

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