Memory array including memory cell strings and method for forming the same

Abstract

The subject application relates to a memory array including a string of memory cells and a method for forming the memory array. The method includes forming a conductor layer including a conductor material on a substrate. A stack including a vertically alternating first layer and a second layer is formed above the conductor layer. The stack includes laterally spaced memory blocks. A string of channel material extends through the first layer and the second layer. The material of the first layer has a different composition than the material of the second layer. Spaced-apart bodies of insulator material are formed in the lowest of the first layers in opposite sides of the individual in the memory blocks and longitudinally along the opposite sides. After forming the spaced-apart bodies of insulator material, a conductive material is formed in the lowest first layer, the conductive material electrically coupling the channel material of the individual in the string of channel material directly with the conductor material of the conductor layer. Other embodiments are disclosed that include structures that are independent of the method.

Description

Technical Field

[0001] Embodiments disclosed herein relate to memory arrays and to methods for forming memory arrays. Background Art

[0002] Memory is a type of integrated circuit system and is used in computer systems to store data. Memory can be fabricated in one or more arrays of individual memory cells. Memory cells can be written to or read from using digit lines (which may also be referred to as bit lines, data lines, or sense lines) and access lines (which may also be referred to as word lines). Sense lines can interconnect memory cells in a conductive manner along the columns of the array, and access lines can interconnect memory cells in a conductive manner along the rows of the array. Each memory cell can be uniquely addressed by a combination of sense lines and access lines.

[0003] Memory cells may be volatile, semi-volatile, or non-volatile. Non-volatile memory cells can store data for long periods of time without power. Non-volatile memory is typically specified as memory having a retention time of at least about 10 years. Volatile memory dissipates and is therefore refreshed / rewritten to maintain data storage. Volatile memory may have a retention time of a few milliseconds or less. In any case, the memory cell is configured to retain or store memory in at least two different selectable states. In a binary system, the state is considered to be "0" or "1". In other systems, at least some individual memory cells may be configured to store information at more than two levels or states.

[0004] Field effect transistors are a type of electronic component that can be used in memory cells. These transistors include a pair of conductive source / drain regions with a semiconductive channel region between them. A conductive gate is adjacent to the channel region and is separated from the channel region by a thin gate insulator. Application of a suitable voltage to the gate allows current to flow from one of the source / drain regions to the other through the channel region. When the voltage is removed from the gate, current is largely prevented from flowing through the channel region. Field effect transistors may also include additional structures, such as a reversibly programmable charge storage region as part of the gate construction between the gate insulator and the conductive gate.

[0005] Flash memory is a type of memory and is used extensively in modern computers and devices. For example, a modern personal computer may store the BIOS on a flash memory chip. As another example, it is increasingly common for computers and other devices to utilize flash memory in solid-state drives to replace conventional hard disk drives. As yet another example, flash memory is popular in wireless electronic devices because it enables manufacturers to support new communication protocols as they become standardized and to provide the ability to remotely upgrade devices for enhanced features.

[0006] NAND may be the basic architecture for integrated flash memory. A NAND cell device includes at least one selection device coupled in series with a series combination of memory cells (wherein the series combination is generally referred to as a NAND string). The NAND architecture may be configured in a three-dimensional arrangement including vertically stacked memory cells that individually include reversibly programmable vertical transistors. Control circuitry or other circuitry may be formed below the vertically stacked memory cells. Other volatile or non-volatile memory array architectures may also include vertically stacked memory cells that individually include transistors.

[0007] The memory array may be arranged in memory pages, memory blocks and partial blocks (e.g., sub-blocks) and memory planes, for example, as shown and described in any of U.S. Patent Application Publication Nos. 2015 / 0228651, 2016 / 0267984, and 2017 / 0140833. The memory blocks may at least partially define the longitudinal profiles of individual word lines in individual word line layers of vertically stacked memory cells. Connections to these word lines may occur in a so-called "staircase structure" at the ends or edges of the array of vertically stacked memory cells. The staircase structure includes individual "steps" (alternatively referred to as "rungs" or "stairs") defining contact areas for individual word lines, with vertically extending conductive vias contacting the contact areas to provide electrical access to the word lines. Summary of the invention

[0008] In some embodiments, a method for forming a memory array including a memory cell string includes forming a conductor layer including a conductor material on a substrate. A stack including a vertically alternating first layer and a second layer is formed above the conductor layer. The stack includes memory blocks that are spaced apart laterally. A channel material string extends through the first layer and the second layer. The material of the first layer has a different composition than the material of the second layer. A spaced-apart insulator material body is formed in the lowest of the first layers in opposite sides of the individual in the memory block area and longitudinally along the opposite sides. After forming the spaced-apart insulator material body, a conductive material is formed in the lowest first layer, the conductive material electrically coupling the channel material of the individual in the channel material string directly with the conductor material of the conductor layer.

[0009] In some embodiments, a method for forming a memory array including a memory cell string includes forming a conductor layer including a conductor material on a substrate. A lower portion of a stack including a first layer and a second layer that alternate vertically is formed above the conductor layer. The stack includes memory blocks that are spaced apart laterally. The material of the first layer has a composition different from that of the material of the second layer. The lowest of the first layers includes a first sacrificial material. A horizontally elongated line is formed in the lowest first layer, and the horizontally elongated line is individually between memory blocks that are adjacent laterally. The line includes a second sacrificial material having a composition different from the following materials: the first sacrificial material, a first layer of material that is formed or to be formed above the first sacrificial material, and a second layer of material that is formed or to be formed above the first sacrificial material. The second sacrificial material of the line is cut to form a spaced-apart second sacrificial material body in the lowest first layer longitudinally along the memory blocks that are adjacent laterally and between the memory blocks that are adjacent laterally, and to expose the first sacrificial material in the lowest first layer for the first time longitudinally between the spaced-apart second sacrificial material bodies. The first exposed first sacrificial material is first isotropically etched from the lowest first layer to form spaced cavities in the first exposed first sacrificial material in the lowest first layer in the laterally adjacent memory blocks and longitudinally along the laterally adjacent memory blocks. The spaced cavities and void spaces are filled with insulator material in the lowest first layer, and the spaced cavities and void spaces are individually between the adjacent spaced second sacrificial material bodies. The vertically alternating first and second layers of the upper portion of the stack are formed above the lower portion and line. Channel material strings are formed to extend through the first and second layers in the upper portion to the lowest first layer in the lower portion. Horizontally elongated grooves are formed into the stack, and the horizontally elongated grooves are individually between the laterally adjacent memory blocks and extend to the spaced second sacrificial material bodies and insulator materials between the memory blocks. The second sacrificial material body is removed through the trenches, and a spaced-apart body of insulator material is formed in the lowest first layer in and longitudinally along opposite sides of the individual ones in the memory block area, and the remaining portion of the first sacrificial material in the lowest first layer is exposed for a second time. After forming the spaced-apart body of insulator material, the second exposed remaining first sacrificial material is isotropically etched a second time from the lowest first layer through the trenches. After the second isotropic etching, a conductive material is formed in the lowest first layer, which directly electrically couples the channel material of the individual ones in the string of channel material with the conductive material of the conductive layer.

[0010] In some embodiments, a memory array including strings of memory cells includes a conductor layer including a conductor material. Laterally spaced memory blocks individually include a vertical stack directly above the conductor layer, the vertical stack including alternating insulating layers and conductive layers. The channel material strings of the memory cells extend through the insulating layer and the conductive layer. The spaced apart insulator material bodies are in the lowest of the first layer in opposite sides of the individual in the memory block and longitudinally along the opposite sides. The conductive material in the lowest first layer directly electrically couples the channel material of the individual in the string of channel materials with the conductor material of the conductor layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 is a diagrammatic cross-sectional view of a portion of a substrate being processed according to an embodiment of the present invention and is a cross-sectional view through Figure 2 Intercepted by line 1-1 in.

[0012] Figure 2 It passes through Figure 1 A diagrammatic cross-sectional view taken along line 2-2 in FIG.

[0013] Figure 3-35 is a process according to some embodiments of the present invention Figure 1 and 2 Illustrations of the structure or parts thereof in sequential cross-section, expansion, enlargement and / or partial views.

[0014] Fig.36 is a diagrammatic cross-sectional view of a portion of a substrate being processed according to an embodiment of the present invention and is a cross-sectional view through Fig.37 The line 36-36 in FIG.

[0015] Fig.37 It passes through Fig.36 A diagrammatic cross-sectional view taken along line 37-37 in FIG.

[0016] Fig.38 yes Fig.37 An enlarged view of a portion of the diagram.

[0017] Fig.39 is a diagrammatic cross-sectional view of a portion of a substrate being processed according to an embodiment of the present invention and is a cross-sectional view through Fig.40 Intercepted at line 39-39 in FIG.

[0018] Fig.40 It passes through Fig.39 A diagrammatic cross-sectional view taken along line 40-40 in FIG. DETAILED DESCRIPTION

[0019] Embodiments of the present invention encompass methods for forming memory arrays, such as arrays of NAND or other memory cells, which may have at least some peripheral control circuitry under the array (e.g., under-array CMOS). Embodiments of the present invention encompass so-called "gate-last" or "replacement-gate" processes, so-called "gate-first" processes, and other processes, whether present or developed in the future, that are independent of when the transistor gates are formed. Embodiments of the present invention also encompass memory arrays that are independent of the method of manufacture (e.g., NAND architecture). Reference Figure 1-35 A first example method embodiment is described, which may be viewed as a "gate last" or "replacement gate" process, and from Figure 1 and 2 start.

[0020] Figure 1 and 2 A construction 10 is shown having an array or array region 12 in which vertically extending strings of transistors and / or memory cells are to be formed. Construction 10 includes a base substrate 11 having any one or more of a conductive / conductor / conductive, semiconductive / semiconductive / semiconductive, or insulating / insulator / isolating (i.e., electrically herein) material. Various materials have been vertically formed over base substrate 11. The materials may be Figure 1 and 2 11. For example, other partially manufactured or fully manufactured components of the integrated circuit system may be provided somewhere above, around, or within the base substrate 11. Control circuitry and / or other peripheral circuitry for operating components within an array of vertically extending memory cell strings (e.g., array 12) may also be manufactured, and the circuitry may or may not be completely or partially within the array or sub-array. In addition, multiple sub-arrays may also be manufactured and operated independently, sequentially, or otherwise relative to each other. In this document, a "sub-array" may also be considered an array.

[0021] In some embodiments and as shown, a conductor material 17 (eg, a top conductively doped polysilicon WSi x ) has been formed over substrate 11. Conductor layer 16 may include portions of control circuitry (e.g., peripheral under-array circuitry and / or a common source line or plate) for controlling read and write access to transistors and / or memory cells to be formed within array 12.

[0022] The lower portion 18L of the stack 18*, when present, has been formed over the substrate 11 and the conductor layer 16 (* is used as a suffix to include all such components designated with the same numerical value that may or may not have other suffixes). The stack 18* will include vertically alternating conductive layers 22* and insulating layers 20*. The example lower portion 18L is shown as including only two insulating layers 20* and one conductive layer 22*. More insulating layers 20*, more conductive layers 22*, or fewer insulating layers 20* (including zero insulating layers 20*) may alternatively be provided in the lower portion 18L (not shown). The conductive layer 22* (alternatively referred to as the first layer) may not include conductive material, and the insulating layer 20* (alternatively referred to as the second layer) may not include insulating material or be insulating when processed in conjunction with the "gate-last" or "replacement-gate" example method embodiments initially described herein. The example conductive layer 22* includes a first material 26 (e.g., silicon nitride) that may be fully or partially sacrificial. The example insulating layer 20* includes a second material (e.g., 39, 27, 21; such as one or more insulating oxides, including, for example, silicon dioxide) having a composition different from that of the first material 26 and may be fully or partially sacrificial. The lowest first layer 22z includes a first sacrificial material 77 (e.g., polysilicon or silicon nitride, and may have the same or different composition than the material of the first layer 22* above it and / or to be formed thereon).

[0023] An example thickness of each of the layers 20* and 22* is 20 to 60 nanometers. In one embodiment, the lowest first layer 22z is thicker than the first layer 22* above it and / or to be formed above it, and in one such embodiment is at least 1.5 times thicker than the first layer 22* above it and / or to be formed above it. In one embodiment and as shown, the lowest first layer 22z does not directly abut the conductor material 17 of the conductor layer 16, for example, where the lowest second layer 20z is vertically between the conductor material 17 of the conductor layer 16 and the lowest first layer 22z. Alternatively, the lowest first layer may directly abut the conductor material of the conductor layer (not shown). In one embodiment, the lowest second layer 20z directly abuts the top 19 of the conductor material 17 of the conductor layer 16. In one embodiment, the second layer 20x (i.e., the next higher second layer 20x) immediately above the lowest first layer 22z is thicker than the second layer 20* above it and / or to be formed above it. A silicon nitride layer (not shown) may be between the second material 39 and the first sacrificial material 77 and, thus, is part of the insulating layer 20z.

[0024] In one embodiment, the second layer material of the second layer 20x immediately above the lowest first layer 22z (i.e., there is no other second layer vertically between the lowest first layer 22z and the second layer 20x immediately above it) includes an upper first insulating material 21 and a lower second material 23 below the upper first insulating material 21, wherein the lower second material 23 has a composition different from that of the upper first insulating material 21. In one such embodiment, the lower second material 23 is thinner than the upper first insulating material 21. Regardless, the upper first insulating material 21 may have the same composition as material 39. In some embodiments, the second layer material of the second layer 20x immediately above the lowest first layer 22z may be considered to include an upper insulating material 21, a lower material 27, and an intermediate material 23 vertically between the upper insulating material 21 and the lower material 27, wherein the intermediate material 23 has a composition different from that of the lower material 27 and that of the upper insulating material 21 (the lower material 27 is optional in some embodiments). In some such embodiments, upper insulating material 21 and lower material 27 have the same thickness as each other. Regardless, in some embodiments, upper insulating material 21 and lower material 27 have the same composition relative to each other (e.g., and the same composition as material 39), and have different compositions relative to each other in other embodiments. In some embodiments, lower second material 23 / intermediate material 23 includes at least one of the following: conductively doped polysilicon, non-conductively doped polysilicon, carbon-doped polysilicon, silicon nitride, undoped silicon nitride, carbon-doped silicon nitride, and a metal material. One or more of materials 21, 23, or 27 may be at least partially sacrificial.

[0025] Stack 18* includes laterally spaced memory block regions 58 that will include laterally spaced memory blocks 58 in a finished circuit system configuration. In this document, a "block" generally includes a "sub-block." Memory block regions 58 and resulting memory blocks 58 (not yet shown) can be considered to be longitudinally elongated and oriented, for example, along direction 55. Memory block regions 58 may not be discernible at this processing point.

[0026] Horizontally elongated wires 13 have been formed in the lowest first layer 22z (and in layer 20*). The wires 13 are individually between laterally adjacent memory block regions 58. The wires 13 include a second sacrificial material 15 having a different composition than the first sacrificial material 77. In one embodiment, the second sacrificial material 15 includes a metallic material, such as elemental tungsten above a thin layer of TiN. In some embodiments, the second sacrificial material 15 has a different composition than the first layer material formed or to be formed above the first sacrificial material 77 and the second layer material (e.g., 27, 23, 21) formed or to be formed above the first sacrificial material 77. In one embodiment, the wires 13 individually include an uppermost surface 31 above the lowest first layer 22z, and in one such embodiment, the uppermost surface is in or at the top 33 of the second layer 20x. In one embodiment, the wires 13 individually include laterally opposed protrusions 66 and / or 54 longitudinally along them, wherein the protrusions 66 are spaced below the uppermost surface 31 and above the lowest wire surface 59. An oxide liner (not shown), such as formed by selective oxidation, may surround the protrusions and along the lowest wire surface 59 in the wires 13. In one embodiment, the second sacrificial material 15 of individual wires 13 may extend laterally into the respective laterally adjacent memory block regions 58, such as shown by example lateral protrusions 66 and 54. Alternatively, more or all of the thickness of the second sacrificial material 15 of wires 13 may extend laterally into the respective laterally adjacent memory block regions 58 (not shown). Regardless, the wires 13 may taper laterally inward (not shown), moving deeper into the lower stack portion 18L.

[0027] In one embodiment, pillars 60 have been formed in lower portion 18L. Pillars 60 are positioned horizontally (i.e., in x, y coordinates) where individual strings of channel material will be formed. By way of example only and for simplicity, pillars 60 are shown arranged in groups or columns of staggered rows of four and five pillars 60 per row. In one embodiment, pillars 60 include second sacrificial material 15. In one embodiment, pillars 60 individually include radial protrusions 62 spaced below uppermost pillar surface 63 and above lowest pillar surface 64. Pillars 60 may have additional radial protrusions, such as radial protrusions 72. An oxide liner (not shown), such as formed by selective oxidation, may surround the protrusions and along lowest pillar surface 64. Pillars 60 may taper radially inward (not shown), moving deeper into lower stack portion 18L. When both pillars 60 and wires 13 are formed, they may be formed simultaneously or at different times.

[0028] refer to Figure 3 and 4, the second sacrificial material 15 of the cut line 13 is cut (for example, by anisotropic etching using a photolithographic patterned mask) to form spaced-apart second sacrificial material bodies 44 (with void spaces 46 therebetween) in the lowest first layer 22z longitudinally along and between the laterally adjacent memory block areas 58, and to expose the first sacrificial material 77 in the lowest first layer 22z for the first time longitudinally between the spaced-apart second sacrificial material bodies 44. The reference to "first exposure" is temporal relative to the "second exposure" mentioned below and is not necessarily the first exposure of the first sacrificial material, and other exposures of the first sacrificial material may occur between the "first exposure" and the "second exposure". Those skilled in the art are able to select one or more suitable anisotropic etching chemicals for etching the second sacrificial material 15 (for example, using a plasma mixture of SF6 and Cl2 to etch tungsten).

[0029] refer to Figure 5 and 6 , the first exposed first sacrificial material 77 has been first isotropically etched (e.g., timed etching) from the lowest first layer 22z to form spaced-apart cavities 45 in the first exposed first sacrificial material 77 in the lowest first layer 22z in the laterally adjacent memory block areas 58 and longitudinally along the laterally adjacent memory block areas. The reference to "first isotropically etching" is temporal with respect to the "second isotropically etching" mentioned below with respect to the first sacrificial material 77 and is not necessarily the first isotropic etching of the first sacrificial material 77, and other isotropic etching of the first sacrificial material may occur between the "first isotropic etching" and the "second isotropic etching". Those skilled in the art are able to select one or more suitable etching chemicals (e.g., using liquid or gaseous H3PO4 as the main etchant where material 26 is silicon nitride, using tetramethylammonium hydroxide [TMAH] where material 26 is polysilicon). In one embodiment in which lower material 27 is present, and as shown, etching of first sacrificial material 77 from lowest first level 22z may be performed selectively relative to lower material 27 in next higher second layer 20x to leave lower material 27 under intermediate material 23 in next higher second layer 20x above cavity 45. Additionally, in one embodiment and as shown, etching of first sacrificial material 77 has been performed selectively relative to material 39 of lowest second layer 20z.

[0030] refer to Figure 7 and 8, the void spaces 46 between adjacent spaced-apart second sacrificial material bodies 44 and the spaced-apart cavities 45 in the lowest first layer 22z have been filled with an insulator material 47 (e.g., an oxide, such as silicon dioxide, aluminum oxide, hafnium oxide, silicon nitride, etc.), respectively.

[0031] refer to Fig. 9 and 10 , the vertically alternating first and second layers 22, 20 of the upper portion 18U of the stack 18* have been formed over the lower portion 18L and the line 13. The example second layer 20 includes a second material 24 (e.g., silicon dioxide) that may be fully or partially sacrificial. The example upper portion 18U is shown as starting with the first layer 22 over the lower portion 18L, but this may alternatively start with the second layer 20 (not shown), which would thereby be part of the immediately lower second layer 20*. In any case, only a small number of layers 20 and 22 are shown, but the upper portion 18U (and thus the stack 18*) is more likely to include dozens, a hundred, or more (etc.) layers 20* and 22*. In addition, other circuit systems that may or may not be part of the peripheral and / or control circuit systems may be between the conductor layer 16 and the stack 18*. By way of example only, multiple vertically alternating layers of conductive and insulating materials of such circuit systems may be below the lowest of the conductive layers 22* and / or above the uppermost of the conductive layers 22*. For example, one or more select gate layers (not shown) may be between conductor layer 16 and the lowest conductive layer 22*, and one or more select gate layers may be above the uppermost one of conductive layers 22*. Alternatively or in addition, at least one of the depicted uppermost and lowest conductive layers 22* may be a select gate layer.

[0032] A channel opening 25 has been formed (e.g., by etching) through the insulating layer 20 and the conductive layer 22 in the upper portion 18U to the lower portion 18L and individually to the pillar 60 (when present). Alternatively, if the pillar 60 is not present, the channel opening 25 may extend to (included in or below) the lowest first layer 22z. In any case, the channel opening 25 may taper radially inward (not shown), thereby moving deeper into the upper stack portion 18U.

[0033] refer to Fig.11 and 12, pillars 60 (not shown) have been removed (e.g., by isotropic etching) through the channel openings 25, thereby effectively extending the channel openings 25 into the individual void spaces 61 created by the removal of the pillars 60 and to the lowest first layer 22z. Those skilled in the art are able to select a suitable isotropic etching chemistry that will selectively etch the pillar material 15 relative to other exposed materials. As an example, a mixture of ammonia and hydrogen peroxide or a mixture of sulfuric acid and hydrogen peroxide can be used to isotropically etch the W material 15 selectively relative to SiO2 and Si3N4.

[0034] refer to Figure 13-16 , transistor channel material 36 has been formed vertically along the first and second layers in individual channel openings 25 and void spaces 61, thereby including individual channel material strings 53, which extend through the first layer 22* and the second layer 20* in the upper portion 18U to the lowest first layer 22z in the lower portion 18L. The channel material 36 in the channel material string 53 will be directly electrically coupled with the conductor material 17 in the conductor layer 16. Individual memory cells of the formed example memory array may include a gate region (e.g., a control gate region) and a memory structure laterally between the gate region and the channel material. In one such embodiment, the memory structure is formed to include a charge blocking region, a storage material (e.g., a charge storage material), and an insulating charge transfer material. The storage material of the individual memory cell (e.g., a floating gate material, such as doped or undoped silicon, or a charge trapping material, such as silicon nitride, metal dots, etc.) is vertically along the individual charge blocking region. An insulating charge transfer material (eg, a bandgap engineered structure having a nitrogen-containing material [eg, silicon nitride] sandwiched between two insulator oxides [eg, silicon dioxide]) is laterally between the channel material and the storage material. Fig.15 and 16 One embodiment is shown in which charge blocking material 30, storage material 32, and charge transfer material 34 have been formed vertically along insulating layer 20* and conductive layer 22* in individual channel openings 25. Transistor materials 30, 32, and 34 (e.g., memory cell materials) may be formed, for example, by depositing their respective thin layers over stack 18* and within individual channel openings 25 and subsequently planarizing such transistor materials back to at least the top surface of stack 18*.

[0035] Channel material 36 may be considered to have its lowest surface 71. In one embodiment, string of channel material 53 has memory cell materials (e.g., 30, 32, and 34) along it, and wherein the second layer of material (e.g., 24) is horizontally between immediately adjacent strings of channel material 53. Due to the proportions, materials 30, 32, 34, and 36 are Fig.13 and 1437. Example channel material 36 includes appropriately doped crystalline semiconductor materials, such as one or more of silicon, germanium, and so-called III / V semiconductor materials (e.g., GaAs, InP, GaP, and GaN). An example thickness of each of materials 30, 32, 34, and 36 is 25 to 100 angstroms. A stamp etch may be performed to remove materials 30, 32, and 34 from a base (not shown) of channel opening 25 to expose conductor layer 16 so that channel material 36 is directly against conductor material 17 of conductor layer 16. Such a stamp etch may occur individually with respect to each of materials 30, 32, and 34 (as shown), or may occur only with respect to some (not shown). Alternatively and by way of example only, a stamp etch may not be performed, and channel material 36 may be directly electrically coupled to conductor material 17 of conductor layer 16 only through a separate conductive interconnect (not shown). Channel opening 25 is shown including a radially central solid dielectric material 38 (eg, spin-on dielectric, silicon dioxide, and / or silicon nitride). Alternatively and by way of example only, a radially central portion within channel opening 25 may include void space (not shown) and / or be free of solid material (not shown).

[0036] refer to Fig.17 and 18 , horizontally elongated trenches 40 have been formed into the stack 18* (eg, by anisotropic etching) and individually between and extending to the spaced apart second sacrificial material bodies 44 and insulator material 47 between laterally adjacent memory block regions 58. As shown in FIG.

[0037] refer to Fig.19 and 20 , the second sacrificial material bodies 44 (not shown) have been removed through the trenches 40 (e.g., by an isotropic etch using a mixture of ammonia and hydrogen peroxide or a mixture of sulfuric acid and hydrogen peroxide if material 15 includes W), thereby effectively extending the trenches 40 deeper into the stack 18* and exposing the remaining first sacrificial material 77 in the lowermost first layer 22z for a second time. In one embodiment (as shown), the insulator material 47 (not shown) between the second sacrificial material bodies has also been removed (e.g., ideally by anisotropic etching). In embodiments where the insulator material 47 is removed, the insulator material may be removed before or after the second sacrificial material bodies are removed. In any event, spaced-apart insulator material bodies 51 (e.g., including material 47) have been formed in the lowermost first layer 22z in and longitudinally along opposite sides of the individual memory block regions 58.

[0038] refer to Figure 21-23, the remaining first sacrificial material 77 (not shown) exposed for the second time isotropically etched from the lowest first layer 22z through the trench 40 for the second time (for example, using liquid or gaseous H3PO4 as the main etchant, where the material 26 is silicon nitride and the other exposed materials include one or more oxides or polysilicon, or using TMAH, where the material 26 is polysilicon). If the first layer material 26 and the first sacrificial material 77 have the same composition, the sidewalls of the first layer material 26 can be shielded by a thin layer (not shown) to prevent them from being etched when etching the first sacrificial material 77.

[0039] In one embodiment, sidewalls of the channel material of the strings of channel material in the lowest first layer are exposed. Fig.24 and 25 An example such subsequent processing is shown where, in one embodiment, material 30 (e.g., silicon dioxide), material 32 (e.g., silicon nitride), and material 34 (e.g., silicon dioxide or a combination of silicon dioxide and silicon nitride) have been etched in layer 22z to expose sidewalls 41 of channel material 36 of channel material string 53 in the lowest first layer 22z. Any of materials 30, 32, and 34 in layer 22z may be considered a sacrificial material therein. As an example, consider an embodiment where materials 39, 27, and 21 are one or more insulating oxides (other than silicon dioxide), materials 23 and 36 are polysilicon, and memory cell materials 30, 32, and 34 are one or more of a silicon dioxide layer and a silicon nitride layer, respectively. In such an example, the depicted construction may be produced by using a modified or different chemistry to selectively etch silicon dioxide and silicon nitride sequentially relative to the other chemistry. As an example, a solution of 100:1 (by volume) water to HF will selectively etch silicon dioxide relative to silicon nitride, while a solution of 1000:1 (by volume) water to HF will selectively etch silicon nitride relative to silicon dioxide. Thus, and in such examples, such etching chemistries may be used in an alternating manner, where it is desired to achieve the desired etching ratio. Fig.24 and 25 The example configuration shown. Those skilled in the art will be able to select other chemistries for etching other different materials, where desired. Fig.24 and 25 The structure shown in .

[0040] refer to Fig.26 and 27, and in one embodiment, the conductive material 42 has been deposited into the void space left in the lowest first layer 22z as a result of the removal of the first sacrificial material 77. In one such embodiment, the conductive material 42 is directly against the exposed sidewalls 41 of the channel material 36 of the channel material string 53 in the lowest first layer 22z, and in one embodiment directly against the uppermost surface 19 of the conductor material 17 of the conductor layer 16. This is but one example whereby the conductive material 42 has been deposited to directly electrically couple together the channel material 36 of the individual channel material strings 53 and the conductor material 17 of the conductor layer 16 (e.g., through the channel material sidewalls 41). Example conductive materials 42 are conductively doped semiconductor materials (e.g., conductively doped polysilicon) and metal materials.

[0041] refer to Fig.28 and 29 , conductive material 42 has been removed from trench 40, such as by a timed isotropic or anisotropic etch that may be selective to materials 24, 26, 17, and 47. This may result in some etching of conductor material 17 when exposed (not shown). Example etch chemistries are anisotropic (HBr) and isotropic (TMAH), where material 42 is conductively doped polysilicon, material 24 is silicon dioxide, and material 26 is silicon nitride. The sidewalls of conductive material 42 and / or conductor material 17 may then be selectively oxidized (not shown).

[0042] refer to Figure 30-35 , material 26 (not shown) of conductive layer 22* has been removed, for example, by isotropically etching away through trench 40, ideally selectively relative to other exposed materials (e.g., using liquid or gaseous H3PO4 as the primary etchant, where material 26 is silicon nitride and the other materials include one or more oxides or polysilicon). In an example embodiment, material 26 (not shown) in conductive layer 22* is sacrificial and has been replaced by conductive material 48 and has thereafter been removed from trench 40, thus forming individual conductive lines 29 (e.g., word lines) and vertically extending strings 49 of individual transistors and / or memory cells 56.

[0043] A thin insulating liner (e.g., Al2O3 and not shown) may be formed prior to forming conductive material 48. The approximate location of transistor and / or memory cell 56 is at Fig.35 Indicated by brackets in Fig.30 , 3234, where the transistor and / or memory cell 56 is substantially annular or ring-shaped in the depicted example. Alternatively, the transistor and / or memory cell 56 may not completely surround the individual channel openings 25, so that each channel opening 25 may have two or more vertically extending strings 49 (e.g., multiple transistors and / or memory cells surround the individual channel openings in the individual conductive layers, where there may be multiple word lines per channel opening in the individual conductive layers, and not shown). The conductive material 48 may be viewed as having ends 50 ( Fig.35 ). In the depicted embodiment, control gate region 52 includes individual portions of individual conductive lines 29. Materials 30, 32, and 34 may be viewed as a memory structure 65 laterally between control gate region 52 and channel material 36. In one embodiment and as shown with respect to an example "gate last" process, conductive material 48 of conductive layer 22* is formed after forming channel opening 25 and / or trench 40. Alternatively, for example with respect to a "gate first" process, the conductive material of the conductive layer may be formed before forming channel opening 25 and / or trench 40 (not shown).

[0044] The charge blocking region (e.g., charge blocking material 30) is between the storage material 32 and the individual control gate region 52. The charge blocking member may have the following functions in the memory cell: in the programming mode, the charge blocking member may prevent charge carriers from flowing from the storage material (e.g., floating gate material, charge trapping material, etc.) to the control gate, and in the erase mode, the charge blocking member may prevent charge carriers from flowing from the control gate into the storage material. Thus, the charge blocking member may be used to block charge migration between the control gate region and the storage material of the individual memory cell. The example charge blocking region as shown includes an insulator material 30. As a further example, the charge blocking region may include a lateral (e.g., radially) outer portion of the storage material (e.g., material 32), where such storage material is insulating (e.g., in the absence of any different composition material between the insulating storage material 32 and the conductive material 48). Regardless, as an additional example, the interface of the storage material and the conductive material of the control gate may be sufficient to act as a charge blocking region in the absence of any separate composition insulator material 30. Furthermore, the interface of conductive material 48 and material 30 (if present) in conjunction with insulator material 30 may together act as a charge blocking region and may alternatively or additionally act as a lateral outer region of insulating storage material, such as silicon nitride material 32. Example material 30 is one or more of hafnium oxide and silicon dioxide.

[0045] In one embodiment and as shown, the lowermost surface 71 of the channel material 36 of the string of channel material 53 never directly abuts any one of the conductor materials 17 of the conductor layer 16 .

[0046] Interposing material 57 has been formed in trench 40 and in the void space left by the removal of second sacrificial material 15 of line 13, and thereby laterally between and longitudinally along laterally adjacent memory blocks 58. Interposing material 57 may provide lateral electrical isolation (insulation) between laterally adjacent memory blocks. Such material may include one or more of insulating, semiconducting, and conductive materials, and in any event, may facilitate shorting of conductive layers 22 relative to each other in the finished circuit system construction. Example insulating materials are one or more of SiO2, Si3N4, Al2O3, and undoped polysilicon. Interposing material 57 may include through-array vias (not shown). Some of the material in trench 40 formed prior to forming the material designated as interposing material 57 may remain and thereby constitute part of interposing material 57.

[0047] In one embodiment, the conductive material 42 is directly against the insulator material body 51. In one embodiment, the insulator material body 51 does not protrude laterally into the space (e.g., trench 40) between immediately adjacent laterally spaced memory block regions 58. In one embodiment and as shown, the conductive material 42 does not completely horizontally surround the respective peripheries of the insulator material body 51, in one such embodiment and as shown, horizontally covers a majority of such respective peripheries, and as shown in another such embodiment, horizontally covers at least 75% of the respective peripheries.

[0048] Any other properties or aspects as shown and / or described herein with respect to other embodiments may be used in the embodiments shown and described with reference to the above embodiments.

[0049] Figure 36-38 An example alternative embodiment configuration 10a is shown. Like reference numerals from the above described embodiments are used where appropriate, with some configuration differences indicated by a suffix "a" or by different reference numerals. Figure 36-38 An example configuration is shown in which the insulator material body 51a also does not protrude laterally into the space between immediately adjacent memory block regions 58. However, and regardless, the conductive material 42 in configuration 10a completely horizontally surrounds the respective peripheries of the insulator material body 51a. This may occur, for example, if the insulator material body 51a is etched circumferentially after initial formation to reduce its radial expansion, thereby pulling away from the sides of the memory block regions 58. For example, and by way of example only, where some of the material 37 is silicon dioxide and the insulator material body 51a is also silicon dioxide, some of the etching exposes the sidewalls 41 of the channel material 36, as shown in FIG. Fig.24 and 25, insulator material body 51a may also be peripherally etched. Further, materials 27 and 39 may have the same composition as insulator material 47 of insulator material body 51a and also be etched therewith, for example as shown. Any other attributes or aspects as shown and / or described herein with respect to other embodiments may be used.

[0050] Fig.39 and 40 An example alternative embodiment configuration 10b is shown. Like reference numerals from the embodiments described above are used where appropriate, with some configuration differences indicated by the suffix "b" or by different reference numerals. Configuration 10b has a body of insulator material 51b that individually spans the space between immediately adjacent laterally spaced memory block regions in the finished circuitry configuration. This may result in material 47 not being etched through in trench 40, which is consistent with Fig.19 and 20 Any other attributes or aspects as shown and / or described herein with respect to other embodiments may be used.

[0051] In some embodiments, a method for forming a memory array (e.g., 12) including a string (e.g., 49) of memory cells (e.g., 56) includes forming a conductor layer (e.g., 16) including a conductor material (e.g., 17) on a substrate (e.g., 11). A stack (e.g., 18*) including vertically alternating first layers (e.g., 22*) and second layers (e.g., 20*) is above the conductor layer. The stack includes laterally spaced memory blocks (e.g., 58). A channel material string (e.g., 53) extends through the first and second layers. The material of the first layer has a different composition than the material of the second layer. Spaced-apart insulator material bodies (e.g., 51, 51a, 51b) are in the lowest of the first layers (e.g., 22z) in opposite sides of the individual ones of the memory blocks and longitudinally along the opposite sides. After forming the spaced-apart insulator material bodies, a conductive material (e.g., 42) is formed in the lowest first layer, the conductive material electrically coupling the channel material of the individual ones of the channel material string with the conductor material of the conductor layer directly. Any other attributes or aspects as shown and / or described herein with respect to other embodiments may be used.

[0052] Alternative embodiment configurations may result from the method embodiments described above or otherwise. In any event, embodiments of the invention encompass memory arrays that are independent of the method of manufacture. Nevertheless, such memory arrays may have any of the properties described herein in the method embodiments. Likewise, the method embodiments described above may incorporate, form and / or have any of the properties described with respect to the device embodiments.

[0053] In one embodiment, a memory array (e.g., 12) including strings (e.g., 49) of memory cells (e.g., 56) includes a conductor layer (e.g., 16) including a conductor material (e.g., 17). The memory array includes laterally spaced memory blocks (e.g., 58), each of which includes a vertical stack (e.g., 18*) directly above the conductor layer, the vertical stack including alternating insulating layers (e.g., 20*) and conductive layers (e.g., 22*). The channel material strings (e.g., 53) of the memory cells (e.g., 56) extend through the insulating and conductive layers. The spaced-apart insulator material bodies (e.g., 51, 51a, 51b) are in the lowest of the first layers (e.g., 22z) in opposite sides of the individual ones of the memory blocks and longitudinally along the opposite sides. The conductive material (e.g., 42) is in the lowest first layer and electrically couples the channel material of the individual ones of the channel material strings directly with the conductor material of the conductor layer. Any other attributes or aspects as shown and / or described herein with respect to other embodiments may be used.

[0054] The above processing or construction may be considered as an array relative to components that are formed as a single stack or a single stack of such components or within a single stack or a single stack, which is above or as part of the underlying base substrate (but a single stack / stack may have multiple layers). Control and / or other peripheral circuitry for operating or accessing such components within the array may also be formed at any location as part of the finished construction, and in some embodiments may be under the array (e.g., CMOS under the array). In any case, one or more additional such stacks / stacks may be provided or manufactured above and / or below the stacks / stacks shown in the figure or described above. In addition, the arrays of components may be the same or different in different stacks / stacks relative to each other, and different stacks / stacks may have the same thickness or different thickness relative to each other. Intervening structures may be provided between stacks / stacks that are adjacent vertically (e.g., additional circuitry and / or dielectric layers). Likewise, different stacks / stacks may be electrically coupled relative to each other. Multiple stacks / stacks may be manufactured individually and sequentially (e.g., one on top of another), or two or more stacks / stacks may be manufactured substantially simultaneously.

[0055] The assemblies and structures discussed above can be used in integrated circuits / circuitry systems and can be incorporated into electronic systems. Such electronic systems can be used, for example, in memory modules, device drivers, power modules, communication modems, processor modules, and application-specific modules, and can include multi-layer, multi-chip modules. The electronic system can be any of a wide range of systems such as cameras, wireless devices, displays, chipsets, set-top boxes, games, lighting, vehicles, clocks, televisions, cellular phones, personal computers, automobiles, industrial control systems, aircraft, etc.

[0056] In this document, unless otherwise indicated, "vertical", "higher", "upper", "lower", "top", "top", "bottom", "above", "below", "down", "under", "upward", and "downward" generally refer to the vertical direction. "Horizontal" refers to the general direction along the surface of the main substrate (i.e., within 10 degrees) and can be relative to the substrate processed during manufacturing, and vertical is a direction generally orthogonal thereto. Reference to "just horizontal" is along the surface of the main substrate (i.e., not forming a degree with the surface) and can be relative to the substrate processed during manufacturing. In addition, "vertical" and "horizontal" as used herein are generally perpendicular directions relative to each other and are independent of the orientation of the substrate in three-dimensional space. In addition, "vertically extending" and "vertically extending" refer to a direction inclined at least 45° from just horizontal. In addition, "vertically extending", "vertically extending", "horizontally extending", "horizontally extending", etc., relative to a field effect transistor, are references to the orientation of the channel length of the transistor, and in operation, the current flows between the source / drain regions along the orientation. For bipolar junction transistors, "vertically extending", "vertically extending", "horizontally extending", "horizontally extending", etc. are referenced to the orientation of the substrate length along which current flows between the emitter and the collector in operation. In some embodiments, any component, feature, and / or region that extends vertically extends vertically or within 10° of vertical.

[0057] In addition, "directly above," "directly below," and "directly below" require at least some lateral overlap (i.e., horizontally) of the two stated areas / materials / components relative to each other. Likewise, the use of "above" without a preceding "directly" requires only that some portion of the stated area / material / component that is above another stated area / material / component is vertically outside of the other stated area / material / component (i.e., regardless of whether there is any lateral overlap of the two stated areas / materials / components). Similarly, the use of "below" and "beneath" without a preceding "directly" requires only that some portion of the stated area / material / component that is below / beneath another stated area / material / component is vertically inside of the other stated area / material / component (i.e., regardless of whether there is any lateral overlap of the two stated areas / materials / components).

[0058] Any of the materials, regions, and structures described herein may be homogeneous or inhomogeneous, and in any case may be continuous or discontinuous over any material overlying it. When one or more example components are provided for any material, the material may include, consist essentially of, or consist of such one or more components. Furthermore, unless otherwise stated, each material may be formed using any suitable present or future developed technology, with atomic layer deposition, chemical vapor deposition, physical vapor deposition, epitaxial growth, diffusion doping, and ion implantation being examples.

[0059] In addition, "thickness" (without a directional adjective in front) used alone is defined as the average straight-line distance perpendicularly passing through a given material or region from the closest surface of an adjacent material or adjacent region with different compositions. In addition, the various materials or regions described herein may have a substantially constant thickness or a variable thickness. If there is a variable thickness, unless otherwise indicated, the thickness refers to the average thickness, and such materials or regions will have a certain minimum thickness and a certain maximum thickness due to the variable thickness. As used herein, "different compositions" only require that those parts of the two stated materials or regions that can directly abut against each other are chemically and / or physically different, such as when such materials or regions are not homogeneous. If the two stated materials or regions do not directly abut against each other, then in the case of such materials or regions being non-homogeneous, "different compositions" only require that those parts of the two stated materials or regions that are closest to each other are chemically and / or physically different. In this document, when the stated materials, regions or structures are in at least some physical contact relative to each other, the material, region or structure "directly abuts" another material, region or structure. In contrast, "above," "on," "adjacent to," "along," and "against" without being preceded by "directly" encompass "directly against" as well as configurations in which intervening materials, regions, or structures are such that the stated materials, regions, or structures are not in physical touching contact with each other.

[0060] As used herein, region-material-components are "electrically coupled" relative to one another if, in normal operation, electrical current is able to flow continuously from one region-material-component to another region-material-component, and the flow occurs primarily through the movement of subatomic positive and / or negative charges when sufficient subatomic positive and / or negative charges are generated. Another electronic component may be between the region-material-components and electrically coupled to the region-material-components. In contrast, when region-material-components are referred to as being "directly electrically coupled," there are no intervening electronic components (e.g., no diodes, transistors, resistors, transducers, switches, fuses, etc.) between the directly electrically coupled region-material-components.

[0061] Any use of "rows" and "columns" in this document is for convenience in distinguishing one series or orientation of features from another series or orientation of features, and components have been or may be formed along such "rows" and "columns". "Rows" and "columns" are used synonymously with respect to any series of regions, components and / or features, regardless of function. Regardless, rows may be straight and / or curved and / or parallel and / or non-parallel relative to each other, and columns may be the same. In addition, rows and columns may intersect at 90° relative to each other or at one or more other angles (i.e., other than straight angles).

[0062] The components of any of the conductive / conductor / conductive materials herein may be metallic materials and / or conductively doped semiconductive / semiconductive / semiconductive materials. "Metallic material" is any one or combination of elemental metals, any mixture or alloy of two or more elemental metals, and any one or more conductive metal compounds.

[0063] Any use of "selective" herein with respect to etching / etching, removing / removal, depositing, and / or forming / formation is such action performed on one stated material relative to another stated material acted upon in a ratio of at least 2:1 by volume. Additionally, any use of selectively depositing, selectively growing, or selectively forming is deposition, growth, or formation of one material relative to another stated material or materials for at least the first 75 angstroms in a ratio of at least 2:1 by volume.

[0064] Unless otherwise indicated, the use of "or" herein includes either and both.

[0065] As specified, the subject matter disclosed herein has been described in language more or less specific with respect to structural and methodological features. However, it should be understood that the claims are not limited to the specific features shown and described, as the components disclosed herein include example embodiments. Therefore, the claims have the full scope as written and should be appropriately interpreted in accordance with the doctrine of equivalents.

Claims

1. A method for forming a memory array including a string of memory cells, comprising: forming a conductor layer including a conductor material on a substrate; forming a stack comprising vertically alternating first and second layers over the conductor layer, the stack comprising laterally spaced apart memory block regions, strings of channel material extending through the first and second layers, the material of the first layer having a different composition than the material of the second layer; forming spaced-apart bodies of insulator material in a lowest one of the first layers in and longitudinally along opposite sides of individual ones of the memory block regions; and After forming the spaced-apart bodies of insulator material, a conductive material is formed in the lowermost first layer that directly electrically couples together channel material of individual ones of the strings of channel material and the conductor material of the conductor layer. The method of claim 1 , wherein the body of insulator material comprises an oxide. The method of claim 1 , wherein the conductive material is directly against the body of insulator material.

4. The method of claim 1 wherein the body of insulator material does not protrude laterally into the space between immediately adjacent laterally spaced memory block regions.

5. The method of claim 4, wherein the conductive material completely horizontally surrounds the respective periphery of the body of insulator material. The method of claim 5 , wherein the conductive material is directly against the body of insulator material.

7. The method of claim 1, wherein the conductive material does not completely horizontally surround a respective periphery of the body of insulator material. The method of claim 7 , wherein the conductive material horizontally covers a majority of the respective periphery.

9. The method of claim 8, wherein the conductive material horizontally covers at least 75% of the respective periphery.

10. The method of claim 9, wherein the conductive material is directly against the body of insulator material.

11. The method of claim 7 wherein the body of insulator material completely spans the space between immediately adjacent laterally spaced memory block regions in a finished circuitry configuration.

12. The method of claim 1, wherein the lowermost first layer is thicker than the first layer above it.

13. The method of claim 1, wherein a lowermost surface of the channel material of the string of channel materials never directly abuts any of the conductor materials in the conductor layer.

14. The method of claim 1, wherein the conductive material in the lowermost first layer directly abuts sidewalls of the channel material of the string of channel material.

15. The method of claim 1, wherein the conductive material in the lowermost first layer is directly against an uppermost surface of the conductive material of the conductor layer.

16. A method for forming a memory array comprising strings of memory cells, comprising: forming a conductor layer including a conductor material on a substrate; forming a lower portion of a stack above the conductor layer, the lower portion of the stack to include vertically alternating first and second layers, the stack including laterally spaced memory block regions, the material of the first layers having a different composition than the material of the second layers, the lowest of the first layers including a first sacrificial material; forming horizontally elongated lines in the lowermost first layer, the horizontally elongated lines individually between laterally adjacent memory block regions; the lines comprising a second sacrificial material having a composition different from: the first sacrificial material, the first layer of material formed or to be formed over the first sacrificial material, and the second layer of material formed or to be formed over the first sacrificial material; cutting the second sacrificial material of the line to form spaced-apart bodies of second sacrificial material in the lowermost first layer longitudinally along and between the laterally adjacent memory block regions and to expose the first sacrificial material in the lowermost first layer longitudinally between the spaced-apart bodies of second sacrificial material for a first time; isotropically etching the first exposed first sacrificial material from the lowermost first layer for a first time to form spaced-apart cavities in the first exposed first sacrificial material in the lowermost first layer in the laterally adjacent memory block regions and longitudinally along the laterally adjacent memory block regions; filling said spaced apart cavities and void spaces in said lowermost first layer with an insulator material, said spaced apart cavities and said void spaces individually between immediately adjacent said spaced apart bodies of second sacrificial material; forming the vertically alternating first and second layers of an upper portion of the stack above the lower portion and the line and forming a string of channel material extending through the first and second layers in the upper portion to the lowermost first layer in the lower portion; forming horizontally elongated trenches into the stack, the horizontally elongated trenches individually between the laterally adjacent memory block regions and extending into the spaced-apart bodies of second sacrificial material and the insulator material between the memory block regions; removing the second body of sacrificial material through the trenches and forming spaced-apart bodies of insulator material in the lowermost first layer in and longitudinally along opposite sides of individual ones of the memory block regions and to expose a second time a remaining portion of the first sacrificial material in the lowermost first layer; after forming the spaced-apart bodies of insulator material, isotropically etching the second exposed remaining first sacrificial material from the lowermost first layer through the trenches a second time; as well as After the second isotropic etching, a conductive material is formed in the lowermost first layer, the conductive material directly electrically coupling the channel material of individual ones of the strings of channel materials with the conductor material of the conductor layer.

17. The method of claim 16, wherein the lines individually include an uppermost surface above the lowermost first layer.

18. The method of claim 17, wherein the uppermost surface is in or at a top of the second layer immediately above the lowermost first layer.

19. The method of claim 16, wherein the wires individually include laterally opposed protrusions longitudinally therealong.

20. The method of claim 19, wherein the laterally opposed projections are spaced below an uppermost surface of the wire.

21. The method of claim 19, wherein the laterally opposed projections are spaced above a lowermost surface of the wire.

22. The method of claim 19, wherein the laterally opposing projections are spaced below an uppermost surface of the wire and spaced above a lowermost surface of the wire.

23. The method of claim 16, wherein the second sacrificial material comprises a metallic material.

24. The method of claim 23, wherein the metallic material comprises elemental tungsten.

25. The method of claim 16, comprising removing the insulator material through the trench prior to the second isotropically etching the second exposed remaining first sacrificial material.

26. The method of claim 16, wherein the lowermost first layer does not directly abut the conductor material of the conductor layer during the first isotropic etching.

27. The method of claim 16, wherein the second layer material of the second layer immediately above the lowermost first layer comprises an upper first insulating material and a lower second material below the upper first insulating material, the lower second material having a composition different from that of the upper first insulating material.

28. The method of claim 27, wherein the conductive material directly abuts the lower second material in the second layer immediately above the lowermost first layer.

29. The method of claim 16, comprising: forming pillars in the lower portion prior to forming the upper portion, the pillars being individually horizontally positioned where individual ones of the strings of channel material are to be formed; as well as removing the pillars prior to forming the strings of channel material; as well as The strings of channel material are formed to extend individually into individual void spaces created by the removal of the pillars.

30. The method of claim 29, wherein the support post comprises the second sacrificial material.

31. The method of claim 29, wherein the struts individually include radial protrusions spaced below an uppermost surface of the struts and spaced above a lowermost surface of the struts.

32. A memory array comprising a string of memory cells, comprising: a conductor layer comprising a conductor material; laterally spaced memory blocks, individually comprising a vertical stack directly above the conductor layer, the vertical stack comprising alternating insulating and conductive layers, with strings of channel material of memory cells extending through the insulating and conductive layers; bodies of insulator material in the lowest of the conductive layers in and longitudinally along opposite sides of individual ones of the memory blocks, the bodies of insulator material being spaced longitudinally along the memory blocks relative to one another; as well as A conductive material is in the lowest conductive layer, the conductive material directly electrically coupling the channel material of individual ones of the strings of channel material with the conductor material of the conductor layer.

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