Semiconductor structure and its formation method

Abstract

The present application provides a semiconductor structure and a method for forming the same, including: providing a semiconductor substrate, wherein an isolation structure is formed in the semiconductor substrate; forming a gate structure on the surface of the semiconductor substrate and the isolation structure, wherein the gate structure includes a gate dielectric layer formed on the surface of the semiconductor substrate and the isolation structure and a gate layer formed on the surface of the gate dielectric layer; forming sidewalls on both sides of the gate structure; removing part of the gate layer located on the isolation structure to expose part of the surface of the gate dielectric layer, and then filling a metal gate at the corresponding position. The semiconductor structure and the method for forming the same provided by the present application can solve the leakage and mismatch problems of existing devices and greatly improve the fault tolerance of semiconductor manufacturing processes.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] With the continuous development of integrated circuit technology, it is required that the number of semiconductor devices that can be integrated in a single chip is as large as possible. When designing integrated circuits, it is usually necessary to use several semiconductor devices with the same electrical parameters, such as MOS transistors. However, during the design and production of devices, due to uncertainty, random errors and other reasons, some MOS transistors that are exactly the same in design have errors after production, that is, the electrical parameters of nominally identical MOS transistors often drift, causing mismatch of the electrical parameters of the MOS transistors that should have been the same, that is, the matching characteristics are reduced, which will affect the performance of the semiconductor.

[0003] There are many specific reasons for this mismatch in transistor electrical parameters, the main of which include: when forming a metal gate (MG) at the connection between the polysilicon gate and the contact hole on the isolation structure, the critical dimension (CD) of the mask used is too large or it is not aligned with the front layer during exposure, resulting in the formation of a metal gate on the active area (AA). Then the threshold voltage (Vt) of the device where the metal gate area is formed on the active area will be controlled by the metal gate, and the threshold voltage of the remaining devices will still be controlled by the polysilicon gate, and the Vt controlled by the metal gate is smaller than the Vt controlled by the polysilicon gate. After the voltage is provided, the device controlled by the metal gate will be turned on earlier than the device controlled by the polysilicon gate, resulting in leakage, which in turn causes differences in the Vt of devices of the same size. Summary of the invention

[0004] The technical problem to be solved by the present application is that the existing metal gate structure has very high requirements on the error tolerance of the formation process. However, when the existing process forms a metal gate on the isolation structure, the metal gate is often formed in part of the active area at the same time due to the existence of process errors, thereby causing leakage and mismatch problems of the active area devices.

[0005] To solve the above technical problems, the present application discloses a method for forming a semiconductor structure, comprising: providing a semiconductor substrate, wherein an isolation structure is formed in the semiconductor substrate; forming a gate structure on the surfaces of the semiconductor substrate and the isolation structure, wherein the gate structure comprises a gate dielectric layer formed on the surfaces of the semiconductor substrate and the isolation structure and a gate layer formed on the surface of the gate dielectric layer; forming side walls on both sides of the gate structure; removing a portion of the gate layer located on the isolation structure to expose a portion of the surface of the gate dielectric layer, and then filling a metal gate at the corresponding position.

[0006] In an embodiment of the present application, a process of removing a portion of the gate layer on the isolation structure to expose a portion of the surface of the gate dielectric layer, and then filling a metal gate at a corresponding position includes: removing a portion of the gate layer on the isolation structure to form a groove, wherein the groove does not penetrate the gate layer in a width direction of the gate layer; and filling metal in the groove to form a metal gate.

[0007] In an embodiment of the present application, the width of the metal gate is at least 160 nanometers.

[0008] In an embodiment of the present application, the depth of the metal gate is 250 to 600 nanometers.

[0009] In an embodiment of the present application, the metal gate is located on both sides of the remaining gate layer.

[0010] In an embodiment of the present application, the distance between the metal gates is at least 160 nanometers.

[0011] In an embodiment of the present application, a dry etching process is used to remove a portion of the gate layer on the surface of the isolation structure.

[0012] In an embodiment of the present application, a top surface of the metal gate is flush with a top surface of the gate layer.

[0013] In an embodiment of the present application, after forming the spacers on both sides of the gate structure, the method further includes: forming a source and a drain in the semiconductor substrate on both sides of the gate structure.

[0014] In an embodiment of the present application, after forming the metal gate, the method further includes: forming an interlayer dielectric layer on the metal gate, the gate layer and the surface of the sidewall; etching the interlayer dielectric layer until the metal gate is exposed to form a contact hole.

[0015] An embodiment of the present application also provides a semiconductor structure, including: a semiconductor substrate, in which an isolation structure is formed; a gate structure, including a gate dielectric layer located on the surface of the semiconductor substrate and the isolation structure and a gate layer located on the surface of the gate dielectric layer; a metal gate located on a portion of the surface of the gate dielectric layer on the isolation structure and flush with the gate layer; and sidewalls located on the surfaces of the semiconductor substrate and the isolation structure on both sides of the gate structure and flush with the gate layer.

[0016] In an embodiment of the present application, the width of the metal gate is at least 160 nanometers.

[0017] In an embodiment of the present application, the thickness of the metal gate is 250 to 600 nanometers.

[0018] In an embodiment of the present application, the metal gate is located on both sides of the gate layer.

[0019] In an embodiment of the present application, the distance between the metal gates is at least 160 nanometers.

[0020] In an embodiment of the present application, a top surface of the metal gate is flush with a top surface of the gate layer.

[0021] Compared with the prior art, the technical solution of the present application has at least the following beneficial effects: in the semiconductor structure of the present application, the metal gate does not penetrate the gate layer in the width direction of the gate layer. Even when etching the gate layer on the isolation structure to form a metal gate, there are errors in the process parameters, such as the mask size is too large or the mask is not aligned with the gate layer, so that a metal gate is also formed on the active area. However, since the metal gate does not penetrate the gate layer in the width direction of the gate layer, the threshold voltage of the device on the active area semiconductor is not controlled by the metal gate, but is still controlled by the gate structure, which will not cause leakage and mismatch problems in the device on the active area semiconductor, greatly improving the fault tolerance of the semiconductor manufacturing process.

[0022] Furthermore, in order to meet the current process manufacturing requirements, the present application preferably forms a metal gate on both sides of the gate layer on the surface of the isolation structure. This metal gate structure reduces the stringent requirements of the etching process on the mask layer CD. If the mask layer CD is large, it can extend beyond the gate layer to the interlayer dielectric layer on both sides.

[0023] Furthermore, the present application adopts a dry etching process with a high etching ratio, which can achieve etching of the gate layer while avoiding loss of the interlayer dielectric layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0025] Figures 1 to 3 A schematic diagram of a semiconductor structure;

[0026] Figures 4 to 14 Schematic diagram of the structure corresponding to each step of the method for forming a semiconductor structure in an embodiment of the present application. DETAILED DESCRIPTION

[0027] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0028] In the description of the present application, it should be understood that the orientation or positional relationship indicated by the terms "upper", "lower", "top", "bottom", etc. is based on the orientation or positional relationship shown in the accompanying drawings, which is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation of the present application. In addition, the terms "first" and "second" are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, the features defined as "first" and "second" can explicitly or implicitly include one or more of the features. Moreover, the terms "first", "second", etc. are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein.

[0029] Combination Figures 1 to 3 As shown, Figure 1 It is a three-dimensional structural schematic diagram of a semiconductor structure. Figure 2 for Figure 1 A top view of Figure 3 for Figure 1 The semiconductor structure includes a semiconductor substrate 100 , in which an isolation structure 110 is formed. The isolation structure 110 may be a shallow trench isolation.

[0030] A gate structure is formed on the surface of the semiconductor substrate 100 and the isolation structure 110. Sidewall spacers 140 are formed on both sides of the gate structure. An interlayer dielectric layer 170 is formed on the surface of the semiconductor substrate 100 and the isolation structure 110 on both sides of the sidewall spacers 140.

[0031] The gate structure includes a gate dielectric layer 131 formed on the surface of the semiconductor substrate 100 and the isolation structure 110 and a gate layer 132 formed on the surface of the gate dielectric layer 131. When a metal gate is formed in a subsequent process, the gate layer 132 on the surface of the isolation structure 110 will be etched and a metal gate material will be filled at the corresponding position.

[0032] Please refer to Figure 1 and Figure 3A metal gate 150 is formed on the surface of the gate dielectric layer 131 on the isolation structure 110, and the top surface of the metal gate 150 is flush with the top surface of the gate layer 132 on the surface of the semiconductor substrate 100. When the metal gate 150 is formed, the gate layer 132 is first removed to form a groove, and then the groove is filled with metal to form the metal gate 150.

[0033] Please refer to Figure 1 and Figure 2 , a dry etching process is usually used to remove the gate layer 132 on the isolation structure 110. The CD of the mask used for etching may have errors, and it is very likely to cover the semiconductor substrate in the active area. Or, when the mask is not strictly aligned with the front layer (such as the gate layer) during exposure, it is possible to etch the gate layer 132 on the semiconductor substrate in the active area. When filling the metal, a metal gate 160 will also be formed on the semiconductor substrate 100 in the active area, thereby generating a parasitic MOS device.

[0034] Specifically, for the device on the semiconductor substrate 100 , the Vt of the device at the location where the metal gate 160 is formed is controlled by the metal gate 160 , and the Vt of the device at other locations is still controlled by the gate layer 132 on the semiconductor substrate 100 .

[0035] When the gate layer 132 is a polysilicon gate, the Vt of the device controlled by the metal gate 160 is lower than the Vt of the device controlled by the polysilicon gate. Therefore, after a voltage is provided to the device on the semiconductor substrate 100, the device controlled by the metal gate 160 will be turned on earlier than the device controlled by the gate layer 132, resulting in leakage, and thus causing differences in the Vt of devices of the same size.

[0036] Based on this, the semiconductor structure provided in the present application improves the existing metal gate structure that penetrates the polysilicon gate, and will not cause device leakage and mismatch problems even if the CD of the mask is too large or misaligned during etching.

[0037] The method for forming a semiconductor structure provided in the present application includes:

[0038] Step S1: providing a semiconductor substrate, wherein an isolation structure is formed in the semiconductor substrate;

[0039] Step S2: forming a gate structure on the surface of the semiconductor substrate and the isolation structure, wherein the gate structure includes a gate dielectric layer formed on the surface of the semiconductor substrate and the isolation structure and a gate layer formed on the surface of the gate dielectric layer;

[0040] Step S3: forming sidewalls on both sides of the gate structure;

[0041] Step S4: removing a portion of the gate layer on the isolation structure to expose a portion of the surface of the gate dielectric layer, and then filling a metal gate at a corresponding position, wherein the metal gate does not penetrate the gate layer in a width direction of the gate layer.

[0042] The above specific process is described in detail below with reference to the accompanying drawings. Figures 4 to 14 This is a structural schematic diagram of the formation process of the semiconductor structure according to an embodiment of the present application.

[0043] Please refer to Figure 4 , step S1, providing a semiconductor substrate 200. The semiconductor substrate 200 may be at least one of the following materials: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP or other III / V compound semiconductors, and may also include a multilayer structure consisting of the material layers or a silicon-on-insulator (SOI), a stacked silicon-on-insulator (SSOI), etc. In this embodiment, the material of the semiconductor substrate 200 is single crystal silicon or silicon-on-insulator.

[0044] An isolation structure is formed on the semiconductor substrate 200. The isolation structure may be a shallow trench isolation. The isolation structure may include an insulating dielectric layer 210 and an oxide layer 220 located between the insulating dielectric layer 210 and the semiconductor substrate 200. The material of the oxide layer 220 is, for example, a silicon oxide layer, which may be formed by a thermal oxidation process. The material of the insulating dielectric layer 210 may be silicon oxide, silicon nitride, or silicon oxynitride. In this embodiment, the material of the insulating dielectric layer 210 is silicon oxide, and the process for forming the insulating dielectric layer 210 may be a chemical vapor deposition process or a physical vapor deposition process. Optionally, the chemical vapor deposition process may be, for example, a high aspect ratio (HARP) deposition process. Of course, the isolation structure may also be any other known trench isolation structure, and the method for forming the isolation structure may also be any method for manufacturing a trench isolation structure, which is not limited in this application.

[0045] Step S2, forming a gate structure on the surface of the semiconductor substrate and the isolation structure, wherein the gate structure includes a gate dielectric layer formed on the surface of the semiconductor substrate and the isolation structure and a gate layer formed on the surface of the gate dielectric layer.

[0046] Please refer to Figure 5 and Figure 6 , Figure 6 for Figure 5Cross-sectional view along direction BB. First, gate dielectric material and gate material are grown in sequence on the surface of the semiconductor substrate 200 and the isolation structure. Deposition methods such as furnace tube process, chemical vapor deposition process or physical vapor deposition process can be adopted. The gate dielectric material may include high dielectric materials such as silicon oxide, silicon oxynitride, hafnium oxide, titanium nitride, etc., and the deposited gate dielectric material may include a single layer or multiple layers. The gate material may be polycrystalline silicon. In other embodiments of the present application, the gate material may also include at least one material selected from silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, carbon oxynitride silicon or amorphous carbon.

[0047] Then, the gate material and the gate dielectric material are etched to form a gate layer 310 and a gate dielectric layer 320, and the gate layer 310 and the gate dielectric layer 320 constitute a gate structure. In other embodiments, the gate structure can also be a single-layer structure, and accordingly, the gate structure includes a gate layer 310, and the thickness of the gate layer 310 is 250 to 600 nanometers.

[0048] Please refer to Figure 7 , step S3, forming sidewalls 410 on both sides of the gate structure. The sidewalls 410 define the position of ion implantation in subsequent processes and can also protect the gate structure.

[0049] In the embodiment of the present application, the sidewall 410 is a single-layer structure, and the material of the sidewall 410 is silicon nitride. In other embodiments of the present application, the material of the sidewall can also be silicon oxide, silicon carbide, silicon carbonitride, silicon carbonitride oxide, silicon nitride oxide, boron nitride or boron carbonitride and other materials. In some other embodiments of the present invention, the sidewall can also be a stacked structure.

[0050] The method for forming the sidewall 410 is to deposit a barrier material layer on the surface of the semiconductor substrate 200, the surface of the gate structure, the sidewall and the surface of the isolation structure, which can be deposited by chemical vapor deposition or grown by furnace tube process. Then, the barrier material layer on the surface of the isolation structure, the surface of the gate layer 310 of the gate structure and the surface of the semiconductor substrate 200 is removed, and the sidewall is formed on both sides of the gate layer 310 and the gate dielectric layer 320 of the gate structure.

[0051] After forming the sidewall 410, the formation method may further include: forming a lightly doped source and drain region (not shown in the figure) in the semiconductor substrate 200 on both sides of the gate structure. Specifically, using the sidewall 410 as a mask, doping ions are implanted into the semiconductor substrate 200 on both sides of the gate structure, and annealing is performed after the ion implantation to activate the doping ions.

[0052] Next, a first interlayer dielectric layer may be formed on the surface of the semiconductor substrate and the surface of the isolation structure on both sides of the sidewalls, and the top surface of the first interlayer dielectric layer is flush with the top surface of the gate layer.

[0053] Please refer to Figure 8 , a chemical vapor deposition process or a physical vapor deposition process can be used to deposit an interlayer dielectric material on the surface of the semiconductor substrate 200, the surface of the isolation structure and the surface of the gate structure, and the interlayer dielectric material is a material with a high aspect ratio, such as silicon oxide. Then, the interlayer dielectric material is planarized to expose the surface of the gate layer 310, and a first interlayer dielectric layer 510 flush with the top surface of the gate layer 310 is formed on the surface of the semiconductor substrate 200 and the surface of the isolation structure.

[0054] Then, step S4 is performed to remove a portion of the gate layer located on the isolation structure to expose a portion of the surface of the gate dielectric layer, and then fill a metal gate at the corresponding position.

[0055] First, a portion of the gate layer 310 on the isolation structure is removed to form a groove. Unlike the groove structure formed in the prior art that penetrates the gate layer 310 in the width direction of the gate layer 310, the groove formed in the present application does not penetrate the gate layer 310 in the width direction of the gate layer 310. The advantage of this improvement is that if the CD of the mask used to form the groove is too large or it is not aligned with the gate layer 310 during etching, so that part of the formed groove is located on the isolation structure and the other part is located on the active area semiconductor substrate, since the groove of the present application does not penetrate the gate layer 310 in the width direction of the gate layer 310, the groove located on the active area semiconductor substrate does not penetrate the gate layer on the semiconductor substrate, so after the subsequent process forms a metal gate in the groove, the metal gate located on the active area semiconductor substrate does not penetrate the gate layer on the active area semiconductor substrate, so the threshold voltage of the device at the metal gate on the active area semiconductor substrate is not controlled by the metal gate, but is still controlled by the original gate structure, thereby solving the leakage and mismatch problems of the device caused by process errors.

[0056] The groove structure formed in the present application that does not penetrate the gate layer 310 in the width direction of the gate layer 310 has the following specific implementations.

[0057] Please refer to Fig. 9, a specific implementation of the present application is to remove part of the gate layer 310 on the surface of the isolation structure, expose part of the surface of the gate dielectric layer 320, and form a groove on both sides of the remaining gate layer 310. Specifically, the groove is located between the sidewall 410 and the gate layer 310, such as the groove 611 and the groove 612 in the figure. The width of the groove 611 and the groove 612 is at least 160 nanometers, and the groove 611 and the groove 612 are not connected. The distance between the groove 611 and the groove 612 is at least 160 nanometers, that is, the width of the gate layer 310 between the groove 611 and the groove 612 is at least 160 nanometers, and the depth of the groove 611 and the groove 612 is 250 to 600 nanometers.

[0058] When forming the grooves 611 and 612, a mask layer (not shown in the figure) is first formed on the surface of the gate layer 310. If the size of the mask layer exceeds the gate layer 310 in the actual process, the mask layer can be extended to the surfaces of the interlayer dielectric layer 510 on both sides, the mask layer is patterned, and the gate layer 310 is etched to form grooves. Since a high selectivity dry etching process is used during etching, there is almost no loss of the interlayer dielectric layer 510. In the embodiment of the present application, the gas used during dry etching can be oxygen, fluorocarbon, etc.

[0059] Please refer to Fig.10 The second specific implementation of the present application is to remove part of the gate layer 310 on the surface of the isolation structure, expose part of the surface of the gate dielectric layer 320, and form a groove 610 between the gate layer 310 and the sidewall 410. The width of the groove 610 is at least 160 nanometers. The specific width of the groove 610 should match other processes, such as the current density of the contact hole. If the current density is large, the number of contact holes required will also be large, so the width of the groove 610 should also increase accordingly. When the width requirement is high, it extends to the interlayer dielectric layer in the direction outside the polysilicon gate width. In short, the width direction does not penetrate the gate layer 310. Its formation process is similar to the first specific implementation.

[0060] Please refer to Fig.11 Another specific implementation of the present application is to remove part of the gate layer 310 on the surface of the isolation structure and form a groove 610 between the remaining gate layers 310. The problem with this method is that when the width of the gate layer 310 itself is small, due to the limitation of the mask layer CD used in the current etching process, it is impossible to ensure that the groove is formed only in the middle of the gate layer 310. The groove formed by the first two methods is located between the gate layer 310 and the sidewall 410, and the mask layer can extend to the interlayer dielectric layer on both sides. Combined with a dry etching process with a high etching ratio, it is possible to form a groove 610 only at the gate layer.

[0061] Taking the formation of grooves on both sides of the remaining gate layer 310 as an example, the subsequent process steps are described.

[0062] Please refer to Fig.12 , metal is filled into the groove 611 and the groove 612 to form metal gates 711 and metal gates 712. The top surfaces of the metal gates 711 and metal gates 712 are flush with the top surface of the gate layer 310. The width of the metal gates 711 and metal gates 712 is at least 160 nanometers, and the thickness is 250 to 600 nanometers. The distance between the metal gates 711 and metal gates 712 is at least 160 nanometers.

[0063] Please refer to Fig.13 and Fig.14 , Fig.13 Schematic diagram of the three-dimensional structure after the metal gate 711 and the metal gate 712 are formed. Fig.14 for Fig.13 The top view of the device is shown in FIG. 1 , where the dotted line in the figure indicates the boundary between the isolation structure and the active area. The reason why the metal gate structure formed in the embodiment of the present application can solve the leakage and mismatch problems of the device is now analyzed in detail.

[0064] Fig.13 and Fig.14 The metal gate of the embodiment of the present application shown is formed in the presence of process errors. When etching the groove, the CD of the mask is too large and covers the gate layer 310 on part of the active area semiconductor. Therefore, while etching the gate layer 310 above the isolation structure, the gate layer 310 above part of the active area semiconductor is also etched away. Metal is filled into the groove formed by etching to form a metal gate. Therefore, it can be seen in the figure that a part of the metal gate is also formed above the active area semiconductor.

[0065] However, since the formed metal gate 711 and metal gate 712 do not completely cover the gate layer 131 on the active area semiconductor in the width direction, that is, there is still a part of the gate layer 310 between the metal gate 711 and the metal gate 712, the threshold voltage of the device located at the metal gate 711 and the metal gate 712 will not be controlled by the metal gate 711 and the metal gate 712, but will still be controlled by the gate structure. Therefore, even if a metal gate is formed on the active area semiconductor substrate due to process errors, it will not affect the threshold voltage of the device on the active area semiconductor substrate, thereby improving the fault tolerance of the semiconductor manufacturing process.

[0066] After forming the metal gate 711 and the metal gate 712, some conventional steps may be performed as follows:

[0067] An interlayer dielectric material is deposited on the surface of the metal gate, gate layer, sidewall and first interlayer dielectric layer. After being deposited to a specified thickness, the interlayer dielectric material is planarized to form a second interlayer dielectric layer, and then the second interlayer dielectric layer is etched until the metal gate is exposed to form a contact hole.

[0068] Please refer to Fig.12 The embodiment of the present application also provides a semiconductor structure, mainly including: a semiconductor substrate 200, in which an isolation structure is formed; a gate structure, including a gate dielectric layer 320 located on the surface of the semiconductor substrate 200 and the isolation structure and a gate layer 310 located on the surface of the gate dielectric layer 320; a metal gate located on the surface of a portion of the gate dielectric layer 320 on the isolation structure and flush with the gate layer 310; and a sidewall 410 located on the surface of the semiconductor substrate and the isolation structure on both sides of the gate structure and flush with the gate layer 310.

[0069] In the embodiment of the present application, the metal gate is located at two sides of the gate layer, namely, the metal gate 711 and the metal gate 712 , and the metal gate 711 and the metal gate 712 are located between the sidewall 410 and the gate layer 310 .

[0070] In the embodiment of the present application, the width of the metal gate is at least 160 nanometers, the thickness is 250 to 600 nanometers, and the distance between the metal gate 711 and the metal gate 712 is at least 160 nanometers.

[0071] In the embodiment of the present application, the material of the gate layer 310 is polysilicon. The material of the metal gate 711 and the metal gate 712 includes a work function metal, for example, at least one of tungsten, aluminum and cobalt.

[0072] In the embodiment of the present application, the semiconductor structure may further include a first interlayer dielectric layer 510 , which is located on the semiconductor substrate 200 and the isolation structure surface on both sides of the sidewall 410 and is flush with the top surface of the gate layer 310 .

[0073] In other embodiments of the present application, the metal gate is Fig.10 or Fig.11 The groove is filled with metal.

[0074] In summary, after reading this detailed disclosure, it will be apparent to those skilled in the art that the foregoing detailed disclosure may be presented only by way of example and may not be limiting. Although not explicitly stated herein, it will be appreciated by those skilled in the art that this application is intended to encompass various reasonable changes, improvements, and modifications to the embodiments. These changes, improvements, and modifications are intended to be proposed by this disclosure and are within the spirit and scope of the exemplary embodiments of this disclosure.

[0075] In addition, certain terms in this application have been used to describe embodiments of the present disclosure. For example, "one embodiment", "embodiment" and / or "some embodiments" mean that a particular feature, structure or characteristic described in conjunction with the embodiment may be included in at least one embodiment of the present disclosure. Therefore, it can be emphasized and should be understood that two or more references to "embodiment" or "one embodiment" or "alternative embodiment" in various parts of this specification do not necessarily refer to the same embodiment. In addition, specific features, structures or characteristics may be appropriately combined in one or more embodiments of the present disclosure.

[0076] It should be understood that in the foregoing description of the embodiments of the present disclosure, in order to help understand a feature and for the purpose of simplifying the present disclosure, the present application sometimes combines various features in a single embodiment, drawing or its description. Alternatively, the present application disperses various features in multiple embodiments of the present application. However, this does not mean that the combination of these features is necessary. It is entirely possible for those skilled in the art to extract some of the features and understand them as separate embodiments when reading the present application. In other words, the embodiments in the present application can also be understood as the integration of multiple secondary embodiments. This is also true when the content of each secondary embodiment is less than all the features of a single aforementioned disclosed embodiment.

[0077] In some embodiments, the numbers expressing the quantity or properties of certain embodiments of the present application used to describe and claim protection should be understood as being modified in some cases by the terms "about", "approximately" or "substantially". For example, unless otherwise stated, "about", "approximately" or "substantially" may represent a ±20% variation of the value described. Therefore, in some embodiments, the numerical parameters listed in the written description and the attached claims are approximate values, which may vary depending on the desired properties that a particular embodiment attempts to obtain. In some embodiments, the numerical parameters should be interpreted according to the number of reported significant figures and by applying ordinary rounding techniques. Although some embodiments of the present application are described, the numerical ranges and parameters listed in a wide range are approximate, but the numerical values ​​that are as accurate as possible are listed in the specific examples.

[0078] Each patent, patent application, patent application publication, and other materials, such as articles, books, specifications, publications, documents, articles, etc., cited herein may be incorporated herein by reference in its entirety for all purposes, except for any prosecution document history related thereto, any equivalent that may be inconsistent or conflicting with this document, or any equivalent prosecution document history that may have a limiting effect on the broadest scope of the claims now or later associated with this document. For example, if there is any inconsistency or conflict between the description, definition, and / or use of a term associated with any of the incorporated materials and the term, description, definition, and / or use associated with this document, the term in this document shall control.

[0079] Finally, it should be understood that the embodiments of the application disclosed herein are explanations of the principles of the embodiments of the present application. Other modified embodiments are also within the scope of the present application. Therefore, the embodiments disclosed in the present application are merely examples and not limitations. Those skilled in the art can adopt alternative configurations according to the embodiments in the present application to implement the application in the present application. Therefore, the embodiments of the present application are not limited to which embodiments have been accurately described in the application.

Claims

1. A method for forming a semiconductor structure, characterized in that: The method is used to form a MOS transistor, comprising: Providing a semiconductor substrate having an isolation structure formed therein; A gate structure is formed on the surface of the semiconductor substrate and the isolation structure, wherein the gate structure includes a gate dielectric layer formed on the surface of the semiconductor substrate and the isolation structure and a gate layer formed on the surface of the gate dielectric layer, the extension direction of the gate structure is perpendicular to the extension direction of the isolation structure, and the material of the gate layer is polycrystalline silicon or the material of the gate layer includes polycrystalline silicon and at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon carbon oxynitride or amorphous carbon; Forming sidewalls on both sides of the gate structure; In the extension direction of the isolation structure, a portion of the gate layer on the isolation structure is removed to form a groove, wherein the groove does not penetrate the gate layer in the extension direction of the isolation structure; The groove is filled with metal to form a metal gate.

2. The method for forming a semiconductor structure according to claim 1, wherein: The width of the metal gate is at least 160 nanometers.

3. The method for forming a semiconductor structure according to claim 1, wherein: The depth of the metal gate is 250 to 600 nanometers.

4. The method for forming a semiconductor structure according to claim 1, wherein: The metal gate is located on both sides of the remaining gate layer.

5. The method for forming a semiconductor structure according to claim 4, characterized in that: The distance between the metal gates is at least 160 nanometers.

6. The method for forming a semiconductor structure according to claim 1, wherein: A dry etching process is used to remove part of the gate layer on the surface of the isolation structure.

7. The method for forming a semiconductor structure according to claim 1, wherein: The top surface of the metal gate is flush with the top surface of the gate layer.

8. The method for forming a semiconductor structure according to claim 1, wherein: After forming the spacers on both sides of the gate structure, the method further includes: forming a source and a drain in the semiconductor substrate on both sides of the gate structure.

9. The method for forming a semiconductor structure according to claim 1, wherein: After forming the metal gate, it also includes: forming an interlayer dielectric layer on the surfaces of the metal gate, the gate layer and the sidewall; The interlayer dielectric layer is etched until the metal gate is exposed to form a contact hole.

10. A semiconductor structure, characterized in that: Formed by any one of claims 1 to 9, the semiconductor structure is a MOS transistor, comprising: a semiconductor substrate having an isolation structure formed therein; A gate structure, comprising a gate dielectric layer located on the surface of the semiconductor substrate and the isolation structure and a gate layer located on the surface of the gate dielectric layer, wherein an extension direction of the gate structure is perpendicular to an extension direction of the isolation structure; A metal gate is located on a surface of a portion of the gate dielectric layer on the isolation structure and is flush with the gate layer; The sidewalls are located on the surfaces of the semiconductor substrate and the isolation structure at both sides of the gate structure and are flush with the gate layer.

11. The method for forming a semiconductor structure according to claim 10, characterized in that: The width of the metal gate is at least 160 nanometers.

12. The method for forming a semiconductor structure according to claim 10, wherein: The thickness of the metal gate is 250 to 600 nanometers.

13. The method for forming a semiconductor structure according to claim 10, wherein: The metal gate is located at two sides of the gate layer.

14. The method for forming a semiconductor structure according to claim 13, wherein: The distance between the metal gates is at least 160 nanometers.

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