Electrical port module and method for obtaining working status thereof, and computer storage medium

Abstract

The present invention discloses an electrical port module and a method for obtaining its working state, and a computer storage medium. The method for obtaining the working state of the electrical port module comprises obtaining state storage address information; determining a target read address of a PHY chip according to the state storage address information; and reading the working state of the electrical port module in the target read address. The present invention first obtains the state storage address information, then determines the target read address of the PHY chip according to the state storage address information, and then reads the working state of the electrical port module from the target read address. Since the state storage address information is obtained in real time according to user needs, the working state of the PHY chip required by the user can be obtained in real time according to user needs, thereby reflecting the working state of the electrical port module in real time through the working state of the PHY chip.

Description

Technical Field

[0001] The present invention relates to the field of on-site communication technology, and in particular to an electrical port module, a method for acquiring a working state thereof, and a computer storage medium. Background Art

[0002] At present, the link distance between devices in most data centers is between 10m and 100m. The use of SFP+ electrical port modules can make up for the shortcomings in this range. Electrical port is a general term for various twisted pair interfaces such as RJ45 in servers and networks. It mainly refers to copper cables, including ordinary network cables and radio frequency coaxial cables, which process electrical signals. Since these ports use electricity as the carrier medium of information, they are collectively referred to as electrical ports. The electrical port module is also called an optical port to electrical port module and an optoelectronic conversion optical module. It is a module that supports hot plugging and is packaged in the form of SFP. The connector type is RJ45 and is mainly used for short-distance data transmission.

[0003] After the gold finger interface device of the traditional electrical port module realizes communication conversion with the PHY chip to connect them, the working status of the electrical port module cannot be reflected in real time. Summary of the invention

[0004] The main purpose of the present invention is to provide an electrical port module and a method for obtaining its working status, and a computer-readable storage medium, aiming to solve the technical problem that the traditional electrical port module cannot reflect the working status of the electrical port module in real time.

[0005] To achieve the above object, the present invention provides a method for obtaining the working status of an electrical port module, wherein the method is used to obtain the working status of the electrical port module in real time, and the method comprises the following steps:

[0006] Get the state storage address information;

[0007] Determine a target read address of the PHY chip according to the state storage address information;

[0008] Read the working status of the electrical port module in the target read address.

[0009] Optionally, the step of determining a target read address of the PHY chip according to the state storage address information includes:

[0010] Determine a first register address and a first valid bit address of the PHY chip according to the state storage address information;

[0011] A target read address is determined according to the first register address and the first valid bit address.

[0012] Optionally, the step of reading the working status of the electrical port module in the target read address includes:

[0013] Get read instructions;

[0014] Read the state parameter in the target read address according to the read instruction;

[0015] The working state of the electrical port module is determined according to the state parameter.

[0016] Optionally, before the step of determining the target read address of the PHY chip according to the state storage address information, the step further includes:

[0017] Obtain a first write operation instruction;

[0018] The step of determining a target read address of the PHY chip according to the status storage address information is performed according to the first write operation instruction.

[0019] Optionally, before the step of determining the target read address of the PHY chip according to the state storage address information, the step further includes:

[0020] Get configuration address information and configuration parameters;

[0021] Determine a target configuration address of the PHY chip according to the configuration address information;

[0022] The configuration parameters are written into the target configuration address.

[0023] Optionally, the step of determining a target configuration address of the PHY chip according to the configuration address information includes:

[0024] Determine a second register address and a second valid bit address of the PHY chip according to the configuration address information;

[0025] A target configuration address is determined according to the second register address and the second valid bit address.

[0026] Optionally, before the step of determining the target configuration address of the PHY chip according to the configuration address information, the step further includes:

[0027] Get the second write operation instruction;

[0028] The step of determining the target configuration address of the PHY chip according to the configuration address information is performed according to the second write operation instruction.

[0029] Optionally, before the step of determining the target configuration address of the PHY chip according to the configuration address information, the step further includes:

[0030] Get the read flag information and write flag information;

[0031] The step of determining the target read address of the PHY chip according to the status storage address information is performed according to the read flag information, and the step of determining the target configuration address of the PHY chip according to the configuration address information is performed according to the write flag information.

[0032] In addition, the present invention also provides an electrical port module, which includes: a gold finger interface module, a PHY chip and a field programmable gate array controller, wherein the field programmable gate array controller is used to receive status storage address information sent from the gold finger interface module, and determine a target read address in the PHY chip according to the status storage address information, and then the field programmable gate array controller reads the working status of the electrical port module from the target read address.

[0033] In addition, the present invention also provides a computer-readable storage medium, on which is stored a program for obtaining the working status of an electrical port module. When the program for obtaining the working status of an electrical port module is executed by a processor, the steps of the method for obtaining the working status of an electrical port module as described in any of the above technical solutions are implemented.

[0034] An embodiment of the present invention proposes a method for obtaining the working status of an electrical port module. The method first obtains status storage address information, then determines a target read address of a PHY chip according to the status storage address information, and then reads the working status of the electrical port module from the target read address. Since the status storage address information is obtained in real time according to user needs, the working status of the PHY chip required by the user can be obtained in real time according to user needs, thereby reflecting the working status of the electrical port module in real time through the working status of the PHY chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 It is a schematic diagram of the terminal structure of the hardware operating environment involved in the embodiment of the present invention;

[0036] Figure 2 It is a flowchart of a first embodiment of a method for obtaining the working status of an electrical port module according to the present invention;

[0037] Figure 3 It is a flow chart of a second embodiment of a method for obtaining the working status of an electrical port module according to the present invention;

[0038] Figure 4 It is a structural schematic diagram of an electrical port module according to an embodiment of the present invention.

[0039] The realization of the purpose, functional features and advantages of the present invention will be further explained in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0040] It should be understood that the specific embodiments described herein are only used to explain the present invention, and are not used to limit the present invention.

[0041] The main solution of the embodiment of the present invention is: obtaining status storage address information; determining the target read address of the PHY chip according to the status storage address information; and reading the working status of the electrical port module in the target read address.

[0042] When the prior art reads the working status data of the PHY chip, the working status information of the PHY chip is read at the same address bit. However, there are multiple working statuses of the PHY chip, for example, the current status of the PHY chip port, including link up and link down, the current link speed of the link up port, the Loss status of different rates, whether the PHY chip is working normally, and the specific bad status of the PHY chip. If the position for reading the working status of the PHY chip does not change with the user's needs, only several fixed working statuses of the PHY chip can be read, and the corresponding working status of the PHY chip cannot be obtained in real time according to the actual needs of the user, and the working status of the electrical port module cannot be reflected in real time through the working status of the PHY chip.

[0043] The present invention provides a solution, which first obtains the status storage address information, then determines the target read address of the PHY chip according to the status storage address information, and then reads the working status of the electrical port module from the target read address. Since the status storage address information is obtained in real time according to user needs, the working status of the PHY chip required by the user can be obtained in real time according to user needs, so that the working status of the electrical port module is reflected in real time through the working status of the PHY chip.

[0044] like Figure 1 As shown, Figure 1 It is a schematic diagram of the terminal structure of the hardware operating environment involved in the embodiment of the present invention.

[0045] The terminal in the embodiment of the present invention may be an electrical port module provided with a Field Programmable Gate Array (FPGA) controller, or may be a Field Programmable Gate Array controller.

[0046] like Figure 1As shown, the terminal may include: a processor 1001, such as an FPGA, a network interface 1004, a user interface 1003, a memory 1005, and a communication bus 1002. Among them, the communication bus 1002 is used to realize the connection and communication between these components. The user interface 1003 may include a display screen (Display), an input unit such as a keyboard (Keyboard), and the optional user interface 1003 may also include a standard wired interface and a wireless interface. The network interface 1004 may optionally include a standard wired interface and a wireless interface (such as a WI-FI interface). The memory 1005 may be a high-speed RAM memory, or a stable memory (non-volatile memory), such as a disk memory. The memory 1005 may also be a storage device independent of the aforementioned processor 1001.

[0047] Those skilled in the art will understand that Figure 1 The terminal structure shown in the figure does not constitute a limitation on the terminal, and may include more or less components than shown in the figure, or combine certain components, or arrange the components differently.

[0048] like Figure 1 As shown, the memory 1005 as a computer storage medium may include an operating system, a network communication module, a user interface module, and a program for obtaining the working status of the electrical port module.

[0049] exist Figure 1 In the terminal shown, the network interface 1004 is mainly used to connect to the backend server and perform data communication with the backend server; the user interface 1003 is mainly used to connect to the client (user end) and perform data communication with the client; and the processor 1001 can be used to call the acquisition program of the working status of the electrical port module stored in the memory 1005, and perform the following operations:

[0050] Get the state storage address information;

[0051] Determine a target read address of the PHY chip according to the state storage address information;

[0052] Read the working status of the electrical port module in the target read address.

[0053] Further, the processor 1001 may call a program for acquiring the working status of the electrical port module stored in the memory 1005, and further perform the following operations:

[0054] Determine a first register address and a first valid bit address of the PHY chip according to the state storage address information;

[0055] A target read address is determined according to the first register address and the first valid bit address.

[0056] Further, the processor 1001 may call a program for acquiring the working status of the electrical port module stored in the memory 1005, and further perform the following operations:

[0057] Get read instructions;

[0058] Read the state parameter in the target read address according to the read instruction;

[0059] The working state of the electrical port module is determined according to the state parameter.

[0060] Further, the processor 1001 may call a program for acquiring the working status of the electrical port module stored in the memory 1005, and further perform the following operations:

[0061] Obtain a first write operation instruction;

[0062] The step of determining a target read address of the PHY chip according to the status storage address information is performed according to the first write operation instruction.

[0063] Further, the processor 1001 may call a program for acquiring the working status of the electrical port module stored in the memory 1005, and further perform the following operations:

[0064] Get configuration address information and configuration parameters;

[0065] Determine a target configuration address of the PHY chip according to the configuration address information;

[0066] The configuration parameters are written into the target configuration address.

[0067] Further, the processor 1001 may call a program for acquiring the working status of the electrical port module stored in the memory 1005, and further perform the following operations:

[0068] Determine a second register address and a second valid bit address of the PHY chip according to the configuration address information;

[0069] A target configuration address is determined according to the second register address and the second valid bit address.

[0070] Further, the processor 1001 may call a program for acquiring the working status of the electrical port module stored in the memory 1005, and further perform the following operations:

[0071] Get the second write operation instruction;

[0072] The step of determining the target configuration address of the PHY chip according to the configuration address information is performed according to the second write operation instruction.

[0073] Further, the processor 1001 may call a program for acquiring the working status of the electrical port module stored in the memory 1005, and further perform the following operations:

[0074] Get the read flag information and write flag information;

[0075] The step of determining the target read address of the PHY chip according to the status storage address information is performed according to the read flag information, and the step of determining the target configuration address of the PHY chip according to the configuration address information is performed according to the write flag information.

[0076] Please refer to Figure 2 A first embodiment of the present invention provides a method for obtaining the working status of an electrical port module, the method for obtaining the working status of the electrical port module comprising:

[0077] Step S10, obtaining status storage address information.

[0078] In this embodiment, the FPGA obtains the state storage address information through the gold finger interface module. When obtaining the state storage address information, the state storage address information can be input by the user in real time, that is, the user inputs the gold finger interface module in real time through an input device such as a keyboard or a touch screen, and then sends it to the FPGA through the gold finger interface module. The state storage address information can also be stored in the memory. When the trigger condition is met, the gold finger interface module sends the state storage address information to the FPGA.

[0079] FPGA can connect the gold finger interface module and the PHY chip for communication. The gold finger interface module is used to receive the Ethernet signal sent by the host computer and the status storage address information sent by the host computer, and send the Ethernet signal to the PHY chip for processing, so as to decode or encode the Ethernet signal through the PHY chip, and send the status storage address information to the FPGA, so as to execute the corresponding operation instructions on the PHY chip through the FPGA.

[0080] The state storage address information may include multiple address information. For example, the state storage address information may include register address information, most significant bit address information, and least significant bit address information, so that the FPGA can find the corresponding register of the PHY chip through the register address information, and find the corresponding address of the register through the most significant bit address information and the least significant bit address information.

[0081] Step S20: determining a target read address of the PHY chip according to the state storage address information.

[0082] In this embodiment, the FPGA searches layer by layer in the PHY chip according to the state storage address information to find the corresponding target read address. The specific method for determining the target read address may be to determine the first register address and the first valid bit address of the PHY chip according to the state storage address information, and then determine the target read address according to the first register address and the first valid bit address. Since the PHY chip has multiple registers, the first register address can be determined according to the state storage address information, and then the first valid bit address is determined under the first register according to the state storage address information, and finally the first valid bit address under the first register is used as the target read address, wherein the first valid bit address includes the most significant bit address and the least significant bit address.

[0083] Step S30, reading the working status of the electrical port module in the target read address.

[0084] When reading the working status of the electrical port module, first obtain the read instruction, then read the state parameters in the target read address according to the read instruction, and finally determine the working status of the PHY chip according to the state parameters, so that the working status of the electrical port module is reflected by the working status of the PHY chip. When performing a read operation through FPGA, it is necessary to obtain the read instruction through the gold finger interface module so that the FPGA enters the state of reading the state parameters and reads the state parameters in the determined target read address. The state parameters are stored in the target read address in the form of binary data. After reading the state parameters, the FPGA can convert the state parameters into the working status of the PHY chip according to the preset mapping relationship, so as to reflect the current working status of the electrical port module to the user in real time.

[0085] The working status of the PHY chip includes the current status of the PHY chip port, including link up and link down, the current link speed of the link up port, the Loss status of different rates, whether the PHY chip is working normally, and the specific bad status of the PHY chip.

[0086] In this embodiment, before executing step S20, the step of determining the target read address of the PHY chip according to the state storage address information, a first write operation instruction is obtained to enable the FPGA to enter a state of executing the operation instruction, reminding the FPGA that an operation instruction is about to arrive, so that the FPGA can execute the instruction obtained from the gold finger interface module, thereby executing the step of determining the target read address of the PHY chip according to the state storage address information.

[0087] The embodiment of the present invention first obtains the status storage address information, then determines the target read address of the PHY chip according to the status storage address information, and then reads the working status of the electrical port module from the target read address. Since the status storage address information is obtained in real time according to user needs, the working status of the PHY chip required by the user can be obtained in real time according to user needs, thereby reflecting the working status of the electrical port module in real time through the working status of the PHY chip.

[0088] Please refer to Figure 3 , based on the above Figure 2 The first embodiment described above, the second embodiment of the present invention provides a method for obtaining the working status of an electrical port module, before the step of determining the target read address of the PHY chip according to the status storage address information in step S20, further comprising:

[0089] Step S01, obtaining configuration address information and configuration parameters.

[0090] In this embodiment, the FPGA receives configuration address information and configuration parameters through the gold finger interface module. The configuration address information and configuration parameters can be input into the gold finger interface module in real time by the user through input devices such as a keyboard and a touch screen, and then sent to the FPGA through the gold finger interface module. The configuration address information and configuration parameters can also be stored in the memory. When the trigger condition is met, the configuration address information and configuration parameters are sent to the FPGA through the gold finger interface module.

[0091] The configuration address information may include multiple addresses. For example, the configuration address information may include a second register address and a second valid bit address, so that the FPGA finds the second register address in multiple registers through the configuration address information and finds the second valid bit address under the second register address, wherein the second valid bit address includes the most significant bit address and the least significant bit address.

[0092] Configuration parameters may include multiple parameters. For example, the FPGA may configure the PHY chip to an interface type of USXGMII, XFI, RXAUI, 5GBASE-R, 2500BASE-X, or SGMII, configure the rate type to 10M, 100M, 1000M, 2.5G, 5G, or 10G, configure the working mode of the PHY chip to single-duplex, half-duplex, or full-duplex, configure the network cable type to a straight-through cable or a crossover cable, and configure whether to enable functions such as flow control.

[0093] Step S02: determining a target configuration address of the PHY chip according to the configuration address information.

[0094] The FPGA can be used to find the address corresponding to the configuration address information in the PHY chip. The configuration address information includes the second register address and the second valid bit address, so that the FPGA can determine the second register address and the second valid bit address of the PHY chip according to the configuration address information, and then determine the target configuration address according to the second register address and the second valid bit address, that is, the FPGA will first find the second register address in multiple registers of the PHY chip, and then find the second valid bit address under the second register address, and use the second valid bit address as the target configuration address.

[0095] Step S03, writing the configuration parameters into the target configuration address.

[0096] After the FPGA finds the target configuration address, the configuration parameters can be written into the target configuration address through the FPGA, so that the PHY chip can work according to the user's needs with the user-selected interface type, rate type, working mode, inserted network cable type and other configurations, thereby realizing online switching of the PHY chip working mode.

[0097] In this embodiment, by configuring the configuration parameters in the target configuration address, the PHY chip can be operated according to the working mode required by the user. When the working mode of the PHY is reconfigured, the working state of the PHY chip will also change accordingly, and the type of PHY chip working state that the user needs to know may also change accordingly. The working state of the PHY chip can be read from the target read address through the FPGA, so that the working state of the electrical port module can be reflected in real time through the working state of the PHY chip.

[0098] In step S02, before the step of determining the target configuration address of the PHY chip according to the configuration address information, a second write operation instruction is obtained to enable the FPGA to enter a state of executing the operation instruction, reminding the FPGA that an operation instruction is about to arrive, so that the FPGA can execute the instruction obtained from the gold finger interface module, thereby executing the step of determining the target configuration address of the PHY chip according to the configuration address information.

[0099] Based on the above-mentioned second embodiment, the third embodiment of the present invention provides a method for obtaining the working status of an electrical port module. Before executing step S02, the step of determining the target configuration address of the PHY chip according to the configuration address information, the read flag information and the write flag information are obtained, so as to execute step S20 according to the read flag information, the step of determining the target read address of the PHY chip according to the state storage address information, and the step of executing step S02 according to the write flag information. The step of determining the target configuration address of the PHY chip according to the configuration address information makes the FPGA select to execute step S20 or step S02 according to the read flag information and the write flag information. For example, "0" can be used to represent the write flag information, and "1" can be used to represent the read flag information.

[0100] In addition, an embodiment of the present invention also proposes an electrical port module, which includes: a gold finger interface module, a PHY chip and a field programmable gate array controller, the field programmable gate array controller is used to receive status storage address information sent from the gold finger interface module, and determine a target read address in the PHY chip according to the status storage address information, and then the field programmable gate array controller reads the working status of the electrical port module from the target read address.

[0101] In this embodiment, a field programmable gate array controller, namely, FPGA, the operating speed of FPGA depends on the crystal oscillator speed, there is no delay in operating the PHY chip, the configuration of the PHY chip can be quickly changed, and the working status of the electrical port module can be reflected in real time.

[0102] See also Figure 4 The electrical port module also includes an Ethernet transformer 3, an RJ45 interface 4, a power management module 7, an initial configuration module 8 and a clock circuit module 6. The gold finger interface module 1, the PHY chip 2, the Ethernet transformer 3 and the RJ45 interface 4 are connected in sequence, wherein the Ethernet transformer 3 is used to protect the various components of the electrical port module from being interfered with; the field programmable gate array controller (i.e., FPGA) 5 is respectively connected to the gold finger interface module 1 and the PHY chip 2 to operate the PHY chip 2 according to the instructions received from the gold finger interface module 1; the power management module 7 is respectively connected to the gold finger interface module 1 and the PHY chip 2 to provide different voltages to various components of the PHY chip 2; the clock circuit module 6 is respectively connected to the field programmable gate array controller 5 and the PHY chip 2 to provide an external synchronous clock to the field programmable gate array controller 5 and the PHY chip 2; the initial configuration module 8 is connected to the PHY chip 2 to configure the PHY chip 2 through the initial configuration module 8 when the electrical port module is started, and to configure the PHY chip 2 through the field programmable gate array controller 5 when the configuration needs to be changed.

[0103] In addition, an embodiment of the present invention also proposes a computer-readable storage medium, on which a program for obtaining the working status of an electrical port module is stored. When the program for obtaining the working status of the electrical port module is executed by a processor, the steps of the method for obtaining the working status of the electrical port module described in any of the above embodiments are implemented.

[0104] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or system including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or system. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or system including the element.

[0105] The serial numbers of the above embodiments of the present invention are only for description and do not represent the advantages or disadvantages of the embodiments.

[0106] Through the description of the above implementation methods, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be implemented by means of software plus a necessary general hardware platform, and of course by hardware, but in many cases the former is a better implementation method. Based on such an understanding, the technical solution of the present invention is essentially or the part that contributes to the prior art can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) as described above, and includes a number of instructions for a terminal device (which can be a mobile phone, computer, server, air conditioner, or network device, etc.) to execute the methods described in each embodiment of the present invention.

[0107] The above are only preferred embodiments of the present invention, and are not intended to limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made using the contents of the present invention specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. A method for obtaining the working status of an electrical port module, characterized in that: The method for acquiring the working status of the electrical port module is used to acquire the working status of the electrical port module in real time. The method for acquiring the working status of the electrical port module comprises the following steps: Acquire state storage address information in real time based on user needs, wherein the state storage address information includes register address information, most significant bit address information, and least significant bit address information; Determine a target read address of the PHY chip according to the state storage address information; The step of determining the target read address of the PHY chip according to the state storage address information comprises: determining a first register address and a first valid bit address of the PHY chip according to the state storage address information; determining a target read address according to the first register address and the first valid bit address; Read the working status of the electrical port module in the target read address.

2. The method for obtaining the working status of the electrical port module according to claim 1, characterized in that: The step of reading the working status of the electrical port module in the target read address comprises: Get read instructions; Read the state parameter in the target read address according to the read instruction; The working state of the electrical port module is determined according to the state parameter.

3. The method for obtaining the working status of the electrical port module according to claim 1, characterized in that: Before the step of determining the target read address of the PHY chip according to the state storage address information, the step further includes: Obtain a first write operation instruction; The step of determining a target read address of the PHY chip according to the status storage address information is performed according to the first write operation instruction.

4. The method for obtaining the working status of the electrical port module according to claim 1, characterized in that: Before the step of determining the target read address of the PHY chip according to the state storage address information, the step further includes: Get configuration address information and configuration parameters; Determine a target configuration address of the PHY chip according to the configuration address information; The configuration parameters are written into the target configuration address.

5. The method for obtaining the working status of the electrical port module according to claim 4, characterized in that: The step of determining the target configuration address of the PHY chip according to the configuration address information comprises: Determine a second register address and a second valid bit address of the PHY chip according to the configuration address information; A target configuration address is determined according to the second register address and the second valid bit address.

6. The method for obtaining the working status of the electrical port module according to claim 4 or 5, characterized in that: Before the step of determining the target configuration address of the PHY chip according to the configuration address information, the step further includes: Get the second write operation instruction; The step of determining the target configuration address of the PHY chip according to the configuration address information is performed according to the second write operation instruction.

7. The method for obtaining the working status of the electrical port module according to claim 5, characterized in that: Before the step of determining the target configuration address of the PHY chip according to the configuration address information, the step further includes: Get the read flag information and write flag information; The step of determining the target read address of the PHY chip according to the status storage address information is performed according to the read flag information, and the step of determining the target configuration address of the PHY chip according to the configuration address information is performed according to the write flag information.

8. An electrical port module, characterized in that: The electrical port module includes: a gold finger interface module, a PHY chip and a field programmable gate array controller, wherein the field programmable gate array controller is used to obtain status storage address information sent from the gold finger interface module in real time based on user needs, wherein the status storage address information includes register address information, most significant bit address information and least significant bit address information; the field programmable gate array controller is also used to determine a target read address of the PHY chip according to the status storage address information; the step of determining the target read address of the PHY chip according to the status storage address information includes: determining a first register address and a first significant bit address of the PHY chip according to the status storage address information; determining a target read address according to the first register address and the first significant bit address; and then the field programmable gate array controller reads the working status of the electrical port module in the target read address.

9. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a program for acquiring the working status of the electrical port module. When the program for acquiring the working status of the electrical port module is executed by the processor, the steps of the method for acquiring the working status of the electrical port module according to any one of claims 1 to 7 are implemented.

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