Voltage Regulation in a Peak Current Mode Power Converter

Abstract

A power converter circuit (100) includes a switch node (105) coupled to a regulated power node (HO) via an inductor (104), the power converter circuit being capable of sinking current from the regulated power node (110) during a discharge cycle. A control circuit may use the voltage levels of an input power node (112) and the regulated power node (110) to generate an increasing ramp signal (113) and a decreasing ramp signal (114). The control circuit (101) may also use the result of comparing (302) the corresponding voltage levels of the generated increasing ramp signal and decreasing ramp signal to determine the duration of the discharge cycle.

Description

Background Art Technical Field

[0001] Implementations described herein relate to integrated circuits and, more particularly, to techniques for generating a regulated supply voltage.

[0002] Related technical description

[0003] Modern computer systems may include multiple circuit blocks designed to perform various functions. For example, such circuit blocks may include a processor, a processor core configured to execute software or program instructions. In addition, circuit blocks may include memory circuits, mixed signal or analog circuits, etc.

[0004] In some computer systems, circuit blocks may be designed to operate at different power supply voltage levels. Power management circuits may be included in such computer systems to generate and monitor varying power supply voltage levels for different circuit blocks.

[0005] The power management circuit generally includes one or more power converter circuits configured to generate a regulator voltage level for a corresponding power signal using the voltage level of the input power signal. Such regulator circuits may employ a plurality of passive circuit elements, such as inductors, capacitors, etc. Summary of the invention

[0006] The present invention discloses various embodiments of a power converter circuit. Broadly speaking, a power converter circuit is envisioned, wherein a switch node is coupled to a regulated power node via an inductor. A voltage regulator circuit may be configured to absorb current from the switch node during a discharge cycle. A control circuit may be configured to generate a falling ramp signal in response to the start of a discharge cycle, the initial voltage level of the falling ramp signal being the same as the voltage level of an input power signal. The control circuit may be further configured to generate a rising ramp signal using a reference clock. The initial voltage level of the rising ramp signal may be the same as the voltage level of the switch node. The control circuit may also be configured to stop the discharge cycle using a comparison result of the corresponding voltage levels of the falling ramp signal and the rising ramp signal. In another non-limiting embodiment, the control circuit may include a first capacitor coupled to an input power node, and the control circuit may be further configured to generate a first current, the value of the first current being proportional to the voltage level of the regulated power node, and the first capacitor is discharged using the first current. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The following detailed description refers to the accompanying drawings, which are now briefly described.

[0008] Figure 1 A block diagram of an embodiment of a power converter circuit is shown.

[0009] Figure 2 A schematic diagram of an embodiment of a regulator unit is shown.

[0010] Figure 3 A block diagram of an embodiment of a control circuit for a power converter circuit is shown.

[0011] Figure 4 A block diagram of an embodiment of a rising ramp generation circuit is shown.

[0012] Figure 5 A block diagram of an embodiment of a falling ramp generation circuit is shown.

[0013] Figure 6 Sample waveforms from the operation of the power converter circuit are shown.

[0014] Figure 7 A flow chart depicting an embodiment of a method for operating a power converter circuit is shown.

[0015] Figure 8 Depicts a block diagram of a computer system.

[0016] Although the present disclosure is susceptible to various modifications and alternative forms, the specific embodiments thereof are shown by way of example in the accompanying drawings and will be described in detail herein. However, it should be understood that the accompanying drawings and specific embodiments are not intended to limit the present disclosure to the specific forms illustrated, but on the contrary, their purpose is to cover all modifications, equivalents and alternative forms falling within the essence and scope of the present disclosure defined by the appended claims. The titles used herein are only for organizational purposes and are not intended to be used to limit the scope of the specification. As used throughout this patent application, the word "may" is used in an allowed sense (i.e., meaning with possibility) rather than a mandatory sense (i.e., meaning must). Similarly, the word "includes" means including but not limited to.

[0017] Various units, circuits or other components may be described as being "configured to" perform one or more tasks. In such contexts, "configured to" is a broad statement of a structure that generally means "having" a "circuit" that performs one or more tasks during operation. In this way, even when the unit / circuit / component is not currently connected, the unit / circuit / component may be configured to perform a task. Typically, the circuit that forms the structure corresponding to "configured to" may include a hardware circuit. Similarly, for convenience in description, various units / circuits / components may be described as performing one or more tasks. Such descriptions should be interpreted as including the phrase "configured to". The statement that a unit / circuit / component configured to perform one or more tasks is explicitly intended to not invoke the interpretation of paragraph f of 35 USC§112 for the unit / circuit / component. More generally, the statement of any element is explicitly intended not to invoke the interpretation of paragraph f of 35 USC§112 for the element, unless the language of "device for..." or "step for..." is specifically stated.

[0018] As used herein, the term "based on" is used to describe one or more factors that influence a determination. This term does not exclude that there may be additional factors that may influence the determination. That is, the determination may be based only on the specified factors or on the specified factors and other unspecified factors. Consider the phrase "A is determined based on B." This phrase specifies that B is a factor used to determine A or that B influences the determination of A. This phrase does not exclude that the determination of A may also be based on some other factor such as C. The phrase is also intended to cover embodiments in which A is determined based only on B. The phrase "based on" is therefore synonymous with the phrase "based at least in part on." DETAILED DESCRIPTION

[0019] A computer system may include multiple circuit blocks configured to perform specific functions. Such circuit blocks may be manufactured on a common substrate and may employ different power supply voltage levels. A power management unit (commonly referred to as a "PMU") may include multiple power converter circuits configured to generate regulated voltage levels for various power supply signals. Such power converter circuits may employ regulator circuits that include both passive circuit elements (e.g., inductors, capacitors, etc.) and active circuit elements (e.g., transistors, diodes, etc.).

[0020] Different types of voltage regulator circuits may be employed based on the power requirements of the load circuit, available circuit area, etc. One common type of voltage regulator circuit is a buck converter circuit. Such a converter circuit includes multiple devices and a switch node that is coupled to a regulated power node via an inductor. Specific devices are then activated to periodically charge and discharge the switch node in order to maintain a desired voltage level on the power node.

[0021] In order to determine the duration of a charge cycle or a discharge cycle, a feedback loop may be employed. Such a feedback loop compares ramp signals whose characteristics are based on operating parameters of the power converter circuit and stops the charge or discharge cycle based on the comparison result. In some cases, the current supplied to the load through the inductor is measured during the charge cycle (called "peak control"), while in other cases, the current absorbed from the load through the inductor is measured during the discharge cycle (called "valley control").

[0022] In some computer systems, multiple power converter circuits may be used. In such cases, the multiple power converter circuits may share an input power node and a ground power node. In order to prevent switching noise caused by coupling of one power converter circuit to another power converter circuit, the phase difference between the power converter circuits in the power converter circuits during operation should be maintained.

[0023] In order to provide phase control for the multiple power converter circuits, each power converter circuit may be individually timed. When such techniques are employed, the power converter circuit may not provide the desired response to transients in the load. Another technique for maintaining the desired phase relationship between the power converter circuits includes incorporating a phase-locked loop system to implement a variable charge (or discharge) time system. In many cases, the phase-locked loop may include two poles and is difficult to stabilize and requires dozens of cycles to lock.

[0024] The embodiments shown in the drawings and described below can provide a technique for operating a power converter circuit using a phase-locked loop system with reduced loop gain. By using such a phase-locked loop system, the stability of the system is improved and the number of cycles required for locking is reduced, thereby improving phase alignment between different converter circuits and transient load response.

[0025] Figure 1 A block diagram depicting an embodiment of a power converter circuit is shown in As shown, the power converter circuit 100 includes a control circuit 101 and a voltage regulator circuit 102 .

[0026] The voltage regulator circuit 102 includes a switch node 105 that is coupled to a regulated power supply node 110 via an inductor 104. In various embodiments, the voltage regulator circuit 102 is configured to discharge the switch node 105 into a ground power supply node 111 in response to the initiation of a discharge cycle 109. Note that although Figure 1 A single voltage regulator circuit is depicted in the embodiments, but in other embodiments, multiple voltage regulator circuits (collectively referred to as "phase units" or "phase circuits") may be coupled in parallel to the regulated power supply node 110 and operate at different timings (or "phases").

[0027] As described above, the duration of charging and discharging cycles in a power converter circuit may be determined using ramp signals that are generated to simulate the behavior of certain electrical characteristics of the power converter circuit (e.g., inductor current). Figure 1 As shown, the control circuit 101 is configured to generate a falling ramp signal in response to the start of a discharge cycle, the initial voltage level of the falling ramp signal being the same as the voltage level of the input power node. As described in more detail below, the control circuit 101 may start the discharge cycle based at least in part on a comparison of the voltage level of the switch node with a reference voltage level. As used herein, a falling ramp signal refers to a signal whose voltage level decreases over a specific period of time.

[0028] In addition to generating a falling ramp signal, the control circuit 101 is further configured to generate a rising ramp signal using a reference clock signal. The initial voltage level of the rising ramp signal may be the same as the voltage level of the switch node. In an embodiment using multiple power converter circuits, each power converter circuit may use a different reference block signal. As used herein, a rising ramp signal is a signal whose voltage level rises within a specific time period.

[0029] In order to adjust the duration of the discharge cycle, the control circuit 101 is further configured to stop the discharge cycle using the comparison result of the corresponding voltage levels of the falling ramp signal and the rising ramp signal. As described in more detail below, the control circuit 101 can be further configured to amplify the difference between the voltage level of the falling ramp signal and the voltage level of the rising ramp signal. By using the result of comparing the two ramp signals with the above-mentioned starting voltage levels, the number of cycles required to achieve the locked state of the power converter circuit 100 can be reduced.

[0030] exist Figure 2 A schematic diagram of the voltage regulator circuit 102 is depicted in As shown, the voltage regulator circuit 102 includes devices 201 and 202, both of which are coupled to a switch node 105 and controlled by control signals 203 and 204, respectively.

[0031] In various implementations, control circuit 101 may generate control signals 203 and 204. Each of control signals 203 and 204 is used to activate a corresponding one of devices 201 and 202 during charge and discharge cycles. During a charge cycle, current is supplied from input power supply node 112 to regulated power supply node 110, and during a discharge cycle, current is sunk from regulated power supply node 110 into ground power supply node 111. Alternating between charge and discharge cycles, and regulating the duration of either the charge or discharge cycle may maintain a desired voltage level on regulated power supply node 110.

[0032] Device 201 is coupled between input power supply node 112 and switch node 105 and is controlled by control signal 203. During a charging cycle, control signal 203 is asserted, which activates device 201 and couples input power supply node 112 to switch node 105, thereby charging switch node 105 by allowing current to flow from input power supply node 112 to switch node 105 and then to regulated power supply node 110. As used herein, asserting a signal or assertion of a signal refers to setting the signal to a specific voltage level that activates a circuit or device coupled to the signal. The specific voltage level can be any suitable value. For example, in the case where device 201 is a p-channel MOSFET, control signal 203 can be set to a voltage at or near ground potential.

[0033] Device 202 is coupled between switch node 105 and ground supply node 111 and is controlled by control signal 204. During a discharge cycle, control signal 204 is asserted, which activates device 202 and couples switch node 105 to ground supply node 111, thereby providing a conduction path from regulated supply node 110 through inductor 104 and into ground supply node 111. When device 202 is active, current flows from regulated supply node 110 into ground supply node 111, thereby reducing the voltage level of regulated supply node 110. As described in more detail below, the duration of the discharge cycle may be based on a comparison of the respective voltage levels of falling ramp signal 114 and rising ramp signal 113.

[0034] Device 201 and device 202 may be specific embodiments of MOSFETs. Specifically, device 201 may be a specific embodiment of a p-channel MOSFET, and device 202 may be a specific embodiment of an n-channel MOSFET. Figure 2 Only two devices are depicted in the embodiment of FIG. , but in other embodiments, any suitable number of devices coupled in series or parallel may be used to achieve a particular electrical characteristic (eg, on-resistance of a device).

[0035] exist Figure 3 A block diagram of an embodiment of the control circuit 101 is depicted in FIG. As shown, the control circuit 101 includes a logic circuit 301, a comparator circuit 302, an up ramp circuit 303, a down ramp circuit 304, and a comparator circuit 312.

[0036] Comparator circuit 312 is coupled to reference voltage level 311, switch node 105, and to logic circuit 301 via node 308. In various embodiments, comparator circuit 312 may be a specific implementation of a differential amplifier configured to generate peak detection signal 309 on node 308. The value of peak detection signal 309 is based on a comparison of reference voltage level 311 and the voltage level of switch node 105.

[0037] The rising ramp circuit 303 is coupled to the control signal 307, the switch node 105 and to the comparator circuit 302 via the node 305, and is configured to generate the rising ramp signal 113 on the node 305. As described in more detail below, in various embodiments, the rising ramp circuit 303 may include one or more current sources configured to supply current to the capacitor in order to generate the rising ramp signal. In some embodiments, the rising ramp circuit 303 may be configured to pre-charge the capacitor to the voltage level of the switch node 105 to provide an initial voltage level of the rising ramp signal 113.

[0038] The falling ramp circuit 304 is coupled to the control signal 307, the input power supply node 112, and to the comparator circuit 302 via a node 306, and is configured to generate the falling ramp signal 114 on the node 306. As described in more detail below, the falling ramp circuit 304 may include one or more current sources configured to sink current from a previously charged capacitor in order to generate the falling ramp signal 114. In some embodiments, the falling ramp circuit 304 may be configured to pre-charge the capacitor to the voltage level of the input power supply node 112 to provide an initial voltage level of the falling ramp signal 114.

[0039] Comparator circuit 302 is coupled to rising ramp circuit 303 and falling ramp circuit 304 via nodes 305 and 306, respectively. Comparator circuit is also coupled to logic circuit 301 via node 313. In various embodiments, comparator circuit 302 may be a specific implementation of a differential amplifier configured to amplify the difference of the respective voltage levels of rising ramp signal 113 and falling ramp signal 114 to generate reset signal 310 at node 313. In some cases, reset signal 310 is activated in response to determining that the respective voltage levels of rising ramp signal 113 and falling ramp signal 114 are substantially the same.

[0040] The logic circuit 301 may be a specific implementation of a sequential logic circuit or state machine configured to generate a control signal 307 using the reference clock signal 115, the peak detection signal 309, and the reset signal 310. In response to receiving the peak detection signal 309, the logic circuit 301 may activate one or more control signals 307 to start a discharge cycle and enable the falling ramp circuit 304 to generate the falling ramp signal 114. In addition, the logic circuit 301 may be configured to activate different groups of control signals 307 in response to the activation of the reference clock signal 115 to enable the rising ramp circuit 303 to generate the rising ramp signal 113. As used herein, activation of a signal (also referred to herein as assertion) refers to the transition of a signal to a logic value that enables a specific circuit or action coupled to the signal. In various embodiments, the activation of a signal may be a transition of the signal to a high value or a logic 1 value. In such cases, the signal is referred to as "high active". Alternatively, the activation of a signal may be a transition of the signal to a low value or a logic 0 value (referred to as "low active").

[0041] Go to Figure 4 , depicts a block diagram of an embodiment of the rising ramp circuit 303. As shown, the rising ramp circuit 303 includes a current source 401, a capacitor 402, and a switch 403.

[0042] The current source 401 is coupled between the regulated power supply node 110 and the rising ramp signal 113, and is configured to supply current to the rising ramp signal 113 and the capacitor 402. In various embodiments, the value of the current generated by the current source 401 may be proportional to the voltage level of the regulated power supply node 110 and the voltage level of the input power supply node 112.

[0043] Current source 401 may be a specific implementation of a transconductance device (e.g., a p-channel MOSFET) whose control voltage is selected to provide a desired current value. In some cases, current source 401 may be included as part of a current mirror or other suitable circuit configured to generate a specific current value.

[0044] Capacitor 402 is coupled between rising ramp signal 113 and switch node 105. When switch 403 is closed, capacitor 402 is charged to the voltage level of switch node 105. When switch 403 is open, as current source 401 supplies charge to capacitor 402, the voltage level across capacitor 402 increases and thus the voltage level of rising ramp signal 113 increases. In various embodiments, capacitor 402 may be fabricated using a metal-oxide-metal structure or any other suitable structure available on a semiconductor fabrication process for fabricating power converter circuit 100.

[0045] The switch 403 is configured to couple the rising ramp signal 113 to the switch node 105 based on the value of the control signal 404. In various embodiments, the control signal 404 may be included in the Figure 3 The control signal 307 is shown. Switch 403 can be a specific implementation of a transmission gate or other suitable switching circuit element. In some cases, switch 403 can include one or more MOSFETs or other suitable transconductance devices. Figure 4 A single control signal (ie, control signal 404) is depicted as controlling switch 403, but in other embodiments, more than one control signal may be employed.

[0046] Go to Figure 5 , depicts a block diagram illustrating an embodiment of a falling ramp circuit 304. As shown, the falling ramp circuit 304 includes a capacitor 501, a current source 502, and a switch 503.

[0047] Capacitor 501 is coupled between input power node 112 and falling ramp signal 114. When switch 503 is closed, falling ramp signal 114 is set to the same voltage level as the voltage level of input power node 112, and capacitor 501 is charged to the voltage level of input power node 112. When switch 503 is open, current source 502 discharges capacitor 501, thereby generating a reduced voltage level for falling ramp signal 114. In various embodiments, capacitor 501 may be fabricated using a metal-oxide-metal structure or any other suitable structure available on a semiconductor fabrication process for fabricating power converter circuit 100.

[0048] Current source 502 may be a specific implementation of a transconductance device (e.g., an n-channel MOSFET) whose control voltage is selected to provide a desired current value. In some cases, current source 502 may be included as part of a current mirror or other suitable circuit configured to generate a specific current value.

[0049] The switch 503 is configured to couple the down ramp signal 114 to the input power supply node 112 based on the value of the control signal 504. In various embodiments, the control signal 504 may be included in the Figure 3 The control signal 307 is shown. The switch 503 can be a specific implementation of a transmission gate or other suitable switching circuit element. In some cases, the switch 503 can include one or more MOSFETs or other suitable transconductance devices. Figure 5 A single control signal (ie, control signal 504) is depicted as controlling switch 503, but in other embodiments, more than one control signal may be employed.

[0050] Functional description language can be used to refer to things like Figures 2 to 5In some embodiments, the structures may be described as including "means for performing the following operations: generating a falling ramp signal in response to the start of a discharge cycle, the initial voltage of the falling ramp signal being the same as the voltage level of the input power node", "means for performing the following operations: generating an rising ramp signal using a reference clock signal, wherein the voltage level of the rising ramp signal is the same as the voltage level of the switch node", and "means for performing the following operations: stopping the discharge cycle using a comparison result of the respective voltage levels of the falling ramp signal and the rising ramp signal".

[0051] The corresponding structure of “means for performing the following operations: generating a falling ramp signal in response to the start of the discharge cycle, the initial voltage of the falling ramp signal being the same as the voltage level of the input power supply node” is the falling ramp circuit 304 and its equivalent. The corresponding structure of “means for performing the following operations: generating a rising ramp signal using a reference clock signal, wherein the voltage level of the rising ramp signal is the same as the voltage level of the switch node” is the rising ramp circuit 303 and its equivalent. The logic circuit 301 and the comparator circuit 302 and their equivalents are the corresponding structures of “means for performing the following operations: using the comparison result of the corresponding voltage levels of the falling ramp signal and the rising ramp signal to stop the discharge cycle”.

[0052] exist Figure 6 A sample waveform associated with the operation of a power converter circuit (eg, power converter circuit 100) is depicted in FIG. As shown, three clock cycles are depicted to demonstrate how the control loop of power converter circuit 100 can be locked within a few cycles using the techniques disclosed herein.

[0053] In the first clock cycle, the reference clock signal 115 is activated at time t0. The activation of the reference clock signal 115 causes the value of the rising ramp signal 113 to begin to increase from the voltage level of the regulated power supply node 110. At some point during the first clock cycle, a peak is detected in the voltage level of the regulated power supply node 110, causing the voltage level of the falling ramp signal 114 to begin to decrease from the voltage level of the input power supply node 112. When the voltage levels of the rising ramp signal 113 and the falling ramp signal 114 are the same, the discharge cycle is stopped. As the next clock cycle begins at time t1, both the falling ramp signal 114 and the rising ramp signal 113 are precharged back to their initial levels to be ready for the next clock cycle.

[0054] As the control loop of the power converter circuit 100 begins to lock, i.e., regulation of the voltage level of the regulated power supply node 110 has been achieved, the peak of the voltage level of the regulated power supply node 110 is detected more quickly within the clock cycle. As depicted in the second cycle, the peak is detected around time t1, causing the falling ramp signal 114 and the rising ramp signal 113 to transition substantially simultaneously.

[0055] In a similar manner to the first cycle, the discharge cycle ends when the respective voltage levels of the falling ramp signal 114 and the rising ramp signal 113 are substantially the same. As used herein, when voltage levels are referred to as being the same or substantially the same, it is when the two voltage levels are within a certain threshold value of each other. For example, if the two voltage levels are within 1 microvolt of each other, the two voltage levels may be considered the same. Depending on the circuit used, different thresholds may be used.

[0056] The waveform depicted in the third clock cycle (which starts at time t2) is similar to the waveform in the second clock cycle. Note that Figure 6 The waveforms depicted in FIG. 1 are exemplary waveforms only. Different operating conditions, different component values ​​used in power converter circuit 100 may produce waveforms with different appearances.

[0057] Go to Figure 7 , a flow chart depicting an embodiment of a method for operating a power converter circuit is shown. Figure 1 The method of the power converter circuit 100 depicted in FIG. 1 starts at block 701 .

[0058] The method includes initiating a discharge cycle of a voltage regulator circuit including a switch node coupled to a regulated power supply node via an inductor (block 702). In various embodiments, the method may include comparing a voltage level of the regulated power supply node with a reference voltage level, and initiating the discharge cycle based at least in part on the result of comparing the voltage level of the regulated power supply node with the reference voltage level. In some embodiments, the method may include sinking a discharge current from the switch node into a ground power supply node in response to initiating the discharge cycle. In some cases, the method may also include amplifying a difference between a voltage level of a falling ramp signal and a voltage level of a rising ramp signal using a comparator circuit.

[0059] In response to initiating a discharge cycle, the method includes generating a down ramp signal (block 703). In various embodiments, generating the down ramp signal may include generating a first current having a value proportional to the voltage level of the regulated power supply node, and using the first current to discharge a first capacitor coupled between a first input of the comparator circuit and the input power supply node.

[0060] The method also includes generating a rising ramp signal using the reference clock signal, the rising ramp signal having an initial voltage level that is the same as the voltage level of the switch node (block 704). In some embodiments, generating the rising ramp signal may include generating a second current having a value proportional to a difference between the voltage level of the input power node and the voltage level of the switch node, and charging a second capacitor coupled between a second input of the comparator circuit and the switch node using the second current.

[0061] The method also includes stopping the discharge cycle using the comparison result of the corresponding voltage levels of the falling ramp signal and the rising ramp signal (block 705). In various embodiments, the method may also include coupling the second input of the comparator circuit to the switch node in response to stopping the discharge cycle, and coupling the first input of the comparator circuit to the input power supply node. The method ends in block 706.

[0062] exist Figure 8 800. In the illustrated embodiment, computer system 800 includes power management circuit 801, processor circuit 802, memory circuit 803, and input / output circuit 804, each of which is coupled to power signal 805. In various embodiments, computer system 800 may be a system on a chip (SoC) and / or may be configured for use in a desktop computer, a server, or in a mobile computing application such as, for example, a tablet computer, a laptop computer, or a wearable computing device.

[0063] The power management circuit 801 includes a power converter circuit 100 configured to generate a regulated voltage level for a power supply signal 805 to provide power to the processor circuit 802, the memory circuit 803, and the input / output circuit 804. Although the power management circuit 801 is depicted as including a single power converter circuit, in other embodiments, any suitable number of power converter circuits may be included in the power management circuit 801, each power converter circuit being configured to generate a regulated voltage level for a corresponding internal power supply signal of a plurality of internal power supply signals included in the computer system 800. Where a plurality of power converter circuits are employed, two or more of the plurality of power converter circuits may be connected to a common power supply terminal set connected to the power supply signal and a ground power supply signal of the computer system 800.

[0064] In various embodiments, processor circuit 802 may represent a general purpose processor that performs computing operations. For example, processor circuit 802 may be a central processing unit (CPU) such as a microprocessor, microcontroller, application specific integrated circuit (ASIC), or field programmable gate array (FPGA).

[0065] In various embodiments, memory circuit 803 may include any suitable type of memory, such as, for example, dynamic random access memory (DRAM), static random access memory (SRAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), or non-volatile memory. Figure 8 A single memory circuit is shown in FIG. 1 , but in other embodiments, any suitable number of memory circuits may be employed.

[0066] Input / output circuitry 804 may be configured to coordinate data transfers between computer system 800 and one or more peripheral devices. Such peripheral devices may include, but are not limited to, storage devices (e.g., storage devices based on magnetic or optical media, including hard drives, tape drives, CD drives, DVD drives, etc.), audio processing subsystems, or any other suitable type of peripheral device. In some embodiments, input / output circuitry 804 may be configured to implement the Universal Serial Bus (USB) protocol or IEEE 1394. The version of the protocol.

[0067] The input / output circuitry 804 may also be configured to coordinate data transfers between the computer system 800 and one or more devices (e.g., other computing systems or integrated circuits) coupled to the computer system 800 via a network. In one embodiment, the input / output circuitry 804 may be configured to perform the data processing necessary to implement an Ethernet (IEEE 802.3) networking standard such as, for example, Gigabit Ethernet or 10 Gigabit Ethernet, although it is contemplated that any suitable networking standard may be implemented. In some embodiments, the input / output circuitry 804 may be configured to implement multiple discrete network interface ports.

[0068] Although specific embodiments have been described above, these embodiments are not intended to limit the scope of the present disclosure, even when only a single embodiment is described with respect to specific features. The feature examples provided in this disclosure are intended to be illustrative, not limiting, unless otherwise stated. The above description is intended to cover such alternatives, modifications, and equivalents, which will be apparent to those skilled in the art who are aware of the effective effects of the present disclosure.

[0069] The scope of the present disclosure includes any feature or combination of features disclosed herein (explicitly or implicitly) or any generalization thereof, whether or not it mitigates any or all of the problems addressed herein. Accordingly, new claims may be made during the prosecution of this patent application (or a patent application claiming priority thereto) for any such combination of features. In particular, with reference to the appended claims, features of the dependent claims may be combined with features of the independent claims, and features from the corresponding independent claims may be combined in any appropriate manner and not just by the specific combinations listed in the appended claims.

Claims

1. A device for voltage regulation, comprising: a voltage regulator circuit including a switch node coupled to a regulated power supply node via an inductor, wherein the voltage regulator circuit is configured to: supply a charging current from an input power supply node to the switch node during a charging cycle; and absorb a discharge current from the switch node during a discharge cycle; and a control circuit configured to: generate a falling ramp signal in response to the start of the discharge cycle, the initial voltage level of the falling ramp signal being the same as the voltage level of the input power supply node; generate a rising ramp signal using a reference clock signal, wherein the initial voltage level of the rising ramp signal is the same as the voltage level of the switch node; compare the rising ramp signal and the falling ramp signal to generate a reset signal; and use the reset signal to stop the discharge cycle.

2. The device according to claim 1, wherein the control circuit includes a first capacitor coupled to the input power supply node, and wherein the control circuit is further configured to: generate a first current, the value of the first current being proportional to the voltage level of the regulated power supply node; and discharge the first capacitor using the first current.

3. The device according to claim 2, wherein the control circuit includes a second capacitor coupled to the switch node, and wherein the control circuit is further configured to: generate a second current, the value of the second current being proportional to the difference between the voltage level of the input power supply node and the voltage level of the regulated power supply node; and charge the second capacitor using the second current.

4. The device according to claim 3, wherein the control circuit is further configured to, in response to stopping the discharge cycle: couple two terminals of the first capacitor to the input power supply node; and couple two terminals of the second capacitor to the switch node.

5. The device according to claim 1, wherein the control circuit is further configured to amplify the difference between the voltage level of the rising ramp signal and the voltage level of the falling ramp signal.

6. The device according to claim 1, wherein the control circuit is further configured to compare the voltage level of the switch node with a reference voltage level.

7. A method for voltage regulation, comprising: starting a discharge cycle of a voltage regulator circuit including a switch node coupled to a regulated power supply node via an inductor; in response to starting the discharge cycle: generate a first current, the value of the first current being proportional to the voltage level of the regulated power supply node; and discharge a first capacitor using the first current to generate a falling ramp signal, wherein the first capacitor is coupled between a first terminal of a comparator circuit and an input power supply node; generate a rising ramp signal in response to asserting a reference clock signal, wherein the initial voltage level of the falling ramp signal is greater than the initial voltage level of the rising ramp signal; Comparing the rising ramp signal and the falling ramp signal by amplifying the difference between the voltage levels of the falling ramp signal and the rising ramp signal using the comparator circuit to generate a reset signal; and Using the reset signal to stop the discharge cycle.

8. The method according to claim 7, wherein generating the rising ramp signal comprises: Generating a second current, the value of which is proportional to the difference between the voltage level of the input power supply node and the voltage level of the regulated power supply node; and Charging a second capacitor using the second current, wherein the second capacitor is coupled between a second terminal of the comparator circuit and the switch node.

9. The method according to claim 8, further comprises: In response to stopping the discharge cycle: Coupling the second terminal of the comparator circuit to the switch node; and Coupling the first terminal of the comparator circuit to the input power supply node.

10. The method according to claim 7, further comprising drawing a discharge current from the switch node into a ground power supply node in response to starting the discharge cycle.

11. The method according to claim 7, wherein starting the discharge cycle of the voltage regulator circuit comprises comparing the voltage level of the switch node with a reference voltage level.

12. An apparatus for voltage regulation, comprising: A voltage regulator circuit including a switch node coupled to a regulated power supply node via an inductor, wherein the voltage regulator circuit is configured to: Supply a charging current from an input power supply node to the switch node; and Draw a discharge current from the switch node in response to activation of one or more control signals; A first ramp circuit configured to generate a falling ramp signal in response to the activation of the one or more control signals, wherein an initial voltage level of the falling ramp signal is the same as a voltage level of the input power supply signal; A second ramp circuit configured to generate a rising ramp signal in response to assertion of a reference clock signal, wherein an initial voltage level of the rising ramp signal is the same as a voltage level of the switch node; and Logic circuitry configured to: Compare the corresponding voltage levels of the falling ramp signal and the rising ramp signal to generate a reset signal; and Deactivate the one or more control signals based on the reset signal.

13. The apparatus according to claim 12, wherein the first ramp circuit includes a first capacitor and a first switching device configured to couple the first capacitor to the input power supply signal in response to determining that the one or more control signals are deactivated.

14. The apparatus according to claim 13, wherein the first ramp circuit further includes a first current source configured to draw a first current from the first capacitor in response to the activation of the one or more control signals, wherein a value of the first current is proportional to the voltage level of the switch node.

15. The apparatus according to claim 12, wherein the second ramp circuit includes a second capacitor and a second switch, and the second switch is configured to couple the second capacitor to the regulated power supply node in response to determining that the reference clock signal is inactive.

16. The apparatus according to claim 15, wherein the second ramp circuit further includes a second current source, and the second current source is configured to supply a second current to the second capacitor, wherein the value of the second current is proportional to the difference between the input power supply signal and the corresponding voltage level of the switch node.

17. The apparatus according to claim 12, further comprising a comparator circuit configured to compare the voltage level of the switch node with a reference voltage level.

18. The apparatus according to claim 12, wherein the voltage regulator circuit is further configured to supply a charging current to the switch node in response to the activation of one or more different control signals.

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